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Merge branch 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
58 };
59
60 enum board_ids {
61 /* board IDs by feature in alphabetical order */
62 board_ahci,
63 board_ahci_ign_iferr,
64 board_ahci_nosntf,
65 board_ahci_yes_fbs,
66
67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
69 board_ahci_mcp77,
70 board_ahci_mcp89,
71 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
81 };
82
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 #ifdef CONFIG_PM
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
91 #endif
92
93 static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95 };
96
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
100 };
101
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
105 };
106
107 static const struct ata_port_info ahci_port_info[] = {
108 /* by features */
109 [board_ahci] = {
110 .flags = AHCI_FLAG_COMMON,
111 .pio_mask = ATA_PIO4,
112 .udma_mask = ATA_UDMA6,
113 .port_ops = &ahci_ops,
114 },
115 [board_ahci_ign_iferr] = {
116 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
117 .flags = AHCI_FLAG_COMMON,
118 .pio_mask = ATA_PIO4,
119 .udma_mask = ATA_UDMA6,
120 .port_ops = &ahci_ops,
121 },
122 [board_ahci_nosntf] = {
123 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
124 .flags = AHCI_FLAG_COMMON,
125 .pio_mask = ATA_PIO4,
126 .udma_mask = ATA_UDMA6,
127 .port_ops = &ahci_ops,
128 },
129 [board_ahci_yes_fbs] = {
130 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
135 },
136 /* by chipsets */
137 [board_ahci_mcp65] = {
138 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
139 AHCI_HFLAG_YES_NCQ),
140 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
145 [board_ahci_mcp77] = {
146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
151 },
152 [board_ahci_mcp89] = {
153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
158 },
159 [board_ahci_mv] = {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
161 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
162 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
167 [board_ahci_sb600] = {
168 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
169 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
170 AHCI_HFLAG_32BIT_ONLY),
171 .flags = AHCI_FLAG_COMMON,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_pmp_retry_srst_ops,
175 },
176 [board_ahci_sb700] = { /* for SB700 and SB800 */
177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
178 .flags = AHCI_FLAG_COMMON,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_pmp_retry_srst_ops,
182 },
183 [board_ahci_vt8251] = {
184 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
188 .port_ops = &ahci_vt8251_ops,
189 },
190 };
191
192 static const struct pci_device_id ahci_pci_tbl[] = {
193 /* Intel */
194 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
195 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
196 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
197 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
198 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
199 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
200 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
201 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
203 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
204 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
205 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
206 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
207 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
208 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
209 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
214 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
215 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
219 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
221 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
222 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
223 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
224 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
225 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
226 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
227 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
228 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
229 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
230 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
231 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
232 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
233 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
234 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
236 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
237 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
240 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
241 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
242 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
243 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
244 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
245 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
247 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
248 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
251 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
252 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
253 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
255 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
259 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
260 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
261 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
262 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
263 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
267 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
268
269 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
270 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
271 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
272 /* JMicron 362B and 362C have an AHCI function with IDE class code */
273 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
274 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
275
276 /* ATI */
277 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
278 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
280 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
281 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
282 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
283 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
284
285 /* AMD */
286 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
287 /* AMD is using RAID class only for ahci controllers */
288 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
289 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
290
291 /* VIA */
292 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
293 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
294
295 /* NVIDIA */
296 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
300 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
301 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
302 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
303 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
304 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
313 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
314 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
315 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
316 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
329 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
330 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
331 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
332 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
341 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
342 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
343 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
353 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
354 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
355 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
356 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
365 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
366 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
367 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
368 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
376 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
377 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
378 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
379 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
380
381 /* SiS */
382 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
383 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
384 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
385
386 /* ST Microelectronics */
387 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
388
389 /* Marvell */
390 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
391 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
392 { PCI_DEVICE(0x1b4b, 0x9123),
393 .class = PCI_CLASS_STORAGE_SATA_AHCI,
394 .class_mask = 0xffffff,
395 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
396 { PCI_DEVICE(0x1b4b, 0x9125),
397 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
398 { PCI_DEVICE(0x1b4b, 0x917a),
399 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
400 { PCI_DEVICE(0x1b4b, 0x9192),
401 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
402 { PCI_DEVICE(0x1b4b, 0x91a3),
403 .driver_data = board_ahci_yes_fbs },
404
405 /* Promise */
406 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
407
408 /* Asmedia */
409 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
410 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
411 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
412 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
413
414 /* Enmotus */
415 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
416
417 /* Generic, PCI class code for AHCI */
418 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
419 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
420
421 { } /* terminate list */
422 };
423
424
425 static struct pci_driver ahci_pci_driver = {
426 .name = DRV_NAME,
427 .id_table = ahci_pci_tbl,
428 .probe = ahci_init_one,
429 .remove = ata_pci_remove_one,
430 #ifdef CONFIG_PM
431 .suspend = ahci_pci_device_suspend,
432 .resume = ahci_pci_device_resume,
433 #endif
434 };
435
436 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
437 static int marvell_enable;
438 #else
439 static int marvell_enable = 1;
440 #endif
441 module_param(marvell_enable, int, 0644);
442 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
443
444
445 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
446 struct ahci_host_priv *hpriv)
447 {
448 unsigned int force_port_map = 0;
449 unsigned int mask_port_map = 0;
450
451 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
452 dev_info(&pdev->dev, "JMB361 has only one port\n");
453 force_port_map = 1;
454 }
455
456 /*
457 * Temporary Marvell 6145 hack: PATA port presence
458 * is asserted through the standard AHCI port
459 * presence register, as bit 4 (counting from 0)
460 */
461 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
462 if (pdev->device == 0x6121)
463 mask_port_map = 0x3;
464 else
465 mask_port_map = 0xf;
466 dev_info(&pdev->dev,
467 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
468 }
469
470 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
471 mask_port_map);
472 }
473
474 static int ahci_pci_reset_controller(struct ata_host *host)
475 {
476 struct pci_dev *pdev = to_pci_dev(host->dev);
477
478 ahci_reset_controller(host);
479
480 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
481 struct ahci_host_priv *hpriv = host->private_data;
482 u16 tmp16;
483
484 /* configure PCS */
485 pci_read_config_word(pdev, 0x92, &tmp16);
486 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
487 tmp16 |= hpriv->port_map;
488 pci_write_config_word(pdev, 0x92, tmp16);
489 }
490 }
491
492 return 0;
493 }
494
495 static void ahci_pci_init_controller(struct ata_host *host)
496 {
497 struct ahci_host_priv *hpriv = host->private_data;
498 struct pci_dev *pdev = to_pci_dev(host->dev);
499 void __iomem *port_mmio;
500 u32 tmp;
501 int mv;
502
503 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
504 if (pdev->device == 0x6121)
505 mv = 2;
506 else
507 mv = 4;
508 port_mmio = __ahci_port_base(host, mv);
509
510 writel(0, port_mmio + PORT_IRQ_MASK);
511
512 /* clear port IRQ */
513 tmp = readl(port_mmio + PORT_IRQ_STAT);
514 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
515 if (tmp)
516 writel(tmp, port_mmio + PORT_IRQ_STAT);
517 }
518
519 ahci_init_controller(host);
520 }
521
522 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
523 unsigned long deadline)
524 {
525 struct ata_port *ap = link->ap;
526 bool online;
527 int rc;
528
529 DPRINTK("ENTER\n");
530
531 ahci_stop_engine(ap);
532
533 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
534 deadline, &online, NULL);
535
536 ahci_start_engine(ap);
537
538 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
539
540 /* vt8251 doesn't clear BSY on signature FIS reception,
541 * request follow-up softreset.
542 */
543 return online ? -EAGAIN : rc;
544 }
545
546 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
547 unsigned long deadline)
548 {
549 struct ata_port *ap = link->ap;
550 struct ahci_port_priv *pp = ap->private_data;
551 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
552 struct ata_taskfile tf;
553 bool online;
554 int rc;
555
556 ahci_stop_engine(ap);
557
558 /* clear D2H reception area to properly wait for D2H FIS */
559 ata_tf_init(link->device, &tf);
560 tf.command = 0x80;
561 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
562
563 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
564 deadline, &online, NULL);
565
566 ahci_start_engine(ap);
567
568 /* The pseudo configuration device on SIMG4726 attached to
569 * ASUS P5W-DH Deluxe doesn't send signature FIS after
570 * hardreset if no device is attached to the first downstream
571 * port && the pseudo device locks up on SRST w/ PMP==0. To
572 * work around this, wait for !BSY only briefly. If BSY isn't
573 * cleared, perform CLO and proceed to IDENTIFY (achieved by
574 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
575 *
576 * Wait for two seconds. Devices attached to downstream port
577 * which can't process the following IDENTIFY after this will
578 * have to be reset again. For most cases, this should
579 * suffice while making probing snappish enough.
580 */
581 if (online) {
582 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
583 ahci_check_ready);
584 if (rc)
585 ahci_kick_engine(ap);
586 }
587 return rc;
588 }
589
590 #ifdef CONFIG_PM
591 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
592 {
593 struct ata_host *host = dev_get_drvdata(&pdev->dev);
594 struct ahci_host_priv *hpriv = host->private_data;
595 void __iomem *mmio = hpriv->mmio;
596 u32 ctl;
597
598 if (mesg.event & PM_EVENT_SUSPEND &&
599 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
600 dev_err(&pdev->dev,
601 "BIOS update required for suspend/resume\n");
602 return -EIO;
603 }
604
605 if (mesg.event & PM_EVENT_SLEEP) {
606 /* AHCI spec rev1.1 section 8.3.3:
607 * Software must disable interrupts prior to requesting a
608 * transition of the HBA to D3 state.
609 */
610 ctl = readl(mmio + HOST_CTL);
611 ctl &= ~HOST_IRQ_EN;
612 writel(ctl, mmio + HOST_CTL);
613 readl(mmio + HOST_CTL); /* flush */
614 }
615
616 return ata_pci_device_suspend(pdev, mesg);
617 }
618
619 static int ahci_pci_device_resume(struct pci_dev *pdev)
620 {
621 struct ata_host *host = dev_get_drvdata(&pdev->dev);
622 int rc;
623
624 rc = ata_pci_device_do_resume(pdev);
625 if (rc)
626 return rc;
627
628 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
629 rc = ahci_pci_reset_controller(host);
630 if (rc)
631 return rc;
632
633 ahci_pci_init_controller(host);
634 }
635
636 ata_host_resume(host);
637
638 return 0;
639 }
640 #endif
641
642 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
643 {
644 int rc;
645
646 /*
647 * If the device fixup already set the dma_mask to some non-standard
648 * value, don't extend it here. This happens on STA2X11, for example.
649 */
650 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
651 return 0;
652
653 if (using_dac &&
654 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
655 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
656 if (rc) {
657 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
658 if (rc) {
659 dev_err(&pdev->dev,
660 "64-bit DMA enable failed\n");
661 return rc;
662 }
663 }
664 } else {
665 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
666 if (rc) {
667 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
668 return rc;
669 }
670 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
671 if (rc) {
672 dev_err(&pdev->dev,
673 "32-bit consistent DMA enable failed\n");
674 return rc;
675 }
676 }
677 return 0;
678 }
679
680 static void ahci_pci_print_info(struct ata_host *host)
681 {
682 struct pci_dev *pdev = to_pci_dev(host->dev);
683 u16 cc;
684 const char *scc_s;
685
686 pci_read_config_word(pdev, 0x0a, &cc);
687 if (cc == PCI_CLASS_STORAGE_IDE)
688 scc_s = "IDE";
689 else if (cc == PCI_CLASS_STORAGE_SATA)
690 scc_s = "SATA";
691 else if (cc == PCI_CLASS_STORAGE_RAID)
692 scc_s = "RAID";
693 else
694 scc_s = "unknown";
695
696 ahci_print_info(host, scc_s);
697 }
698
699 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
700 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
701 * support PMP and the 4726 either directly exports the device
702 * attached to the first downstream port or acts as a hardware storage
703 * controller and emulate a single ATA device (can be RAID 0/1 or some
704 * other configuration).
705 *
706 * When there's no device attached to the first downstream port of the
707 * 4726, "Config Disk" appears, which is a pseudo ATA device to
708 * configure the 4726. However, ATA emulation of the device is very
709 * lame. It doesn't send signature D2H Reg FIS after the initial
710 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
711 *
712 * The following function works around the problem by always using
713 * hardreset on the port and not depending on receiving signature FIS
714 * afterward. If signature FIS isn't received soon, ATA class is
715 * assumed without follow-up softreset.
716 */
717 static void ahci_p5wdh_workaround(struct ata_host *host)
718 {
719 static struct dmi_system_id sysids[] = {
720 {
721 .ident = "P5W DH Deluxe",
722 .matches = {
723 DMI_MATCH(DMI_SYS_VENDOR,
724 "ASUSTEK COMPUTER INC"),
725 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
726 },
727 },
728 { }
729 };
730 struct pci_dev *pdev = to_pci_dev(host->dev);
731
732 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
733 dmi_check_system(sysids)) {
734 struct ata_port *ap = host->ports[1];
735
736 dev_info(&pdev->dev,
737 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
738
739 ap->ops = &ahci_p5wdh_ops;
740 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
741 }
742 }
743
744 /* only some SB600 ahci controllers can do 64bit DMA */
745 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
746 {
747 static const struct dmi_system_id sysids[] = {
748 /*
749 * The oldest version known to be broken is 0901 and
750 * working is 1501 which was released on 2007-10-26.
751 * Enable 64bit DMA on 1501 and anything newer.
752 *
753 * Please read bko#9412 for more info.
754 */
755 {
756 .ident = "ASUS M2A-VM",
757 .matches = {
758 DMI_MATCH(DMI_BOARD_VENDOR,
759 "ASUSTeK Computer INC."),
760 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
761 },
762 .driver_data = "20071026", /* yyyymmdd */
763 },
764 /*
765 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
766 * support 64bit DMA.
767 *
768 * BIOS versions earlier than 1.5 had the Manufacturer DMI
769 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
770 * This spelling mistake was fixed in BIOS version 1.5, so
771 * 1.5 and later have the Manufacturer as
772 * "MICRO-STAR INTERNATIONAL CO.,LTD".
773 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
774 *
775 * BIOS versions earlier than 1.9 had a Board Product Name
776 * DMI field of "MS-7376". This was changed to be
777 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
778 * match on DMI_BOARD_NAME of "MS-7376".
779 */
780 {
781 .ident = "MSI K9A2 Platinum",
782 .matches = {
783 DMI_MATCH(DMI_BOARD_VENDOR,
784 "MICRO-STAR INTER"),
785 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
786 },
787 },
788 /*
789 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
790 * 64bit DMA.
791 *
792 * This board also had the typo mentioned above in the
793 * Manufacturer DMI field (fixed in BIOS version 1.5), so
794 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
795 */
796 {
797 .ident = "MSI K9AGM2",
798 .matches = {
799 DMI_MATCH(DMI_BOARD_VENDOR,
800 "MICRO-STAR INTER"),
801 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
802 },
803 },
804 /*
805 * All BIOS versions for the Asus M3A support 64bit DMA.
806 * (all release versions from 0301 to 1206 were tested)
807 */
808 {
809 .ident = "ASUS M3A",
810 .matches = {
811 DMI_MATCH(DMI_BOARD_VENDOR,
812 "ASUSTeK Computer INC."),
813 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
814 },
815 },
816 { }
817 };
818 const struct dmi_system_id *match;
819 int year, month, date;
820 char buf[9];
821
822 match = dmi_first_match(sysids);
823 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
824 !match)
825 return false;
826
827 if (!match->driver_data)
828 goto enable_64bit;
829
830 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
831 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
832
833 if (strcmp(buf, match->driver_data) >= 0)
834 goto enable_64bit;
835 else {
836 dev_warn(&pdev->dev,
837 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
838 match->ident);
839 return false;
840 }
841
842 enable_64bit:
843 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
844 return true;
845 }
846
847 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
848 {
849 static const struct dmi_system_id broken_systems[] = {
850 {
851 .ident = "HP Compaq nx6310",
852 .matches = {
853 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
854 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
855 },
856 /* PCI slot number of the controller */
857 .driver_data = (void *)0x1FUL,
858 },
859 {
860 .ident = "HP Compaq 6720s",
861 .matches = {
862 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
863 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
864 },
865 /* PCI slot number of the controller */
866 .driver_data = (void *)0x1FUL,
867 },
868
869 { } /* terminate list */
870 };
871 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
872
873 if (dmi) {
874 unsigned long slot = (unsigned long)dmi->driver_data;
875 /* apply the quirk only to on-board controllers */
876 return slot == PCI_SLOT(pdev->devfn);
877 }
878
879 return false;
880 }
881
882 static bool ahci_broken_suspend(struct pci_dev *pdev)
883 {
884 static const struct dmi_system_id sysids[] = {
885 /*
886 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
887 * to the harddisk doesn't become online after
888 * resuming from STR. Warn and fail suspend.
889 *
890 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
891 *
892 * Use dates instead of versions to match as HP is
893 * apparently recycling both product and version
894 * strings.
895 *
896 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
897 */
898 {
899 .ident = "dv4",
900 .matches = {
901 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
902 DMI_MATCH(DMI_PRODUCT_NAME,
903 "HP Pavilion dv4 Notebook PC"),
904 },
905 .driver_data = "20090105", /* F.30 */
906 },
907 {
908 .ident = "dv5",
909 .matches = {
910 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
911 DMI_MATCH(DMI_PRODUCT_NAME,
912 "HP Pavilion dv5 Notebook PC"),
913 },
914 .driver_data = "20090506", /* F.16 */
915 },
916 {
917 .ident = "dv6",
918 .matches = {
919 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
920 DMI_MATCH(DMI_PRODUCT_NAME,
921 "HP Pavilion dv6 Notebook PC"),
922 },
923 .driver_data = "20090423", /* F.21 */
924 },
925 {
926 .ident = "HDX18",
927 .matches = {
928 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
929 DMI_MATCH(DMI_PRODUCT_NAME,
930 "HP HDX18 Notebook PC"),
931 },
932 .driver_data = "20090430", /* F.23 */
933 },
934 /*
935 * Acer eMachines G725 has the same problem. BIOS
936 * V1.03 is known to be broken. V3.04 is known to
937 * work. Between, there are V1.06, V2.06 and V3.03
938 * that we don't have much idea about. For now,
939 * blacklist anything older than V3.04.
940 *
941 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
942 */
943 {
944 .ident = "G725",
945 .matches = {
946 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
947 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
948 },
949 .driver_data = "20091216", /* V3.04 */
950 },
951 { } /* terminate list */
952 };
953 const struct dmi_system_id *dmi = dmi_first_match(sysids);
954 int year, month, date;
955 char buf[9];
956
957 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
958 return false;
959
960 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
961 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
962
963 return strcmp(buf, dmi->driver_data) < 0;
964 }
965
966 static bool ahci_broken_online(struct pci_dev *pdev)
967 {
968 #define ENCODE_BUSDEVFN(bus, slot, func) \
969 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
970 static const struct dmi_system_id sysids[] = {
971 /*
972 * There are several gigabyte boards which use
973 * SIMG5723s configured as hardware RAID. Certain
974 * 5723 firmware revisions shipped there keep the link
975 * online but fail to answer properly to SRST or
976 * IDENTIFY when no device is attached downstream
977 * causing libata to retry quite a few times leading
978 * to excessive detection delay.
979 *
980 * As these firmwares respond to the second reset try
981 * with invalid device signature, considering unknown
982 * sig as offline works around the problem acceptably.
983 */
984 {
985 .ident = "EP45-DQ6",
986 .matches = {
987 DMI_MATCH(DMI_BOARD_VENDOR,
988 "Gigabyte Technology Co., Ltd."),
989 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
990 },
991 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
992 },
993 {
994 .ident = "EP45-DS5",
995 .matches = {
996 DMI_MATCH(DMI_BOARD_VENDOR,
997 "Gigabyte Technology Co., Ltd."),
998 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
999 },
1000 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1001 },
1002 { } /* terminate list */
1003 };
1004 #undef ENCODE_BUSDEVFN
1005 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1006 unsigned int val;
1007
1008 if (!dmi)
1009 return false;
1010
1011 val = (unsigned long)dmi->driver_data;
1012
1013 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1014 }
1015
1016 #ifdef CONFIG_ATA_ACPI
1017 static void ahci_gtf_filter_workaround(struct ata_host *host)
1018 {
1019 static const struct dmi_system_id sysids[] = {
1020 /*
1021 * Aspire 3810T issues a bunch of SATA enable commands
1022 * via _GTF including an invalid one and one which is
1023 * rejected by the device. Among the successful ones
1024 * is FPDMA non-zero offset enable which when enabled
1025 * only on the drive side leads to NCQ command
1026 * failures. Filter it out.
1027 */
1028 {
1029 .ident = "Aspire 3810T",
1030 .matches = {
1031 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1032 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1033 },
1034 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1035 },
1036 { }
1037 };
1038 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1039 unsigned int filter;
1040 int i;
1041
1042 if (!dmi)
1043 return;
1044
1045 filter = (unsigned long)dmi->driver_data;
1046 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1047 filter, dmi->ident);
1048
1049 for (i = 0; i < host->n_ports; i++) {
1050 struct ata_port *ap = host->ports[i];
1051 struct ata_link *link;
1052 struct ata_device *dev;
1053
1054 ata_for_each_link(link, ap, EDGE)
1055 ata_for_each_dev(dev, link, ALL)
1056 dev->gtf_filter |= filter;
1057 }
1058 }
1059 #else
1060 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1061 {}
1062 #endif
1063
1064 int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1065 {
1066 int rc;
1067 unsigned int maxvec;
1068
1069 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1070 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1071 if (rc > 0) {
1072 if ((rc == maxvec) || (rc == 1))
1073 return rc;
1074 /*
1075 * Assume that advantage of multipe MSIs is negated,
1076 * so fallback to single MSI mode to save resources
1077 */
1078 pci_disable_msi(pdev);
1079 if (!pci_enable_msi(pdev))
1080 return 1;
1081 }
1082 }
1083
1084 pci_intx(pdev, 1);
1085 return 0;
1086 }
1087
1088 /**
1089 * ahci_host_activate - start AHCI host, request IRQs and register it
1090 * @host: target ATA host
1091 * @irq: base IRQ number to request
1092 * @n_msis: number of MSIs allocated for this host
1093 * @irq_handler: irq_handler used when requesting IRQs
1094 * @irq_flags: irq_flags used when requesting IRQs
1095 *
1096 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1097 * when multiple MSIs were allocated. That is one MSI per port, starting
1098 * from @irq.
1099 *
1100 * LOCKING:
1101 * Inherited from calling layer (may sleep).
1102 *
1103 * RETURNS:
1104 * 0 on success, -errno otherwise.
1105 */
1106 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1107 {
1108 int i, rc;
1109
1110 /* Sharing Last Message among several ports is not supported */
1111 if (n_msis < host->n_ports)
1112 return -EINVAL;
1113
1114 rc = ata_host_start(host);
1115 if (rc)
1116 return rc;
1117
1118 for (i = 0; i < host->n_ports; i++) {
1119 rc = devm_request_threaded_irq(host->dev,
1120 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1121 dev_driver_string(host->dev), host->ports[i]);
1122 if (rc)
1123 goto out_free_irqs;
1124 }
1125
1126 for (i = 0; i < host->n_ports; i++)
1127 ata_port_desc(host->ports[i], "irq %d", irq + i);
1128
1129 rc = ata_host_register(host, &ahci_sht);
1130 if (rc)
1131 goto out_free_all_irqs;
1132
1133 return 0;
1134
1135 out_free_all_irqs:
1136 i = host->n_ports;
1137 out_free_irqs:
1138 for (i--; i >= 0; i--)
1139 devm_free_irq(host->dev, irq + i, host->ports[i]);
1140
1141 return rc;
1142 }
1143
1144 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1145 {
1146 unsigned int board_id = ent->driver_data;
1147 struct ata_port_info pi = ahci_port_info[board_id];
1148 const struct ata_port_info *ppi[] = { &pi, NULL };
1149 struct device *dev = &pdev->dev;
1150 struct ahci_host_priv *hpriv;
1151 struct ata_host *host;
1152 int n_ports, n_msis, i, rc;
1153 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1154
1155 VPRINTK("ENTER\n");
1156
1157 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1158
1159 ata_print_version_once(&pdev->dev, DRV_VERSION);
1160
1161 /* The AHCI driver can only drive the SATA ports, the PATA driver
1162 can drive them all so if both drivers are selected make sure
1163 AHCI stays out of the way */
1164 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1165 return -ENODEV;
1166
1167 /*
1168 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1169 * ahci, use ata_generic instead.
1170 */
1171 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1172 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1173 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1174 pdev->subsystem_device == 0xcb89)
1175 return -ENODEV;
1176
1177 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1178 * At the moment, we can only use the AHCI mode. Let the users know
1179 * that for SAS drives they're out of luck.
1180 */
1181 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1182 dev_info(&pdev->dev,
1183 "PDC42819 can only drive SATA devices with this driver\n");
1184
1185 /* Both Connext and Enmotus devices use non-standard BARs */
1186 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1187 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1188 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1189 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1190
1191 /* acquire resources */
1192 rc = pcim_enable_device(pdev);
1193 if (rc)
1194 return rc;
1195
1196 /* AHCI controllers often implement SFF compatible interface.
1197 * Grab all PCI BARs just in case.
1198 */
1199 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1200 if (rc == -EBUSY)
1201 pcim_pin_device(pdev);
1202 if (rc)
1203 return rc;
1204
1205 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1206 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1207 u8 map;
1208
1209 /* ICH6s share the same PCI ID for both piix and ahci
1210 * modes. Enabling ahci mode while MAP indicates
1211 * combined mode is a bad idea. Yield to ata_piix.
1212 */
1213 pci_read_config_byte(pdev, ICH_MAP, &map);
1214 if (map & 0x3) {
1215 dev_info(&pdev->dev,
1216 "controller is in combined mode, can't enable AHCI mode\n");
1217 return -ENODEV;
1218 }
1219 }
1220
1221 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1222 if (!hpriv)
1223 return -ENOMEM;
1224 hpriv->flags |= (unsigned long)pi.private_data;
1225
1226 /* MCP65 revision A1 and A2 can't do MSI */
1227 if (board_id == board_ahci_mcp65 &&
1228 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1229 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1230
1231 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1232 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1233 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1234
1235 /* only some SB600s can do 64bit DMA */
1236 if (ahci_sb600_enable_64bit(pdev))
1237 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1238
1239 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1240
1241 n_msis = ahci_init_interrupts(pdev, hpriv);
1242 if (n_msis > 1)
1243 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1244
1245 /* save initial config */
1246 ahci_pci_save_initial_config(pdev, hpriv);
1247
1248 /* prepare host */
1249 if (hpriv->cap & HOST_CAP_NCQ) {
1250 pi.flags |= ATA_FLAG_NCQ;
1251 /*
1252 * Auto-activate optimization is supposed to be
1253 * supported on all AHCI controllers indicating NCQ
1254 * capability, but it seems to be broken on some
1255 * chipsets including NVIDIAs.
1256 */
1257 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1258 pi.flags |= ATA_FLAG_FPDMA_AA;
1259 }
1260
1261 if (hpriv->cap & HOST_CAP_PMP)
1262 pi.flags |= ATA_FLAG_PMP;
1263
1264 ahci_set_em_messages(hpriv, &pi);
1265
1266 if (ahci_broken_system_poweroff(pdev)) {
1267 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1268 dev_info(&pdev->dev,
1269 "quirky BIOS, skipping spindown on poweroff\n");
1270 }
1271
1272 if (ahci_broken_suspend(pdev)) {
1273 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1274 dev_warn(&pdev->dev,
1275 "BIOS update required for suspend/resume\n");
1276 }
1277
1278 if (ahci_broken_online(pdev)) {
1279 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1280 dev_info(&pdev->dev,
1281 "online status unreliable, applying workaround\n");
1282 }
1283
1284 /* CAP.NP sometimes indicate the index of the last enabled
1285 * port, at other times, that of the last possible port, so
1286 * determining the maximum port number requires looking at
1287 * both CAP.NP and port_map.
1288 */
1289 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1290
1291 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1292 if (!host)
1293 return -ENOMEM;
1294 host->private_data = hpriv;
1295
1296 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1297 host->flags |= ATA_HOST_PARALLEL_SCAN;
1298 else
1299 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1300
1301 if (pi.flags & ATA_FLAG_EM)
1302 ahci_reset_em(host);
1303
1304 for (i = 0; i < host->n_ports; i++) {
1305 struct ata_port *ap = host->ports[i];
1306
1307 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1308 ata_port_pbar_desc(ap, ahci_pci_bar,
1309 0x100 + ap->port_no * 0x80, "port");
1310
1311 /* set enclosure management message type */
1312 if (ap->flags & ATA_FLAG_EM)
1313 ap->em_message_type = hpriv->em_msg_type;
1314
1315
1316 /* disabled/not-implemented port */
1317 if (!(hpriv->port_map & (1 << i)))
1318 ap->ops = &ata_dummy_port_ops;
1319 }
1320
1321 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1322 ahci_p5wdh_workaround(host);
1323
1324 /* apply gtf filter quirk */
1325 ahci_gtf_filter_workaround(host);
1326
1327 /* initialize adapter */
1328 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1329 if (rc)
1330 return rc;
1331
1332 rc = ahci_pci_reset_controller(host);
1333 if (rc)
1334 return rc;
1335
1336 ahci_pci_init_controller(host);
1337 ahci_pci_print_info(host);
1338
1339 pci_set_master(pdev);
1340
1341 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1342 return ahci_host_activate(host, pdev->irq, n_msis);
1343
1344 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1345 &ahci_sht);
1346 }
1347
1348 module_pci_driver(ahci_pci_driver);
1349
1350 MODULE_AUTHOR("Jeff Garzik");
1351 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1352 MODULE_LICENSE("GPL");
1353 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1354 MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)