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Merge branch 'master' into next
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 };
57
58 enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
63 board_ahci_yes_fbs,
64
65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
67 board_ahci_mcp77,
68 board_ahci_mcp89,
69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
79 };
80
81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 #ifdef CONFIG_PM
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
91 #endif
92
93 static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95 };
96
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
100 };
101
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
105 };
106
107 static struct ata_port_operations ahci_sb600_ops = {
108 .inherits = &ahci_ops,
109 .softreset = ahci_sb600_softreset,
110 .pmp_softreset = ahci_sb600_softreset,
111 };
112
113 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114
115 static const struct ata_port_info ahci_port_info[] = {
116 /* by features */
117 [board_ahci] =
118 {
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
123 },
124 [board_ahci_ign_iferr] =
125 {
126 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_nosntf] =
133 {
134 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
140 [board_ahci_yes_fbs] =
141 {
142 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
147 },
148 /* by chipsets */
149 [board_ahci_mcp65] =
150 {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
152 AHCI_HFLAG_YES_NCQ),
153 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mcp77] =
159 {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_mcp89] =
167 {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_mv] =
175 {
176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
178 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
182 },
183 [board_ahci_sb600] =
184 {
185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
186 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187 AHCI_HFLAG_32BIT_ONLY),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_sb600_ops,
192 },
193 [board_ahci_sb700] = /* for SB700 and SB800 */
194 {
195 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_sb600_ops,
200 },
201 [board_ahci_vt8251] =
202 {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_vt8251_ops,
208 },
209 };
210
211 static const struct pci_device_id ahci_pci_tbl[] = {
212 /* Intel */
213 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
214 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
215 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
216 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
217 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
218 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
219 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
221 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
222 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
223 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
224 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
225 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
226 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
227 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
228 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
239 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
240 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
241 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
242 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
243 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
244 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
245 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
246 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
248 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
250 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
251 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
252 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
253 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
254 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
255 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
258 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
259 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
260 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
261 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
262 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
263 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
264 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
265 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
266 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
267 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
268 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
269 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
270
271 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
272 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
273 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
274
275 /* ATI */
276 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
277 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
278 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
280 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
281 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
282 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
283
284 /* AMD */
285 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
286 /* AMD is using RAID class only for ahci controllers */
287 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
288 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
289
290 /* VIA */
291 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
292 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
293
294 /* NVIDIA */
295 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
300 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
301 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
302 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
303 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
313 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
314 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
315 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
329 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
330 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
331 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
341 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
342 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
353 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
354 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
355 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
365 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
366 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
367 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
376 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
377 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
378 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
379
380 /* SiS */
381 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
382 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
383 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
384
385 /* Marvell */
386 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
387 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
388 { PCI_DEVICE(0x1b4b, 0x9123),
389 .class = PCI_CLASS_STORAGE_SATA_AHCI,
390 .class_mask = 0xffffff,
391 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
392 { PCI_DEVICE(0x1b4b, 0x9125),
393 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
394 { PCI_DEVICE(0x1b4b, 0x91a3),
395 .driver_data = board_ahci_yes_fbs },
396
397 /* Promise */
398 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
399
400 /* Generic, PCI class code for AHCI */
401 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
402 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
403
404 { } /* terminate list */
405 };
406
407
408 static struct pci_driver ahci_pci_driver = {
409 .name = DRV_NAME,
410 .id_table = ahci_pci_tbl,
411 .probe = ahci_init_one,
412 .remove = ata_pci_remove_one,
413 #ifdef CONFIG_PM
414 .suspend = ahci_pci_device_suspend,
415 .resume = ahci_pci_device_resume,
416 #endif
417 };
418
419 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
420 static int marvell_enable;
421 #else
422 static int marvell_enable = 1;
423 #endif
424 module_param(marvell_enable, int, 0644);
425 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
426
427
428 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
429 struct ahci_host_priv *hpriv)
430 {
431 unsigned int force_port_map = 0;
432 unsigned int mask_port_map = 0;
433
434 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
435 dev_info(&pdev->dev, "JMB361 has only one port\n");
436 force_port_map = 1;
437 }
438
439 /*
440 * Temporary Marvell 6145 hack: PATA port presence
441 * is asserted through the standard AHCI port
442 * presence register, as bit 4 (counting from 0)
443 */
444 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
445 if (pdev->device == 0x6121)
446 mask_port_map = 0x3;
447 else
448 mask_port_map = 0xf;
449 dev_info(&pdev->dev,
450 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
451 }
452
453 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
454 mask_port_map);
455 }
456
457 static int ahci_pci_reset_controller(struct ata_host *host)
458 {
459 struct pci_dev *pdev = to_pci_dev(host->dev);
460
461 ahci_reset_controller(host);
462
463 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
464 struct ahci_host_priv *hpriv = host->private_data;
465 u16 tmp16;
466
467 /* configure PCS */
468 pci_read_config_word(pdev, 0x92, &tmp16);
469 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
470 tmp16 |= hpriv->port_map;
471 pci_write_config_word(pdev, 0x92, tmp16);
472 }
473 }
474
475 return 0;
476 }
477
478 static void ahci_pci_init_controller(struct ata_host *host)
479 {
480 struct ahci_host_priv *hpriv = host->private_data;
481 struct pci_dev *pdev = to_pci_dev(host->dev);
482 void __iomem *port_mmio;
483 u32 tmp;
484 int mv;
485
486 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
487 if (pdev->device == 0x6121)
488 mv = 2;
489 else
490 mv = 4;
491 port_mmio = __ahci_port_base(host, mv);
492
493 writel(0, port_mmio + PORT_IRQ_MASK);
494
495 /* clear port IRQ */
496 tmp = readl(port_mmio + PORT_IRQ_STAT);
497 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
498 if (tmp)
499 writel(tmp, port_mmio + PORT_IRQ_STAT);
500 }
501
502 ahci_init_controller(host);
503 }
504
505 static int ahci_sb600_check_ready(struct ata_link *link)
506 {
507 void __iomem *port_mmio = ahci_port_base(link->ap);
508 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
509 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
510
511 /*
512 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
513 * which can save timeout delay.
514 */
515 if (irq_status & PORT_IRQ_BAD_PMP)
516 return -EIO;
517
518 return ata_check_ready(status);
519 }
520
521 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
522 unsigned long deadline)
523 {
524 struct ata_port *ap = link->ap;
525 void __iomem *port_mmio = ahci_port_base(ap);
526 int pmp = sata_srst_pmp(link);
527 int rc;
528 u32 irq_sts;
529
530 DPRINTK("ENTER\n");
531
532 rc = ahci_do_softreset(link, class, pmp, deadline,
533 ahci_sb600_check_ready);
534
535 /*
536 * Soft reset fails on some ATI chips with IPMS set when PMP
537 * is enabled but SATA HDD/ODD is connected to SATA port,
538 * do soft reset again to port 0.
539 */
540 if (rc == -EIO) {
541 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
542 if (irq_sts & PORT_IRQ_BAD_PMP) {
543 ata_link_printk(link, KERN_WARNING,
544 "applying SB600 PMP SRST workaround "
545 "and retrying\n");
546 rc = ahci_do_softreset(link, class, 0, deadline,
547 ahci_check_ready);
548 }
549 }
550
551 return rc;
552 }
553
554 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
555 unsigned long deadline)
556 {
557 struct ata_port *ap = link->ap;
558 bool online;
559 int rc;
560
561 DPRINTK("ENTER\n");
562
563 ahci_stop_engine(ap);
564
565 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
566 deadline, &online, NULL);
567
568 ahci_start_engine(ap);
569
570 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
571
572 /* vt8251 doesn't clear BSY on signature FIS reception,
573 * request follow-up softreset.
574 */
575 return online ? -EAGAIN : rc;
576 }
577
578 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
579 unsigned long deadline)
580 {
581 struct ata_port *ap = link->ap;
582 struct ahci_port_priv *pp = ap->private_data;
583 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
584 struct ata_taskfile tf;
585 bool online;
586 int rc;
587
588 ahci_stop_engine(ap);
589
590 /* clear D2H reception area to properly wait for D2H FIS */
591 ata_tf_init(link->device, &tf);
592 tf.command = 0x80;
593 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
594
595 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
596 deadline, &online, NULL);
597
598 ahci_start_engine(ap);
599
600 /* The pseudo configuration device on SIMG4726 attached to
601 * ASUS P5W-DH Deluxe doesn't send signature FIS after
602 * hardreset if no device is attached to the first downstream
603 * port && the pseudo device locks up on SRST w/ PMP==0. To
604 * work around this, wait for !BSY only briefly. If BSY isn't
605 * cleared, perform CLO and proceed to IDENTIFY (achieved by
606 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
607 *
608 * Wait for two seconds. Devices attached to downstream port
609 * which can't process the following IDENTIFY after this will
610 * have to be reset again. For most cases, this should
611 * suffice while making probing snappish enough.
612 */
613 if (online) {
614 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
615 ahci_check_ready);
616 if (rc)
617 ahci_kick_engine(ap);
618 }
619 return rc;
620 }
621
622 #ifdef CONFIG_PM
623 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
624 {
625 struct ata_host *host = dev_get_drvdata(&pdev->dev);
626 struct ahci_host_priv *hpriv = host->private_data;
627 void __iomem *mmio = hpriv->mmio;
628 u32 ctl;
629
630 if (mesg.event & PM_EVENT_SUSPEND &&
631 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
632 dev_printk(KERN_ERR, &pdev->dev,
633 "BIOS update required for suspend/resume\n");
634 return -EIO;
635 }
636
637 if (mesg.event & PM_EVENT_SLEEP) {
638 /* AHCI spec rev1.1 section 8.3.3:
639 * Software must disable interrupts prior to requesting a
640 * transition of the HBA to D3 state.
641 */
642 ctl = readl(mmio + HOST_CTL);
643 ctl &= ~HOST_IRQ_EN;
644 writel(ctl, mmio + HOST_CTL);
645 readl(mmio + HOST_CTL); /* flush */
646 }
647
648 return ata_pci_device_suspend(pdev, mesg);
649 }
650
651 static int ahci_pci_device_resume(struct pci_dev *pdev)
652 {
653 struct ata_host *host = dev_get_drvdata(&pdev->dev);
654 int rc;
655
656 rc = ata_pci_device_do_resume(pdev);
657 if (rc)
658 return rc;
659
660 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
661 rc = ahci_pci_reset_controller(host);
662 if (rc)
663 return rc;
664
665 ahci_pci_init_controller(host);
666 }
667
668 ata_host_resume(host);
669
670 return 0;
671 }
672 #endif
673
674 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
675 {
676 int rc;
677
678 if (using_dac &&
679 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
680 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
681 if (rc) {
682 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
683 if (rc) {
684 dev_printk(KERN_ERR, &pdev->dev,
685 "64-bit DMA enable failed\n");
686 return rc;
687 }
688 }
689 } else {
690 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
691 if (rc) {
692 dev_printk(KERN_ERR, &pdev->dev,
693 "32-bit DMA enable failed\n");
694 return rc;
695 }
696 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
697 if (rc) {
698 dev_printk(KERN_ERR, &pdev->dev,
699 "32-bit consistent DMA enable failed\n");
700 return rc;
701 }
702 }
703 return 0;
704 }
705
706 static void ahci_pci_print_info(struct ata_host *host)
707 {
708 struct pci_dev *pdev = to_pci_dev(host->dev);
709 u16 cc;
710 const char *scc_s;
711
712 pci_read_config_word(pdev, 0x0a, &cc);
713 if (cc == PCI_CLASS_STORAGE_IDE)
714 scc_s = "IDE";
715 else if (cc == PCI_CLASS_STORAGE_SATA)
716 scc_s = "SATA";
717 else if (cc == PCI_CLASS_STORAGE_RAID)
718 scc_s = "RAID";
719 else
720 scc_s = "unknown";
721
722 ahci_print_info(host, scc_s);
723 }
724
725 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
726 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
727 * support PMP and the 4726 either directly exports the device
728 * attached to the first downstream port or acts as a hardware storage
729 * controller and emulate a single ATA device (can be RAID 0/1 or some
730 * other configuration).
731 *
732 * When there's no device attached to the first downstream port of the
733 * 4726, "Config Disk" appears, which is a pseudo ATA device to
734 * configure the 4726. However, ATA emulation of the device is very
735 * lame. It doesn't send signature D2H Reg FIS after the initial
736 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
737 *
738 * The following function works around the problem by always using
739 * hardreset on the port and not depending on receiving signature FIS
740 * afterward. If signature FIS isn't received soon, ATA class is
741 * assumed without follow-up softreset.
742 */
743 static void ahci_p5wdh_workaround(struct ata_host *host)
744 {
745 static struct dmi_system_id sysids[] = {
746 {
747 .ident = "P5W DH Deluxe",
748 .matches = {
749 DMI_MATCH(DMI_SYS_VENDOR,
750 "ASUSTEK COMPUTER INC"),
751 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
752 },
753 },
754 { }
755 };
756 struct pci_dev *pdev = to_pci_dev(host->dev);
757
758 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
759 dmi_check_system(sysids)) {
760 struct ata_port *ap = host->ports[1];
761
762 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
763 "Deluxe on-board SIMG4726 workaround\n");
764
765 ap->ops = &ahci_p5wdh_ops;
766 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
767 }
768 }
769
770 /* only some SB600 ahci controllers can do 64bit DMA */
771 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
772 {
773 static const struct dmi_system_id sysids[] = {
774 /*
775 * The oldest version known to be broken is 0901 and
776 * working is 1501 which was released on 2007-10-26.
777 * Enable 64bit DMA on 1501 and anything newer.
778 *
779 * Please read bko#9412 for more info.
780 */
781 {
782 .ident = "ASUS M2A-VM",
783 .matches = {
784 DMI_MATCH(DMI_BOARD_VENDOR,
785 "ASUSTeK Computer INC."),
786 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
787 },
788 .driver_data = "20071026", /* yyyymmdd */
789 },
790 /*
791 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
792 * support 64bit DMA.
793 *
794 * BIOS versions earlier than 1.5 had the Manufacturer DMI
795 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
796 * This spelling mistake was fixed in BIOS version 1.5, so
797 * 1.5 and later have the Manufacturer as
798 * "MICRO-STAR INTERNATIONAL CO.,LTD".
799 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
800 *
801 * BIOS versions earlier than 1.9 had a Board Product Name
802 * DMI field of "MS-7376". This was changed to be
803 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
804 * match on DMI_BOARD_NAME of "MS-7376".
805 */
806 {
807 .ident = "MSI K9A2 Platinum",
808 .matches = {
809 DMI_MATCH(DMI_BOARD_VENDOR,
810 "MICRO-STAR INTER"),
811 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
812 },
813 },
814 { }
815 };
816 const struct dmi_system_id *match;
817 int year, month, date;
818 char buf[9];
819
820 match = dmi_first_match(sysids);
821 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
822 !match)
823 return false;
824
825 if (!match->driver_data)
826 goto enable_64bit;
827
828 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
829 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
830
831 if (strcmp(buf, match->driver_data) >= 0)
832 goto enable_64bit;
833 else {
834 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
835 "forcing 32bit DMA, update BIOS\n", match->ident);
836 return false;
837 }
838
839 enable_64bit:
840 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
841 match->ident);
842 return true;
843 }
844
845 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
846 {
847 static const struct dmi_system_id broken_systems[] = {
848 {
849 .ident = "HP Compaq nx6310",
850 .matches = {
851 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
852 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
853 },
854 /* PCI slot number of the controller */
855 .driver_data = (void *)0x1FUL,
856 },
857 {
858 .ident = "HP Compaq 6720s",
859 .matches = {
860 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
861 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
862 },
863 /* PCI slot number of the controller */
864 .driver_data = (void *)0x1FUL,
865 },
866
867 { } /* terminate list */
868 };
869 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
870
871 if (dmi) {
872 unsigned long slot = (unsigned long)dmi->driver_data;
873 /* apply the quirk only to on-board controllers */
874 return slot == PCI_SLOT(pdev->devfn);
875 }
876
877 return false;
878 }
879
880 static bool ahci_broken_suspend(struct pci_dev *pdev)
881 {
882 static const struct dmi_system_id sysids[] = {
883 /*
884 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
885 * to the harddisk doesn't become online after
886 * resuming from STR. Warn and fail suspend.
887 *
888 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
889 *
890 * Use dates instead of versions to match as HP is
891 * apparently recycling both product and version
892 * strings.
893 *
894 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
895 */
896 {
897 .ident = "dv4",
898 .matches = {
899 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
900 DMI_MATCH(DMI_PRODUCT_NAME,
901 "HP Pavilion dv4 Notebook PC"),
902 },
903 .driver_data = "20090105", /* F.30 */
904 },
905 {
906 .ident = "dv5",
907 .matches = {
908 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
909 DMI_MATCH(DMI_PRODUCT_NAME,
910 "HP Pavilion dv5 Notebook PC"),
911 },
912 .driver_data = "20090506", /* F.16 */
913 },
914 {
915 .ident = "dv6",
916 .matches = {
917 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
918 DMI_MATCH(DMI_PRODUCT_NAME,
919 "HP Pavilion dv6 Notebook PC"),
920 },
921 .driver_data = "20090423", /* F.21 */
922 },
923 {
924 .ident = "HDX18",
925 .matches = {
926 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
927 DMI_MATCH(DMI_PRODUCT_NAME,
928 "HP HDX18 Notebook PC"),
929 },
930 .driver_data = "20090430", /* F.23 */
931 },
932 /*
933 * Acer eMachines G725 has the same problem. BIOS
934 * V1.03 is known to be broken. V3.04 is known to
935 * work. Between, there are V1.06, V2.06 and V3.03
936 * that we don't have much idea about. For now,
937 * blacklist anything older than V3.04.
938 *
939 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
940 */
941 {
942 .ident = "G725",
943 .matches = {
944 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
945 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
946 },
947 .driver_data = "20091216", /* V3.04 */
948 },
949 { } /* terminate list */
950 };
951 const struct dmi_system_id *dmi = dmi_first_match(sysids);
952 int year, month, date;
953 char buf[9];
954
955 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
956 return false;
957
958 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
959 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
960
961 return strcmp(buf, dmi->driver_data) < 0;
962 }
963
964 static bool ahci_broken_online(struct pci_dev *pdev)
965 {
966 #define ENCODE_BUSDEVFN(bus, slot, func) \
967 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
968 static const struct dmi_system_id sysids[] = {
969 /*
970 * There are several gigabyte boards which use
971 * SIMG5723s configured as hardware RAID. Certain
972 * 5723 firmware revisions shipped there keep the link
973 * online but fail to answer properly to SRST or
974 * IDENTIFY when no device is attached downstream
975 * causing libata to retry quite a few times leading
976 * to excessive detection delay.
977 *
978 * As these firmwares respond to the second reset try
979 * with invalid device signature, considering unknown
980 * sig as offline works around the problem acceptably.
981 */
982 {
983 .ident = "EP45-DQ6",
984 .matches = {
985 DMI_MATCH(DMI_BOARD_VENDOR,
986 "Gigabyte Technology Co., Ltd."),
987 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
988 },
989 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
990 },
991 {
992 .ident = "EP45-DS5",
993 .matches = {
994 DMI_MATCH(DMI_BOARD_VENDOR,
995 "Gigabyte Technology Co., Ltd."),
996 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
997 },
998 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
999 },
1000 { } /* terminate list */
1001 };
1002 #undef ENCODE_BUSDEVFN
1003 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1004 unsigned int val;
1005
1006 if (!dmi)
1007 return false;
1008
1009 val = (unsigned long)dmi->driver_data;
1010
1011 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1012 }
1013
1014 #ifdef CONFIG_ATA_ACPI
1015 static void ahci_gtf_filter_workaround(struct ata_host *host)
1016 {
1017 static const struct dmi_system_id sysids[] = {
1018 /*
1019 * Aspire 3810T issues a bunch of SATA enable commands
1020 * via _GTF including an invalid one and one which is
1021 * rejected by the device. Among the successful ones
1022 * is FPDMA non-zero offset enable which when enabled
1023 * only on the drive side leads to NCQ command
1024 * failures. Filter it out.
1025 */
1026 {
1027 .ident = "Aspire 3810T",
1028 .matches = {
1029 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1030 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1031 },
1032 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1033 },
1034 { }
1035 };
1036 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1037 unsigned int filter;
1038 int i;
1039
1040 if (!dmi)
1041 return;
1042
1043 filter = (unsigned long)dmi->driver_data;
1044 dev_printk(KERN_INFO, host->dev,
1045 "applying extra ACPI _GTF filter 0x%x for %s\n",
1046 filter, dmi->ident);
1047
1048 for (i = 0; i < host->n_ports; i++) {
1049 struct ata_port *ap = host->ports[i];
1050 struct ata_link *link;
1051 struct ata_device *dev;
1052
1053 ata_for_each_link(link, ap, EDGE)
1054 ata_for_each_dev(dev, link, ALL)
1055 dev->gtf_filter |= filter;
1056 }
1057 }
1058 #else
1059 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1060 {}
1061 #endif
1062
1063 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1064 {
1065 static int printed_version;
1066 unsigned int board_id = ent->driver_data;
1067 struct ata_port_info pi = ahci_port_info[board_id];
1068 const struct ata_port_info *ppi[] = { &pi, NULL };
1069 struct device *dev = &pdev->dev;
1070 struct ahci_host_priv *hpriv;
1071 struct ata_host *host;
1072 int n_ports, i, rc;
1073
1074 VPRINTK("ENTER\n");
1075
1076 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1077
1078 if (!printed_version++)
1079 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1080
1081 /* The AHCI driver can only drive the SATA ports, the PATA driver
1082 can drive them all so if both drivers are selected make sure
1083 AHCI stays out of the way */
1084 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1085 return -ENODEV;
1086
1087 /*
1088 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1089 * ahci, use ata_generic instead.
1090 */
1091 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1092 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1093 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1094 pdev->subsystem_device == 0xcb89)
1095 return -ENODEV;
1096
1097 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1098 * At the moment, we can only use the AHCI mode. Let the users know
1099 * that for SAS drives they're out of luck.
1100 */
1101 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1102 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1103 "can only drive SATA devices with this driver\n");
1104
1105 /* acquire resources */
1106 rc = pcim_enable_device(pdev);
1107 if (rc)
1108 return rc;
1109
1110 /* AHCI controllers often implement SFF compatible interface.
1111 * Grab all PCI BARs just in case.
1112 */
1113 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1114 if (rc == -EBUSY)
1115 pcim_pin_device(pdev);
1116 if (rc)
1117 return rc;
1118
1119 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1120 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1121 u8 map;
1122
1123 /* ICH6s share the same PCI ID for both piix and ahci
1124 * modes. Enabling ahci mode while MAP indicates
1125 * combined mode is a bad idea. Yield to ata_piix.
1126 */
1127 pci_read_config_byte(pdev, ICH_MAP, &map);
1128 if (map & 0x3) {
1129 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1130 "combined mode, can't enable AHCI mode\n");
1131 return -ENODEV;
1132 }
1133 }
1134
1135 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1136 if (!hpriv)
1137 return -ENOMEM;
1138 hpriv->flags |= (unsigned long)pi.private_data;
1139
1140 /* MCP65 revision A1 and A2 can't do MSI */
1141 if (board_id == board_ahci_mcp65 &&
1142 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1143 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1144
1145 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1146 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1147 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1148
1149 /* only some SB600s can do 64bit DMA */
1150 if (ahci_sb600_enable_64bit(pdev))
1151 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1152
1153 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1154 pci_intx(pdev, 1);
1155
1156 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1157
1158 /* save initial config */
1159 ahci_pci_save_initial_config(pdev, hpriv);
1160
1161 /* prepare host */
1162 if (hpriv->cap & HOST_CAP_NCQ) {
1163 pi.flags |= ATA_FLAG_NCQ;
1164 /*
1165 * Auto-activate optimization is supposed to be
1166 * supported on all AHCI controllers indicating NCQ
1167 * capability, but it seems to be broken on some
1168 * chipsets including NVIDIAs.
1169 */
1170 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1171 pi.flags |= ATA_FLAG_FPDMA_AA;
1172 }
1173
1174 if (hpriv->cap & HOST_CAP_PMP)
1175 pi.flags |= ATA_FLAG_PMP;
1176
1177 ahci_set_em_messages(hpriv, &pi);
1178
1179 if (ahci_broken_system_poweroff(pdev)) {
1180 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1181 dev_info(&pdev->dev,
1182 "quirky BIOS, skipping spindown on poweroff\n");
1183 }
1184
1185 if (ahci_broken_suspend(pdev)) {
1186 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1187 dev_printk(KERN_WARNING, &pdev->dev,
1188 "BIOS update required for suspend/resume\n");
1189 }
1190
1191 if (ahci_broken_online(pdev)) {
1192 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1193 dev_info(&pdev->dev,
1194 "online status unreliable, applying workaround\n");
1195 }
1196
1197 /* CAP.NP sometimes indicate the index of the last enabled
1198 * port, at other times, that of the last possible port, so
1199 * determining the maximum port number requires looking at
1200 * both CAP.NP and port_map.
1201 */
1202 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1203
1204 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1205 if (!host)
1206 return -ENOMEM;
1207 host->private_data = hpriv;
1208
1209 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1210 host->flags |= ATA_HOST_PARALLEL_SCAN;
1211 else
1212 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1213
1214 if (pi.flags & ATA_FLAG_EM)
1215 ahci_reset_em(host);
1216
1217 for (i = 0; i < host->n_ports; i++) {
1218 struct ata_port *ap = host->ports[i];
1219
1220 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1221 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1222 0x100 + ap->port_no * 0x80, "port");
1223
1224 /* set enclosure management message type */
1225 if (ap->flags & ATA_FLAG_EM)
1226 ap->em_message_type = hpriv->em_msg_type;
1227
1228
1229 /* disabled/not-implemented port */
1230 if (!(hpriv->port_map & (1 << i)))
1231 ap->ops = &ata_dummy_port_ops;
1232 }
1233
1234 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1235 ahci_p5wdh_workaround(host);
1236
1237 /* apply gtf filter quirk */
1238 ahci_gtf_filter_workaround(host);
1239
1240 /* initialize adapter */
1241 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1242 if (rc)
1243 return rc;
1244
1245 rc = ahci_pci_reset_controller(host);
1246 if (rc)
1247 return rc;
1248
1249 ahci_pci_init_controller(host);
1250 ahci_pci_print_info(host);
1251
1252 pci_set_master(pdev);
1253 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1254 &ahci_sht);
1255 }
1256
1257 static int __init ahci_init(void)
1258 {
1259 return pci_register_driver(&ahci_pci_driver);
1260 }
1261
1262 static void __exit ahci_exit(void)
1263 {
1264 pci_unregister_driver(&ahci_pci_driver);
1265 }
1266
1267
1268 MODULE_AUTHOR("Jeff Garzik");
1269 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1270 MODULE_LICENSE("GPL");
1271 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1272 MODULE_VERSION(DRV_VERSION);
1273
1274 module_init(ahci_init);
1275 module_exit(ahci_exit);
kernel source for telekom puls (alcatel/mediatek)