ACPI: idle: rename lapic timer workaround routines
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / acpi / processor_idle.c
1 /*
2 * processor_idle - idle state submodule to the ACPI processor driver
3 *
4 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
5 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
6 * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de>
7 * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
8 * - Added processor hotplug support
9 * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
10 * - Added support for C3 on SMP
11 *
12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or (at
17 * your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22 * General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 *
28 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
29 */
30
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/init.h>
34 #include <linux/cpufreq.h>
35 #include <linux/proc_fs.h>
36 #include <linux/seq_file.h>
37 #include <linux/acpi.h>
38 #include <linux/dmi.h>
39 #include <linux/moduleparam.h>
40 #include <linux/sched.h> /* need_resched() */
41 #include <linux/pm_qos_params.h>
42 #include <linux/clockchips.h>
43 #include <linux/cpuidle.h>
44 #include <linux/irqflags.h>
45
46 /*
47 * Include the apic definitions for x86 to have the APIC timer related defines
48 * available also for UP (on SMP it gets magically included via linux/smp.h).
49 * asm/acpi.h is not an option, as it would require more include magic. Also
50 * creating an empty asm-ia64/apic.h would just trade pest vs. cholera.
51 */
52 #ifdef CONFIG_X86
53 #include <asm/apic.h>
54 #endif
55
56 #include <asm/io.h>
57 #include <asm/uaccess.h>
58
59 #include <acpi/acpi_bus.h>
60 #include <acpi/processor.h>
61 #include <asm/processor.h>
62
63 #define ACPI_PROCESSOR_CLASS "processor"
64 #define _COMPONENT ACPI_PROCESSOR_COMPONENT
65 ACPI_MODULE_NAME("processor_idle");
66 #define ACPI_PROCESSOR_FILE_POWER "power"
67 #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY)
68 #define C2_OVERHEAD 1 /* 1us */
69 #define C3_OVERHEAD 1 /* 1us */
70 #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000))
71
72 static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER;
73 module_param(max_cstate, uint, 0000);
74 static unsigned int nocst __read_mostly;
75 module_param(nocst, uint, 0000);
76
77 static unsigned int latency_factor __read_mostly = 2;
78 module_param(latency_factor, uint, 0644);
79
80 static s64 us_to_pm_timer_ticks(s64 t)
81 {
82 return div64_u64(t * PM_TIMER_FREQUENCY, 1000000);
83 }
84 /*
85 * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3.
86 * For now disable this. Probably a bug somewhere else.
87 *
88 * To skip this limit, boot/load with a large max_cstate limit.
89 */
90 static int set_max_cstate(const struct dmi_system_id *id)
91 {
92 if (max_cstate > ACPI_PROCESSOR_MAX_POWER)
93 return 0;
94
95 printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate."
96 " Override with \"processor.max_cstate=%d\"\n", id->ident,
97 (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1);
98
99 max_cstate = (long)id->driver_data;
100
101 return 0;
102 }
103
104 /* Actually this shouldn't be __cpuinitdata, would be better to fix the
105 callers to only run once -AK */
106 static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = {
107 { set_max_cstate, "Clevo 5600D", {
108 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
109 DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")},
110 (void *)2},
111 {},
112 };
113
114
115 /*
116 * Callers should disable interrupts before the call and enable
117 * interrupts after return.
118 */
119 static void acpi_safe_halt(void)
120 {
121 current_thread_info()->status &= ~TS_POLLING;
122 /*
123 * TS_POLLING-cleared state must be visible before we
124 * test NEED_RESCHED:
125 */
126 smp_mb();
127 if (!need_resched()) {
128 safe_halt();
129 local_irq_disable();
130 }
131 current_thread_info()->status |= TS_POLLING;
132 }
133
134 #ifdef ARCH_APICTIMER_STOPS_ON_C3
135
136 /*
137 * Some BIOS implementations switch to C3 in the published C2 state.
138 * This seems to be a common problem on AMD boxen, but other vendors
139 * are affected too. We pick the most conservative approach: we assume
140 * that the local APIC stops in both C2 and C3.
141 */
142 static void lapic_timer_check_state(int state, struct acpi_processor *pr,
143 struct acpi_processor_cx *cx)
144 {
145 struct acpi_processor_power *pwr = &pr->power;
146 u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2;
147
148 if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT))
149 return;
150
151 if (boot_cpu_has(X86_FEATURE_AMDC1E))
152 type = ACPI_STATE_C1;
153
154 /*
155 * Check, if one of the previous states already marked the lapic
156 * unstable
157 */
158 if (pwr->timer_broadcast_on_state < state)
159 return;
160
161 if (cx->type >= type)
162 pr->power.timer_broadcast_on_state = state;
163 }
164
165 static void lapic_timer_propagate_broadcast(struct acpi_processor *pr)
166 {
167 unsigned long reason;
168
169 reason = pr->power.timer_broadcast_on_state < INT_MAX ?
170 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
171
172 clockevents_notify(reason, &pr->id);
173 }
174
175 /* Power(C) State timer broadcast control */
176 static void lapic_timer_state_broadcast(struct acpi_processor *pr,
177 struct acpi_processor_cx *cx,
178 int broadcast)
179 {
180 int state = cx - pr->power.states;
181
182 if (state >= pr->power.timer_broadcast_on_state) {
183 unsigned long reason;
184
185 reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER :
186 CLOCK_EVT_NOTIFY_BROADCAST_EXIT;
187 clockevents_notify(reason, &pr->id);
188 }
189 }
190
191 #else
192
193 static void lapic_timer_check_state(int state, struct acpi_processor *pr,
194 struct acpi_processor_cx *cstate) { }
195 static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { }
196 static void lapic_timer_state_broadcast(struct acpi_processor *pr,
197 struct acpi_processor_cx *cx,
198 int broadcast)
199 {
200 }
201
202 #endif
203
204 /*
205 * Suspend / resume control
206 */
207 static int acpi_idle_suspend;
208 static u32 saved_bm_rld;
209
210 static void acpi_idle_bm_rld_save(void)
211 {
212 acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld);
213 }
214 static void acpi_idle_bm_rld_restore(void)
215 {
216 u32 resumed_bm_rld;
217
218 acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &resumed_bm_rld);
219
220 if (resumed_bm_rld != saved_bm_rld)
221 acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld);
222 }
223
224 int acpi_processor_suspend(struct acpi_device * device, pm_message_t state)
225 {
226 if (acpi_idle_suspend == 1)
227 return 0;
228
229 acpi_idle_bm_rld_save();
230 acpi_idle_suspend = 1;
231 return 0;
232 }
233
234 int acpi_processor_resume(struct acpi_device * device)
235 {
236 if (acpi_idle_suspend == 0)
237 return 0;
238
239 acpi_idle_bm_rld_restore();
240 acpi_idle_suspend = 0;
241 return 0;
242 }
243
244 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
245 static void tsc_check_state(int state)
246 {
247 switch (boot_cpu_data.x86_vendor) {
248 case X86_VENDOR_AMD:
249 case X86_VENDOR_INTEL:
250 /*
251 * AMD Fam10h TSC will tick in all
252 * C/P/S0/S1 states when this bit is set.
253 */
254 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
255 return;
256
257 /*FALL THROUGH*/
258 default:
259 /* TSC could halt in idle, so notify users */
260 if (state > ACPI_STATE_C1)
261 mark_tsc_unstable("TSC halts in idle");
262 }
263 }
264 #else
265 static void tsc_check_state(int state) { return; }
266 #endif
267
268 static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
269 {
270
271 if (!pr)
272 return -EINVAL;
273
274 if (!pr->pblk)
275 return -ENODEV;
276
277 /* if info is obtained from pblk/fadt, type equals state */
278 pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2;
279 pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3;
280
281 #ifndef CONFIG_HOTPLUG_CPU
282 /*
283 * Check for P_LVL2_UP flag before entering C2 and above on
284 * an SMP system.
285 */
286 if ((num_online_cpus() > 1) &&
287 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
288 return -ENODEV;
289 #endif
290
291 /* determine C2 and C3 address from pblk */
292 pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4;
293 pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5;
294
295 /* determine latencies from FADT */
296 pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency;
297 pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency;
298
299 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
300 "lvl2[0x%08x] lvl3[0x%08x]\n",
301 pr->power.states[ACPI_STATE_C2].address,
302 pr->power.states[ACPI_STATE_C3].address));
303
304 return 0;
305 }
306
307 static int acpi_processor_get_power_info_default(struct acpi_processor *pr)
308 {
309 if (!pr->power.states[ACPI_STATE_C1].valid) {
310 /* set the first C-State to C1 */
311 /* all processors need to support C1 */
312 pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1;
313 pr->power.states[ACPI_STATE_C1].valid = 1;
314 pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT;
315 }
316 /* the C0 state only exists as a filler in our array */
317 pr->power.states[ACPI_STATE_C0].valid = 1;
318 return 0;
319 }
320
321 static int acpi_processor_get_power_info_cst(struct acpi_processor *pr)
322 {
323 acpi_status status = 0;
324 acpi_integer count;
325 int current_count;
326 int i;
327 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
328 union acpi_object *cst;
329
330
331 if (nocst)
332 return -ENODEV;
333
334 current_count = 0;
335
336 status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer);
337 if (ACPI_FAILURE(status)) {
338 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n"));
339 return -ENODEV;
340 }
341
342 cst = buffer.pointer;
343
344 /* There must be at least 2 elements */
345 if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) {
346 printk(KERN_ERR PREFIX "not enough elements in _CST\n");
347 status = -EFAULT;
348 goto end;
349 }
350
351 count = cst->package.elements[0].integer.value;
352
353 /* Validate number of power states. */
354 if (count < 1 || count != cst->package.count - 1) {
355 printk(KERN_ERR PREFIX "count given by _CST is not valid\n");
356 status = -EFAULT;
357 goto end;
358 }
359
360 /* Tell driver that at least _CST is supported. */
361 pr->flags.has_cst = 1;
362
363 for (i = 1; i <= count; i++) {
364 union acpi_object *element;
365 union acpi_object *obj;
366 struct acpi_power_register *reg;
367 struct acpi_processor_cx cx;
368
369 memset(&cx, 0, sizeof(cx));
370
371 element = &(cst->package.elements[i]);
372 if (element->type != ACPI_TYPE_PACKAGE)
373 continue;
374
375 if (element->package.count != 4)
376 continue;
377
378 obj = &(element->package.elements[0]);
379
380 if (obj->type != ACPI_TYPE_BUFFER)
381 continue;
382
383 reg = (struct acpi_power_register *)obj->buffer.pointer;
384
385 if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO &&
386 (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE))
387 continue;
388
389 /* There should be an easy way to extract an integer... */
390 obj = &(element->package.elements[1]);
391 if (obj->type != ACPI_TYPE_INTEGER)
392 continue;
393
394 cx.type = obj->integer.value;
395 /*
396 * Some buggy BIOSes won't list C1 in _CST -
397 * Let acpi_processor_get_power_info_default() handle them later
398 */
399 if (i == 1 && cx.type != ACPI_STATE_C1)
400 current_count++;
401
402 cx.address = reg->address;
403 cx.index = current_count + 1;
404
405 cx.entry_method = ACPI_CSTATE_SYSTEMIO;
406 if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) {
407 if (acpi_processor_ffh_cstate_probe
408 (pr->id, &cx, reg) == 0) {
409 cx.entry_method = ACPI_CSTATE_FFH;
410 } else if (cx.type == ACPI_STATE_C1) {
411 /*
412 * C1 is a special case where FIXED_HARDWARE
413 * can be handled in non-MWAIT way as well.
414 * In that case, save this _CST entry info.
415 * Otherwise, ignore this info and continue.
416 */
417 cx.entry_method = ACPI_CSTATE_HALT;
418 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT");
419 } else {
420 continue;
421 }
422 if (cx.type == ACPI_STATE_C1 &&
423 (idle_halt || idle_nomwait)) {
424 /*
425 * In most cases the C1 space_id obtained from
426 * _CST object is FIXED_HARDWARE access mode.
427 * But when the option of idle=halt is added,
428 * the entry_method type should be changed from
429 * CSTATE_FFH to CSTATE_HALT.
430 * When the option of idle=nomwait is added,
431 * the C1 entry_method type should be
432 * CSTATE_HALT.
433 */
434 cx.entry_method = ACPI_CSTATE_HALT;
435 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT");
436 }
437 } else {
438 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x",
439 cx.address);
440 }
441
442 if (cx.type == ACPI_STATE_C1) {
443 cx.valid = 1;
444 }
445
446 obj = &(element->package.elements[2]);
447 if (obj->type != ACPI_TYPE_INTEGER)
448 continue;
449
450 cx.latency = obj->integer.value;
451
452 obj = &(element->package.elements[3]);
453 if (obj->type != ACPI_TYPE_INTEGER)
454 continue;
455
456 cx.power = obj->integer.value;
457
458 current_count++;
459 memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx));
460
461 /*
462 * We support total ACPI_PROCESSOR_MAX_POWER - 1
463 * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1)
464 */
465 if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) {
466 printk(KERN_WARNING
467 "Limiting number of power states to max (%d)\n",
468 ACPI_PROCESSOR_MAX_POWER);
469 printk(KERN_WARNING
470 "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n");
471 break;
472 }
473 }
474
475 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n",
476 current_count));
477
478 /* Validate number of power states discovered */
479 if (current_count < 2)
480 status = -EFAULT;
481
482 end:
483 kfree(buffer.pointer);
484
485 return status;
486 }
487
488 static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx)
489 {
490
491 if (!cx->address)
492 return;
493
494 /*
495 * C2 latency must be less than or equal to 100
496 * microseconds.
497 */
498 else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) {
499 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
500 "latency too large [%d]\n", cx->latency));
501 return;
502 }
503
504 /*
505 * Otherwise we've met all of our C2 requirements.
506 * Normalize the C2 latency to expidite policy
507 */
508 cx->valid = 1;
509
510 cx->latency_ticks = cx->latency;
511
512 return;
513 }
514
515 static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
516 struct acpi_processor_cx *cx)
517 {
518 static int bm_check_flag;
519
520
521 if (!cx->address)
522 return;
523
524 /*
525 * C3 latency must be less than or equal to 1000
526 * microseconds.
527 */
528 else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) {
529 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
530 "latency too large [%d]\n", cx->latency));
531 return;
532 }
533
534 /*
535 * PIIX4 Erratum #18: We don't support C3 when Type-F (fast)
536 * DMA transfers are used by any ISA device to avoid livelock.
537 * Note that we could disable Type-F DMA (as recommended by
538 * the erratum), but this is known to disrupt certain ISA
539 * devices thus we take the conservative approach.
540 */
541 else if (errata.piix4.fdma) {
542 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
543 "C3 not supported on PIIX4 with Type-F DMA\n"));
544 return;
545 }
546
547 /* All the logic here assumes flags.bm_check is same across all CPUs */
548 if (!bm_check_flag) {
549 /* Determine whether bm_check is needed based on CPU */
550 acpi_processor_power_init_bm_check(&(pr->flags), pr->id);
551 bm_check_flag = pr->flags.bm_check;
552 } else {
553 pr->flags.bm_check = bm_check_flag;
554 }
555
556 if (pr->flags.bm_check) {
557 if (!pr->flags.bm_control) {
558 if (pr->flags.has_cst != 1) {
559 /* bus mastering control is necessary */
560 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
561 "C3 support requires BM control\n"));
562 return;
563 } else {
564 /* Here we enter C3 without bus mastering */
565 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
566 "C3 support without BM control\n"));
567 }
568 }
569 } else {
570 /*
571 * WBINVD should be set in fadt, for C3 state to be
572 * supported on when bm_check is not required.
573 */
574 if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) {
575 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
576 "Cache invalidation should work properly"
577 " for C3 to be enabled on SMP systems\n"));
578 return;
579 }
580 }
581
582 /*
583 * Otherwise we've met all of our C3 requirements.
584 * Normalize the C3 latency to expidite policy. Enable
585 * checking of bus mastering status (bm_check) so we can
586 * use this in our C3 policy
587 */
588 cx->valid = 1;
589
590 cx->latency_ticks = cx->latency;
591 /*
592 * On older chipsets, BM_RLD needs to be set
593 * in order for Bus Master activity to wake the
594 * system from C3. Newer chipsets handle DMA
595 * during C3 automatically and BM_RLD is a NOP.
596 * In either case, the proper way to
597 * handle BM_RLD is to set it and leave it set.
598 */
599 acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1);
600
601 return;
602 }
603
604 static int acpi_processor_power_verify(struct acpi_processor *pr)
605 {
606 unsigned int i;
607 unsigned int working = 0;
608
609 pr->power.timer_broadcast_on_state = INT_MAX;
610
611 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) {
612 struct acpi_processor_cx *cx = &pr->power.states[i];
613
614 switch (cx->type) {
615 case ACPI_STATE_C1:
616 cx->valid = 1;
617 break;
618
619 case ACPI_STATE_C2:
620 acpi_processor_power_verify_c2(cx);
621 break;
622
623 case ACPI_STATE_C3:
624 acpi_processor_power_verify_c3(pr, cx);
625 break;
626 }
627 if (!cx->valid)
628 continue;
629
630 lapic_timer_check_state(i, pr, cx);
631 tsc_check_state(cx->type);
632 working++;
633 }
634
635 lapic_timer_propagate_broadcast(pr);
636
637 return (working);
638 }
639
640 static int acpi_processor_get_power_info(struct acpi_processor *pr)
641 {
642 unsigned int i;
643 int result;
644
645
646 /* NOTE: the idle thread may not be running while calling
647 * this function */
648
649 /* Zero initialize all the C-states info. */
650 memset(pr->power.states, 0, sizeof(pr->power.states));
651
652 result = acpi_processor_get_power_info_cst(pr);
653 if (result == -ENODEV)
654 result = acpi_processor_get_power_info_fadt(pr);
655
656 if (result)
657 return result;
658
659 acpi_processor_get_power_info_default(pr);
660
661 pr->power.count = acpi_processor_power_verify(pr);
662
663 /*
664 * if one state of type C2 or C3 is available, mark this
665 * CPU as being "idle manageable"
666 */
667 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
668 if (pr->power.states[i].valid) {
669 pr->power.count = i;
670 if (pr->power.states[i].type >= ACPI_STATE_C2)
671 pr->flags.power = 1;
672 }
673 }
674
675 return 0;
676 }
677
678 static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset)
679 {
680 struct acpi_processor *pr = seq->private;
681 unsigned int i;
682
683
684 if (!pr)
685 goto end;
686
687 seq_printf(seq, "active state: C%zd\n"
688 "max_cstate: C%d\n"
689 "maximum allowed latency: %d usec\n",
690 pr->power.state ? pr->power.state - pr->power.states : 0,
691 max_cstate, pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY));
692
693 seq_puts(seq, "states:\n");
694
695 for (i = 1; i <= pr->power.count; i++) {
696 seq_printf(seq, " %cC%d: ",
697 (&pr->power.states[i] ==
698 pr->power.state ? '*' : ' '), i);
699
700 if (!pr->power.states[i].valid) {
701 seq_puts(seq, "<not supported>\n");
702 continue;
703 }
704
705 switch (pr->power.states[i].type) {
706 case ACPI_STATE_C1:
707 seq_printf(seq, "type[C1] ");
708 break;
709 case ACPI_STATE_C2:
710 seq_printf(seq, "type[C2] ");
711 break;
712 case ACPI_STATE_C3:
713 seq_printf(seq, "type[C3] ");
714 break;
715 default:
716 seq_printf(seq, "type[--] ");
717 break;
718 }
719
720 if (pr->power.states[i].promotion.state)
721 seq_printf(seq, "promotion[C%zd] ",
722 (pr->power.states[i].promotion.state -
723 pr->power.states));
724 else
725 seq_puts(seq, "promotion[--] ");
726
727 if (pr->power.states[i].demotion.state)
728 seq_printf(seq, "demotion[C%zd] ",
729 (pr->power.states[i].demotion.state -
730 pr->power.states));
731 else
732 seq_puts(seq, "demotion[--] ");
733
734 seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n",
735 pr->power.states[i].latency,
736 pr->power.states[i].usage,
737 (unsigned long long)pr->power.states[i].time);
738 }
739
740 end:
741 return 0;
742 }
743
744 static int acpi_processor_power_open_fs(struct inode *inode, struct file *file)
745 {
746 return single_open(file, acpi_processor_power_seq_show,
747 PDE(inode)->data);
748 }
749
750 static const struct file_operations acpi_processor_power_fops = {
751 .owner = THIS_MODULE,
752 .open = acpi_processor_power_open_fs,
753 .read = seq_read,
754 .llseek = seq_lseek,
755 .release = single_release,
756 };
757
758
759 /**
760 * acpi_idle_bm_check - checks if bus master activity was detected
761 */
762 static int acpi_idle_bm_check(void)
763 {
764 u32 bm_status = 0;
765
766 acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
767 if (bm_status)
768 acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
769 /*
770 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
771 * the true state of bus mastering activity; forcing us to
772 * manually check the BMIDEA bit of each IDE channel.
773 */
774 else if (errata.piix4.bmisx) {
775 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
776 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
777 bm_status = 1;
778 }
779 return bm_status;
780 }
781
782 /**
783 * acpi_idle_do_entry - a helper function that does C2 and C3 type entry
784 * @cx: cstate data
785 *
786 * Caller disables interrupt before call and enables interrupt after return.
787 */
788 static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx)
789 {
790 /* Don't trace irqs off for idle */
791 stop_critical_timings();
792 if (cx->entry_method == ACPI_CSTATE_FFH) {
793 /* Call into architectural FFH based C-state */
794 acpi_processor_ffh_cstate_enter(cx);
795 } else if (cx->entry_method == ACPI_CSTATE_HALT) {
796 acpi_safe_halt();
797 } else {
798 int unused;
799 /* IO port based C-state */
800 inb(cx->address);
801 /* Dummy wait op - must do something useless after P_LVL2 read
802 because chipsets cannot guarantee that STPCLK# signal
803 gets asserted in time to freeze execution properly. */
804 unused = inl(acpi_gbl_FADT.xpm_timer_block.address);
805 }
806 start_critical_timings();
807 }
808
809 /**
810 * acpi_idle_enter_c1 - enters an ACPI C1 state-type
811 * @dev: the target CPU
812 * @state: the state data
813 *
814 * This is equivalent to the HALT instruction.
815 */
816 static int acpi_idle_enter_c1(struct cpuidle_device *dev,
817 struct cpuidle_state *state)
818 {
819 ktime_t kt1, kt2;
820 s64 idle_time;
821 struct acpi_processor *pr;
822 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
823
824 pr = __get_cpu_var(processors);
825
826 if (unlikely(!pr))
827 return 0;
828
829 local_irq_disable();
830
831 /* Do not access any ACPI IO ports in suspend path */
832 if (acpi_idle_suspend) {
833 local_irq_enable();
834 cpu_relax();
835 return 0;
836 }
837
838 lapic_timer_state_broadcast(pr, cx, 1);
839 kt1 = ktime_get_real();
840 acpi_idle_do_entry(cx);
841 kt2 = ktime_get_real();
842 idle_time = ktime_to_us(ktime_sub(kt2, kt1));
843
844 local_irq_enable();
845 cx->usage++;
846 lapic_timer_state_broadcast(pr, cx, 0);
847
848 return idle_time;
849 }
850
851 /**
852 * acpi_idle_enter_simple - enters an ACPI state without BM handling
853 * @dev: the target CPU
854 * @state: the state data
855 */
856 static int acpi_idle_enter_simple(struct cpuidle_device *dev,
857 struct cpuidle_state *state)
858 {
859 struct acpi_processor *pr;
860 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
861 ktime_t kt1, kt2;
862 s64 idle_time;
863 s64 sleep_ticks = 0;
864
865 pr = __get_cpu_var(processors);
866
867 if (unlikely(!pr))
868 return 0;
869
870 if (acpi_idle_suspend)
871 return(acpi_idle_enter_c1(dev, state));
872
873 local_irq_disable();
874 current_thread_info()->status &= ~TS_POLLING;
875 /*
876 * TS_POLLING-cleared state must be visible before we test
877 * NEED_RESCHED:
878 */
879 smp_mb();
880
881 if (unlikely(need_resched())) {
882 current_thread_info()->status |= TS_POLLING;
883 local_irq_enable();
884 return 0;
885 }
886
887 /*
888 * Must be done before busmaster disable as we might need to
889 * access HPET !
890 */
891 lapic_timer_state_broadcast(pr, cx, 1);
892
893 if (cx->type == ACPI_STATE_C3)
894 ACPI_FLUSH_CPU_CACHE();
895
896 kt1 = ktime_get_real();
897 /* Tell the scheduler that we are going deep-idle: */
898 sched_clock_idle_sleep_event();
899 acpi_idle_do_entry(cx);
900 kt2 = ktime_get_real();
901 idle_time = ktime_to_us(ktime_sub(kt2, kt1));
902
903 sleep_ticks = us_to_pm_timer_ticks(idle_time);
904
905 /* Tell the scheduler how much we idled: */
906 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
907
908 local_irq_enable();
909 current_thread_info()->status |= TS_POLLING;
910
911 cx->usage++;
912
913 lapic_timer_state_broadcast(pr, cx, 0);
914 cx->time += sleep_ticks;
915 return idle_time;
916 }
917
918 static int c3_cpu_count;
919 static DEFINE_SPINLOCK(c3_lock);
920
921 /**
922 * acpi_idle_enter_bm - enters C3 with proper BM handling
923 * @dev: the target CPU
924 * @state: the state data
925 *
926 * If BM is detected, the deepest non-C3 idle state is entered instead.
927 */
928 static int acpi_idle_enter_bm(struct cpuidle_device *dev,
929 struct cpuidle_state *state)
930 {
931 struct acpi_processor *pr;
932 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
933 ktime_t kt1, kt2;
934 s64 idle_time;
935 s64 sleep_ticks = 0;
936
937
938 pr = __get_cpu_var(processors);
939
940 if (unlikely(!pr))
941 return 0;
942
943 if (acpi_idle_suspend)
944 return(acpi_idle_enter_c1(dev, state));
945
946 if (acpi_idle_bm_check()) {
947 if (dev->safe_state) {
948 dev->last_state = dev->safe_state;
949 return dev->safe_state->enter(dev, dev->safe_state);
950 } else {
951 local_irq_disable();
952 acpi_safe_halt();
953 local_irq_enable();
954 return 0;
955 }
956 }
957
958 local_irq_disable();
959 current_thread_info()->status &= ~TS_POLLING;
960 /*
961 * TS_POLLING-cleared state must be visible before we test
962 * NEED_RESCHED:
963 */
964 smp_mb();
965
966 if (unlikely(need_resched())) {
967 current_thread_info()->status |= TS_POLLING;
968 local_irq_enable();
969 return 0;
970 }
971
972 acpi_unlazy_tlb(smp_processor_id());
973
974 /* Tell the scheduler that we are going deep-idle: */
975 sched_clock_idle_sleep_event();
976 /*
977 * Must be done before busmaster disable as we might need to
978 * access HPET !
979 */
980 lapic_timer_state_broadcast(pr, cx, 1);
981
982 kt1 = ktime_get_real();
983 /*
984 * disable bus master
985 * bm_check implies we need ARB_DIS
986 * !bm_check implies we need cache flush
987 * bm_control implies whether we can do ARB_DIS
988 *
989 * That leaves a case where bm_check is set and bm_control is
990 * not set. In that case we cannot do much, we enter C3
991 * without doing anything.
992 */
993 if (pr->flags.bm_check && pr->flags.bm_control) {
994 spin_lock(&c3_lock);
995 c3_cpu_count++;
996 /* Disable bus master arbitration when all CPUs are in C3 */
997 if (c3_cpu_count == num_online_cpus())
998 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1);
999 spin_unlock(&c3_lock);
1000 } else if (!pr->flags.bm_check) {
1001 ACPI_FLUSH_CPU_CACHE();
1002 }
1003
1004 acpi_idle_do_entry(cx);
1005
1006 /* Re-enable bus master arbitration */
1007 if (pr->flags.bm_check && pr->flags.bm_control) {
1008 spin_lock(&c3_lock);
1009 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0);
1010 c3_cpu_count--;
1011 spin_unlock(&c3_lock);
1012 }
1013 kt2 = ktime_get_real();
1014 idle_time = ktime_to_us(ktime_sub(kt2, kt1));
1015
1016 sleep_ticks = us_to_pm_timer_ticks(idle_time);
1017 /* Tell the scheduler how much we idled: */
1018 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
1019
1020 local_irq_enable();
1021 current_thread_info()->status |= TS_POLLING;
1022
1023 cx->usage++;
1024
1025 lapic_timer_state_broadcast(pr, cx, 0);
1026 cx->time += sleep_ticks;
1027 return idle_time;
1028 }
1029
1030 struct cpuidle_driver acpi_idle_driver = {
1031 .name = "acpi_idle",
1032 .owner = THIS_MODULE,
1033 };
1034
1035 /**
1036 * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE
1037 * @pr: the ACPI processor
1038 */
1039 static int acpi_processor_setup_cpuidle(struct acpi_processor *pr)
1040 {
1041 int i, count = CPUIDLE_DRIVER_STATE_START;
1042 struct acpi_processor_cx *cx;
1043 struct cpuidle_state *state;
1044 struct cpuidle_device *dev = &pr->power.dev;
1045
1046 if (!pr->flags.power_setup_done)
1047 return -EINVAL;
1048
1049 if (pr->flags.power == 0) {
1050 return -EINVAL;
1051 }
1052
1053 dev->cpu = pr->id;
1054 for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
1055 dev->states[i].name[0] = '\0';
1056 dev->states[i].desc[0] = '\0';
1057 }
1058
1059 if (max_cstate == 0)
1060 max_cstate = 1;
1061
1062 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) {
1063 cx = &pr->power.states[i];
1064 state = &dev->states[count];
1065
1066 if (!cx->valid)
1067 continue;
1068
1069 #ifdef CONFIG_HOTPLUG_CPU
1070 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
1071 !pr->flags.has_cst &&
1072 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
1073 continue;
1074 #endif
1075 cpuidle_set_statedata(state, cx);
1076
1077 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i);
1078 strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
1079 state->exit_latency = cx->latency;
1080 state->target_residency = cx->latency * latency_factor;
1081 state->power_usage = cx->power;
1082
1083 state->flags = 0;
1084 switch (cx->type) {
1085 case ACPI_STATE_C1:
1086 state->flags |= CPUIDLE_FLAG_SHALLOW;
1087 if (cx->entry_method == ACPI_CSTATE_FFH)
1088 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1089
1090 state->enter = acpi_idle_enter_c1;
1091 dev->safe_state = state;
1092 break;
1093
1094 case ACPI_STATE_C2:
1095 state->flags |= CPUIDLE_FLAG_BALANCED;
1096 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1097 state->enter = acpi_idle_enter_simple;
1098 dev->safe_state = state;
1099 break;
1100
1101 case ACPI_STATE_C3:
1102 state->flags |= CPUIDLE_FLAG_DEEP;
1103 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1104 state->flags |= CPUIDLE_FLAG_CHECK_BM;
1105 state->enter = pr->flags.bm_check ?
1106 acpi_idle_enter_bm :
1107 acpi_idle_enter_simple;
1108 break;
1109 }
1110
1111 count++;
1112 if (count == CPUIDLE_STATE_MAX)
1113 break;
1114 }
1115
1116 dev->state_count = count;
1117
1118 if (!count)
1119 return -EINVAL;
1120
1121 return 0;
1122 }
1123
1124 int acpi_processor_cst_has_changed(struct acpi_processor *pr)
1125 {
1126 int ret = 0;
1127
1128 if (boot_option_idle_override)
1129 return 0;
1130
1131 if (!pr)
1132 return -EINVAL;
1133
1134 if (nocst) {
1135 return -ENODEV;
1136 }
1137
1138 if (!pr->flags.power_setup_done)
1139 return -ENODEV;
1140
1141 cpuidle_pause_and_lock();
1142 cpuidle_disable_device(&pr->power.dev);
1143 acpi_processor_get_power_info(pr);
1144 if (pr->flags.power) {
1145 acpi_processor_setup_cpuidle(pr);
1146 ret = cpuidle_enable_device(&pr->power.dev);
1147 }
1148 cpuidle_resume_and_unlock();
1149
1150 return ret;
1151 }
1152
1153 int __cpuinit acpi_processor_power_init(struct acpi_processor *pr,
1154 struct acpi_device *device)
1155 {
1156 acpi_status status = 0;
1157 static int first_run;
1158 struct proc_dir_entry *entry = NULL;
1159 unsigned int i;
1160
1161 if (boot_option_idle_override)
1162 return 0;
1163
1164 if (!first_run) {
1165 if (idle_halt) {
1166 /*
1167 * When the boot option of "idle=halt" is added, halt
1168 * is used for CPU IDLE.
1169 * In such case C2/C3 is meaningless. So the max_cstate
1170 * is set to one.
1171 */
1172 max_cstate = 1;
1173 }
1174 dmi_check_system(processor_power_dmi_table);
1175 max_cstate = acpi_processor_cstate_check(max_cstate);
1176 if (max_cstate < ACPI_C_STATES_MAX)
1177 printk(KERN_NOTICE
1178 "ACPI: processor limited to max C-state %d\n",
1179 max_cstate);
1180 first_run++;
1181 }
1182
1183 if (!pr)
1184 return -EINVAL;
1185
1186 if (acpi_gbl_FADT.cst_control && !nocst) {
1187 status =
1188 acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8);
1189 if (ACPI_FAILURE(status)) {
1190 ACPI_EXCEPTION((AE_INFO, status,
1191 "Notifying BIOS of _CST ability failed"));
1192 }
1193 }
1194
1195 acpi_processor_get_power_info(pr);
1196 pr->flags.power_setup_done = 1;
1197
1198 /*
1199 * Install the idle handler if processor power management is supported.
1200 * Note that we use previously set idle handler will be used on
1201 * platforms that only support C1.
1202 */
1203 if (pr->flags.power) {
1204 acpi_processor_setup_cpuidle(pr);
1205 if (cpuidle_register_device(&pr->power.dev))
1206 return -EIO;
1207
1208 printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id);
1209 for (i = 1; i <= pr->power.count; i++)
1210 if (pr->power.states[i].valid)
1211 printk(" C%d[C%d]", i,
1212 pr->power.states[i].type);
1213 printk(")\n");
1214 }
1215
1216 /* 'power' [R] */
1217 entry = proc_create_data(ACPI_PROCESSOR_FILE_POWER,
1218 S_IRUGO, acpi_device_dir(device),
1219 &acpi_processor_power_fops,
1220 acpi_driver_data(device));
1221 if (!entry)
1222 return -EIO;
1223 return 0;
1224 }
1225
1226 int acpi_processor_power_exit(struct acpi_processor *pr,
1227 struct acpi_device *device)
1228 {
1229 if (boot_option_idle_override)
1230 return 0;
1231
1232 cpuidle_unregister_device(&pr->power.dev);
1233 pr->flags.power_setup_done = 0;
1234
1235 if (acpi_device_dir(device))
1236 remove_proc_entry(ACPI_PROCESSOR_FILE_POWER,
1237 acpi_device_dir(device));
1238
1239 return 0;
1240 }