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ACPI: remove BM_RLD access from idle entry path
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / acpi / processor_idle.c
1 /*
2 * processor_idle - idle state submodule to the ACPI processor driver
3 *
4 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
5 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
6 * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de>
7 * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
8 * - Added processor hotplug support
9 * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
10 * - Added support for C3 on SMP
11 *
12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or (at
17 * your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22 * General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 *
28 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
29 */
30
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/init.h>
34 #include <linux/cpufreq.h>
35 #include <linux/proc_fs.h>
36 #include <linux/seq_file.h>
37 #include <linux/acpi.h>
38 #include <linux/dmi.h>
39 #include <linux/moduleparam.h>
40 #include <linux/sched.h> /* need_resched() */
41 #include <linux/pm_qos_params.h>
42 #include <linux/clockchips.h>
43 #include <linux/cpuidle.h>
44 #include <linux/irqflags.h>
45
46 /*
47 * Include the apic definitions for x86 to have the APIC timer related defines
48 * available also for UP (on SMP it gets magically included via linux/smp.h).
49 * asm/acpi.h is not an option, as it would require more include magic. Also
50 * creating an empty asm-ia64/apic.h would just trade pest vs. cholera.
51 */
52 #ifdef CONFIG_X86
53 #include <asm/apic.h>
54 #endif
55
56 #include <asm/io.h>
57 #include <asm/uaccess.h>
58
59 #include <acpi/acpi_bus.h>
60 #include <acpi/processor.h>
61 #include <asm/processor.h>
62
63 #define ACPI_PROCESSOR_CLASS "processor"
64 #define _COMPONENT ACPI_PROCESSOR_COMPONENT
65 ACPI_MODULE_NAME("processor_idle");
66 #define ACPI_PROCESSOR_FILE_POWER "power"
67 #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000)
68 #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY)
69 #ifndef CONFIG_CPU_IDLE
70 #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */
71 #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */
72 static void (*pm_idle_save) (void) __read_mostly;
73 #else
74 #define C2_OVERHEAD 1 /* 1us */
75 #define C3_OVERHEAD 1 /* 1us */
76 #endif
77 #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000))
78
79 static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER;
80 #ifdef CONFIG_CPU_IDLE
81 module_param(max_cstate, uint, 0000);
82 #else
83 module_param(max_cstate, uint, 0644);
84 #endif
85 static unsigned int nocst __read_mostly;
86 module_param(nocst, uint, 0000);
87
88 #ifndef CONFIG_CPU_IDLE
89 /*
90 * bm_history -- bit-mask with a bit per jiffy of bus-master activity
91 * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms
92 * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms
93 * 100 HZ: 0x0000000F: 4 jiffies = 40ms
94 * reduce history for more aggressive entry into C3
95 */
96 static unsigned int bm_history __read_mostly =
97 (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1));
98 module_param(bm_history, uint, 0644);
99
100 static int acpi_processor_set_power_policy(struct acpi_processor *pr);
101
102 #else /* CONFIG_CPU_IDLE */
103 static unsigned int latency_factor __read_mostly = 2;
104 module_param(latency_factor, uint, 0644);
105 #endif
106
107 /*
108 * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3.
109 * For now disable this. Probably a bug somewhere else.
110 *
111 * To skip this limit, boot/load with a large max_cstate limit.
112 */
113 static int set_max_cstate(const struct dmi_system_id *id)
114 {
115 if (max_cstate > ACPI_PROCESSOR_MAX_POWER)
116 return 0;
117
118 printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate."
119 " Override with \"processor.max_cstate=%d\"\n", id->ident,
120 (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1);
121
122 max_cstate = (long)id->driver_data;
123
124 return 0;
125 }
126
127 /* Actually this shouldn't be __cpuinitdata, would be better to fix the
128 callers to only run once -AK */
129 static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = {
130 { set_max_cstate, "IBM ThinkPad R40e", {
131 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
132 DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1},
133 { set_max_cstate, "IBM ThinkPad R40e", {
134 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
135 DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1},
136 { set_max_cstate, "IBM ThinkPad R40e", {
137 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
138 DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1},
139 { set_max_cstate, "IBM ThinkPad R40e", {
140 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
141 DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1},
142 { set_max_cstate, "IBM ThinkPad R40e", {
143 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
144 DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1},
145 { set_max_cstate, "IBM ThinkPad R40e", {
146 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
147 DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1},
148 { set_max_cstate, "IBM ThinkPad R40e", {
149 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
150 DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1},
151 { set_max_cstate, "IBM ThinkPad R40e", {
152 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
153 DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1},
154 { set_max_cstate, "IBM ThinkPad R40e", {
155 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
156 DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1},
157 { set_max_cstate, "IBM ThinkPad R40e", {
158 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
159 DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1},
160 { set_max_cstate, "IBM ThinkPad R40e", {
161 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
162 DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1},
163 { set_max_cstate, "IBM ThinkPad R40e", {
164 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
165 DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1},
166 { set_max_cstate, "IBM ThinkPad R40e", {
167 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
168 DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1},
169 { set_max_cstate, "IBM ThinkPad R40e", {
170 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
171 DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1},
172 { set_max_cstate, "IBM ThinkPad R40e", {
173 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
174 DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1},
175 { set_max_cstate, "IBM ThinkPad R40e", {
176 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
177 DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1},
178 { set_max_cstate, "Medion 41700", {
179 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
180 DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1},
181 { set_max_cstate, "Clevo 5600D", {
182 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
183 DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")},
184 (void *)2},
185 {},
186 };
187
188 static inline u32 ticks_elapsed(u32 t1, u32 t2)
189 {
190 if (t2 >= t1)
191 return (t2 - t1);
192 else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER))
193 return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF);
194 else
195 return ((0xFFFFFFFF - t1) + t2);
196 }
197
198 static inline u32 ticks_elapsed_in_us(u32 t1, u32 t2)
199 {
200 if (t2 >= t1)
201 return PM_TIMER_TICKS_TO_US(t2 - t1);
202 else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER))
203 return PM_TIMER_TICKS_TO_US(((0x00FFFFFF - t1) + t2) & 0x00FFFFFF);
204 else
205 return PM_TIMER_TICKS_TO_US((0xFFFFFFFF - t1) + t2);
206 }
207
208 /*
209 * Callers should disable interrupts before the call and enable
210 * interrupts after return.
211 */
212 static void acpi_safe_halt(void)
213 {
214 current_thread_info()->status &= ~TS_POLLING;
215 /*
216 * TS_POLLING-cleared state must be visible before we
217 * test NEED_RESCHED:
218 */
219 smp_mb();
220 if (!need_resched()) {
221 safe_halt();
222 local_irq_disable();
223 }
224 current_thread_info()->status |= TS_POLLING;
225 }
226
227 #ifndef CONFIG_CPU_IDLE
228
229 static void
230 acpi_processor_power_activate(struct acpi_processor *pr,
231 struct acpi_processor_cx *new)
232 {
233 struct acpi_processor_cx *old;
234
235 if (!pr || !new)
236 return;
237
238 old = pr->power.state;
239
240 if (old)
241 old->promotion.count = 0;
242 new->demotion.count = 0;
243
244 pr->power.state = new;
245
246 return;
247 }
248
249 static atomic_t c3_cpu_count;
250
251 /* Common C-state entry for C2, C3, .. */
252 static void acpi_cstate_enter(struct acpi_processor_cx *cstate)
253 {
254 /* Don't trace irqs off for idle */
255 stop_critical_timings();
256 if (cstate->entry_method == ACPI_CSTATE_FFH) {
257 /* Call into architectural FFH based C-state */
258 acpi_processor_ffh_cstate_enter(cstate);
259 } else {
260 int unused;
261 /* IO port based C-state */
262 inb(cstate->address);
263 /* Dummy wait op - must do something useless after P_LVL2 read
264 because chipsets cannot guarantee that STPCLK# signal
265 gets asserted in time to freeze execution properly. */
266 unused = inl(acpi_gbl_FADT.xpm_timer_block.address);
267 }
268 start_critical_timings();
269 }
270 #endif /* !CONFIG_CPU_IDLE */
271
272 #ifdef ARCH_APICTIMER_STOPS_ON_C3
273
274 /*
275 * Some BIOS implementations switch to C3 in the published C2 state.
276 * This seems to be a common problem on AMD boxen, but other vendors
277 * are affected too. We pick the most conservative approach: we assume
278 * that the local APIC stops in both C2 and C3.
279 */
280 static void acpi_timer_check_state(int state, struct acpi_processor *pr,
281 struct acpi_processor_cx *cx)
282 {
283 struct acpi_processor_power *pwr = &pr->power;
284 u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2;
285
286 /*
287 * Check, if one of the previous states already marked the lapic
288 * unstable
289 */
290 if (pwr->timer_broadcast_on_state < state)
291 return;
292
293 if (cx->type >= type)
294 pr->power.timer_broadcast_on_state = state;
295 }
296
297 static void acpi_propagate_timer_broadcast(struct acpi_processor *pr)
298 {
299 unsigned long reason;
300
301 reason = pr->power.timer_broadcast_on_state < INT_MAX ?
302 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
303
304 clockevents_notify(reason, &pr->id);
305 }
306
307 /* Power(C) State timer broadcast control */
308 static void acpi_state_timer_broadcast(struct acpi_processor *pr,
309 struct acpi_processor_cx *cx,
310 int broadcast)
311 {
312 int state = cx - pr->power.states;
313
314 if (state >= pr->power.timer_broadcast_on_state) {
315 unsigned long reason;
316
317 reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER :
318 CLOCK_EVT_NOTIFY_BROADCAST_EXIT;
319 clockevents_notify(reason, &pr->id);
320 }
321 }
322
323 #else
324
325 static void acpi_timer_check_state(int state, struct acpi_processor *pr,
326 struct acpi_processor_cx *cstate) { }
327 static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { }
328 static void acpi_state_timer_broadcast(struct acpi_processor *pr,
329 struct acpi_processor_cx *cx,
330 int broadcast)
331 {
332 }
333
334 #endif
335
336 /*
337 * Suspend / resume control
338 */
339 static int acpi_idle_suspend;
340
341 int acpi_processor_suspend(struct acpi_device * device, pm_message_t state)
342 {
343 acpi_idle_suspend = 1;
344 return 0;
345 }
346
347 int acpi_processor_resume(struct acpi_device * device)
348 {
349 acpi_idle_suspend = 0;
350 return 0;
351 }
352
353 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
354 static int tsc_halts_in_c(int state)
355 {
356 switch (boot_cpu_data.x86_vendor) {
357 case X86_VENDOR_AMD:
358 case X86_VENDOR_INTEL:
359 /*
360 * AMD Fam10h TSC will tick in all
361 * C/P/S0/S1 states when this bit is set.
362 */
363 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
364 return 0;
365
366 /*FALL THROUGH*/
367 default:
368 return state > ACPI_STATE_C1;
369 }
370 }
371 #endif
372
373 #ifndef CONFIG_CPU_IDLE
374 static void acpi_processor_idle(void)
375 {
376 struct acpi_processor *pr = NULL;
377 struct acpi_processor_cx *cx = NULL;
378 struct acpi_processor_cx *next_state = NULL;
379 int sleep_ticks = 0;
380 u32 t1, t2 = 0;
381
382 /*
383 * Interrupts must be disabled during bus mastering calculations and
384 * for C2/C3 transitions.
385 */
386 local_irq_disable();
387
388 pr = __get_cpu_var(processors);
389 if (!pr) {
390 local_irq_enable();
391 return;
392 }
393
394 /*
395 * Check whether we truly need to go idle, or should
396 * reschedule:
397 */
398 if (unlikely(need_resched())) {
399 local_irq_enable();
400 return;
401 }
402
403 cx = pr->power.state;
404 if (!cx || acpi_idle_suspend) {
405 if (pm_idle_save) {
406 pm_idle_save(); /* enables IRQs */
407 } else {
408 acpi_safe_halt();
409 local_irq_enable();
410 }
411
412 return;
413 }
414
415 /*
416 * Check BM Activity
417 * -----------------
418 * Check for bus mastering activity (if required), record, and check
419 * for demotion.
420 */
421 if (pr->flags.bm_check) {
422 u32 bm_status = 0;
423 unsigned long diff = jiffies - pr->power.bm_check_timestamp;
424
425 if (diff > 31)
426 diff = 31;
427
428 pr->power.bm_activity <<= diff;
429
430 acpi_get_register_unlocked(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
431 if (bm_status) {
432 pr->power.bm_activity |= 0x1;
433 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
434 }
435 /*
436 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
437 * the true state of bus mastering activity; forcing us to
438 * manually check the BMIDEA bit of each IDE channel.
439 */
440 else if (errata.piix4.bmisx) {
441 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
442 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
443 pr->power.bm_activity |= 0x1;
444 }
445
446 pr->power.bm_check_timestamp = jiffies;
447
448 /*
449 * If bus mastering is or was active this jiffy, demote
450 * to avoid a faulty transition. Note that the processor
451 * won't enter a low-power state during this call (to this
452 * function) but should upon the next.
453 *
454 * TBD: A better policy might be to fallback to the demotion
455 * state (use it for this quantum only) istead of
456 * demoting -- and rely on duration as our sole demotion
457 * qualification. This may, however, introduce DMA
458 * issues (e.g. floppy DMA transfer overrun/underrun).
459 */
460 if ((pr->power.bm_activity & 0x1) &&
461 cx->demotion.threshold.bm) {
462 local_irq_enable();
463 next_state = cx->demotion.state;
464 goto end;
465 }
466 }
467
468 #ifdef CONFIG_HOTPLUG_CPU
469 /*
470 * Check for P_LVL2_UP flag before entering C2 and above on
471 * an SMP system. We do it here instead of doing it at _CST/P_LVL
472 * detection phase, to work cleanly with logical CPU hotplug.
473 */
474 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
475 !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
476 cx = &pr->power.states[ACPI_STATE_C1];
477 #endif
478
479 /*
480 * Sleep:
481 * ------
482 * Invoke the current Cx state to put the processor to sleep.
483 */
484 if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) {
485 current_thread_info()->status &= ~TS_POLLING;
486 /*
487 * TS_POLLING-cleared state must be visible before we
488 * test NEED_RESCHED:
489 */
490 smp_mb();
491 if (need_resched()) {
492 current_thread_info()->status |= TS_POLLING;
493 local_irq_enable();
494 return;
495 }
496 }
497
498 switch (cx->type) {
499
500 case ACPI_STATE_C1:
501 /*
502 * Invoke C1.
503 * Use the appropriate idle routine, the one that would
504 * be used without acpi C-states.
505 */
506 if (pm_idle_save) {
507 pm_idle_save(); /* enables IRQs */
508 } else {
509 acpi_safe_halt();
510 local_irq_enable();
511 }
512
513 /*
514 * TBD: Can't get time duration while in C1, as resumes
515 * go to an ISR rather than here. Need to instrument
516 * base interrupt handler.
517 *
518 * Note: the TSC better not stop in C1, sched_clock() will
519 * skew otherwise.
520 */
521 sleep_ticks = 0xFFFFFFFF;
522
523 break;
524
525 case ACPI_STATE_C2:
526 /* Get start time (ticks) */
527 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
528 /* Tell the scheduler that we are going deep-idle: */
529 sched_clock_idle_sleep_event();
530 /* Invoke C2 */
531 acpi_state_timer_broadcast(pr, cx, 1);
532 acpi_cstate_enter(cx);
533 /* Get end time (ticks) */
534 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
535
536 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
537 /* TSC halts in C2, so notify users */
538 if (tsc_halts_in_c(ACPI_STATE_C2))
539 mark_tsc_unstable("possible TSC halt in C2");
540 #endif
541 /* Compute time (ticks) that we were actually asleep */
542 sleep_ticks = ticks_elapsed(t1, t2);
543
544 /* Tell the scheduler how much we idled: */
545 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
546
547 /* Re-enable interrupts */
548 local_irq_enable();
549 /* Do not account our idle-switching overhead: */
550 sleep_ticks -= cx->latency_ticks + C2_OVERHEAD;
551
552 current_thread_info()->status |= TS_POLLING;
553 acpi_state_timer_broadcast(pr, cx, 0);
554 break;
555
556 case ACPI_STATE_C3:
557 acpi_unlazy_tlb(smp_processor_id());
558 /*
559 * Must be done before busmaster disable as we might
560 * need to access HPET !
561 */
562 acpi_state_timer_broadcast(pr, cx, 1);
563 /*
564 * disable bus master
565 * bm_check implies we need ARB_DIS
566 * !bm_check implies we need cache flush
567 * bm_control implies whether we can do ARB_DIS
568 *
569 * That leaves a case where bm_check is set and bm_control is
570 * not set. In that case we cannot do much, we enter C3
571 * without doing anything.
572 */
573 if (pr->flags.bm_check && pr->flags.bm_control) {
574 if (atomic_inc_return(&c3_cpu_count) ==
575 num_online_cpus()) {
576 /*
577 * All CPUs are trying to go to C3
578 * Disable bus master arbitration
579 */
580 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
581 }
582 } else if (!pr->flags.bm_check) {
583 /* SMP with no shared cache... Invalidate cache */
584 ACPI_FLUSH_CPU_CACHE();
585 }
586
587 /* Get start time (ticks) */
588 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
589 /* Invoke C3 */
590 /* Tell the scheduler that we are going deep-idle: */
591 sched_clock_idle_sleep_event();
592 acpi_cstate_enter(cx);
593 /* Get end time (ticks) */
594 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
595 if (pr->flags.bm_check && pr->flags.bm_control) {
596 /* Enable bus master arbitration */
597 atomic_dec(&c3_cpu_count);
598 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
599 }
600
601 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
602 /* TSC halts in C3, so notify users */
603 if (tsc_halts_in_c(ACPI_STATE_C3))
604 mark_tsc_unstable("TSC halts in C3");
605 #endif
606 /* Compute time (ticks) that we were actually asleep */
607 sleep_ticks = ticks_elapsed(t1, t2);
608 /* Tell the scheduler how much we idled: */
609 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
610
611 /* Re-enable interrupts */
612 local_irq_enable();
613 /* Do not account our idle-switching overhead: */
614 sleep_ticks -= cx->latency_ticks + C3_OVERHEAD;
615
616 current_thread_info()->status |= TS_POLLING;
617 acpi_state_timer_broadcast(pr, cx, 0);
618 break;
619
620 default:
621 local_irq_enable();
622 return;
623 }
624 cx->usage++;
625 if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0))
626 cx->time += sleep_ticks;
627
628 next_state = pr->power.state;
629
630 #ifdef CONFIG_HOTPLUG_CPU
631 /* Don't do promotion/demotion */
632 if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) &&
633 !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) {
634 next_state = cx;
635 goto end;
636 }
637 #endif
638
639 /*
640 * Promotion?
641 * ----------
642 * Track the number of longs (time asleep is greater than threshold)
643 * and promote when the count threshold is reached. Note that bus
644 * mastering activity may prevent promotions.
645 * Do not promote above max_cstate.
646 */
647 if (cx->promotion.state &&
648 ((cx->promotion.state - pr->power.states) <= max_cstate)) {
649 if (sleep_ticks > cx->promotion.threshold.ticks &&
650 cx->promotion.state->latency <=
651 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) {
652 cx->promotion.count++;
653 cx->demotion.count = 0;
654 if (cx->promotion.count >=
655 cx->promotion.threshold.count) {
656 if (pr->flags.bm_check) {
657 if (!
658 (pr->power.bm_activity & cx->
659 promotion.threshold.bm)) {
660 next_state =
661 cx->promotion.state;
662 goto end;
663 }
664 } else {
665 next_state = cx->promotion.state;
666 goto end;
667 }
668 }
669 }
670 }
671
672 /*
673 * Demotion?
674 * ---------
675 * Track the number of shorts (time asleep is less than time threshold)
676 * and demote when the usage threshold is reached.
677 */
678 if (cx->demotion.state) {
679 if (sleep_ticks < cx->demotion.threshold.ticks) {
680 cx->demotion.count++;
681 cx->promotion.count = 0;
682 if (cx->demotion.count >= cx->demotion.threshold.count) {
683 next_state = cx->demotion.state;
684 goto end;
685 }
686 }
687 }
688
689 end:
690 /*
691 * Demote if current state exceeds max_cstate
692 * or if the latency of the current state is unacceptable
693 */
694 if ((pr->power.state - pr->power.states) > max_cstate ||
695 pr->power.state->latency >
696 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) {
697 if (cx->demotion.state)
698 next_state = cx->demotion.state;
699 }
700
701 /*
702 * New Cx State?
703 * -------------
704 * If we're going to start using a new Cx state we must clean up
705 * from the previous and prepare to use the new.
706 */
707 if (next_state != pr->power.state)
708 acpi_processor_power_activate(pr, next_state);
709 }
710
711 static int acpi_processor_set_power_policy(struct acpi_processor *pr)
712 {
713 unsigned int i;
714 unsigned int state_is_set = 0;
715 struct acpi_processor_cx *lower = NULL;
716 struct acpi_processor_cx *higher = NULL;
717 struct acpi_processor_cx *cx;
718
719
720 if (!pr)
721 return -EINVAL;
722
723 /*
724 * This function sets the default Cx state policy (OS idle handler).
725 * Our scheme is to promote quickly to C2 but more conservatively
726 * to C3. We're favoring C2 for its characteristics of low latency
727 * (quick response), good power savings, and ability to allow bus
728 * mastering activity. Note that the Cx state policy is completely
729 * customizable and can be altered dynamically.
730 */
731
732 /* startup state */
733 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
734 cx = &pr->power.states[i];
735 if (!cx->valid)
736 continue;
737
738 if (!state_is_set)
739 pr->power.state = cx;
740 state_is_set++;
741 break;
742 }
743
744 if (!state_is_set)
745 return -ENODEV;
746
747 /* demotion */
748 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
749 cx = &pr->power.states[i];
750 if (!cx->valid)
751 continue;
752
753 if (lower) {
754 cx->demotion.state = lower;
755 cx->demotion.threshold.ticks = cx->latency_ticks;
756 cx->demotion.threshold.count = 1;
757 if (cx->type == ACPI_STATE_C3)
758 cx->demotion.threshold.bm = bm_history;
759 }
760
761 lower = cx;
762 }
763
764 /* promotion */
765 for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) {
766 cx = &pr->power.states[i];
767 if (!cx->valid)
768 continue;
769
770 if (higher) {
771 cx->promotion.state = higher;
772 cx->promotion.threshold.ticks = cx->latency_ticks;
773 if (cx->type >= ACPI_STATE_C2)
774 cx->promotion.threshold.count = 4;
775 else
776 cx->promotion.threshold.count = 10;
777 if (higher->type == ACPI_STATE_C3)
778 cx->promotion.threshold.bm = bm_history;
779 }
780
781 higher = cx;
782 }
783
784 return 0;
785 }
786 #endif /* !CONFIG_CPU_IDLE */
787
788 static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
789 {
790
791 if (!pr)
792 return -EINVAL;
793
794 if (!pr->pblk)
795 return -ENODEV;
796
797 /* if info is obtained from pblk/fadt, type equals state */
798 pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2;
799 pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3;
800
801 #ifndef CONFIG_HOTPLUG_CPU
802 /*
803 * Check for P_LVL2_UP flag before entering C2 and above on
804 * an SMP system.
805 */
806 if ((num_online_cpus() > 1) &&
807 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
808 return -ENODEV;
809 #endif
810
811 /* determine C2 and C3 address from pblk */
812 pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4;
813 pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5;
814
815 /* determine latencies from FADT */
816 pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency;
817 pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency;
818
819 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
820 "lvl2[0x%08x] lvl3[0x%08x]\n",
821 pr->power.states[ACPI_STATE_C2].address,
822 pr->power.states[ACPI_STATE_C3].address));
823
824 return 0;
825 }
826
827 static int acpi_processor_get_power_info_default(struct acpi_processor *pr)
828 {
829 if (!pr->power.states[ACPI_STATE_C1].valid) {
830 /* set the first C-State to C1 */
831 /* all processors need to support C1 */
832 pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1;
833 pr->power.states[ACPI_STATE_C1].valid = 1;
834 pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT;
835 }
836 /* the C0 state only exists as a filler in our array */
837 pr->power.states[ACPI_STATE_C0].valid = 1;
838 return 0;
839 }
840
841 static int acpi_processor_get_power_info_cst(struct acpi_processor *pr)
842 {
843 acpi_status status = 0;
844 acpi_integer count;
845 int current_count;
846 int i;
847 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
848 union acpi_object *cst;
849
850
851 if (nocst)
852 return -ENODEV;
853
854 current_count = 0;
855
856 status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer);
857 if (ACPI_FAILURE(status)) {
858 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n"));
859 return -ENODEV;
860 }
861
862 cst = buffer.pointer;
863
864 /* There must be at least 2 elements */
865 if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) {
866 printk(KERN_ERR PREFIX "not enough elements in _CST\n");
867 status = -EFAULT;
868 goto end;
869 }
870
871 count = cst->package.elements[0].integer.value;
872
873 /* Validate number of power states. */
874 if (count < 1 || count != cst->package.count - 1) {
875 printk(KERN_ERR PREFIX "count given by _CST is not valid\n");
876 status = -EFAULT;
877 goto end;
878 }
879
880 /* Tell driver that at least _CST is supported. */
881 pr->flags.has_cst = 1;
882
883 for (i = 1; i <= count; i++) {
884 union acpi_object *element;
885 union acpi_object *obj;
886 struct acpi_power_register *reg;
887 struct acpi_processor_cx cx;
888
889 memset(&cx, 0, sizeof(cx));
890
891 element = &(cst->package.elements[i]);
892 if (element->type != ACPI_TYPE_PACKAGE)
893 continue;
894
895 if (element->package.count != 4)
896 continue;
897
898 obj = &(element->package.elements[0]);
899
900 if (obj->type != ACPI_TYPE_BUFFER)
901 continue;
902
903 reg = (struct acpi_power_register *)obj->buffer.pointer;
904
905 if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO &&
906 (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE))
907 continue;
908
909 /* There should be an easy way to extract an integer... */
910 obj = &(element->package.elements[1]);
911 if (obj->type != ACPI_TYPE_INTEGER)
912 continue;
913
914 cx.type = obj->integer.value;
915 /*
916 * Some buggy BIOSes won't list C1 in _CST -
917 * Let acpi_processor_get_power_info_default() handle them later
918 */
919 if (i == 1 && cx.type != ACPI_STATE_C1)
920 current_count++;
921
922 cx.address = reg->address;
923 cx.index = current_count + 1;
924
925 cx.entry_method = ACPI_CSTATE_SYSTEMIO;
926 if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) {
927 if (acpi_processor_ffh_cstate_probe
928 (pr->id, &cx, reg) == 0) {
929 cx.entry_method = ACPI_CSTATE_FFH;
930 } else if (cx.type == ACPI_STATE_C1) {
931 /*
932 * C1 is a special case where FIXED_HARDWARE
933 * can be handled in non-MWAIT way as well.
934 * In that case, save this _CST entry info.
935 * Otherwise, ignore this info and continue.
936 */
937 cx.entry_method = ACPI_CSTATE_HALT;
938 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT");
939 } else {
940 continue;
941 }
942 if (cx.type == ACPI_STATE_C1 &&
943 (idle_halt || idle_nomwait)) {
944 /*
945 * In most cases the C1 space_id obtained from
946 * _CST object is FIXED_HARDWARE access mode.
947 * But when the option of idle=halt is added,
948 * the entry_method type should be changed from
949 * CSTATE_FFH to CSTATE_HALT.
950 * When the option of idle=nomwait is added,
951 * the C1 entry_method type should be
952 * CSTATE_HALT.
953 */
954 cx.entry_method = ACPI_CSTATE_HALT;
955 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT");
956 }
957 } else {
958 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x",
959 cx.address);
960 }
961
962 if (cx.type == ACPI_STATE_C1) {
963 cx.valid = 1;
964 }
965
966 obj = &(element->package.elements[2]);
967 if (obj->type != ACPI_TYPE_INTEGER)
968 continue;
969
970 cx.latency = obj->integer.value;
971
972 obj = &(element->package.elements[3]);
973 if (obj->type != ACPI_TYPE_INTEGER)
974 continue;
975
976 cx.power = obj->integer.value;
977
978 current_count++;
979 memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx));
980
981 /*
982 * We support total ACPI_PROCESSOR_MAX_POWER - 1
983 * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1)
984 */
985 if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) {
986 printk(KERN_WARNING
987 "Limiting number of power states to max (%d)\n",
988 ACPI_PROCESSOR_MAX_POWER);
989 printk(KERN_WARNING
990 "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n");
991 break;
992 }
993 }
994
995 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n",
996 current_count));
997
998 /* Validate number of power states discovered */
999 if (current_count < 2)
1000 status = -EFAULT;
1001
1002 end:
1003 kfree(buffer.pointer);
1004
1005 return status;
1006 }
1007
1008 static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx)
1009 {
1010
1011 if (!cx->address)
1012 return;
1013
1014 /*
1015 * C2 latency must be less than or equal to 100
1016 * microseconds.
1017 */
1018 else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) {
1019 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1020 "latency too large [%d]\n", cx->latency));
1021 return;
1022 }
1023
1024 /*
1025 * Otherwise we've met all of our C2 requirements.
1026 * Normalize the C2 latency to expidite policy
1027 */
1028 cx->valid = 1;
1029
1030 #ifndef CONFIG_CPU_IDLE
1031 cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
1032 #else
1033 cx->latency_ticks = cx->latency;
1034 #endif
1035
1036 return;
1037 }
1038
1039 static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
1040 struct acpi_processor_cx *cx)
1041 {
1042 static int bm_check_flag;
1043
1044
1045 if (!cx->address)
1046 return;
1047
1048 /*
1049 * C3 latency must be less than or equal to 1000
1050 * microseconds.
1051 */
1052 else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) {
1053 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1054 "latency too large [%d]\n", cx->latency));
1055 return;
1056 }
1057
1058 /*
1059 * PIIX4 Erratum #18: We don't support C3 when Type-F (fast)
1060 * DMA transfers are used by any ISA device to avoid livelock.
1061 * Note that we could disable Type-F DMA (as recommended by
1062 * the erratum), but this is known to disrupt certain ISA
1063 * devices thus we take the conservative approach.
1064 */
1065 else if (errata.piix4.fdma) {
1066 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1067 "C3 not supported on PIIX4 with Type-F DMA\n"));
1068 return;
1069 }
1070
1071 /* All the logic here assumes flags.bm_check is same across all CPUs */
1072 if (!bm_check_flag) {
1073 /* Determine whether bm_check is needed based on CPU */
1074 acpi_processor_power_init_bm_check(&(pr->flags), pr->id);
1075 bm_check_flag = pr->flags.bm_check;
1076 } else {
1077 pr->flags.bm_check = bm_check_flag;
1078 }
1079
1080 if (pr->flags.bm_check) {
1081 if (!pr->flags.bm_control) {
1082 if (pr->flags.has_cst != 1) {
1083 /* bus mastering control is necessary */
1084 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1085 "C3 support requires BM control\n"));
1086 return;
1087 } else {
1088 /* Here we enter C3 without bus mastering */
1089 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1090 "C3 support without BM control\n"));
1091 }
1092 }
1093 } else {
1094 /*
1095 * WBINVD should be set in fadt, for C3 state to be
1096 * supported on when bm_check is not required.
1097 */
1098 if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) {
1099 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1100 "Cache invalidation should work properly"
1101 " for C3 to be enabled on SMP systems\n"));
1102 return;
1103 }
1104 }
1105
1106 /*
1107 * Otherwise we've met all of our C3 requirements.
1108 * Normalize the C3 latency to expidite policy. Enable
1109 * checking of bus mastering status (bm_check) so we can
1110 * use this in our C3 policy
1111 */
1112 cx->valid = 1;
1113
1114 #ifndef CONFIG_CPU_IDLE
1115 cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
1116 #else
1117 cx->latency_ticks = cx->latency;
1118 #endif
1119 /*
1120 * On older chipsets, BM_RLD needs to be set
1121 * in order for Bus Master activity to wake the
1122 * system from C3. Newer chipsets handle DMA
1123 * during C3 automatically and BM_RLD is a NOP.
1124 * In either case, the proper way to
1125 * handle BM_RLD is to set it and leave it set.
1126 */
1127 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1);
1128
1129 return;
1130 }
1131
1132 static int acpi_processor_power_verify(struct acpi_processor *pr)
1133 {
1134 unsigned int i;
1135 unsigned int working = 0;
1136
1137 pr->power.timer_broadcast_on_state = INT_MAX;
1138
1139 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
1140 struct acpi_processor_cx *cx = &pr->power.states[i];
1141
1142 switch (cx->type) {
1143 case ACPI_STATE_C1:
1144 cx->valid = 1;
1145 break;
1146
1147 case ACPI_STATE_C2:
1148 acpi_processor_power_verify_c2(cx);
1149 if (cx->valid)
1150 acpi_timer_check_state(i, pr, cx);
1151 break;
1152
1153 case ACPI_STATE_C3:
1154 acpi_processor_power_verify_c3(pr, cx);
1155 if (cx->valid)
1156 acpi_timer_check_state(i, pr, cx);
1157 break;
1158 }
1159
1160 if (cx->valid)
1161 working++;
1162 }
1163
1164 acpi_propagate_timer_broadcast(pr);
1165
1166 return (working);
1167 }
1168
1169 static int acpi_processor_get_power_info(struct acpi_processor *pr)
1170 {
1171 unsigned int i;
1172 int result;
1173
1174
1175 /* NOTE: the idle thread may not be running while calling
1176 * this function */
1177
1178 /* Zero initialize all the C-states info. */
1179 memset(pr->power.states, 0, sizeof(pr->power.states));
1180
1181 result = acpi_processor_get_power_info_cst(pr);
1182 if (result == -ENODEV)
1183 result = acpi_processor_get_power_info_fadt(pr);
1184
1185 if (result)
1186 return result;
1187
1188 acpi_processor_get_power_info_default(pr);
1189
1190 pr->power.count = acpi_processor_power_verify(pr);
1191
1192 #ifndef CONFIG_CPU_IDLE
1193 /*
1194 * Set Default Policy
1195 * ------------------
1196 * Now that we know which states are supported, set the default
1197 * policy. Note that this policy can be changed dynamically
1198 * (e.g. encourage deeper sleeps to conserve battery life when
1199 * not on AC).
1200 */
1201 result = acpi_processor_set_power_policy(pr);
1202 if (result)
1203 return result;
1204 #endif
1205
1206 /*
1207 * if one state of type C2 or C3 is available, mark this
1208 * CPU as being "idle manageable"
1209 */
1210 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
1211 if (pr->power.states[i].valid) {
1212 pr->power.count = i;
1213 if (pr->power.states[i].type >= ACPI_STATE_C2)
1214 pr->flags.power = 1;
1215 }
1216 }
1217
1218 return 0;
1219 }
1220
1221 static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset)
1222 {
1223 struct acpi_processor *pr = seq->private;
1224 unsigned int i;
1225
1226
1227 if (!pr)
1228 goto end;
1229
1230 seq_printf(seq, "active state: C%zd\n"
1231 "max_cstate: C%d\n"
1232 "bus master activity: %08x\n"
1233 "maximum allowed latency: %d usec\n",
1234 pr->power.state ? pr->power.state - pr->power.states : 0,
1235 max_cstate, (unsigned)pr->power.bm_activity,
1236 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY));
1237
1238 seq_puts(seq, "states:\n");
1239
1240 for (i = 1; i <= pr->power.count; i++) {
1241 seq_printf(seq, " %cC%d: ",
1242 (&pr->power.states[i] ==
1243 pr->power.state ? '*' : ' '), i);
1244
1245 if (!pr->power.states[i].valid) {
1246 seq_puts(seq, "<not supported>\n");
1247 continue;
1248 }
1249
1250 switch (pr->power.states[i].type) {
1251 case ACPI_STATE_C1:
1252 seq_printf(seq, "type[C1] ");
1253 break;
1254 case ACPI_STATE_C2:
1255 seq_printf(seq, "type[C2] ");
1256 break;
1257 case ACPI_STATE_C3:
1258 seq_printf(seq, "type[C3] ");
1259 break;
1260 default:
1261 seq_printf(seq, "type[--] ");
1262 break;
1263 }
1264
1265 if (pr->power.states[i].promotion.state)
1266 seq_printf(seq, "promotion[C%zd] ",
1267 (pr->power.states[i].promotion.state -
1268 pr->power.states));
1269 else
1270 seq_puts(seq, "promotion[--] ");
1271
1272 if (pr->power.states[i].demotion.state)
1273 seq_printf(seq, "demotion[C%zd] ",
1274 (pr->power.states[i].demotion.state -
1275 pr->power.states));
1276 else
1277 seq_puts(seq, "demotion[--] ");
1278
1279 seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n",
1280 pr->power.states[i].latency,
1281 pr->power.states[i].usage,
1282 (unsigned long long)pr->power.states[i].time);
1283 }
1284
1285 end:
1286 return 0;
1287 }
1288
1289 static int acpi_processor_power_open_fs(struct inode *inode, struct file *file)
1290 {
1291 return single_open(file, acpi_processor_power_seq_show,
1292 PDE(inode)->data);
1293 }
1294
1295 static const struct file_operations acpi_processor_power_fops = {
1296 .owner = THIS_MODULE,
1297 .open = acpi_processor_power_open_fs,
1298 .read = seq_read,
1299 .llseek = seq_lseek,
1300 .release = single_release,
1301 };
1302
1303 #ifndef CONFIG_CPU_IDLE
1304
1305 int acpi_processor_cst_has_changed(struct acpi_processor *pr)
1306 {
1307 int result = 0;
1308
1309 if (boot_option_idle_override)
1310 return 0;
1311
1312 if (!pr)
1313 return -EINVAL;
1314
1315 if (nocst) {
1316 return -ENODEV;
1317 }
1318
1319 if (!pr->flags.power_setup_done)
1320 return -ENODEV;
1321
1322 /*
1323 * Fall back to the default idle loop, when pm_idle_save had
1324 * been initialized.
1325 */
1326 if (pm_idle_save) {
1327 pm_idle = pm_idle_save;
1328 /* Relies on interrupts forcing exit from idle. */
1329 synchronize_sched();
1330 }
1331
1332 pr->flags.power = 0;
1333 result = acpi_processor_get_power_info(pr);
1334 if ((pr->flags.power == 1) && (pr->flags.power_setup_done))
1335 pm_idle = acpi_processor_idle;
1336
1337 return result;
1338 }
1339
1340 #ifdef CONFIG_SMP
1341 static void smp_callback(void *v)
1342 {
1343 /* we already woke the CPU up, nothing more to do */
1344 }
1345
1346 /*
1347 * This function gets called when a part of the kernel has a new latency
1348 * requirement. This means we need to get all processors out of their C-state,
1349 * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that
1350 * wakes them all right up.
1351 */
1352 static int acpi_processor_latency_notify(struct notifier_block *b,
1353 unsigned long l, void *v)
1354 {
1355 smp_call_function(smp_callback, NULL, 1);
1356 return NOTIFY_OK;
1357 }
1358
1359 static struct notifier_block acpi_processor_latency_notifier = {
1360 .notifier_call = acpi_processor_latency_notify,
1361 };
1362
1363 #endif
1364
1365 #else /* CONFIG_CPU_IDLE */
1366
1367 /**
1368 * acpi_idle_bm_check - checks if bus master activity was detected
1369 */
1370 static int acpi_idle_bm_check(void)
1371 {
1372 u32 bm_status = 0;
1373
1374 acpi_get_register_unlocked(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
1375 if (bm_status)
1376 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
1377 /*
1378 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
1379 * the true state of bus mastering activity; forcing us to
1380 * manually check the BMIDEA bit of each IDE channel.
1381 */
1382 else if (errata.piix4.bmisx) {
1383 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
1384 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
1385 bm_status = 1;
1386 }
1387 return bm_status;
1388 }
1389
1390 /**
1391 * acpi_idle_do_entry - a helper function that does C2 and C3 type entry
1392 * @cx: cstate data
1393 *
1394 * Caller disables interrupt before call and enables interrupt after return.
1395 */
1396 static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx)
1397 {
1398 /* Don't trace irqs off for idle */
1399 stop_critical_timings();
1400 if (cx->entry_method == ACPI_CSTATE_FFH) {
1401 /* Call into architectural FFH based C-state */
1402 acpi_processor_ffh_cstate_enter(cx);
1403 } else if (cx->entry_method == ACPI_CSTATE_HALT) {
1404 acpi_safe_halt();
1405 } else {
1406 int unused;
1407 /* IO port based C-state */
1408 inb(cx->address);
1409 /* Dummy wait op - must do something useless after P_LVL2 read
1410 because chipsets cannot guarantee that STPCLK# signal
1411 gets asserted in time to freeze execution properly. */
1412 unused = inl(acpi_gbl_FADT.xpm_timer_block.address);
1413 }
1414 start_critical_timings();
1415 }
1416
1417 /**
1418 * acpi_idle_enter_c1 - enters an ACPI C1 state-type
1419 * @dev: the target CPU
1420 * @state: the state data
1421 *
1422 * This is equivalent to the HALT instruction.
1423 */
1424 static int acpi_idle_enter_c1(struct cpuidle_device *dev,
1425 struct cpuidle_state *state)
1426 {
1427 u32 t1, t2;
1428 struct acpi_processor *pr;
1429 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1430
1431 pr = __get_cpu_var(processors);
1432
1433 if (unlikely(!pr))
1434 return 0;
1435
1436 local_irq_disable();
1437
1438 /* Do not access any ACPI IO ports in suspend path */
1439 if (acpi_idle_suspend) {
1440 acpi_safe_halt();
1441 local_irq_enable();
1442 return 0;
1443 }
1444
1445 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1446 acpi_idle_do_entry(cx);
1447 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1448
1449 local_irq_enable();
1450 cx->usage++;
1451
1452 return ticks_elapsed_in_us(t1, t2);
1453 }
1454
1455 /**
1456 * acpi_idle_enter_simple - enters an ACPI state without BM handling
1457 * @dev: the target CPU
1458 * @state: the state data
1459 */
1460 static int acpi_idle_enter_simple(struct cpuidle_device *dev,
1461 struct cpuidle_state *state)
1462 {
1463 struct acpi_processor *pr;
1464 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1465 u32 t1, t2;
1466 int sleep_ticks = 0;
1467
1468 pr = __get_cpu_var(processors);
1469
1470 if (unlikely(!pr))
1471 return 0;
1472
1473 if (acpi_idle_suspend)
1474 return(acpi_idle_enter_c1(dev, state));
1475
1476 local_irq_disable();
1477 current_thread_info()->status &= ~TS_POLLING;
1478 /*
1479 * TS_POLLING-cleared state must be visible before we test
1480 * NEED_RESCHED:
1481 */
1482 smp_mb();
1483
1484 if (unlikely(need_resched())) {
1485 current_thread_info()->status |= TS_POLLING;
1486 local_irq_enable();
1487 return 0;
1488 }
1489
1490 /*
1491 * Must be done before busmaster disable as we might need to
1492 * access HPET !
1493 */
1494 acpi_state_timer_broadcast(pr, cx, 1);
1495
1496 if (cx->type == ACPI_STATE_C3)
1497 ACPI_FLUSH_CPU_CACHE();
1498
1499 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1500 /* Tell the scheduler that we are going deep-idle: */
1501 sched_clock_idle_sleep_event();
1502 acpi_idle_do_entry(cx);
1503 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1504
1505 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
1506 /* TSC could halt in idle, so notify users */
1507 if (tsc_halts_in_c(cx->type))
1508 mark_tsc_unstable("TSC halts in idle");;
1509 #endif
1510 sleep_ticks = ticks_elapsed(t1, t2);
1511
1512 /* Tell the scheduler how much we idled: */
1513 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
1514
1515 local_irq_enable();
1516 current_thread_info()->status |= TS_POLLING;
1517
1518 cx->usage++;
1519
1520 acpi_state_timer_broadcast(pr, cx, 0);
1521 cx->time += sleep_ticks;
1522 return ticks_elapsed_in_us(t1, t2);
1523 }
1524
1525 static int c3_cpu_count;
1526 static DEFINE_SPINLOCK(c3_lock);
1527
1528 /**
1529 * acpi_idle_enter_bm - enters C3 with proper BM handling
1530 * @dev: the target CPU
1531 * @state: the state data
1532 *
1533 * If BM is detected, the deepest non-C3 idle state is entered instead.
1534 */
1535 static int acpi_idle_enter_bm(struct cpuidle_device *dev,
1536 struct cpuidle_state *state)
1537 {
1538 struct acpi_processor *pr;
1539 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1540 u32 t1, t2;
1541 int sleep_ticks = 0;
1542
1543 pr = __get_cpu_var(processors);
1544
1545 if (unlikely(!pr))
1546 return 0;
1547
1548 if (acpi_idle_suspend)
1549 return(acpi_idle_enter_c1(dev, state));
1550
1551 if (acpi_idle_bm_check()) {
1552 if (dev->safe_state) {
1553 dev->last_state = dev->safe_state;
1554 return dev->safe_state->enter(dev, dev->safe_state);
1555 } else {
1556 local_irq_disable();
1557 acpi_safe_halt();
1558 local_irq_enable();
1559 return 0;
1560 }
1561 }
1562
1563 local_irq_disable();
1564 current_thread_info()->status &= ~TS_POLLING;
1565 /*
1566 * TS_POLLING-cleared state must be visible before we test
1567 * NEED_RESCHED:
1568 */
1569 smp_mb();
1570
1571 if (unlikely(need_resched())) {
1572 current_thread_info()->status |= TS_POLLING;
1573 local_irq_enable();
1574 return 0;
1575 }
1576
1577 acpi_unlazy_tlb(smp_processor_id());
1578
1579 /* Tell the scheduler that we are going deep-idle: */
1580 sched_clock_idle_sleep_event();
1581 /*
1582 * Must be done before busmaster disable as we might need to
1583 * access HPET !
1584 */
1585 acpi_state_timer_broadcast(pr, cx, 1);
1586
1587 /*
1588 * disable bus master
1589 * bm_check implies we need ARB_DIS
1590 * !bm_check implies we need cache flush
1591 * bm_control implies whether we can do ARB_DIS
1592 *
1593 * That leaves a case where bm_check is set and bm_control is
1594 * not set. In that case we cannot do much, we enter C3
1595 * without doing anything.
1596 */
1597 if (pr->flags.bm_check && pr->flags.bm_control) {
1598 spin_lock(&c3_lock);
1599 c3_cpu_count++;
1600 /* Disable bus master arbitration when all CPUs are in C3 */
1601 if (c3_cpu_count == num_online_cpus())
1602 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
1603 spin_unlock(&c3_lock);
1604 } else if (!pr->flags.bm_check) {
1605 ACPI_FLUSH_CPU_CACHE();
1606 }
1607
1608 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1609 acpi_idle_do_entry(cx);
1610 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1611
1612 /* Re-enable bus master arbitration */
1613 if (pr->flags.bm_check && pr->flags.bm_control) {
1614 spin_lock(&c3_lock);
1615 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
1616 c3_cpu_count--;
1617 spin_unlock(&c3_lock);
1618 }
1619
1620 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
1621 /* TSC could halt in idle, so notify users */
1622 if (tsc_halts_in_c(ACPI_STATE_C3))
1623 mark_tsc_unstable("TSC halts in idle");
1624 #endif
1625 sleep_ticks = ticks_elapsed(t1, t2);
1626 /* Tell the scheduler how much we idled: */
1627 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
1628
1629 local_irq_enable();
1630 current_thread_info()->status |= TS_POLLING;
1631
1632 cx->usage++;
1633
1634 acpi_state_timer_broadcast(pr, cx, 0);
1635 cx->time += sleep_ticks;
1636 return ticks_elapsed_in_us(t1, t2);
1637 }
1638
1639 struct cpuidle_driver acpi_idle_driver = {
1640 .name = "acpi_idle",
1641 .owner = THIS_MODULE,
1642 };
1643
1644 /**
1645 * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE
1646 * @pr: the ACPI processor
1647 */
1648 static int acpi_processor_setup_cpuidle(struct acpi_processor *pr)
1649 {
1650 int i, count = CPUIDLE_DRIVER_STATE_START;
1651 struct acpi_processor_cx *cx;
1652 struct cpuidle_state *state;
1653 struct cpuidle_device *dev = &pr->power.dev;
1654
1655 if (!pr->flags.power_setup_done)
1656 return -EINVAL;
1657
1658 if (pr->flags.power == 0) {
1659 return -EINVAL;
1660 }
1661
1662 dev->cpu = pr->id;
1663 for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
1664 dev->states[i].name[0] = '\0';
1665 dev->states[i].desc[0] = '\0';
1666 }
1667
1668 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) {
1669 cx = &pr->power.states[i];
1670 state = &dev->states[count];
1671
1672 if (!cx->valid)
1673 continue;
1674
1675 #ifdef CONFIG_HOTPLUG_CPU
1676 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
1677 !pr->flags.has_cst &&
1678 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
1679 continue;
1680 #endif
1681 cpuidle_set_statedata(state, cx);
1682
1683 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i);
1684 strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
1685 state->exit_latency = cx->latency;
1686 state->target_residency = cx->latency * latency_factor;
1687 state->power_usage = cx->power;
1688
1689 state->flags = 0;
1690 switch (cx->type) {
1691 case ACPI_STATE_C1:
1692 state->flags |= CPUIDLE_FLAG_SHALLOW;
1693 if (cx->entry_method == ACPI_CSTATE_FFH)
1694 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1695
1696 state->enter = acpi_idle_enter_c1;
1697 dev->safe_state = state;
1698 break;
1699
1700 case ACPI_STATE_C2:
1701 state->flags |= CPUIDLE_FLAG_BALANCED;
1702 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1703 state->enter = acpi_idle_enter_simple;
1704 dev->safe_state = state;
1705 break;
1706
1707 case ACPI_STATE_C3:
1708 state->flags |= CPUIDLE_FLAG_DEEP;
1709 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1710 state->flags |= CPUIDLE_FLAG_CHECK_BM;
1711 state->enter = pr->flags.bm_check ?
1712 acpi_idle_enter_bm :
1713 acpi_idle_enter_simple;
1714 break;
1715 }
1716
1717 count++;
1718 if (count == CPUIDLE_STATE_MAX)
1719 break;
1720 }
1721
1722 dev->state_count = count;
1723
1724 if (!count)
1725 return -EINVAL;
1726
1727 return 0;
1728 }
1729
1730 int acpi_processor_cst_has_changed(struct acpi_processor *pr)
1731 {
1732 int ret = 0;
1733
1734 if (boot_option_idle_override)
1735 return 0;
1736
1737 if (!pr)
1738 return -EINVAL;
1739
1740 if (nocst) {
1741 return -ENODEV;
1742 }
1743
1744 if (!pr->flags.power_setup_done)
1745 return -ENODEV;
1746
1747 cpuidle_pause_and_lock();
1748 cpuidle_disable_device(&pr->power.dev);
1749 acpi_processor_get_power_info(pr);
1750 if (pr->flags.power) {
1751 acpi_processor_setup_cpuidle(pr);
1752 ret = cpuidle_enable_device(&pr->power.dev);
1753 }
1754 cpuidle_resume_and_unlock();
1755
1756 return ret;
1757 }
1758
1759 #endif /* CONFIG_CPU_IDLE */
1760
1761 int __cpuinit acpi_processor_power_init(struct acpi_processor *pr,
1762 struct acpi_device *device)
1763 {
1764 acpi_status status = 0;
1765 static int first_run;
1766 struct proc_dir_entry *entry = NULL;
1767 unsigned int i;
1768
1769 if (boot_option_idle_override)
1770 return 0;
1771
1772 if (!first_run) {
1773 if (idle_halt) {
1774 /*
1775 * When the boot option of "idle=halt" is added, halt
1776 * is used for CPU IDLE.
1777 * In such case C2/C3 is meaningless. So the max_cstate
1778 * is set to one.
1779 */
1780 max_cstate = 1;
1781 }
1782 dmi_check_system(processor_power_dmi_table);
1783 max_cstate = acpi_processor_cstate_check(max_cstate);
1784 if (max_cstate < ACPI_C_STATES_MAX)
1785 printk(KERN_NOTICE
1786 "ACPI: processor limited to max C-state %d\n",
1787 max_cstate);
1788 first_run++;
1789 #if !defined(CONFIG_CPU_IDLE) && defined(CONFIG_SMP)
1790 pm_qos_add_notifier(PM_QOS_CPU_DMA_LATENCY,
1791 &acpi_processor_latency_notifier);
1792 #endif
1793 }
1794
1795 if (!pr)
1796 return -EINVAL;
1797
1798 if (acpi_gbl_FADT.cst_control && !nocst) {
1799 status =
1800 acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8);
1801 if (ACPI_FAILURE(status)) {
1802 ACPI_EXCEPTION((AE_INFO, status,
1803 "Notifying BIOS of _CST ability failed"));
1804 }
1805 }
1806
1807 acpi_processor_get_power_info(pr);
1808 pr->flags.power_setup_done = 1;
1809
1810 /*
1811 * Install the idle handler if processor power management is supported.
1812 * Note that we use previously set idle handler will be used on
1813 * platforms that only support C1.
1814 */
1815 if (pr->flags.power) {
1816 #ifdef CONFIG_CPU_IDLE
1817 acpi_processor_setup_cpuidle(pr);
1818 if (cpuidle_register_device(&pr->power.dev))
1819 return -EIO;
1820 #endif
1821
1822 printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id);
1823 for (i = 1; i <= pr->power.count; i++)
1824 if (pr->power.states[i].valid)
1825 printk(" C%d[C%d]", i,
1826 pr->power.states[i].type);
1827 printk(")\n");
1828
1829 #ifndef CONFIG_CPU_IDLE
1830 if (pr->id == 0) {
1831 pm_idle_save = pm_idle;
1832 pm_idle = acpi_processor_idle;
1833 }
1834 #endif
1835 }
1836
1837 /* 'power' [R] */
1838 entry = proc_create_data(ACPI_PROCESSOR_FILE_POWER,
1839 S_IRUGO, acpi_device_dir(device),
1840 &acpi_processor_power_fops,
1841 acpi_driver_data(device));
1842 if (!entry)
1843 return -EIO;
1844 return 0;
1845 }
1846
1847 int acpi_processor_power_exit(struct acpi_processor *pr,
1848 struct acpi_device *device)
1849 {
1850 if (boot_option_idle_override)
1851 return 0;
1852
1853 #ifdef CONFIG_CPU_IDLE
1854 cpuidle_unregister_device(&pr->power.dev);
1855 #endif
1856 pr->flags.power_setup_done = 0;
1857
1858 if (acpi_device_dir(device))
1859 remove_proc_entry(ACPI_PROCESSOR_FILE_POWER,
1860 acpi_device_dir(device));
1861
1862 #ifndef CONFIG_CPU_IDLE
1863
1864 /* Unregister the idle handler when processor #0 is removed. */
1865 if (pr->id == 0) {
1866 if (pm_idle_save)
1867 pm_idle = pm_idle_save;
1868
1869 /*
1870 * We are about to unload the current idle thread pm callback
1871 * (pm_idle), Wait for all processors to update cached/local
1872 * copies of pm_idle before proceeding.
1873 */
1874 cpu_idle_wait();
1875 #ifdef CONFIG_SMP
1876 pm_qos_remove_notifier(PM_QOS_CPU_DMA_LATENCY,
1877 &acpi_processor_latency_notifier);
1878 #endif
1879 }
1880 #endif
1881
1882 return 0;
1883 }
kernel source for telekom puls (alcatel/mediatek)