bcmdhd.100.10.315.x/include/bcmsdstd.h

   1 /*
   2  *  'Standard' SDIO HOST CONTROLLER driver
   3  *
   4  * Copyright (C) 1999-2019, Broadcom.
   5  *
   6  *      Unless you and Broadcom execute a separate written software license
   7  * agreement governing use of this software, this software is licensed to you
   8  * under the terms of the GNU General Public License version 2 (the "GPL"),
   9  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
  10  * following added to such license:
  11  *
  12  *      As a special exception, the copyright holders of this software give you
  13  * permission to link this software with independent modules, and to copy and
  14  * distribute the resulting executable under terms of your choice, provided that
  15  * you also meet, for each linked independent module, the terms and conditions of
  16  * the license of that module.  An independent module is a module which is not
  17  * derived from this software.  The special exception does not apply to any
  18  * modifications of the software.
  19  *
  20  *      Notwithstanding the above, under no circumstances may you combine this
  21  * software in any way with any other Broadcom software provided under a license
  22  * other than the GPL, without Broadcom's express prior written consent.
  23  *
  24  *
  25  * <<Broadcom-WL-IPTag/Open:>>
  26  *
  27  * $Id: bcmsdstd.h 768214 2018-06-19 03:53:58Z $
  28  */
  29 #ifndef _BCM_SD_STD_H
  30 #define _BCM_SD_STD_H
  31
  32 /* global msglevel for debug messages - bitvals come from sdiovar.h */
  33 #define sd_err(x)       do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0)
  34 #define sd_trace(x)
  35 #define sd_info(x)
  36 #define sd_debug(x)
  37 #define sd_data(x)
  38 #define sd_ctrl(x)
  39 #define sd_dma(x)
  40
  41 #define sd_sync_dma(sd, read, nbytes)
  42 #define sd_init_dma(sd)
  43 #define sd_ack_intr(sd)
  44 #define sd_wakeup(sd);
  45 /* Allocate/init/free per-OS private data */
  46 extern int sdstd_osinit(sdioh_info_t *sd);
  47 extern void sdstd_osfree(sdioh_info_t *sd);
  48
  49 #define sd_log(x)
  50
  51 #define SDIOH_ASSERT(exp) \
  52         do { if (!(exp)) \
  53                 printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
  54         } while (0)
  55
  56 #define BLOCK_SIZE_4318 64
  57 #define BLOCK_SIZE_4328 512
  58
  59 /* internal return code */
  60 #define SUCCESS 0
  61 #define ERROR   1
  62
  63 /* private bus modes */
  64 #define SDIOH_MODE_SPI          0
  65 #define SDIOH_MODE_SD1          1
  66 #define SDIOH_MODE_SD4          2
  67
  68 #define MAX_SLOTS 6     /* For PCI: Only 6 BAR entries => 6 slots */
  69 #define SDIOH_REG_WINSZ 0x100 /* Number of registers in Standard Host Controller */
  70
  71 #define SDIOH_TYPE_ARASAN_HDK   1
  72 #define SDIOH_TYPE_BCM27XX      2
  73 #define SDIOH_TYPE_TI_PCIXX21   4       /* TI PCIxx21 Standard Host Controller */
  74 #define SDIOH_TYPE_RICOH_R5C822 5       /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter */
  75 #define SDIOH_TYPE_JMICRON      6       /* JMicron Standard SDIO Host Controller */
  76
  77 /* For linux, allow yielding for dongle */
  78 #define BCMSDYIELD
  79
  80 /* Expected card status value for CMD7 */
  81 #define SDIOH_CMD7_EXP_STATUS   0x00001E00
  82
  83 #define RETRIES_LARGE 100000
  84 #define sdstd_os_yield(sd)      do {} while (0)
  85 #define RETRIES_SMALL 100
  86
  87 #define USE_BLOCKMODE           0x2     /* Block mode can be single block or multi */
  88 #define USE_MULTIBLOCK          0x4
  89
  90 #define USE_FIFO                0x8     /* Fifo vs non-fifo */
  91
  92 #define CLIENT_INTR             0x100   /* Get rid of this! */
  93
  94 #define HC_INTR_RETUNING        0x1000
  95
  96 #ifdef BCMSDIOH_TXGLOM
  97 /* Total glom pkt can not exceed 64K
  98  * need one more slot for glom padding packet
  99  */
 100 #define SDIOH_MAXGLOM_SIZE      (40+1)
 101
 102 typedef struct glom_buf {
 103         uint32 count;                           /* Total number of pkts queued */
 104         void *dma_buf_arr[SDIOH_MAXGLOM_SIZE];  /* Frame address */
 105         ulong dma_phys_arr[SDIOH_MAXGLOM_SIZE]; /* DMA_MAPed address of frames */
 106         uint16 nbytes[SDIOH_MAXGLOM_SIZE];      /* Size of each frame */
 107 } glom_buf_t;
 108 #endif // endif
 109
 110 struct sdioh_info {
 111         uint cfg_bar;                           /* pci cfg address for bar */
 112         uint32 caps;                            /* cached value of capabilities reg */
 113         uint32 curr_caps;                       /* max current capabilities reg */
 114
 115         osl_t           *osh;                   /* osh handler */
 116         volatile char   *mem_space;             /* pci device memory va */
 117         uint            lockcount;              /* nest count of sdstd_lock() calls */
 118         bool            client_intr_enabled;    /* interrupt connnected flag */
 119         bool            intr_handler_valid;     /* client driver interrupt handler valid */
 120         sdioh_cb_fn_t   intr_handler;           /* registered interrupt handler */
 121         void            *intr_handler_arg;      /* argument to call interrupt handler */
 122         bool            initialized;            /* card initialized */
 123         uint            target_dev;             /* Target device ID */
 124         uint16          intmask;                /* Current active interrupts */
 125         void            *sdos_info;             /* Pointer to per-OS private data */
 126         void            *bcmsdh;                /* handler to upper layer stack (bcmsdh) */
 127
 128         uint32          controller_type;        /* Host controller type */
 129         uint8           version;                /* Host Controller Spec Compliance Version */
 130         uint            irq;                    /* Client irq */
 131         int             intrcount;              /* Client interrupts */
 132         int             local_intrcount;        /* Controller interrupts */
 133         bool            host_init_done;         /* Controller initted */
 134         bool            card_init_done;         /* Client SDIO interface initted */
 135         bool            polled_mode;            /* polling for command completion */
 136
 137         bool            sd_blockmode;           /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
 138                                                 /*  Must be on for sd_multiblock to be effective */
 139         bool            use_client_ints;        /* If this is false, make sure to restore */
 140                                                 /*  polling hack in wl_linux.c:wl_timer() */
 141         int             adapter_slot;           /* Maybe dealing with multiple slots/controllers */
 142         int             sd_mode;                /* SD1/SD4/SPI */
 143         int             client_block_size[SDIOD_MAX_IOFUNCS];           /* Blocksize */
 144         uint32          data_xfer_count;        /* Current transfer */
 145         uint16          card_rca;               /* Current Address */
 146         int8            sd_dma_mode;            /* DMA Mode (PIO, SDMA, ... ADMA2) on CMD53 */
 147         uint8           num_funcs;              /* Supported funcs on client */
 148         uint32          com_cis_ptr;
 149         uint32          func_cis_ptr[SDIOD_MAX_IOFUNCS];
 150         void            *dma_buf;               /* DMA Buffer virtual address */
 151         ulong           dma_phys;               /* DMA Buffer physical address */
 152         void            *adma2_dscr_buf;        /* ADMA2 Descriptor Buffer virtual address */
 153         ulong           adma2_dscr_phys;        /* ADMA2 Descriptor Buffer physical address */
 154
 155         /* adjustments needed to make the dma align properly */
 156         void            *dma_start_buf;
 157         ulong           dma_start_phys;
 158         uint            alloced_dma_size;
 159         void            *adma2_dscr_start_buf;
 160         ulong           adma2_dscr_start_phys;
 161         uint            alloced_adma2_dscr_size;
 162
 163         int             r_cnt;                  /* rx count */
 164         int             t_cnt;                  /* tx_count */
 165         bool            got_hcint;              /* local interrupt flag */
 166         uint16          last_intrstatus;        /* to cache intrstatus */
 167         int     host_UHSISupported;             /* whether UHSI is supported for HC. */
 168         int     card_UHSI_voltage_Supported;    /* whether UHSI is supported for
 169                                                  * Card in terms of Voltage [1.8 or 3.3].
 170                                                  */
 171         int     global_UHSI_Supp;       /* type of UHSI support in both host and card.
 172                                          * HOST_SDR_UNSUPP: capabilities not supported/matched
 173                                          * HOST_SDR_12_25: SDR12 and SDR25 supported
 174                                          * HOST_SDR_50_104_DDR: one of SDR50/SDR104 or DDR50 supptd
 175                                          */
 176         volatile int    sd3_dat_state;          /* data transfer state used for retuning check */
 177         volatile int    sd3_tun_state;          /* tuning state used for retuning check */
 178         bool    sd3_tuning_reqd;        /* tuning requirement parameter */
 179         bool    sd3_tuning_disable;     /* tuning disable due to bus sleeping */
 180         uint32  caps3;                  /* cached value of 32 MSbits capabilities reg (SDIO 3.0) */
 181 #ifdef BCMSDIOH_TXGLOM
 182         glom_buf_t glom_info;           /* pkt information used for glomming */
 183         uint    txglom_mode;            /* Txglom mode: 0 - copy, 1 - multi-descriptor */
 184 #endif // endif
 185 };
 186
 187 #define DMA_MODE_NONE   0
 188 #define DMA_MODE_SDMA   1
 189 #define DMA_MODE_ADMA1  2
 190 #define DMA_MODE_ADMA2  3
 191 #define DMA_MODE_ADMA2_64 4
 192 #define DMA_MODE_AUTO   -1
 193
 194 #define USE_DMA(sd)             ((bool)((sd->sd_dma_mode > 0) ? TRUE : FALSE))
 195
 196 /* States for Tuning and corr data */
 197 #define TUNING_IDLE                     0
 198 #define TUNING_START                    1
 199 #define TUNING_START_AFTER_DAT  2
 200 #define TUNING_ONGOING                  3
 201
 202 #define DATA_TRANSFER_IDLE              0
 203 #define DATA_TRANSFER_ONGOING   1
 204
 205 #define CHECK_TUNING_PRE_DATA   1
 206 #define CHECK_TUNING_POST_DATA  2
 207
 208 #ifdef DHD_DEBUG
 209 #define SD_DHD_DISABLE_PERIODIC_TUNING 0x01
 210 #define SD_DHD_ENABLE_PERIODIC_TUNING  0x00
 211 #endif // endif
 212
 213 /************************************************************
 214  * Internal interfaces: per-port references into bcmsdstd.c
 215  */
 216
 217 /* Global message bits */
 218 extern uint sd_msglevel;
 219
 220 /* OS-independent interrupt handler */
 221 extern bool check_client_intr(sdioh_info_t *sd);
 222
 223 /* Core interrupt enable/disable of device interrupts */
 224 extern void sdstd_devintr_on(sdioh_info_t *sd);
 225 extern void sdstd_devintr_off(sdioh_info_t *sd);
 226
 227 /* Enable/disable interrupts for local controller events */
 228 extern void sdstd_intrs_on(sdioh_info_t *sd, uint16 norm, uint16 err);
 229 extern void sdstd_intrs_off(sdioh_info_t *sd, uint16 norm, uint16 err);
 230
 231 /* Wait for specified interrupt and error bits to be set */
 232 extern void sdstd_spinbits(sdioh_info_t *sd, uint16 norm, uint16 err);
 233
 234 /**************************************************************
 235  * Internal interfaces: bcmsdstd.c references to per-port code
 236  */
 237
 238 /* Register mapping routines */
 239 extern uint32 *sdstd_reg_map(osl_t *osh, ulong addr, int size);
 240 extern void sdstd_reg_unmap(osl_t *osh, ulong addr, int size);
 241
 242 /* Interrupt (de)registration routines */
 243 extern int sdstd_register_irq(sdioh_info_t *sd, uint irq);
 244 extern void sdstd_free_irq(uint irq, sdioh_info_t *sd);
 245
 246 /* OS-specific interrupt wrappers (atomic interrupt enable/disable) */
 247 extern void sdstd_lock(sdioh_info_t *sd);
 248 extern void sdstd_unlock(sdioh_info_t *sd);
 249 extern void sdstd_waitlockfree(sdioh_info_t *sd);
 250
 251 /* OS-specific wrappers for safe concurrent register access */
 252 extern void sdstd_os_lock_irqsave(sdioh_info_t *sd, ulong* flags);
 253 extern void sdstd_os_unlock_irqrestore(sdioh_info_t *sd, ulong* flags);
 254
 255 /* OS-specific wait-for-interrupt-or-status */
 256 extern int sdstd_waitbits(sdioh_info_t *sd, uint16 norm, uint16 err, bool yield, uint16 *bits);
 257
 258 /* used by bcmsdstd_linux [implemented in sdstd] */
 259 extern void sdstd_3_enable_retuning_int(sdioh_info_t *sd);
 260 extern void sdstd_3_disable_retuning_int(sdioh_info_t *sd);
 261 extern bool sdstd_3_is_retuning_int_set(sdioh_info_t *sd);
 262 extern void sdstd_3_check_and_do_tuning(sdioh_info_t *sd, int tuning_param);
 263 extern bool sdstd_3_check_and_set_retuning(sdioh_info_t *sd);
 264 extern int sdstd_3_get_tune_state(sdioh_info_t *sd);
 265 extern int sdstd_3_get_data_state(sdioh_info_t *sd);
 266 extern void sdstd_3_set_tune_state(sdioh_info_t *sd, int state);
 267 extern void sdstd_3_set_data_state(sdioh_info_t *sd, int state);
 268 extern uint8 sdstd_3_get_tuning_exp(sdioh_info_t *sd);
 269 extern uint32 sdstd_3_get_uhsi_clkmode(sdioh_info_t *sd);
 270 extern int sdstd_3_clk_tuning(sdioh_info_t *sd, uint32 sd3ClkMode);
 271
 272 /* used by sdstd [implemented in bcmsdstd_linux/ndis] */
 273 extern void sdstd_3_start_tuning(sdioh_info_t *sd);
 274 extern void sdstd_3_osinit_tuning(sdioh_info_t *sd);
 275 extern void sdstd_3_osclean_tuning(sdioh_info_t *sd);
 276
 277 extern void sdstd_enable_disable_periodic_timer(sdioh_info_t * sd, uint val);
 278
 279 extern sdioh_info_t *sdioh_attach(osl_t *osh, void *bar0, uint irq);
 280 extern SDIOH_API_RC sdioh_detach(osl_t *osh, sdioh_info_t *sd);
 281 #endif /* _BCM_SD_STD_H */