bcmdhd.1.363.59.144.x.cn/siutils_priv.h

   1 /*
   2  * Include file private to the SOC Interconnect support files.
   3  *
   4  * Copyright (C) 1999-2016, Broadcom Corporation
   5  *
   6  *      Unless you and Broadcom execute a separate written software license
   7  * agreement governing use of this software, this software is licensed to you
   8  * under the terms of the GNU General Public License version 2 (the "GPL"),
   9  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
  10  * following added to such license:
  11  *
  12  *      As a special exception, the copyright holders of this software give you
  13  * permission to link this software with independent modules, and to copy and
  14  * distribute the resulting executable under terms of your choice, provided that
  15  * you also meet, for each linked independent module, the terms and conditions of
  16  * the license of that module.  An independent module is a module which is not
  17  * derived from this software.  The special exception does not apply to any
  18  * modifications of the software.
  19  *
  20  *      Notwithstanding the above, under no circumstances may you combine this
  21  * software in any way with any other Broadcom software provided under a license
  22  * other than the GPL, without Broadcom's express prior written consent.
  23  *
  24  *
  25  * <<Broadcom-WL-IPTag/Open:>>
  26  *
  27  * $Id: siutils_priv.h 520760 2014-12-15 00:54:16Z $
  28  */
  29
  30 #ifndef _siutils_priv_h_
  31 #define _siutils_priv_h_
  32
  33 #define SI_ERROR(args) printf args
  34
  35 #define SI_MSG(args)
  36
  37 #ifdef BCMDBG_SI
  38 #define SI_VMSG(args)   printf args
  39 #else
  40 #define SI_VMSG(args)
  41 #endif
  42
  43 #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
  44
  45 typedef uint32 (*si_intrsoff_t)(void *intr_arg);
  46 typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg);
  47 typedef bool (*si_intrsenabled_t)(void *intr_arg);
  48
  49
  50 #define SI_GPIO_MAX             16
  51
  52 typedef struct gci_gpio_item {
  53         void                    *arg;
  54         uint8                   gci_gpio;
  55         uint8                   status;
  56         gci_gpio_handler_t      handler;
  57         struct gci_gpio_item    *next;
  58 } gci_gpio_item_t;
  59
  60
  61 typedef struct si_cores_info {
  62         void    *regs[SI_MAXCORES];     /* other regs va */
  63
  64         uint    coreid[SI_MAXCORES];    /* id of each core */
  65         uint32  coresba[SI_MAXCORES];   /* backplane address of each core */
  66         void    *regs2[SI_MAXCORES];    /* va of each core second register set (usbh20) */
  67         uint32  coresba2[SI_MAXCORES];  /* address of each core second register set (usbh20) */
  68         uint32  coresba_size[SI_MAXCORES]; /* backplane address space size */
  69         uint32  coresba2_size[SI_MAXCORES]; /* second address space size */
  70
  71         void    *wrappers[SI_MAXCORES]; /* other cores wrapper va */
  72         uint32  wrapba[SI_MAXCORES];    /* address of controlling wrapper */
  73
  74         void    *wrappers2[SI_MAXCORES];        /* other cores wrapper va */
  75         uint32  wrapba2[SI_MAXCORES];   /* address of controlling wrapper */
  76
  77         uint32  cia[SI_MAXCORES];       /* erom cia entry for each core */
  78         uint32  cib[SI_MAXCORES];       /* erom cia entry for each core */
  79 } si_cores_info_t;
  80
  81 /* misc si info needed by some of the routines */
  82 typedef struct si_info {
  83         struct si_pub pub;              /* back plane public state (must be first field) */
  84
  85         void    *osh;                   /* osl os handle */
  86         void    *sdh;                   /* bcmsdh handle */
  87
  88         uint    dev_coreid;             /* the core provides driver functions */
  89         void    *intr_arg;              /* interrupt callback function arg */
  90         si_intrsoff_t intrsoff_fn;      /* turns chip interrupts off */
  91         si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
  92         si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
  93
  94         void *pch;                      /* PCI/E core handle */
  95
  96         bool    memseg;                 /* flag to toggle MEM_SEG register */
  97
  98         char *vars;
  99         uint varsz;
 100
 101         void    *curmap;                /* current regs va */
 102
 103         uint    curidx;                 /* current core index */
 104         uint    numcores;               /* # discovered cores */
 105
 106         void    *curwrap;               /* current wrapper va */
 107
 108         uint32  oob_router;             /* oob router registers for axi */
 109
 110         void *cores_info;
 111         gci_gpio_item_t *gci_gpio_head; /* gci gpio interrupts head */
 112         uint    chipnew;                /* new chip number */
 113         uint second_bar0win;            /* Backplane region */
 114         uint    num_br;         /* # discovered bridges */
 115         uint32  br_wrapba[SI_MAXBR];    /* address of bridge controlling wrapper */
 116         uint32  xtalfreq;
 117 } si_info_t;
 118
 119
 120 #define SI_INFO(sih)    ((si_info_t *)(uintptr)sih)
 121
 122 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
 123                 ISALIGNED((x), SI_CORE_SIZE))
 124 #define GOODREGS(regs)  ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
 125 #define BADCOREADDR     0
 126 #define GOODIDX(idx)    (((uint)idx) < SI_MAXCORES)
 127 #define NOREV           -1              /* Invalid rev */
 128
 129 #define PCI(si)         ((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&     \
 130                          ((si)->pub.buscoretype == PCI_CORE_ID))
 131
 132 #define PCIE_GEN1(si)   ((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&     \
 133                          ((si)->pub.buscoretype == PCIE_CORE_ID))
 134
 135 #define PCIE_GEN2(si)   ((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&     \
 136                          ((si)->pub.buscoretype == PCIE2_CORE_ID))
 137
 138 #define PCIE(si)        (PCIE_GEN1(si) || PCIE_GEN2(si))
 139
 140 #define PCMCIA(si)      ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE))
 141
 142 /* Newer chips can access PCI/PCIE and CC core without requiring to change
 143  * PCI BAR0 WIN
 144  */
 145 #define SI_FAST(si) (PCIE(si) || (PCI(si) && ((si)->pub.buscorerev >= 13)))
 146
 147 #define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
 148 #define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
 149
 150 /*
 151  * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
 152  * after core switching to avoid invalid register accesss inside ISR.
 153  */
 154 #define INTR_OFF(si, intr_val) \
 155         if ((si)->intrsoff_fn && (cores_info)->coreid[(si)->curidx] == (si)->dev_coreid) {      \
 156                 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
 157 #define INTR_RESTORE(si, intr_val) \
 158         if ((si)->intrsrestore_fn && (cores_info)->coreid[(si)->curidx] == (si)->dev_coreid) {  \
 159                 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
 160
 161 /* dynamic clock control defines */
 162 #define LPOMINFREQ              25000           /* low power oscillator min */
 163 #define LPOMAXFREQ              43000           /* low power oscillator max */
 164 #define XTALMINFREQ             19800000        /* 20 MHz - 1% */
 165 #define XTALMAXFREQ             20200000        /* 20 MHz + 1% */
 166 #define PCIMINFREQ              25000000        /* 25 MHz */
 167 #define PCIMAXFREQ              34000000        /* 33 MHz + fudge */
 168
 169 #define ILP_DIV_5MHZ            0               /* ILP = 5 MHz */
 170 #define ILP_DIV_1MHZ            4               /* ILP = 1 MHz */
 171
 172 /* Force fast clock for 4360b0 */
 173 #define PCI_FORCEHT(si) \
 174         (((PCIE_GEN1(si)) && (CHIPID(si->pub.chip) == BCM4311_CHIP_ID) && \
 175         ((CHIPREV(si->pub.chiprev) <= 1))) || \
 176         ((PCI(si) || PCIE_GEN1(si)) && (CHIPID(si->pub.chip) == BCM4321_CHIP_ID)) || \
 177         (PCIE_GEN1(si) && (CHIPID(si->pub.chip) == BCM4716_CHIP_ID)) || \
 178         (PCIE_GEN1(si) && (CHIPID(si->pub.chip) == BCM4748_CHIP_ID)))
 179
 180 /* GPIO Based LED powersave defines */
 181 #define DEFAULT_GPIO_ONTIME     10              /* Default: 10% on */
 182 #define DEFAULT_GPIO_OFFTIME    90              /* Default: 10% on */
 183
 184 #ifndef DEFAULT_GPIOTIMERVAL
 185 #define DEFAULT_GPIOTIMERVAL  ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
 186 #endif
 187
 188 /* Silicon Backplane externs */
 189 extern void sb_scan(si_t *sih, void *regs, uint devid);
 190 extern uint sb_coreid(si_t *sih);
 191 extern uint sb_intflag(si_t *sih);
 192 extern uint sb_flag(si_t *sih);
 193 extern void sb_setint(si_t *sih, int siflag);
 194 extern uint sb_corevendor(si_t *sih);
 195 extern uint sb_corerev(si_t *sih);
 196 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
 197 extern uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff);
 198 extern bool sb_iscoreup(si_t *sih);
 199 extern void *sb_setcoreidx(si_t *sih, uint coreidx);
 200 extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val);
 201 extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
 202 extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val);
 203 extern void sb_commit(si_t *sih);
 204 extern uint32 sb_base(uint32 admatch);
 205 extern uint32 sb_size(uint32 admatch);
 206 extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
 207 extern void sb_core_disable(si_t *sih, uint32 bits);
 208 extern uint32 sb_addrspace(si_t *sih, uint asidx);
 209 extern uint32 sb_addrspacesize(si_t *sih, uint asidx);
 210 extern int sb_numaddrspaces(si_t *sih);
 211
 212 extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx);
 213
 214 extern bool sb_taclear(si_t *sih, bool details);
 215
 216 #if defined(BCMDBG_PHYDUMP)
 217 extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b);
 218 #endif
 219
 220 /* Wake-on-wireless-LAN (WOWL) */
 221 extern bool sb_pci_pmecap(si_t *sih);
 222 struct osl_info;
 223 extern bool sb_pci_fastpmecap(struct osl_info *osh);
 224 extern bool sb_pci_pmeclr(si_t *sih);
 225 extern void sb_pci_pmeen(si_t *sih);
 226 extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset);
 227
 228 /* AMBA Interconnect exported externs */
 229 extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
 230                        void *sdh, char **vars, uint *varsz);
 231 extern si_t *ai_kattach(osl_t *osh);
 232 extern void ai_scan(si_t *sih, void *regs, uint devid);
 233
 234 extern uint ai_flag(si_t *sih);
 235 extern uint ai_flag_alt(si_t *sih);
 236 extern void ai_setint(si_t *sih, int siflag);
 237 extern uint ai_coreidx(si_t *sih);
 238 extern uint ai_corevendor(si_t *sih);
 239 extern uint ai_corerev(si_t *sih);
 240 extern uint32 *ai_corereg_addr(si_t *sih, uint coreidx, uint regoff);
 241 extern bool ai_iscoreup(si_t *sih);
 242 extern void *ai_setcoreidx(si_t *sih, uint coreidx);
 243 extern void *ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx);
 244 extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val);
 245 extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
 246 extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val);
 247 extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
 248 extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
 249 extern void ai_d11rsdb_core_reset(si_t *sih, uint32 bits,
 250         uint32 resetbits, void *p, void *s);
 251 extern void ai_d11rsdb_core1_alt_reg_clk_en(si_t *sih);
 252 extern void ai_d11rsdb_core1_alt_reg_clk_dis(si_t *sih);
 253
 254 extern void ai_core_disable(si_t *sih, uint32 bits);
 255 extern void ai_d11rsdb_core_disable(const si_info_t *sii, uint32 bits,
 256         aidmp_t *pmacai, aidmp_t *smacai);
 257 extern int ai_numaddrspaces(si_t *sih);
 258 extern uint32 ai_addrspace(si_t *sih, uint asidx);
 259 extern uint32 ai_addrspacesize(si_t *sih, uint asidx);
 260 extern void ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
 261 extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
 262 extern void ai_enable_backplane_timeouts(si_t *sih);
 263 extern void ai_clear_backplane_to(si_t *sih);
 264
 265 #if defined(BCMDBG_PHYDUMP)
 266 extern void ai_dumpregs(si_t *sih, struct bcmstrbuf *b);
 267 #endif
 268
 269
 270 #define ub_scan(a, b, c) do {} while (0)
 271 #define ub_flag(a) (0)
 272 #define ub_setint(a, b) do {} while (0)
 273 #define ub_coreidx(a) (0)
 274 #define ub_corevendor(a) (0)
 275 #define ub_corerev(a) (0)
 276 #define ub_iscoreup(a) (0)
 277 #define ub_setcoreidx(a, b) (0)
 278 #define ub_core_cflags(a, b, c) (0)
 279 #define ub_core_cflags_wo(a, b, c) do {} while (0)
 280 #define ub_core_sflags(a, b, c) (0)
 281 #define ub_corereg(a, b, c, d, e) (0)
 282 #define ub_core_reset(a, b, c) do {} while (0)
 283 #define ub_core_disable(a, b) do {} while (0)
 284 #define ub_numaddrspaces(a) (0)
 285 #define ub_addrspace(a, b)  (0)
 286 #define ub_addrspacesize(a, b) (0)
 287 #define ub_view(a, b) do {} while (0)
 288 #define ub_dumpregs(a, b) do {} while (0)
 289
 290 #endif  /* _siutils_priv_h_ */