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Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / xtensa / kernel / entry.S
1 /*
2 * arch/xtensa/kernel/entry.S
3 *
4 * Low-level exception handling
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2004 - 2008 by Tensilica Inc.
11 *
12 * Chris Zankel <chris@zankel.net>
13 *
14 */
15
16 #include <linux/linkage.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/processor.h>
19 #include <asm/coprocessor.h>
20 #include <asm/thread_info.h>
21 #include <asm/uaccess.h>
22 #include <asm/unistd.h>
23 #include <asm/ptrace.h>
24 #include <asm/current.h>
25 #include <asm/pgtable.h>
26 #include <asm/page.h>
27 #include <asm/signal.h>
28 #include <asm/tlbflush.h>
29 #include <variant/tie-asm.h>
30
31 /* Unimplemented features. */
32
33 #undef KERNEL_STACK_OVERFLOW_CHECK
34 #undef PREEMPTIBLE_KERNEL
35 #undef ALLOCA_EXCEPTION_IN_IRAM
36
37 /* Not well tested.
38 *
39 * - fast_coprocessor
40 */
41
42 /*
43 * Macro to find first bit set in WINDOWBASE from the left + 1
44 *
45 * 100....0 -> 1
46 * 010....0 -> 2
47 * 000....1 -> WSBITS
48 */
49
50 .macro ffs_ws bit mask
51
52 #if XCHAL_HAVE_NSA
53 nsau \bit, \mask # 32-WSBITS ... 31 (32 iff 0)
54 addi \bit, \bit, WSBITS - 32 + 1 # uppest bit set -> return 1
55 #else
56 movi \bit, WSBITS
57 #if WSBITS > 16
58 _bltui \mask, 0x10000, 99f
59 addi \bit, \bit, -16
60 extui \mask, \mask, 16, 16
61 #endif
62 #if WSBITS > 8
63 99: _bltui \mask, 0x100, 99f
64 addi \bit, \bit, -8
65 srli \mask, \mask, 8
66 #endif
67 99: _bltui \mask, 0x10, 99f
68 addi \bit, \bit, -4
69 srli \mask, \mask, 4
70 99: _bltui \mask, 0x4, 99f
71 addi \bit, \bit, -2
72 srli \mask, \mask, 2
73 99: _bltui \mask, 0x2, 99f
74 addi \bit, \bit, -1
75 99:
76
77 #endif
78 .endm
79
80 /* ----------------- DEFAULT FIRST LEVEL EXCEPTION HANDLERS ----------------- */
81
82 /*
83 * First-level exception handler for user exceptions.
84 * Save some special registers, extra states and all registers in the AR
85 * register file that were in use in the user task, and jump to the common
86 * exception code.
87 * We save SAR (used to calculate WMASK), and WB and WS (we don't have to
88 * save them for kernel exceptions).
89 *
90 * Entry condition for user_exception:
91 *
92 * a0: trashed, original value saved on stack (PT_AREG0)
93 * a1: a1
94 * a2: new stack pointer, original value in depc
95 * a3: dispatch table
96 * depc: a2, original value saved on stack (PT_DEPC)
97 * excsave1: a3
98 *
99 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
100 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
101 *
102 * Entry condition for _user_exception:
103 *
104 * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC
105 * excsave has been restored, and
106 * stack pointer (a1) has been set.
107 *
108 * Note: _user_exception might be at an odd address. Don't use call0..call12
109 */
110
111 ENTRY(user_exception)
112
113 /* Save a2, a3, and depc, restore excsave_1 and set SP. */
114
115 xsr a3, excsave1
116 rsr a0, depc
117 s32i a1, a2, PT_AREG1
118 s32i a0, a2, PT_AREG2
119 s32i a3, a2, PT_AREG3
120 mov a1, a2
121
122 .globl _user_exception
123 _user_exception:
124
125 /* Save SAR and turn off single stepping */
126
127 movi a2, 0
128 rsr a3, sar
129 xsr a2, icountlevel
130 s32i a3, a1, PT_SAR
131 s32i a2, a1, PT_ICOUNTLEVEL
132
133 #if XCHAL_HAVE_THREADPTR
134 rur a2, threadptr
135 s32i a2, a1, PT_THREADPTR
136 #endif
137
138 /* Rotate ws so that the current windowbase is at bit0. */
139 /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
140
141 rsr a2, windowbase
142 rsr a3, windowstart
143 ssr a2
144 s32i a2, a1, PT_WINDOWBASE
145 s32i a3, a1, PT_WINDOWSTART
146 slli a2, a3, 32-WSBITS
147 src a2, a3, a2
148 srli a2, a2, 32-WSBITS
149 s32i a2, a1, PT_WMASK # needed for restoring registers
150
151 /* Save only live registers. */
152
153 _bbsi.l a2, 1, 1f
154 s32i a4, a1, PT_AREG4
155 s32i a5, a1, PT_AREG5
156 s32i a6, a1, PT_AREG6
157 s32i a7, a1, PT_AREG7
158 _bbsi.l a2, 2, 1f
159 s32i a8, a1, PT_AREG8
160 s32i a9, a1, PT_AREG9
161 s32i a10, a1, PT_AREG10
162 s32i a11, a1, PT_AREG11
163 _bbsi.l a2, 3, 1f
164 s32i a12, a1, PT_AREG12
165 s32i a13, a1, PT_AREG13
166 s32i a14, a1, PT_AREG14
167 s32i a15, a1, PT_AREG15
168 _bnei a2, 1, 1f # only one valid frame?
169
170 /* Only one valid frame, skip saving regs. */
171
172 j 2f
173
174 /* Save the remaining registers.
175 * We have to save all registers up to the first '1' from
176 * the right, except the current frame (bit 0).
177 * Assume a2 is: 001001000110001
178 * All register frames starting from the top field to the marked '1'
179 * must be saved.
180 */
181
182 1: addi a3, a2, -1 # eliminate '1' in bit 0: yyyyxxww0
183 neg a3, a3 # yyyyxxww0 -> YYYYXXWW1+1
184 and a3, a3, a2 # max. only one bit is set
185
186 /* Find number of frames to save */
187
188 ffs_ws a0, a3 # number of frames to the '1' from left
189
190 /* Store information into WMASK:
191 * bits 0..3: xxx1 masked lower 4 bits of the rotated windowstart,
192 * bits 4...: number of valid 4-register frames
193 */
194
195 slli a3, a0, 4 # number of frames to save in bits 8..4
196 extui a2, a2, 0, 4 # mask for the first 16 registers
197 or a2, a3, a2
198 s32i a2, a1, PT_WMASK # needed when we restore the reg-file
199
200 /* Save 4 registers at a time */
201
202 1: rotw -1
203 s32i a0, a5, PT_AREG_END - 16
204 s32i a1, a5, PT_AREG_END - 12
205 s32i a2, a5, PT_AREG_END - 8
206 s32i a3, a5, PT_AREG_END - 4
207 addi a0, a4, -1
208 addi a1, a5, -16
209 _bnez a0, 1b
210
211 /* WINDOWBASE still in SAR! */
212
213 rsr a2, sar # original WINDOWBASE
214 movi a3, 1
215 ssl a2
216 sll a3, a3
217 wsr a3, windowstart # set corresponding WINDOWSTART bit
218 wsr a2, windowbase # and WINDOWSTART
219 rsync
220
221 /* We are back to the original stack pointer (a1) */
222
223 2: /* Now, jump to the common exception handler. */
224
225 j common_exception
226
227 ENDPROC(user_exception)
228
229 /*
230 * First-level exit handler for kernel exceptions
231 * Save special registers and the live window frame.
232 * Note: Even though we changes the stack pointer, we don't have to do a
233 * MOVSP here, as we do that when we return from the exception.
234 * (See comment in the kernel exception exit code)
235 *
236 * Entry condition for kernel_exception:
237 *
238 * a0: trashed, original value saved on stack (PT_AREG0)
239 * a1: a1
240 * a2: new stack pointer, original in DEPC
241 * a3: dispatch table
242 * depc: a2, original value saved on stack (PT_DEPC)
243 * excsave_1: a3
244 *
245 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
246 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
247 *
248 * Entry condition for _kernel_exception:
249 *
250 * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC
251 * excsave has been restored, and
252 * stack pointer (a1) has been set.
253 *
254 * Note: _kernel_exception might be at an odd address. Don't use call0..call12
255 */
256
257 ENTRY(kernel_exception)
258
259 /* Save a0, a2, a3, DEPC and set SP. */
260
261 xsr a3, excsave1 # restore a3, excsave_1
262 rsr a0, depc # get a2
263 s32i a1, a2, PT_AREG1
264 s32i a0, a2, PT_AREG2
265 s32i a3, a2, PT_AREG3
266 mov a1, a2
267
268 .globl _kernel_exception
269 _kernel_exception:
270
271 /* Save SAR and turn off single stepping */
272
273 movi a2, 0
274 rsr a3, sar
275 xsr a2, icountlevel
276 s32i a3, a1, PT_SAR
277 s32i a2, a1, PT_ICOUNTLEVEL
278
279 /* Rotate ws so that the current windowbase is at bit0. */
280 /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
281
282 rsr a2, windowbase # don't need to save these, we only
283 rsr a3, windowstart # need shifted windowstart: windowmask
284 ssr a2
285 slli a2, a3, 32-WSBITS
286 src a2, a3, a2
287 srli a2, a2, 32-WSBITS
288 s32i a2, a1, PT_WMASK # needed for kernel_exception_exit
289
290 /* Save only the live window-frame */
291
292 _bbsi.l a2, 1, 1f
293 s32i a4, a1, PT_AREG4
294 s32i a5, a1, PT_AREG5
295 s32i a6, a1, PT_AREG6
296 s32i a7, a1, PT_AREG7
297 _bbsi.l a2, 2, 1f
298 s32i a8, a1, PT_AREG8
299 s32i a9, a1, PT_AREG9
300 s32i a10, a1, PT_AREG10
301 s32i a11, a1, PT_AREG11
302 _bbsi.l a2, 3, 1f
303 s32i a12, a1, PT_AREG12
304 s32i a13, a1, PT_AREG13
305 s32i a14, a1, PT_AREG14
306 s32i a15, a1, PT_AREG15
307
308 1:
309
310 #ifdef KERNEL_STACK_OVERFLOW_CHECK
311
312 /* Stack overflow check, for debugging */
313 extui a2, a1, TASK_SIZE_BITS,XX
314 movi a3, SIZE??
315 _bge a2, a3, out_of_stack_panic
316
317 #endif
318
319 /*
320 * This is the common exception handler.
321 * We get here from the user exception handler or simply by falling through
322 * from the kernel exception handler.
323 * Save the remaining special registers, switch to kernel mode, and jump
324 * to the second-level exception handler.
325 *
326 */
327
328 common_exception:
329
330 /* Save some registers, disable loops and clear the syscall flag. */
331
332 rsr a2, debugcause
333 rsr a3, epc1
334 s32i a2, a1, PT_DEBUGCAUSE
335 s32i a3, a1, PT_PC
336
337 movi a2, -1
338 rsr a3, excvaddr
339 s32i a2, a1, PT_SYSCALL
340 movi a2, 0
341 s32i a3, a1, PT_EXCVADDR
342 xsr a2, lcount
343 s32i a2, a1, PT_LCOUNT
344
345 /* It is now save to restore the EXC_TABLE_FIXUP variable. */
346
347 rsr a0, exccause
348 movi a3, 0
349 rsr a2, excsave1
350 s32i a0, a1, PT_EXCCAUSE
351 s32i a3, a2, EXC_TABLE_FIXUP
352
353 /* All unrecoverable states are saved on stack, now, and a1 is valid,
354 * so we can allow exceptions and interrupts (*) again.
355 * Set PS(EXCM = 0, UM = 0, RING = 0, OWB = 0, WOE = 1, INTLEVEL = X)
356 *
357 * (*) We only allow interrupts of higher priority than current IRQ
358 */
359
360 rsr a3, ps
361 addi a0, a0, -4
362 movi a2, 1
363 extui a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
364 # a3 = PS.INTLEVEL
365 movnez a2, a3, a3 # a2 = 1: level-1, > 1: high priority
366 moveqz a3, a2, a0 # a3 = IRQ level iff interrupt
367 movi a2, 1 << PS_WOE_BIT
368 or a3, a3, a2
369 rsr a0, exccause
370 xsr a3, ps
371
372 s32i a3, a1, PT_PS # save ps
373
374 /* Save lbeg, lend */
375
376 rsr a2, lbeg
377 rsr a3, lend
378 s32i a2, a1, PT_LBEG
379 s32i a3, a1, PT_LEND
380
381 /* Save SCOMPARE1 */
382
383 #if XCHAL_HAVE_S32C1I
384 rsr a2, scompare1
385 s32i a2, a1, PT_SCOMPARE1
386 #endif
387
388 /* Save optional registers. */
389
390 save_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT
391
392 /* Go to second-level dispatcher. Set up parameters to pass to the
393 * exception handler and call the exception handler.
394 */
395
396 movi a4, exc_table
397 mov a6, a1 # pass stack frame
398 mov a7, a0 # pass EXCCAUSE
399 addx4 a4, a0, a4
400 l32i a4, a4, EXC_TABLE_DEFAULT # load handler
401
402 /* Call the second-level handler */
403
404 callx4 a4
405
406 /* Jump here for exception exit */
407 .global common_exception_return
408 common_exception_return:
409
410 /* Jump if we are returning from kernel exceptions. */
411
412 1: l32i a3, a1, PT_PS
413 _bbci.l a3, PS_UM_BIT, 4f
414
415 /* Specific to a user exception exit:
416 * We need to check some flags for signal handling and rescheduling,
417 * and have to restore WB and WS, extra states, and all registers
418 * in the register file that were in use in the user task.
419 * Note that we don't disable interrupts here.
420 */
421
422 GET_THREAD_INFO(a2,a1)
423 l32i a4, a2, TI_FLAGS
424
425 _bbsi.l a4, TIF_NEED_RESCHED, 3f
426 _bbsi.l a4, TIF_NOTIFY_RESUME, 2f
427 _bbci.l a4, TIF_SIGPENDING, 4f
428
429 2: l32i a4, a1, PT_DEPC
430 bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f
431
432 /* Call do_signal() */
433
434 movi a4, do_notify_resume # int do_notify_resume(struct pt_regs*)
435 mov a6, a1
436 callx4 a4
437 j 1b
438
439 3: /* Reschedule */
440
441 movi a4, schedule # void schedule (void)
442 callx4 a4
443 j 1b
444
445 4: /* Restore optional registers. */
446
447 load_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT
448
449 /* Restore SCOMPARE1 */
450
451 #if XCHAL_HAVE_S32C1I
452 l32i a2, a1, PT_SCOMPARE1
453 wsr a2, scompare1
454 #endif
455 wsr a3, ps /* disable interrupts */
456
457 _bbci.l a3, PS_UM_BIT, kernel_exception_exit
458
459 user_exception_exit:
460
461 /* Restore the state of the task and return from the exception. */
462
463 /* Switch to the user thread WINDOWBASE. Save SP temporarily in DEPC */
464
465 l32i a2, a1, PT_WINDOWBASE
466 l32i a3, a1, PT_WINDOWSTART
467 wsr a1, depc # use DEPC as temp storage
468 wsr a3, windowstart # restore WINDOWSTART
469 ssr a2 # preserve user's WB in the SAR
470 wsr a2, windowbase # switch to user's saved WB
471 rsync
472 rsr a1, depc # restore stack pointer
473 l32i a2, a1, PT_WMASK # register frames saved (in bits 4...9)
474 rotw -1 # we restore a4..a7
475 _bltui a6, 16, 1f # only have to restore current window?
476
477 /* The working registers are a0 and a3. We are restoring to
478 * a4..a7. Be careful not to destroy what we have just restored.
479 * Note: wmask has the format YYYYM:
480 * Y: number of registers saved in groups of 4
481 * M: 4 bit mask of first 16 registers
482 */
483
484 mov a2, a6
485 mov a3, a5
486
487 2: rotw -1 # a0..a3 become a4..a7
488 addi a3, a7, -4*4 # next iteration
489 addi a2, a6, -16 # decrementing Y in WMASK
490 l32i a4, a3, PT_AREG_END + 0
491 l32i a5, a3, PT_AREG_END + 4
492 l32i a6, a3, PT_AREG_END + 8
493 l32i a7, a3, PT_AREG_END + 12
494 _bgeui a2, 16, 2b
495
496 /* Clear unrestored registers (don't leak anything to user-land */
497
498 1: rsr a0, windowbase
499 rsr a3, sar
500 sub a3, a0, a3
501 beqz a3, 2f
502 extui a3, a3, 0, WBBITS
503
504 1: rotw -1
505 addi a3, a7, -1
506 movi a4, 0
507 movi a5, 0
508 movi a6, 0
509 movi a7, 0
510 bgei a3, 1, 1b
511
512 /* We are back were we were when we started.
513 * Note: a2 still contains WMASK (if we've returned to the original
514 * frame where we had loaded a2), or at least the lower 4 bits
515 * (if we have restored WSBITS-1 frames).
516 */
517
518 #if XCHAL_HAVE_THREADPTR
519 l32i a3, a1, PT_THREADPTR
520 wur a3, threadptr
521 #endif
522
523 2: j common_exception_exit
524
525 /* This is the kernel exception exit.
526 * We avoided to do a MOVSP when we entered the exception, but we
527 * have to do it here.
528 */
529
530 kernel_exception_exit:
531
532 #ifdef PREEMPTIBLE_KERNEL
533
534 #ifdef CONFIG_PREEMPT
535
536 /*
537 * Note: We've just returned from a call4, so we have
538 * at least 4 addt'l regs.
539 */
540
541 /* Check current_thread_info->preempt_count */
542
543 GET_THREAD_INFO(a2)
544 l32i a3, a2, TI_PREEMPT
545 bnez a3, 1f
546
547 l32i a2, a2, TI_FLAGS
548
549 1:
550
551 #endif
552
553 #endif
554
555 /* Check if we have to do a movsp.
556 *
557 * We only have to do a movsp if the previous window-frame has
558 * been spilled to the *temporary* exception stack instead of the
559 * task's stack. This is the case if the corresponding bit in
560 * WINDOWSTART for the previous window-frame was set before
561 * (not spilled) but is zero now (spilled).
562 * If this bit is zero, all other bits except the one for the
563 * current window frame are also zero. So, we can use a simple test:
564 * 'and' WINDOWSTART and WINDOWSTART-1:
565 *
566 * (XXXXXX1[0]* - 1) AND XXXXXX1[0]* = XXXXXX0[0]*
567 *
568 * The result is zero only if one bit was set.
569 *
570 * (Note: We might have gone through several task switches before
571 * we come back to the current task, so WINDOWBASE might be
572 * different from the time the exception occurred.)
573 */
574
575 /* Test WINDOWSTART before and after the exception.
576 * We actually have WMASK, so we only have to test if it is 1 or not.
577 */
578
579 l32i a2, a1, PT_WMASK
580 _beqi a2, 1, common_exception_exit # Spilled before exception,jump
581
582 /* Test WINDOWSTART now. If spilled, do the movsp */
583
584 rsr a3, windowstart
585 addi a0, a3, -1
586 and a3, a3, a0
587 _bnez a3, common_exception_exit
588
589 /* Do a movsp (we returned from a call4, so we have at least a0..a7) */
590
591 addi a0, a1, -16
592 l32i a3, a0, 0
593 l32i a4, a0, 4
594 s32i a3, a1, PT_SIZE+0
595 s32i a4, a1, PT_SIZE+4
596 l32i a3, a0, 8
597 l32i a4, a0, 12
598 s32i a3, a1, PT_SIZE+8
599 s32i a4, a1, PT_SIZE+12
600
601 /* Common exception exit.
602 * We restore the special register and the current window frame, and
603 * return from the exception.
604 *
605 * Note: We expect a2 to hold PT_WMASK
606 */
607
608 common_exception_exit:
609
610 /* Restore address registers. */
611
612 _bbsi.l a2, 1, 1f
613 l32i a4, a1, PT_AREG4
614 l32i a5, a1, PT_AREG5
615 l32i a6, a1, PT_AREG6
616 l32i a7, a1, PT_AREG7
617 _bbsi.l a2, 2, 1f
618 l32i a8, a1, PT_AREG8
619 l32i a9, a1, PT_AREG9
620 l32i a10, a1, PT_AREG10
621 l32i a11, a1, PT_AREG11
622 _bbsi.l a2, 3, 1f
623 l32i a12, a1, PT_AREG12
624 l32i a13, a1, PT_AREG13
625 l32i a14, a1, PT_AREG14
626 l32i a15, a1, PT_AREG15
627
628 /* Restore PC, SAR */
629
630 1: l32i a2, a1, PT_PC
631 l32i a3, a1, PT_SAR
632 wsr a2, epc1
633 wsr a3, sar
634
635 /* Restore LBEG, LEND, LCOUNT */
636
637 l32i a2, a1, PT_LBEG
638 l32i a3, a1, PT_LEND
639 wsr a2, lbeg
640 l32i a2, a1, PT_LCOUNT
641 wsr a3, lend
642 wsr a2, lcount
643
644 /* We control single stepping through the ICOUNTLEVEL register. */
645
646 l32i a2, a1, PT_ICOUNTLEVEL
647 movi a3, -2
648 wsr a2, icountlevel
649 wsr a3, icount
650
651 /* Check if it was double exception. */
652
653 l32i a0, a1, PT_DEPC
654 l32i a3, a1, PT_AREG3
655 _bltui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
656
657 wsr a0, depc
658 l32i a2, a1, PT_AREG2
659 l32i a0, a1, PT_AREG0
660 l32i a1, a1, PT_AREG1
661 rfde
662
663 1:
664 /* Restore a0...a3 and return */
665
666 rsr a0, ps
667 extui a2, a0, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
668 movi a0, 2f
669 slli a2, a2, 4
670 add a0, a2, a0
671 l32i a2, a1, PT_AREG2
672 jx a0
673
674 .macro irq_exit_level level
675 .align 16
676 .if XCHAL_EXCM_LEVEL >= \level
677 l32i a0, a1, PT_PC
678 wsr a0, epc\level
679 l32i a0, a1, PT_AREG0
680 l32i a1, a1, PT_AREG1
681 rfi \level
682 .endif
683 .endm
684
685 .align 16
686 2:
687 l32i a0, a1, PT_AREG0
688 l32i a1, a1, PT_AREG1
689 rfe
690
691 .align 16
692 /* no rfi for level-1 irq, handled by rfe above*/
693 nop
694
695 irq_exit_level 2
696 irq_exit_level 3
697 irq_exit_level 4
698 irq_exit_level 5
699 irq_exit_level 6
700
701 ENDPROC(kernel_exception)
702
703 /*
704 * Debug exception handler.
705 *
706 * Currently, we don't support KGDB, so only user application can be debugged.
707 *
708 * When we get here, a0 is trashed and saved to excsave[debuglevel]
709 */
710
711 ENTRY(debug_exception)
712
713 rsr a0, SREG_EPS + XCHAL_DEBUGLEVEL
714 bbsi.l a0, PS_EXCM_BIT, 1f # exception mode
715
716 /* Set EPC1 and EXCCAUSE */
717
718 wsr a2, depc # save a2 temporarily
719 rsr a2, SREG_EPC + XCHAL_DEBUGLEVEL
720 wsr a2, epc1
721
722 movi a2, EXCCAUSE_MAPPED_DEBUG
723 wsr a2, exccause
724
725 /* Restore PS to the value before the debug exc but with PS.EXCM set.*/
726
727 movi a2, 1 << PS_EXCM_BIT
728 or a2, a0, a2
729 movi a0, debug_exception # restore a3, debug jump vector
730 wsr a2, ps
731 xsr a0, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
732
733 /* Switch to kernel/user stack, restore jump vector, and save a0 */
734
735 bbsi.l a2, PS_UM_BIT, 2f # jump if user mode
736
737 addi a2, a1, -16-PT_SIZE # assume kernel stack
738 s32i a0, a2, PT_AREG0
739 movi a0, 0
740 s32i a1, a2, PT_AREG1
741 s32i a0, a2, PT_DEPC # mark it as a regular exception
742 xsr a0, depc
743 s32i a3, a2, PT_AREG3
744 s32i a0, a2, PT_AREG2
745 mov a1, a2
746 j _kernel_exception
747
748 2: rsr a2, excsave1
749 l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer
750 s32i a0, a2, PT_AREG0
751 movi a0, 0
752 s32i a1, a2, PT_AREG1
753 s32i a0, a2, PT_DEPC
754 xsr a0, depc
755 s32i a3, a2, PT_AREG3
756 s32i a0, a2, PT_AREG2
757 mov a1, a2
758 j _user_exception
759
760 /* Debug exception while in exception mode. */
761 1: j 1b // FIXME!!
762
763 ENDPROC(debug_exception)
764
765 /*
766 * We get here in case of an unrecoverable exception.
767 * The only thing we can do is to be nice and print a panic message.
768 * We only produce a single stack frame for panic, so ???
769 *
770 *
771 * Entry conditions:
772 *
773 * - a0 contains the caller address; original value saved in excsave1.
774 * - the original a0 contains a valid return address (backtrace) or 0.
775 * - a2 contains a valid stackpointer
776 *
777 * Notes:
778 *
779 * - If the stack pointer could be invalid, the caller has to setup a
780 * dummy stack pointer (e.g. the stack of the init_task)
781 *
782 * - If the return address could be invalid, the caller has to set it
783 * to 0, so the backtrace would stop.
784 *
785 */
786 .align 4
787 unrecoverable_text:
788 .ascii "Unrecoverable error in exception handler\0"
789
790 ENTRY(unrecoverable_exception)
791
792 movi a0, 1
793 movi a1, 0
794
795 wsr a0, windowstart
796 wsr a1, windowbase
797 rsync
798
799 movi a1, (1 << PS_WOE_BIT) | LOCKLEVEL
800 wsr a1, ps
801 rsync
802
803 movi a1, init_task
804 movi a0, 0
805 addi a1, a1, PT_REGS_OFFSET
806
807 movi a4, panic
808 movi a6, unrecoverable_text
809
810 callx4 a4
811
812 1: j 1b
813
814 ENDPROC(unrecoverable_exception)
815
816 /* -------------------------- FAST EXCEPTION HANDLERS ----------------------- */
817
818 /*
819 * Fast-handler for alloca exceptions
820 *
821 * The ALLOCA handler is entered when user code executes the MOVSP
822 * instruction and the caller's frame is not in the register file.
823 * In this case, the caller frame's a0..a3 are on the stack just
824 * below sp (a1), and this handler moves them.
825 *
826 * For "MOVSP <ar>,<as>" without destination register a1, this routine
827 * simply moves the value from <as> to <ar> without moving the save area.
828 *
829 * Entry condition:
830 *
831 * a0: trashed, original value saved on stack (PT_AREG0)
832 * a1: a1
833 * a2: new stack pointer, original in DEPC
834 * a3: dispatch table
835 * depc: a2, original value saved on stack (PT_DEPC)
836 * excsave_1: a3
837 *
838 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
839 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
840 */
841
842 #if XCHAL_HAVE_BE
843 #define _EXTUI_MOVSP_SRC(ar) extui ar, ar, 4, 4
844 #define _EXTUI_MOVSP_DST(ar) extui ar, ar, 0, 4
845 #else
846 #define _EXTUI_MOVSP_SRC(ar) extui ar, ar, 0, 4
847 #define _EXTUI_MOVSP_DST(ar) extui ar, ar, 4, 4
848 #endif
849
850 ENTRY(fast_alloca)
851
852 /* We shouldn't be in a double exception. */
853
854 l32i a0, a2, PT_DEPC
855 _bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, .Lunhandled_double
856
857 rsr a0, depc # get a2
858 s32i a4, a2, PT_AREG4 # save a4 and
859 s32i a0, a2, PT_AREG2 # a2 to stack
860
861 /* Exit critical section. */
862
863 movi a0, 0
864 s32i a0, a3, EXC_TABLE_FIXUP
865
866 /* Restore a3, excsave_1 */
867
868 xsr a3, excsave1 # make sure excsave_1 is valid for dbl.
869 rsr a4, epc1 # get exception address
870 s32i a3, a2, PT_AREG3 # save a3 to stack
871
872 #ifdef ALLOCA_EXCEPTION_IN_IRAM
873 #error iram not supported
874 #else
875 /* Note: l8ui not allowed in IRAM/IROM!! */
876 l8ui a0, a4, 1 # read as(src) from MOVSP instruction
877 #endif
878 movi a3, .Lmovsp_src
879 _EXTUI_MOVSP_SRC(a0) # extract source register number
880 addx8 a3, a0, a3
881 jx a3
882
883 .Lunhandled_double:
884 wsr a0, excsave1
885 movi a0, unrecoverable_exception
886 callx0 a0
887
888 .align 8
889 .Lmovsp_src:
890 l32i a3, a2, PT_AREG0; _j 1f; .align 8
891 mov a3, a1; _j 1f; .align 8
892 l32i a3, a2, PT_AREG2; _j 1f; .align 8
893 l32i a3, a2, PT_AREG3; _j 1f; .align 8
894 l32i a3, a2, PT_AREG4; _j 1f; .align 8
895 mov a3, a5; _j 1f; .align 8
896 mov a3, a6; _j 1f; .align 8
897 mov a3, a7; _j 1f; .align 8
898 mov a3, a8; _j 1f; .align 8
899 mov a3, a9; _j 1f; .align 8
900 mov a3, a10; _j 1f; .align 8
901 mov a3, a11; _j 1f; .align 8
902 mov a3, a12; _j 1f; .align 8
903 mov a3, a13; _j 1f; .align 8
904 mov a3, a14; _j 1f; .align 8
905 mov a3, a15; _j 1f; .align 8
906
907 1:
908
909 #ifdef ALLOCA_EXCEPTION_IN_IRAM
910 #error iram not supported
911 #else
912 l8ui a0, a4, 0 # read ar(dst) from MOVSP instruction
913 #endif
914 addi a4, a4, 3 # step over movsp
915 _EXTUI_MOVSP_DST(a0) # extract destination register
916 wsr a4, epc1 # save new epc_1
917
918 _bnei a0, 1, 1f # no 'movsp a1, ax': jump
919
920 /* Move the save area. This implies the use of the L32E
921 * and S32E instructions, because this move must be done with
922 * the user's PS.RING privilege levels, not with ring 0
923 * (kernel's) privileges currently active with PS.EXCM
924 * set. Note that we have stil registered a fixup routine with the
925 * double exception vector in case a double exception occurs.
926 */
927
928 /* a0,a4:avail a1:old user stack a2:exc. stack a3:new user stack. */
929
930 l32e a0, a1, -16
931 l32e a4, a1, -12
932 s32e a0, a3, -16
933 s32e a4, a3, -12
934 l32e a0, a1, -8
935 l32e a4, a1, -4
936 s32e a0, a3, -8
937 s32e a4, a3, -4
938
939 /* Restore stack-pointer and all the other saved registers. */
940
941 mov a1, a3
942
943 l32i a4, a2, PT_AREG4
944 l32i a3, a2, PT_AREG3
945 l32i a0, a2, PT_AREG0
946 l32i a2, a2, PT_AREG2
947 rfe
948
949 /* MOVSP <at>,<as> was invoked with <at> != a1.
950 * Because the stack pointer is not being modified,
951 * we should be able to just modify the pointer
952 * without moving any save area.
953 * The processor only traps these occurrences if the
954 * caller window isn't live, so unfortunately we can't
955 * use this as an alternate trap mechanism.
956 * So we just do the move. This requires that we
957 * resolve the destination register, not just the source,
958 * so there's some extra work.
959 * (PERHAPS NOT REALLY NEEDED, BUT CLEANER...)
960 */
961
962 /* a0 dst-reg, a1 user-stack, a2 stack, a3 value of src reg. */
963
964 1: movi a4, .Lmovsp_dst
965 addx8 a4, a0, a4
966 jx a4
967
968 .align 8
969 .Lmovsp_dst:
970 s32i a3, a2, PT_AREG0; _j 1f; .align 8
971 mov a1, a3; _j 1f; .align 8
972 s32i a3, a2, PT_AREG2; _j 1f; .align 8
973 s32i a3, a2, PT_AREG3; _j 1f; .align 8
974 s32i a3, a2, PT_AREG4; _j 1f; .align 8
975 mov a5, a3; _j 1f; .align 8
976 mov a6, a3; _j 1f; .align 8
977 mov a7, a3; _j 1f; .align 8
978 mov a8, a3; _j 1f; .align 8
979 mov a9, a3; _j 1f; .align 8
980 mov a10, a3; _j 1f; .align 8
981 mov a11, a3; _j 1f; .align 8
982 mov a12, a3; _j 1f; .align 8
983 mov a13, a3; _j 1f; .align 8
984 mov a14, a3; _j 1f; .align 8
985 mov a15, a3; _j 1f; .align 8
986
987 1: l32i a4, a2, PT_AREG4
988 l32i a3, a2, PT_AREG3
989 l32i a0, a2, PT_AREG0
990 l32i a2, a2, PT_AREG2
991 rfe
992
993 ENDPROC(fast_alloca)
994
995 /*
996 * fast system calls.
997 *
998 * WARNING: The kernel doesn't save the entire user context before
999 * handling a fast system call. These functions are small and short,
1000 * usually offering some functionality not available to user tasks.
1001 *
1002 * BE CAREFUL TO PRESERVE THE USER'S CONTEXT.
1003 *
1004 * Entry condition:
1005 *
1006 * a0: trashed, original value saved on stack (PT_AREG0)
1007 * a1: a1
1008 * a2: new stack pointer, original in DEPC
1009 * a3: dispatch table
1010 * depc: a2, original value saved on stack (PT_DEPC)
1011 * excsave_1: a3
1012 */
1013
1014 ENTRY(fast_syscall_kernel)
1015
1016 /* Skip syscall. */
1017
1018 rsr a0, epc1
1019 addi a0, a0, 3
1020 wsr a0, epc1
1021
1022 l32i a0, a2, PT_DEPC
1023 bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable
1024
1025 rsr a0, depc # get syscall-nr
1026 _beqz a0, fast_syscall_spill_registers
1027 _beqi a0, __NR_xtensa, fast_syscall_xtensa
1028
1029 j kernel_exception
1030
1031 ENDPROC(fast_syscall_kernel)
1032
1033 ENTRY(fast_syscall_user)
1034
1035 /* Skip syscall. */
1036
1037 rsr a0, epc1
1038 addi a0, a0, 3
1039 wsr a0, epc1
1040
1041 l32i a0, a2, PT_DEPC
1042 bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable
1043
1044 rsr a0, depc # get syscall-nr
1045 _beqz a0, fast_syscall_spill_registers
1046 _beqi a0, __NR_xtensa, fast_syscall_xtensa
1047
1048 j user_exception
1049
1050 ENDPROC(fast_syscall_user)
1051
1052 ENTRY(fast_syscall_unrecoverable)
1053
1054 /* Restore all states. */
1055
1056 l32i a0, a2, PT_AREG0 # restore a0
1057 xsr a2, depc # restore a2, depc
1058 rsr a3, excsave1
1059
1060 wsr a0, excsave1
1061 movi a0, unrecoverable_exception
1062 callx0 a0
1063
1064 ENDPROC(fast_syscall_unrecoverable)
1065
1066 /*
1067 * sysxtensa syscall handler
1068 *
1069 * int sysxtensa (SYS_XTENSA_ATOMIC_SET, ptr, val, unused);
1070 * int sysxtensa (SYS_XTENSA_ATOMIC_ADD, ptr, val, unused);
1071 * int sysxtensa (SYS_XTENSA_ATOMIC_EXG_ADD, ptr, val, unused);
1072 * int sysxtensa (SYS_XTENSA_ATOMIC_CMP_SWP, ptr, oldval, newval);
1073 * a2 a6 a3 a4 a5
1074 *
1075 * Entry condition:
1076 *
1077 * a0: a2 (syscall-nr), original value saved on stack (PT_AREG0)
1078 * a1: a1
1079 * a2: new stack pointer, original in a0 and DEPC
1080 * a3: dispatch table, original in excsave_1
1081 * a4..a15: unchanged
1082 * depc: a2, original value saved on stack (PT_DEPC)
1083 * excsave_1: a3
1084 *
1085 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
1086 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
1087 *
1088 * Note: we don't have to save a2; a2 holds the return value
1089 *
1090 * We use the two macros TRY and CATCH:
1091 *
1092 * TRY adds an entry to the __ex_table fixup table for the immediately
1093 * following instruction.
1094 *
1095 * CATCH catches any exception that occurred at one of the preceding TRY
1096 * statements and continues from there
1097 *
1098 * Usage TRY l32i a0, a1, 0
1099 * <other code>
1100 * done: rfe
1101 * CATCH <set return code>
1102 * j done
1103 */
1104
1105 #define TRY \
1106 .section __ex_table, "a"; \
1107 .word 66f, 67f; \
1108 .text; \
1109 66:
1110
1111 #define CATCH \
1112 67:
1113
1114 ENTRY(fast_syscall_xtensa)
1115
1116 xsr a3, excsave1 # restore a3, excsave1
1117
1118 s32i a7, a2, PT_AREG7 # we need an additional register
1119 movi a7, 4 # sizeof(unsigned int)
1120 access_ok a3, a7, a0, a2, .Leac # a0: scratch reg, a2: sp
1121
1122 addi a6, a6, -1 # assuming SYS_XTENSA_ATOMIC_SET = 1
1123 _bgeui a6, SYS_XTENSA_COUNT - 1, .Lill
1124 _bnei a6, SYS_XTENSA_ATOMIC_CMP_SWP - 1, .Lnswp
1125
1126 /* Fall through for ATOMIC_CMP_SWP. */
1127
1128 .Lswp: /* Atomic compare and swap */
1129
1130 TRY l32i a0, a3, 0 # read old value
1131 bne a0, a4, 1f # same as old value? jump
1132 TRY s32i a5, a3, 0 # different, modify value
1133 l32i a7, a2, PT_AREG7 # restore a7
1134 l32i a0, a2, PT_AREG0 # restore a0
1135 movi a2, 1 # and return 1
1136 addi a6, a6, 1 # restore a6 (really necessary?)
1137 rfe
1138
1139 1: l32i a7, a2, PT_AREG7 # restore a7
1140 l32i a0, a2, PT_AREG0 # restore a0
1141 movi a2, 0 # return 0 (note that we cannot set
1142 addi a6, a6, 1 # restore a6 (really necessary?)
1143 rfe
1144
1145 .Lnswp: /* Atomic set, add, and exg_add. */
1146
1147 TRY l32i a7, a3, 0 # orig
1148 add a0, a4, a7 # + arg
1149 moveqz a0, a4, a6 # set
1150 TRY s32i a0, a3, 0 # write new value
1151
1152 mov a0, a2
1153 mov a2, a7
1154 l32i a7, a0, PT_AREG7 # restore a7
1155 l32i a0, a0, PT_AREG0 # restore a0
1156 addi a6, a6, 1 # restore a6 (really necessary?)
1157 rfe
1158
1159 CATCH
1160 .Leac: l32i a7, a2, PT_AREG7 # restore a7
1161 l32i a0, a2, PT_AREG0 # restore a0
1162 movi a2, -EFAULT
1163 rfe
1164
1165 .Lill: l32i a7, a2, PT_AREG0 # restore a7
1166 l32i a0, a2, PT_AREG0 # restore a0
1167 movi a2, -EINVAL
1168 rfe
1169
1170 ENDPROC(fast_syscall_xtensa)
1171
1172
1173 /* fast_syscall_spill_registers.
1174 *
1175 * Entry condition:
1176 *
1177 * a0: trashed, original value saved on stack (PT_AREG0)
1178 * a1: a1
1179 * a2: new stack pointer, original in DEPC
1180 * a3: dispatch table
1181 * depc: a2, original value saved on stack (PT_DEPC)
1182 * excsave_1: a3
1183 *
1184 * Note: We assume the stack pointer is EXC_TABLE_KSTK in the fixup handler.
1185 */
1186
1187 ENTRY(fast_syscall_spill_registers)
1188
1189 /* Register a FIXUP handler (pass current wb as a parameter) */
1190
1191 movi a0, fast_syscall_spill_registers_fixup
1192 s32i a0, a3, EXC_TABLE_FIXUP
1193 rsr a0, windowbase
1194 s32i a0, a3, EXC_TABLE_PARAM
1195
1196 /* Save a3 and SAR on stack. */
1197
1198 rsr a0, sar
1199 xsr a3, excsave1 # restore a3 and excsave_1
1200 s32i a3, a2, PT_AREG3
1201 s32i a4, a2, PT_AREG4
1202 s32i a0, a2, PT_AREG5 # store SAR to PT_AREG5
1203
1204 /* The spill routine might clobber a7, a11, and a15. */
1205
1206 s32i a7, a2, PT_AREG7
1207 s32i a11, a2, PT_AREG11
1208 s32i a15, a2, PT_AREG15
1209
1210 call0 _spill_registers # destroys a3, a4, and SAR
1211
1212 /* Advance PC, restore registers and SAR, and return from exception. */
1213
1214 l32i a3, a2, PT_AREG5
1215 l32i a4, a2, PT_AREG4
1216 l32i a0, a2, PT_AREG0
1217 wsr a3, sar
1218 l32i a3, a2, PT_AREG3
1219
1220 /* Restore clobbered registers. */
1221
1222 l32i a7, a2, PT_AREG7
1223 l32i a11, a2, PT_AREG11
1224 l32i a15, a2, PT_AREG15
1225
1226 movi a2, 0
1227 rfe
1228
1229 ENDPROC(fast_syscall_spill_registers)
1230
1231 /* Fixup handler.
1232 *
1233 * We get here if the spill routine causes an exception, e.g. tlb miss.
1234 * We basically restore WINDOWBASE and WINDOWSTART to the condition when
1235 * we entered the spill routine and jump to the user exception handler.
1236 *
1237 * a0: value of depc, original value in depc
1238 * a2: trashed, original value in EXC_TABLE_DOUBLE_SAVE
1239 * a3: exctable, original value in excsave1
1240 */
1241
1242 fast_syscall_spill_registers_fixup:
1243
1244 rsr a2, windowbase # get current windowbase (a2 is saved)
1245 xsr a0, depc # restore depc and a0
1246 ssl a2 # set shift (32 - WB)
1247
1248 /* We need to make sure the current registers (a0-a3) are preserved.
1249 * To do this, we simply set the bit for the current window frame
1250 * in WS, so that the exception handlers save them to the task stack.
1251 */
1252
1253 rsr a3, excsave1 # get spill-mask
1254 slli a2, a3, 1 # shift left by one
1255
1256 slli a3, a2, 32-WSBITS
1257 src a2, a2, a3 # a1 = xxwww1yyxxxwww1yy......
1258 wsr a2, windowstart # set corrected windowstart
1259
1260 movi a3, exc_table
1261 l32i a2, a3, EXC_TABLE_DOUBLE_SAVE # restore a2
1262 l32i a3, a3, EXC_TABLE_PARAM # original WB (in user task)
1263
1264 /* Return to the original (user task) WINDOWBASE.
1265 * We leave the following frame behind:
1266 * a0, a1, a2 same
1267 * a3: trashed (saved in excsave_1)
1268 * depc: depc (we have to return to that address)
1269 * excsave_1: a3
1270 */
1271
1272 wsr a3, windowbase
1273 rsync
1274
1275 /* We are now in the original frame when we entered _spill_registers:
1276 * a0: return address
1277 * a1: used, stack pointer
1278 * a2: kernel stack pointer
1279 * a3: available, saved in EXCSAVE_1
1280 * depc: exception address
1281 * excsave: a3
1282 * Note: This frame might be the same as above.
1283 */
1284
1285 /* Setup stack pointer. */
1286
1287 addi a2, a2, -PT_USER_SIZE
1288 s32i a0, a2, PT_AREG0
1289
1290 /* Make sure we return to this fixup handler. */
1291
1292 movi a3, fast_syscall_spill_registers_fixup_return
1293 s32i a3, a2, PT_DEPC # setup depc
1294
1295 /* Jump to the exception handler. */
1296
1297 movi a3, exc_table
1298 rsr a0, exccause
1299 addx4 a0, a0, a3 # find entry in table
1300 l32i a0, a0, EXC_TABLE_FAST_USER # load handler
1301 jx a0
1302
1303 fast_syscall_spill_registers_fixup_return:
1304
1305 /* When we return here, all registers have been restored (a2: DEPC) */
1306
1307 wsr a2, depc # exception address
1308
1309 /* Restore fixup handler. */
1310
1311 xsr a3, excsave1
1312 movi a2, fast_syscall_spill_registers_fixup
1313 s32i a2, a3, EXC_TABLE_FIXUP
1314 rsr a2, windowbase
1315 s32i a2, a3, EXC_TABLE_PARAM
1316 l32i a2, a3, EXC_TABLE_KSTK
1317
1318 /* Load WB at the time the exception occurred. */
1319
1320 rsr a3, sar # WB is still in SAR
1321 neg a3, a3
1322 wsr a3, windowbase
1323 rsync
1324
1325 /* Restore a3 and return. */
1326
1327 movi a3, exc_table
1328 xsr a3, excsave1
1329
1330 rfde
1331
1332
1333 /*
1334 * spill all registers.
1335 *
1336 * This is not a real function. The following conditions must be met:
1337 *
1338 * - must be called with call0.
1339 * - uses a3, a4 and SAR.
1340 * - the last 'valid' register of each frame are clobbered.
1341 * - the caller must have registered a fixup handler
1342 * (or be inside a critical section)
1343 * - PS_EXCM must be set (PS_WOE cleared?)
1344 */
1345
1346 ENTRY(_spill_registers)
1347
1348 /*
1349 * Rotate ws so that the current windowbase is at bit 0.
1350 * Assume ws = xxxwww1yy (www1 current window frame).
1351 * Rotate ws right so that a4 = yyxxxwww1.
1352 */
1353
1354 rsr a4, windowbase
1355 rsr a3, windowstart # a3 = xxxwww1yy
1356 ssr a4 # holds WB
1357 slli a4, a3, WSBITS
1358 or a3, a3, a4 # a3 = xxxwww1yyxxxwww1yy
1359 srl a3, a3 # a3 = 00xxxwww1yyxxxwww1
1360
1361 /* We are done if there are no more than the current register frame. */
1362
1363 extui a3, a3, 1, WSBITS-1 # a3 = 0yyxxxwww
1364 movi a4, (1 << (WSBITS-1))
1365 _beqz a3, .Lnospill # only one active frame? jump
1366
1367 /* We want 1 at the top, so that we return to the current windowbase */
1368
1369 or a3, a3, a4 # 1yyxxxwww
1370
1371 /* Skip empty frames - get 'oldest' WINDOWSTART-bit. */
1372
1373 wsr a3, windowstart # save shifted windowstart
1374 neg a4, a3
1375 and a3, a4, a3 # first bit set from right: 000010000
1376
1377 ffs_ws a4, a3 # a4: shifts to skip empty frames
1378 movi a3, WSBITS
1379 sub a4, a3, a4 # WSBITS-a4:number of 0-bits from right
1380 ssr a4 # save in SAR for later.
1381
1382 rsr a3, windowbase
1383 add a3, a3, a4
1384 wsr a3, windowbase
1385 rsync
1386
1387 rsr a3, windowstart
1388 srl a3, a3 # shift windowstart
1389
1390 /* WB is now just one frame below the oldest frame in the register
1391 window. WS is shifted so the oldest frame is in bit 0, thus, WB
1392 and WS differ by one 4-register frame. */
1393
1394 /* Save frames. Depending what call was used (call4, call8, call12),
1395 * we have to save 4,8. or 12 registers.
1396 */
1397
1398 _bbsi.l a3, 1, .Lc4
1399 _bbsi.l a3, 2, .Lc8
1400
1401 /* Special case: we have a call12-frame starting at a4. */
1402
1403 _bbci.l a3, 3, .Lc12 # bit 3 shouldn't be zero! (Jump to Lc12 first)
1404
1405 s32e a4, a1, -16 # a1 is valid with an empty spill area
1406 l32e a4, a5, -12
1407 s32e a8, a4, -48
1408 mov a8, a4
1409 l32e a4, a1, -16
1410 j .Lc12c
1411
1412 .Lnospill:
1413 ret
1414
1415 .Lloop: _bbsi.l a3, 1, .Lc4
1416 _bbci.l a3, 2, .Lc12
1417
1418 .Lc8: s32e a4, a13, -16
1419 l32e a4, a5, -12
1420 s32e a8, a4, -32
1421 s32e a5, a13, -12
1422 s32e a6, a13, -8
1423 s32e a7, a13, -4
1424 s32e a9, a4, -28
1425 s32e a10, a4, -24
1426 s32e a11, a4, -20
1427
1428 srli a11, a3, 2 # shift windowbase by 2
1429 rotw 2
1430 _bnei a3, 1, .Lloop
1431
1432 .Lexit: /* Done. Do the final rotation, set WS, and return. */
1433
1434 rotw 1
1435 rsr a3, windowbase
1436 ssl a3
1437 movi a3, 1
1438 sll a3, a3
1439 wsr a3, windowstart
1440 ret
1441
1442 .Lc4: s32e a4, a9, -16
1443 s32e a5, a9, -12
1444 s32e a6, a9, -8
1445 s32e a7, a9, -4
1446
1447 srli a7, a3, 1
1448 rotw 1
1449 _bnei a3, 1, .Lloop
1450 j .Lexit
1451
1452 .Lc12: _bbci.l a3, 3, .Linvalid_mask # bit 2 shouldn't be zero!
1453
1454 /* 12-register frame (call12) */
1455
1456 l32e a2, a5, -12
1457 s32e a8, a2, -48
1458 mov a8, a2
1459
1460 .Lc12c: s32e a9, a8, -44
1461 s32e a10, a8, -40
1462 s32e a11, a8, -36
1463 s32e a12, a8, -32
1464 s32e a13, a8, -28
1465 s32e a14, a8, -24
1466 s32e a15, a8, -20
1467 srli a15, a3, 3
1468
1469 /* The stack pointer for a4..a7 is out of reach, so we rotate the
1470 * window, grab the stackpointer, and rotate back.
1471 * Alternatively, we could also use the following approach, but that
1472 * makes the fixup routine much more complicated:
1473 * rotw 1
1474 * s32e a0, a13, -16
1475 * ...
1476 * rotw 2
1477 */
1478
1479 rotw 1
1480 mov a5, a13
1481 rotw -1
1482
1483 s32e a4, a9, -16
1484 s32e a5, a9, -12
1485 s32e a6, a9, -8
1486 s32e a7, a9, -4
1487
1488 rotw 3
1489
1490 _beqi a3, 1, .Lexit
1491 j .Lloop
1492
1493 .Linvalid_mask:
1494
1495 /* We get here because of an unrecoverable error in the window
1496 * registers. If we are in user space, we kill the application,
1497 * however, this condition is unrecoverable in kernel space.
1498 */
1499
1500 rsr a0, ps
1501 _bbci.l a0, PS_UM_BIT, 1f
1502
1503 /* User space: Setup a dummy frame and kill application.
1504 * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer.
1505 */
1506
1507 movi a0, 1
1508 movi a1, 0
1509
1510 wsr a0, windowstart
1511 wsr a1, windowbase
1512 rsync
1513
1514 movi a0, 0
1515
1516 movi a3, exc_table
1517 l32i a1, a3, EXC_TABLE_KSTK
1518 wsr a3, excsave1
1519
1520 movi a4, (1 << PS_WOE_BIT) | LOCKLEVEL
1521 wsr a4, ps
1522 rsync
1523
1524 movi a6, SIGSEGV
1525 movi a4, do_exit
1526 callx4 a4
1527
1528 1: /* Kernel space: PANIC! */
1529
1530 wsr a0, excsave1
1531 movi a0, unrecoverable_exception
1532 callx0 a0 # should not return
1533 1: j 1b
1534
1535 ENDPROC(_spill_registers)
1536
1537 #ifdef CONFIG_MMU
1538 /*
1539 * We should never get here. Bail out!
1540 */
1541
1542 ENTRY(fast_second_level_miss_double_kernel)
1543
1544 1: movi a0, unrecoverable_exception
1545 callx0 a0 # should not return
1546 1: j 1b
1547
1548 ENDPROC(fast_second_level_miss_double_kernel)
1549
1550 /* First-level entry handler for user, kernel, and double 2nd-level
1551 * TLB miss exceptions. Note that for now, user and kernel miss
1552 * exceptions share the same entry point and are handled identically.
1553 *
1554 * An old, less-efficient C version of this function used to exist.
1555 * We include it below, interleaved as comments, for reference.
1556 *
1557 * Entry condition:
1558 *
1559 * a0: trashed, original value saved on stack (PT_AREG0)
1560 * a1: a1
1561 * a2: new stack pointer, original in DEPC
1562 * a3: dispatch table
1563 * depc: a2, original value saved on stack (PT_DEPC)
1564 * excsave_1: a3
1565 *
1566 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
1567 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
1568 */
1569
1570 ENTRY(fast_second_level_miss)
1571
1572 /* Save a1. Note: we don't expect a double exception. */
1573
1574 s32i a1, a2, PT_AREG1
1575
1576 /* We need to map the page of PTEs for the user task. Find
1577 * the pointer to that page. Also, it's possible for tsk->mm
1578 * to be NULL while tsk->active_mm is nonzero if we faulted on
1579 * a vmalloc address. In that rare case, we must use
1580 * active_mm instead to avoid a fault in this handler. See
1581 *
1582 * http://mail.nl.linux.org/linux-mm/2002-08/msg00258.html
1583 * (or search Internet on "mm vs. active_mm")
1584 *
1585 * if (!mm)
1586 * mm = tsk->active_mm;
1587 * pgd = pgd_offset (mm, regs->excvaddr);
1588 * pmd = pmd_offset (pgd, regs->excvaddr);
1589 * pmdval = *pmd;
1590 */
1591
1592 GET_CURRENT(a1,a2)
1593 l32i a0, a1, TASK_MM # tsk->mm
1594 beqz a0, 9f
1595
1596
1597 /* We deliberately destroy a3 that holds the exception table. */
1598
1599 8: rsr a3, excvaddr # fault address
1600 _PGD_OFFSET(a0, a3, a1)
1601 l32i a0, a0, 0 # read pmdval
1602 beqz a0, 2f
1603
1604 /* Read ptevaddr and convert to top of page-table page.
1605 *
1606 * vpnval = read_ptevaddr_register() & PAGE_MASK;
1607 * vpnval += DTLB_WAY_PGTABLE;
1608 * pteval = mk_pte (virt_to_page(pmd_val(pmdval)), PAGE_KERNEL);
1609 * write_dtlb_entry (pteval, vpnval);
1610 *
1611 * The messy computation for 'pteval' above really simplifies
1612 * into the following:
1613 *
1614 * pteval = ((pmdval - PAGE_OFFSET) & PAGE_MASK) | PAGE_DIRECTORY
1615 */
1616
1617 movi a1, (-PAGE_OFFSET) & 0xffffffff
1618 add a0, a0, a1 # pmdval - PAGE_OFFSET
1619 extui a1, a0, 0, PAGE_SHIFT # ... & PAGE_MASK
1620 xor a0, a0, a1
1621
1622 movi a1, _PAGE_DIRECTORY
1623 or a0, a0, a1 # ... | PAGE_DIRECTORY
1624
1625 /*
1626 * We utilize all three wired-ways (7-9) to hold pmd translations.
1627 * Memory regions are mapped to the DTLBs according to bits 28 and 29.
1628 * This allows to map the three most common regions to three different
1629 * DTLBs:
1630 * 0,1 -> way 7 program (0040.0000) and virtual (c000.0000)
1631 * 2 -> way 8 shared libaries (2000.0000)
1632 * 3 -> way 0 stack (3000.0000)
1633 */
1634
1635 extui a3, a3, 28, 2 # addr. bit 28 and 29 0,1,2,3
1636 rsr a1, ptevaddr
1637 addx2 a3, a3, a3 # -> 0,3,6,9
1638 srli a1, a1, PAGE_SHIFT
1639 extui a3, a3, 2, 2 # -> 0,0,1,2
1640 slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK
1641 addi a3, a3, DTLB_WAY_PGD
1642 add a1, a1, a3 # ... + way_number
1643
1644 3: wdtlb a0, a1
1645 dsync
1646
1647 /* Exit critical section. */
1648
1649 4: movi a3, exc_table # restore a3
1650 movi a0, 0
1651 s32i a0, a3, EXC_TABLE_FIXUP
1652
1653 /* Restore the working registers, and return. */
1654
1655 l32i a0, a2, PT_AREG0
1656 l32i a1, a2, PT_AREG1
1657 l32i a2, a2, PT_DEPC
1658 xsr a3, excsave1
1659
1660 bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
1661
1662 /* Restore excsave1 and return. */
1663
1664 rsr a2, depc
1665 rfe
1666
1667 /* Return from double exception. */
1668
1669 1: xsr a2, depc
1670 esync
1671 rfde
1672
1673 9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
1674 j 8b
1675
1676 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
1677
1678 2: /* Special case for cache aliasing.
1679 * We (should) only get here if a clear_user_page, copy_user_page
1680 * or the aliased cache flush functions got preemptively interrupted
1681 * by another task. Re-establish temporary mapping to the
1682 * TLBTEMP_BASE areas.
1683 */
1684
1685 /* We shouldn't be in a double exception */
1686
1687 l32i a0, a2, PT_DEPC
1688 bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 2f
1689
1690 /* Make sure the exception originated in the special functions */
1691
1692 movi a0, __tlbtemp_mapping_start
1693 rsr a3, epc1
1694 bltu a3, a0, 2f
1695 movi a0, __tlbtemp_mapping_end
1696 bgeu a3, a0, 2f
1697
1698 /* Check if excvaddr was in one of the TLBTEMP_BASE areas. */
1699
1700 movi a3, TLBTEMP_BASE_1
1701 rsr a0, excvaddr
1702 bltu a0, a3, 2f
1703
1704 addi a1, a0, -(2 << (DCACHE_ALIAS_ORDER + PAGE_SHIFT))
1705 bgeu a1, a3, 2f
1706
1707 /* Check if we have to restore an ITLB mapping. */
1708
1709 movi a1, __tlbtemp_mapping_itlb
1710 rsr a3, epc1
1711 sub a3, a3, a1
1712
1713 /* Calculate VPN */
1714
1715 movi a1, PAGE_MASK
1716 and a1, a1, a0
1717
1718 /* Jump for ITLB entry */
1719
1720 bgez a3, 1f
1721
1722 /* We can use up to two TLBTEMP areas, one for src and one for dst. */
1723
1724 extui a3, a0, PAGE_SHIFT + DCACHE_ALIAS_ORDER, 1
1725 add a1, a3, a1
1726
1727 /* PPN is in a6 for the first TLBTEMP area and in a7 for the second. */
1728
1729 mov a0, a6
1730 movnez a0, a7, a3
1731 j 3b
1732
1733 /* ITLB entry. We only use dst in a6. */
1734
1735 1: witlb a6, a1
1736 isync
1737 j 4b
1738
1739
1740 #endif // DCACHE_WAY_SIZE > PAGE_SIZE
1741
1742
1743 2: /* Invalid PGD, default exception handling */
1744
1745 movi a3, exc_table
1746 rsr a1, depc
1747 xsr a3, excsave1
1748 s32i a1, a2, PT_AREG2
1749 s32i a3, a2, PT_AREG3
1750 mov a1, a2
1751
1752 rsr a2, ps
1753 bbsi.l a2, PS_UM_BIT, 1f
1754 j _kernel_exception
1755 1: j _user_exception
1756
1757 ENDPROC(fast_second_level_miss)
1758
1759 /*
1760 * StoreProhibitedException
1761 *
1762 * Update the pte and invalidate the itlb mapping for this pte.
1763 *
1764 * Entry condition:
1765 *
1766 * a0: trashed, original value saved on stack (PT_AREG0)
1767 * a1: a1
1768 * a2: new stack pointer, original in DEPC
1769 * a3: dispatch table
1770 * depc: a2, original value saved on stack (PT_DEPC)
1771 * excsave_1: a3
1772 *
1773 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
1774 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
1775 */
1776
1777 ENTRY(fast_store_prohibited)
1778
1779 /* Save a1 and a4. */
1780
1781 s32i a1, a2, PT_AREG1
1782 s32i a4, a2, PT_AREG4
1783
1784 GET_CURRENT(a1,a2)
1785 l32i a0, a1, TASK_MM # tsk->mm
1786 beqz a0, 9f
1787
1788 8: rsr a1, excvaddr # fault address
1789 _PGD_OFFSET(a0, a1, a4)
1790 l32i a0, a0, 0
1791 beqz a0, 2f
1792
1793 /* Note that we assume _PAGE_WRITABLE_BIT is only set if pte is valid.*/
1794
1795 _PTE_OFFSET(a0, a1, a4)
1796 l32i a4, a0, 0 # read pteval
1797 bbci.l a4, _PAGE_WRITABLE_BIT, 2f
1798
1799 movi a1, _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_HW_WRITE
1800 or a4, a4, a1
1801 rsr a1, excvaddr
1802 s32i a4, a0, 0
1803
1804 /* We need to flush the cache if we have page coloring. */
1805 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
1806 dhwb a0, 0
1807 #endif
1808 pdtlb a0, a1
1809 wdtlb a4, a0
1810
1811 /* Exit critical section. */
1812
1813 movi a0, 0
1814 s32i a0, a3, EXC_TABLE_FIXUP
1815
1816 /* Restore the working registers, and return. */
1817
1818 l32i a4, a2, PT_AREG4
1819 l32i a1, a2, PT_AREG1
1820 l32i a0, a2, PT_AREG0
1821 l32i a2, a2, PT_DEPC
1822
1823 /* Restore excsave1 and a3. */
1824
1825 xsr a3, excsave1
1826 bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
1827
1828 rsr a2, depc
1829 rfe
1830
1831 /* Double exception. Restore FIXUP handler and return. */
1832
1833 1: xsr a2, depc
1834 esync
1835 rfde
1836
1837 9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
1838 j 8b
1839
1840 2: /* If there was a problem, handle fault in C */
1841
1842 rsr a4, depc # still holds a2
1843 xsr a3, excsave1
1844 s32i a4, a2, PT_AREG2
1845 s32i a3, a2, PT_AREG3
1846 l32i a4, a2, PT_AREG4
1847 mov a1, a2
1848
1849 rsr a2, ps
1850 bbsi.l a2, PS_UM_BIT, 1f
1851 j _kernel_exception
1852 1: j _user_exception
1853
1854 ENDPROC(fast_store_prohibited)
1855
1856 #endif /* CONFIG_MMU */
1857
1858 /*
1859 * System Calls.
1860 *
1861 * void system_call (struct pt_regs* regs, int exccause)
1862 * a2 a3
1863 */
1864
1865 ENTRY(system_call)
1866
1867 entry a1, 32
1868
1869 /* regs->syscall = regs->areg[2] */
1870
1871 l32i a3, a2, PT_AREG2
1872 mov a6, a2
1873 movi a4, do_syscall_trace_enter
1874 s32i a3, a2, PT_SYSCALL
1875 callx4 a4
1876
1877 /* syscall = sys_call_table[syscall_nr] */
1878
1879 movi a4, sys_call_table;
1880 movi a5, __NR_syscall_count
1881 movi a6, -ENOSYS
1882 bgeu a3, a5, 1f
1883
1884 addx4 a4, a3, a4
1885 l32i a4, a4, 0
1886 movi a5, sys_ni_syscall;
1887 beq a4, a5, 1f
1888
1889 /* Load args: arg0 - arg5 are passed via regs. */
1890
1891 l32i a6, a2, PT_AREG6
1892 l32i a7, a2, PT_AREG3
1893 l32i a8, a2, PT_AREG4
1894 l32i a9, a2, PT_AREG5
1895 l32i a10, a2, PT_AREG8
1896 l32i a11, a2, PT_AREG9
1897
1898 /* Pass one additional argument to the syscall: pt_regs (on stack) */
1899 s32i a2, a1, 0
1900
1901 callx4 a4
1902
1903 1: /* regs->areg[2] = return_value */
1904
1905 s32i a6, a2, PT_AREG2
1906 movi a4, do_syscall_trace_leave
1907 mov a6, a2
1908 callx4 a4
1909 retw
1910
1911 ENDPROC(system_call)
1912
1913
1914 /*
1915 * Task switch.
1916 *
1917 * struct task* _switch_to (struct task* prev, struct task* next)
1918 * a2 a2 a3
1919 */
1920
1921 ENTRY(_switch_to)
1922
1923 entry a1, 16
1924
1925 mov a12, a2 # preserve 'prev' (a2)
1926 mov a13, a3 # and 'next' (a3)
1927
1928 l32i a4, a2, TASK_THREAD_INFO
1929 l32i a5, a3, TASK_THREAD_INFO
1930
1931 save_xtregs_user a4 a6 a8 a9 a10 a11 THREAD_XTREGS_USER
1932
1933 s32i a0, a12, THREAD_RA # save return address
1934 s32i a1, a12, THREAD_SP # save stack pointer
1935
1936 /* Disable ints while we manipulate the stack pointer. */
1937
1938 movi a14, (1 << PS_EXCM_BIT) | LOCKLEVEL
1939 xsr a14, ps
1940 rsr a3, excsave1
1941 rsync
1942 s32i a3, a3, EXC_TABLE_FIXUP /* enter critical section */
1943
1944 /* Switch CPENABLE */
1945
1946 #if (XTENSA_HAVE_COPROCESSORS || XTENSA_HAVE_IO_PORTS)
1947 l32i a3, a5, THREAD_CPENABLE
1948 xsr a3, cpenable
1949 s32i a3, a4, THREAD_CPENABLE
1950 #endif
1951
1952 /* Flush register file. */
1953
1954 call0 _spill_registers # destroys a3, a4, and SAR
1955
1956 /* Set kernel stack (and leave critical section)
1957 * Note: It's save to set it here. The stack will not be overwritten
1958 * because the kernel stack will only be loaded again after
1959 * we return from kernel space.
1960 */
1961
1962 rsr a3, excsave1 # exc_table
1963 movi a6, 0
1964 addi a7, a5, PT_REGS_OFFSET
1965 s32i a6, a3, EXC_TABLE_FIXUP
1966 s32i a7, a3, EXC_TABLE_KSTK
1967
1968 /* restore context of the task 'next' */
1969
1970 l32i a0, a13, THREAD_RA # restore return address
1971 l32i a1, a13, THREAD_SP # restore stack pointer
1972
1973 load_xtregs_user a5 a6 a8 a9 a10 a11 THREAD_XTREGS_USER
1974
1975 wsr a14, ps
1976 mov a2, a12 # return 'prev'
1977 rsync
1978
1979 retw
1980
1981 ENDPROC(_switch_to)
1982
1983 ENTRY(ret_from_fork)
1984
1985 /* void schedule_tail (struct task_struct *prev)
1986 * Note: prev is still in a6 (return value from fake call4 frame)
1987 */
1988 movi a4, schedule_tail
1989 callx4 a4
1990
1991 movi a4, do_syscall_trace_leave
1992 mov a6, a1
1993 callx4 a4
1994
1995 j common_exception_return
1996
1997 ENDPROC(ret_from_fork)
1998
1999 /*
2000 * Kernel thread creation helper
2001 * On entry, set up by copy_thread: a2 = thread_fn, a3 = thread_fn arg
2002 * left from _switch_to: a6 = prev
2003 */
2004 ENTRY(ret_from_kernel_thread)
2005
2006 call4 schedule_tail
2007 mov a6, a3
2008 callx4 a2
2009 j common_exception_return
2010
2011 ENDPROC(ret_from_kernel_thread)
kernel source for telekom puls (alcatel/mediatek)