arch/x86/pci/mmconfig-shared.c

   1 /*
   2  * mmconfig-shared.c - Low-level direct PCI config space access via
   3  *                     MMCONFIG - common code between i386 and x86-64.
   4  *
   5  * This code does:
   6  * - known chipset handling
   7  * - ACPI decoding and validation
   8  *
   9  * Per-architecture code takes care of the mappings and accesses
  10  * themselves.
  11  */
  12
  13 #include <linux/pci.h>
  14 #include <linux/init.h>
  15 #include <linux/acpi.h>
  16 #include <linux/sfi_acpi.h>
  17 #include <linux/bitmap.h>
  18 #include <linux/dmi.h>
  19 #include <asm/e820.h>
  20 #include <asm/pci_x86.h>
  21 #include <asm/acpi.h>
  22
  23 #define PREFIX "PCI: "
  24
  25 /* Indicate if the mmcfg resources have been placed into the resource table. */
  26 static int __initdata pci_mmcfg_resources_inserted;
  27
  28 LIST_HEAD(pci_mmcfg_list);
  29
  30 static __init void pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
  31 {
  32         if (cfg->res.parent)
  33                 release_resource(&cfg->res);
  34         list_del(&cfg->list);
  35         kfree(cfg);
  36 }
  37
  38 static __init void free_all_mmcfg(void)
  39 {
  40         struct pci_mmcfg_region *cfg, *tmp;
  41
  42         pci_mmcfg_arch_free();
  43         list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
  44                 pci_mmconfig_remove(cfg);
  45 }
  46
  47 static __init void list_add_sorted(struct pci_mmcfg_region *new)
  48 {
  49         struct pci_mmcfg_region *cfg;
  50
  51         /* keep list sorted by segment and starting bus number */
  52         list_for_each_entry(cfg, &pci_mmcfg_list, list) {
  53                 if (cfg->segment > new->segment ||
  54                     (cfg->segment == new->segment &&
  55                      cfg->start_bus >= new->start_bus)) {
  56                         list_add_tail(&new->list, &cfg->list);
  57                         return;
  58                 }
  59         }
  60         list_add_tail(&new->list, &pci_mmcfg_list);
  61 }
  62
  63 static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
  64                                                         int end, u64 addr)
  65 {
  66         struct pci_mmcfg_region *new;
  67         int num_buses;
  68         struct resource *res;
  69
  70         if (addr == 0)
  71                 return NULL;
  72
  73         new = kzalloc(sizeof(*new), GFP_KERNEL);
  74         if (!new)
  75                 return NULL;
  76
  77         new->address = addr;
  78         new->segment = segment;
  79         new->start_bus = start;
  80         new->end_bus = end;
  81
  82         list_add_sorted(new);
  83
  84         num_buses = end - start + 1;
  85         res = &new->res;
  86         res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
  87         res->end = addr + PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
  88         res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
  89         snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
  90                  "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
  91         res->name = new->name;
  92
  93         printk(KERN_INFO PREFIX "MMCONFIG for domain %04x [bus %02x-%02x] at "
  94                "%pR (base %#lx)\n", segment, start, end, &new->res,
  95                (unsigned long) addr);
  96
  97         return new;
  98 }
  99
 100 struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
 101 {
 102         struct pci_mmcfg_region *cfg;
 103
 104         list_for_each_entry(cfg, &pci_mmcfg_list, list)
 105                 if (cfg->segment == segment &&
 106                     cfg->start_bus <= bus && bus <= cfg->end_bus)
 107                         return cfg;
 108
 109         return NULL;
 110 }
 111
 112 static const char __init *pci_mmcfg_e7520(void)
 113 {
 114         u32 win;
 115         raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
 116
 117         win = win & 0xf000;
 118         if (win == 0x0000 || win == 0xf000)
 119                 return NULL;
 120
 121         if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
 122                 return NULL;
 123
 124         return "Intel Corporation E7520 Memory Controller Hub";
 125 }
 126
 127 static const char __init *pci_mmcfg_intel_945(void)
 128 {
 129         u32 pciexbar, mask = 0, len = 0;
 130
 131         raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
 132
 133         /* Enable bit */
 134         if (!(pciexbar & 1))
 135                 return NULL;
 136
 137         /* Size bits */
 138         switch ((pciexbar >> 1) & 3) {
 139         case 0:
 140                 mask = 0xf0000000U;
 141                 len  = 0x10000000U;
 142                 break;
 143         case 1:
 144                 mask = 0xf8000000U;
 145                 len  = 0x08000000U;
 146                 break;
 147         case 2:
 148                 mask = 0xfc000000U;
 149                 len  = 0x04000000U;
 150                 break;
 151         default:
 152                 return NULL;
 153         }
 154
 155         /* Errata #2, things break when not aligned on a 256Mb boundary */
 156         /* Can only happen in 64M/128M mode */
 157
 158         if ((pciexbar & mask) & 0x0fffffffU)
 159                 return NULL;
 160
 161         /* Don't hit the APIC registers and their friends */
 162         if ((pciexbar & mask) >= 0xf0000000U)
 163                 return NULL;
 164
 165         if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
 166                 return NULL;
 167
 168         return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
 169 }
 170
 171 static const char __init *pci_mmcfg_amd_fam10h(void)
 172 {
 173         u32 low, high, address;
 174         u64 base, msr;
 175         int i;
 176         unsigned segnbits = 0, busnbits, end_bus;
 177
 178         if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
 179                 return NULL;
 180
 181         address = MSR_FAM10H_MMIO_CONF_BASE;
 182         if (rdmsr_safe(address, &low, &high))
 183                 return NULL;
 184
 185         msr = high;
 186         msr <<= 32;
 187         msr |= low;
 188
 189         /* mmconfig is not enable */
 190         if (!(msr & FAM10H_MMIO_CONF_ENABLE))
 191                 return NULL;
 192
 193         base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
 194
 195         busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 196                          FAM10H_MMIO_CONF_BUSRANGE_MASK;
 197
 198         /*
 199          * only handle bus 0 ?
 200          * need to skip it
 201          */
 202         if (!busnbits)
 203                 return NULL;
 204
 205         if (busnbits > 8) {
 206                 segnbits = busnbits - 8;
 207                 busnbits = 8;
 208         }
 209
 210         end_bus = (1 << busnbits) - 1;
 211         for (i = 0; i < (1 << segnbits); i++)
 212                 if (pci_mmconfig_add(i, 0, end_bus,
 213                                      base + (1<<28) * i) == NULL) {
 214                         free_all_mmcfg();
 215                         return NULL;
 216                 }
 217
 218         return "AMD Family 10h NB";
 219 }
 220
 221 static bool __initdata mcp55_checked;
 222 static const char __init *pci_mmcfg_nvidia_mcp55(void)
 223 {
 224         int bus;
 225         int mcp55_mmconf_found = 0;
 226
 227         static const u32 extcfg_regnum          = 0x90;
 228         static const u32 extcfg_regsize         = 4;
 229         static const u32 extcfg_enable_mask     = 1<<31;
 230         static const u32 extcfg_start_mask      = 0xff<<16;
 231         static const int extcfg_start_shift     = 16;
 232         static const u32 extcfg_size_mask       = 0x3<<28;
 233         static const int extcfg_size_shift      = 28;
 234         static const int extcfg_sizebus[]       = {0x100, 0x80, 0x40, 0x20};
 235         static const u32 extcfg_base_mask[]     = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
 236         static const int extcfg_base_lshift     = 25;
 237
 238         /*
 239          * do check if amd fam10h already took over
 240          */
 241         if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
 242                 return NULL;
 243
 244         mcp55_checked = true;
 245         for (bus = 0; bus < 256; bus++) {
 246                 u64 base;
 247                 u32 l, extcfg;
 248                 u16 vendor, device;
 249                 int start, size_index, end;
 250
 251                 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
 252                 vendor = l & 0xffff;
 253                 device = (l >> 16) & 0xffff;
 254
 255                 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
 256                         continue;
 257
 258                 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
 259                                   extcfg_regsize, &extcfg);
 260
 261                 if (!(extcfg & extcfg_enable_mask))
 262                         continue;
 263
 264                 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
 265                 base = extcfg & extcfg_base_mask[size_index];
 266                 /* base could > 4G */
 267                 base <<= extcfg_base_lshift;
 268                 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
 269                 end = start + extcfg_sizebus[size_index] - 1;
 270                 if (pci_mmconfig_add(0, start, end, base) == NULL)
 271                         continue;
 272                 mcp55_mmconf_found++;
 273         }
 274
 275         if (!mcp55_mmconf_found)
 276                 return NULL;
 277
 278         return "nVidia MCP55";
 279 }
 280
 281 struct pci_mmcfg_hostbridge_probe {
 282         u32 bus;
 283         u32 devfn;
 284         u32 vendor;
 285         u32 device;
 286         const char *(*probe)(void);
 287 };
 288
 289 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
 290         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
 291           PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
 292         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
 293           PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
 294         { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
 295           0x1200, pci_mmcfg_amd_fam10h },
 296         { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
 297           0x1200, pci_mmcfg_amd_fam10h },
 298         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
 299           0x0369, pci_mmcfg_nvidia_mcp55 },
 300 };
 301
 302 static void __init pci_mmcfg_check_end_bus_number(void)
 303 {
 304         struct pci_mmcfg_region *cfg, *cfgx;
 305
 306         /* Fixup overlaps */
 307         list_for_each_entry(cfg, &pci_mmcfg_list, list) {
 308                 if (cfg->end_bus < cfg->start_bus)
 309                         cfg->end_bus = 255;
 310
 311                 /* Don't access the list head ! */
 312                 if (cfg->list.next == &pci_mmcfg_list)
 313                         break;
 314
 315                 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
 316                 if (cfg->end_bus >= cfgx->start_bus)
 317                         cfg->end_bus = cfgx->start_bus - 1;
 318         }
 319 }
 320
 321 static int __init pci_mmcfg_check_hostbridge(void)
 322 {
 323         u32 l;
 324         u32 bus, devfn;
 325         u16 vendor, device;
 326         int i;
 327         const char *name;
 328
 329         if (!raw_pci_ops)
 330                 return 0;
 331
 332         free_all_mmcfg();
 333
 334         for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
 335                 bus =  pci_mmcfg_probes[i].bus;
 336                 devfn = pci_mmcfg_probes[i].devfn;
 337                 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
 338                 vendor = l & 0xffff;
 339                 device = (l >> 16) & 0xffff;
 340
 341                 name = NULL;
 342                 if (pci_mmcfg_probes[i].vendor == vendor &&
 343                     pci_mmcfg_probes[i].device == device)
 344                         name = pci_mmcfg_probes[i].probe();
 345
 346                 if (name)
 347                         printk(KERN_INFO PREFIX "%s with MMCONFIG support\n",
 348                                name);
 349         }
 350
 351         /* some end_bus_number is crazy, fix it */
 352         pci_mmcfg_check_end_bus_number();
 353
 354         return !list_empty(&pci_mmcfg_list);
 355 }
 356
 357 static void __init pci_mmcfg_insert_resources(void)
 358 {
 359         struct pci_mmcfg_region *cfg;
 360
 361         list_for_each_entry(cfg, &pci_mmcfg_list, list)
 362                 insert_resource(&iomem_resource, &cfg->res);
 363
 364         /* Mark that the resources have been inserted. */
 365         pci_mmcfg_resources_inserted = 1;
 366 }
 367
 368 static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
 369                                               void *data)
 370 {
 371         struct resource *mcfg_res = data;
 372         struct acpi_resource_address64 address;
 373         acpi_status status;
 374
 375         if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
 376                 struct acpi_resource_fixed_memory32 *fixmem32 =
 377                         &res->data.fixed_memory32;
 378                 if (!fixmem32)
 379                         return AE_OK;
 380                 if ((mcfg_res->start >= fixmem32->address) &&
 381                     (mcfg_res->end < (fixmem32->address +
 382                                       fixmem32->address_length))) {
 383                         mcfg_res->flags = 1;
 384                         return AE_CTRL_TERMINATE;
 385                 }
 386         }
 387         if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
 388             (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
 389                 return AE_OK;
 390
 391         status = acpi_resource_to_address64(res, &address);
 392         if (ACPI_FAILURE(status) ||
 393            (address.address_length <= 0) ||
 394            (address.resource_type != ACPI_MEMORY_RANGE))
 395                 return AE_OK;
 396
 397         if ((mcfg_res->start >= address.minimum) &&
 398             (mcfg_res->end < (address.minimum + address.address_length))) {
 399                 mcfg_res->flags = 1;
 400                 return AE_CTRL_TERMINATE;
 401         }
 402         return AE_OK;
 403 }
 404
 405 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
 406                 void *context, void **rv)
 407 {
 408         struct resource *mcfg_res = context;
 409
 410         acpi_walk_resources(handle, METHOD_NAME__CRS,
 411                             check_mcfg_resource, context);
 412
 413         if (mcfg_res->flags)
 414                 return AE_CTRL_TERMINATE;
 415
 416         return AE_OK;
 417 }
 418
 419 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
 420 {
 421         struct resource mcfg_res;
 422
 423         mcfg_res.start = start;
 424         mcfg_res.end = end - 1;
 425         mcfg_res.flags = 0;
 426
 427         acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
 428
 429         if (!mcfg_res.flags)
 430                 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
 431                                  NULL);
 432
 433         return mcfg_res.flags;
 434 }
 435
 436 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
 437
 438 static int __init is_mmconf_reserved(check_reserved_t is_reserved,
 439                                     struct pci_mmcfg_region *cfg, int with_e820)
 440 {
 441         u64 addr = cfg->res.start;
 442         u64 size = resource_size(&cfg->res);
 443         u64 old_size = size;
 444         int valid = 0, num_buses;
 445
 446         while (!is_reserved(addr, addr + size, E820_RESERVED)) {
 447                 size >>= 1;
 448                 if (size < (16UL<<20))
 449                         break;
 450         }
 451
 452         if (size >= (16UL<<20) || size == old_size) {
 453                 printk(KERN_INFO PREFIX "MMCONFIG at %pR reserved in %s\n",
 454                        &cfg->res,
 455                        with_e820 ? "E820" : "ACPI motherboard resources");
 456                 valid = 1;
 457
 458                 if (old_size != size) {
 459                         /* update end_bus */
 460                         cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
 461                         num_buses = cfg->end_bus - cfg->start_bus + 1;
 462                         cfg->res.end = cfg->res.start +
 463                             PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
 464                         snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
 465                                  "PCI MMCONFIG %04x [bus %02x-%02x]",
 466                                  cfg->segment, cfg->start_bus, cfg->end_bus);
 467                         printk(KERN_INFO PREFIX
 468                                "MMCONFIG for %04x [bus%02x-%02x] "
 469                                "at %pR (base %#lx) (size reduced!)\n",
 470                                cfg->segment, cfg->start_bus, cfg->end_bus,
 471                                &cfg->res, (unsigned long) cfg->address);
 472                 }
 473         }
 474
 475         return valid;
 476 }
 477
 478 static void __init pci_mmcfg_reject_broken(int early)
 479 {
 480         struct pci_mmcfg_region *cfg;
 481
 482         list_for_each_entry(cfg, &pci_mmcfg_list, list) {
 483                 int valid = 0;
 484
 485                 if (!early && !acpi_disabled)
 486                         valid = is_mmconf_reserved(is_acpi_reserved, cfg, 0);
 487
 488                 if (valid)
 489                         continue;
 490
 491                 if (!early)
 492                         printk(KERN_ERR FW_BUG PREFIX
 493                                "MMCONFIG at %pR not reserved in "
 494                                "ACPI motherboard resources\n", &cfg->res);
 495
 496                 /* Don't try to do this check unless configuration
 497                    type 1 is available. how about type 2 ?*/
 498                 if (raw_pci_ops)
 499                         valid = is_mmconf_reserved(e820_all_mapped, cfg, 1);
 500
 501                 if (!valid)
 502                         goto reject;
 503         }
 504
 505         return;
 506
 507 reject:
 508         printk(KERN_INFO PREFIX "not using MMCONFIG\n");
 509         free_all_mmcfg();
 510 }
 511
 512 static int __initdata known_bridge;
 513
 514 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
 515                                         struct acpi_mcfg_allocation *cfg)
 516 {
 517         int year;
 518
 519         if (cfg->address < 0xFFFFFFFF)
 520                 return 0;
 521
 522         if (!strcmp(mcfg->header.oem_id, "SGI"))
 523                 return 0;
 524
 525         if (mcfg->header.revision >= 1) {
 526                 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
 527                     year >= 2010)
 528                         return 0;
 529         }
 530
 531         printk(KERN_ERR PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
 532                "is above 4GB, ignored\n", cfg->pci_segment,
 533                cfg->start_bus_number, cfg->end_bus_number, cfg->address);
 534         return -EINVAL;
 535 }
 536
 537 static int __init pci_parse_mcfg(struct acpi_table_header *header)
 538 {
 539         struct acpi_table_mcfg *mcfg;
 540         struct acpi_mcfg_allocation *cfg_table, *cfg;
 541         unsigned long i;
 542         int entries;
 543
 544         if (!header)
 545                 return -EINVAL;
 546
 547         mcfg = (struct acpi_table_mcfg *)header;
 548
 549         /* how many config structures do we have */
 550         free_all_mmcfg();
 551         entries = 0;
 552         i = header->length - sizeof(struct acpi_table_mcfg);
 553         while (i >= sizeof(struct acpi_mcfg_allocation)) {
 554                 entries++;
 555                 i -= sizeof(struct acpi_mcfg_allocation);
 556         };
 557         if (entries == 0) {
 558                 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
 559                 return -ENODEV;
 560         }
 561
 562         cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
 563         for (i = 0; i < entries; i++) {
 564                 cfg = &cfg_table[i];
 565                 if (acpi_mcfg_check_entry(mcfg, cfg)) {
 566                         free_all_mmcfg();
 567                         return -ENODEV;
 568                 }
 569
 570                 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
 571                                    cfg->end_bus_number, cfg->address) == NULL) {
 572                         printk(KERN_WARNING PREFIX
 573                                "no memory for MCFG entries\n");
 574                         free_all_mmcfg();
 575                         return -ENOMEM;
 576                 }
 577         }
 578
 579         return 0;
 580 }
 581
 582 static void __init __pci_mmcfg_init(int early)
 583 {
 584         /* MMCONFIG disabled */
 585         if ((pci_probe & PCI_PROBE_MMCONF) == 0)
 586                 return;
 587
 588         /* MMCONFIG already enabled */
 589         if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
 590                 return;
 591
 592         /* for late to exit */
 593         if (known_bridge)
 594                 return;
 595
 596         if (early) {
 597                 if (pci_mmcfg_check_hostbridge())
 598                         known_bridge = 1;
 599         }
 600
 601         if (!known_bridge)
 602                 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
 603
 604         pci_mmcfg_reject_broken(early);
 605
 606         if (list_empty(&pci_mmcfg_list))
 607                 return;
 608
 609         if (pci_mmcfg_arch_init())
 610                 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
 611         else {
 612                 /*
 613                  * Signal not to attempt to insert mmcfg resources because
 614                  * the architecture mmcfg setup could not initialize.
 615                  */
 616                 pci_mmcfg_resources_inserted = 1;
 617         }
 618 }
 619
 620 void __init pci_mmcfg_early_init(void)
 621 {
 622         __pci_mmcfg_init(1);
 623 }
 624
 625 void __init pci_mmcfg_late_init(void)
 626 {
 627         __pci_mmcfg_init(0);
 628 }
 629
 630 static int __init pci_mmcfg_late_insert_resources(void)
 631 {
 632         /*
 633          * If resources are already inserted or we are not using MMCONFIG,
 634          * don't insert the resources.
 635          */
 636         if ((pci_mmcfg_resources_inserted == 1) ||
 637             (pci_probe & PCI_PROBE_MMCONF) == 0 ||
 638             list_empty(&pci_mmcfg_list))
 639                 return 1;
 640
 641         /*
 642          * Attempt to insert the mmcfg resources but not with the busy flag
 643          * marked so it won't cause request errors when __request_region is
 644          * called.
 645          */
 646         pci_mmcfg_insert_resources();
 647
 648         return 0;
 649 }
 650
 651 /*
 652  * Perform MMCONFIG resource insertion after PCI initialization to allow for
 653  * misprogrammed MCFG tables that state larger sizes but actually conflict
 654  * with other system resources.
 655  */
 656 late_initcall(pci_mmcfg_late_insert_resources);