1 /* bpf_jit_comp.c : BPF JIT compiler
3 * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com)
4 * Internal BPF Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; version 2
11 #include <linux/netdevice.h>
12 #include <linux/filter.h>
13 #include <linux/if_vlan.h>
14 #include <asm/cacheflush.h>
15 #include <asm/set_memory.h>
16 #include <asm/nospec-branch.h>
17 #include <linux/bpf.h>
19 int bpf_jit_enable __read_mostly
;
22 * assembly code in arch/x86/net/bpf_jit.S
24 extern u8 sk_load_word
[], sk_load_half
[], sk_load_byte
[];
25 extern u8 sk_load_word_positive_offset
[], sk_load_half_positive_offset
[];
26 extern u8 sk_load_byte_positive_offset
[];
27 extern u8 sk_load_word_negative_offset
[], sk_load_half_negative_offset
[];
28 extern u8 sk_load_byte_negative_offset
[];
30 static u8
*emit_code(u8
*ptr
, u32 bytes
, unsigned int len
)
43 #define EMIT(bytes, len) \
44 do { prog = emit_code(prog, bytes, len); cnt += len; } while (0)
46 #define EMIT1(b1) EMIT(b1, 1)
47 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2)
48 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
49 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
50 #define EMIT1_off32(b1, off) \
51 do {EMIT1(b1); EMIT(off, 4); } while (0)
52 #define EMIT2_off32(b1, b2, off) \
53 do {EMIT2(b1, b2); EMIT(off, 4); } while (0)
54 #define EMIT3_off32(b1, b2, b3, off) \
55 do {EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
56 #define EMIT4_off32(b1, b2, b3, b4, off) \
57 do {EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
59 static bool is_imm8(int value
)
61 return value
<= 127 && value
>= -128;
64 static bool is_simm32(s64 value
)
66 return value
== (s64
) (s32
) value
;
70 #define EMIT_mov(DST, SRC) \
72 EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \
75 static int bpf_size_to_x86_bytes(int bpf_size
)
77 if (bpf_size
== BPF_W
)
79 else if (bpf_size
== BPF_H
)
81 else if (bpf_size
== BPF_B
)
83 else if (bpf_size
== BPF_DW
)
89 /* list of x86 cond jumps opcodes (. + s8)
90 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
103 static void bpf_flush_icache(void *start
, void *end
)
105 mm_segment_t old_fs
= get_fs();
109 flush_icache_range((unsigned long)start
, (unsigned long)end
);
113 #define CHOOSE_LOAD_FUNC(K, func) \
114 ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset)
116 /* pick a register outside of BPF range for JIT internal work */
117 #define AUX_REG (MAX_BPF_JIT_REG + 1)
119 /* The following table maps BPF registers to x64 registers.
121 * x64 register r12 is unused, since if used as base address
122 * register in load/store instructions, it always needs an
123 * extra byte of encoding and is callee saved.
125 * r9 caches skb->len - skb->data_len
126 * r10 caches skb->data, and used for blinding (if enabled)
128 static const int reg2hex
[] = {
129 [BPF_REG_0
] = 0, /* rax */
130 [BPF_REG_1
] = 7, /* rdi */
131 [BPF_REG_2
] = 6, /* rsi */
132 [BPF_REG_3
] = 2, /* rdx */
133 [BPF_REG_4
] = 1, /* rcx */
134 [BPF_REG_5
] = 0, /* r8 */
135 [BPF_REG_6
] = 3, /* rbx callee saved */
136 [BPF_REG_7
] = 5, /* r13 callee saved */
137 [BPF_REG_8
] = 6, /* r14 callee saved */
138 [BPF_REG_9
] = 7, /* r15 callee saved */
139 [BPF_REG_FP
] = 5, /* rbp readonly */
140 [BPF_REG_AX
] = 2, /* r10 temp register */
141 [AUX_REG
] = 3, /* r11 temp register */
144 /* is_ereg() == true if BPF register 'reg' maps to x64 r8..r15
145 * which need extra byte of encoding.
146 * rax,rcx,...,rbp have simpler encoding
148 static bool is_ereg(u32 reg
)
150 return (1 << reg
) & (BIT(BPF_REG_5
) |
158 /* add modifiers if 'reg' maps to x64 registers r8..r15 */
159 static u8
add_1mod(u8 byte
, u32 reg
)
166 static u8
add_2mod(u8 byte
, u32 r1
, u32 r2
)
175 /* encode 'dst_reg' register into x64 opcode 'byte' */
176 static u8
add_1reg(u8 byte
, u32 dst_reg
)
178 return byte
+ reg2hex
[dst_reg
];
181 /* encode 'dst_reg' and 'src_reg' registers into x64 opcode 'byte' */
182 static u8
add_2reg(u8 byte
, u32 dst_reg
, u32 src_reg
)
184 return byte
+ reg2hex
[dst_reg
] + (reg2hex
[src_reg
] << 3);
187 static void jit_fill_hole(void *area
, unsigned int size
)
189 /* fill whole space with int3 instructions */
190 memset(area
, 0xcc, size
);
194 int cleanup_addr
; /* epilogue code offset */
199 /* maximum number of bytes emitted while JITing one eBPF insn */
200 #define BPF_MAX_INSN_SIZE 128
201 #define BPF_INSN_SAFETY 64
203 #define AUX_STACK_SPACE \
204 (32 /* space for rbx, r13, r14, r15 */ + \
205 8 /* space for skb_copy_bits() buffer */)
207 #define PROLOGUE_SIZE 37
209 /* emit x64 prologue code for BPF program and check it's size.
210 * bpf_tail_call helper will skip it while jumping into another program
212 static void emit_prologue(u8
**pprog
, u32 stack_depth
)
217 EMIT1(0x55); /* push rbp */
218 EMIT3(0x48, 0x89, 0xE5); /* mov rbp,rsp */
220 /* sub rsp, rounded_stack_depth + AUX_STACK_SPACE */
221 EMIT3_off32(0x48, 0x81, 0xEC,
222 round_up(stack_depth
, 8) + AUX_STACK_SPACE
);
224 /* sub rbp, AUX_STACK_SPACE */
225 EMIT4(0x48, 0x83, 0xED, AUX_STACK_SPACE
);
227 /* all classic BPF filters use R6(rbx) save it */
229 /* mov qword ptr [rbp+0],rbx */
230 EMIT4(0x48, 0x89, 0x5D, 0);
232 /* bpf_convert_filter() maps classic BPF register X to R7 and uses R8
233 * as temporary, so all tcpdump filters need to spill/fill R7(r13) and
234 * R8(r14). R9(r15) spill could be made conditional, but there is only
235 * one 'bpf_error' return path out of helper functions inside bpf_jit.S
236 * The overhead of extra spill is negligible for any filter other
237 * than synthetic ones. Therefore not worth adding complexity.
240 /* mov qword ptr [rbp+8],r13 */
241 EMIT4(0x4C, 0x89, 0x6D, 8);
242 /* mov qword ptr [rbp+16],r14 */
243 EMIT4(0x4C, 0x89, 0x75, 16);
244 /* mov qword ptr [rbp+24],r15 */
245 EMIT4(0x4C, 0x89, 0x7D, 24);
247 /* Clear the tail call counter (tail_call_cnt): for eBPF tail calls
248 * we need to reset the counter to 0. It's done in two instructions,
249 * resetting rax register to 0 (xor on eax gets 0 extended), and
250 * moving it to the counter location.
255 /* mov qword ptr [rbp+32], rax */
256 EMIT4(0x48, 0x89, 0x45, 32);
258 BUILD_BUG_ON(cnt
!= PROLOGUE_SIZE
);
262 /* generate the following code:
263 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
264 * if (index >= array->map.max_entries)
266 * if (++tail_call_cnt > MAX_TAIL_CALL_CNT)
268 * prog = array->ptrs[index];
271 * goto *(prog->bpf_func + prologue_size);
274 static void emit_bpf_tail_call(u8
**pprog
)
277 int label1
, label2
, label3
;
280 /* rdi - pointer to ctx
281 * rsi - pointer to bpf_array
282 * rdx - index in bpf_array
285 /* if (index >= array->map.max_entries)
288 EMIT2(0x89, 0xD2); /* mov edx, edx */
289 EMIT3(0x39, 0x56, /* cmp dword ptr [rsi + 16], edx */
290 offsetof(struct bpf_array
, map
.max_entries
));
291 #define OFFSET1 (41 + RETPOLINE_RAX_BPF_JIT_SIZE) /* number of bytes to jump */
292 EMIT2(X86_JBE
, OFFSET1
); /* jbe out */
295 /* if (tail_call_cnt > MAX_TAIL_CALL_CNT)
298 EMIT2_off32(0x8B, 0x85, 36); /* mov eax, dword ptr [rbp + 36] */
299 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT
); /* cmp eax, MAX_TAIL_CALL_CNT */
300 #define OFFSET2 (30 + RETPOLINE_RAX_BPF_JIT_SIZE)
301 EMIT2(X86_JA
, OFFSET2
); /* ja out */
303 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */
304 EMIT2_off32(0x89, 0x85, 36); /* mov dword ptr [rbp + 36], eax */
306 /* prog = array->ptrs[index]; */
307 EMIT4_off32(0x48, 0x8B, 0x84, 0xD6, /* mov rax, [rsi + rdx * 8 + offsetof(...)] */
308 offsetof(struct bpf_array
, ptrs
));
313 EMIT3(0x48, 0x85, 0xC0); /* test rax,rax */
314 #define OFFSET3 (8 + RETPOLINE_RAX_BPF_JIT_SIZE)
315 EMIT2(X86_JE
, OFFSET3
); /* je out */
318 /* goto *(prog->bpf_func + prologue_size); */
319 EMIT4(0x48, 0x8B, 0x40, /* mov rax, qword ptr [rax + 32] */
320 offsetof(struct bpf_prog
, bpf_func
));
321 EMIT4(0x48, 0x83, 0xC0, PROLOGUE_SIZE
); /* add rax, prologue_size */
323 /* now we're ready to jump into next BPF program
324 * rdi == ctx (1st arg)
325 * rax == prog->bpf_func + prologue_size
327 RETPOLINE_RAX_BPF_JIT();
330 BUILD_BUG_ON(cnt
- label1
!= OFFSET1
);
331 BUILD_BUG_ON(cnt
- label2
!= OFFSET2
);
332 BUILD_BUG_ON(cnt
- label3
!= OFFSET3
);
337 static void emit_load_skb_data_hlen(u8
**pprog
)
342 /* r9d = skb->len - skb->data_len (headlen)
345 /* mov %r9d, off32(%rdi) */
346 EMIT3_off32(0x44, 0x8b, 0x8f, offsetof(struct sk_buff
, len
));
348 /* sub %r9d, off32(%rdi) */
349 EMIT3_off32(0x44, 0x2b, 0x8f, offsetof(struct sk_buff
, data_len
));
351 /* mov %r10, off32(%rdi) */
352 EMIT3_off32(0x4c, 0x8b, 0x97, offsetof(struct sk_buff
, data
));
356 static int do_jit(struct bpf_prog
*bpf_prog
, int *addrs
, u8
*image
,
357 int oldproglen
, struct jit_context
*ctx
)
359 struct bpf_insn
*insn
= bpf_prog
->insnsi
;
360 int insn_cnt
= bpf_prog
->len
;
361 bool seen_ld_abs
= ctx
->seen_ld_abs
| (oldproglen
== 0);
362 bool seen_ax_reg
= ctx
->seen_ax_reg
| (oldproglen
== 0);
363 bool seen_exit
= false;
364 u8 temp
[BPF_MAX_INSN_SIZE
+ BPF_INSN_SAFETY
];
369 emit_prologue(&prog
, bpf_prog
->aux
->stack_depth
);
372 emit_load_skb_data_hlen(&prog
);
374 for (i
= 0; i
< insn_cnt
; i
++, insn
++) {
375 const s32 imm32
= insn
->imm
;
376 u32 dst_reg
= insn
->dst_reg
;
377 u32 src_reg
= insn
->src_reg
;
378 u8 b1
= 0, b2
= 0, b3
= 0;
381 bool reload_skb_data
;
385 if (dst_reg
== BPF_REG_AX
|| src_reg
== BPF_REG_AX
)
386 ctx
->seen_ax_reg
= seen_ax_reg
= true;
388 switch (insn
->code
) {
390 case BPF_ALU
| BPF_ADD
| BPF_X
:
391 case BPF_ALU
| BPF_SUB
| BPF_X
:
392 case BPF_ALU
| BPF_AND
| BPF_X
:
393 case BPF_ALU
| BPF_OR
| BPF_X
:
394 case BPF_ALU
| BPF_XOR
| BPF_X
:
395 case BPF_ALU64
| BPF_ADD
| BPF_X
:
396 case BPF_ALU64
| BPF_SUB
| BPF_X
:
397 case BPF_ALU64
| BPF_AND
| BPF_X
:
398 case BPF_ALU64
| BPF_OR
| BPF_X
:
399 case BPF_ALU64
| BPF_XOR
| BPF_X
:
400 switch (BPF_OP(insn
->code
)) {
401 case BPF_ADD
: b2
= 0x01; break;
402 case BPF_SUB
: b2
= 0x29; break;
403 case BPF_AND
: b2
= 0x21; break;
404 case BPF_OR
: b2
= 0x09; break;
405 case BPF_XOR
: b2
= 0x31; break;
407 if (BPF_CLASS(insn
->code
) == BPF_ALU64
)
408 EMIT1(add_2mod(0x48, dst_reg
, src_reg
));
409 else if (is_ereg(dst_reg
) || is_ereg(src_reg
))
410 EMIT1(add_2mod(0x40, dst_reg
, src_reg
));
411 EMIT2(b2
, add_2reg(0xC0, dst_reg
, src_reg
));
415 case BPF_ALU64
| BPF_MOV
| BPF_X
:
416 EMIT_mov(dst_reg
, src_reg
);
420 case BPF_ALU
| BPF_MOV
| BPF_X
:
421 if (is_ereg(dst_reg
) || is_ereg(src_reg
))
422 EMIT1(add_2mod(0x40, dst_reg
, src_reg
));
423 EMIT2(0x89, add_2reg(0xC0, dst_reg
, src_reg
));
427 case BPF_ALU
| BPF_NEG
:
428 case BPF_ALU64
| BPF_NEG
:
429 if (BPF_CLASS(insn
->code
) == BPF_ALU64
)
430 EMIT1(add_1mod(0x48, dst_reg
));
431 else if (is_ereg(dst_reg
))
432 EMIT1(add_1mod(0x40, dst_reg
));
433 EMIT2(0xF7, add_1reg(0xD8, dst_reg
));
436 case BPF_ALU
| BPF_ADD
| BPF_K
:
437 case BPF_ALU
| BPF_SUB
| BPF_K
:
438 case BPF_ALU
| BPF_AND
| BPF_K
:
439 case BPF_ALU
| BPF_OR
| BPF_K
:
440 case BPF_ALU
| BPF_XOR
| BPF_K
:
441 case BPF_ALU64
| BPF_ADD
| BPF_K
:
442 case BPF_ALU64
| BPF_SUB
| BPF_K
:
443 case BPF_ALU64
| BPF_AND
| BPF_K
:
444 case BPF_ALU64
| BPF_OR
| BPF_K
:
445 case BPF_ALU64
| BPF_XOR
| BPF_K
:
446 if (BPF_CLASS(insn
->code
) == BPF_ALU64
)
447 EMIT1(add_1mod(0x48, dst_reg
));
448 else if (is_ereg(dst_reg
))
449 EMIT1(add_1mod(0x40, dst_reg
));
451 switch (BPF_OP(insn
->code
)) {
452 case BPF_ADD
: b3
= 0xC0; break;
453 case BPF_SUB
: b3
= 0xE8; break;
454 case BPF_AND
: b3
= 0xE0; break;
455 case BPF_OR
: b3
= 0xC8; break;
456 case BPF_XOR
: b3
= 0xF0; break;
460 EMIT3(0x83, add_1reg(b3
, dst_reg
), imm32
);
462 EMIT2_off32(0x81, add_1reg(b3
, dst_reg
), imm32
);
465 case BPF_ALU64
| BPF_MOV
| BPF_K
:
466 /* optimization: if imm32 is positive,
467 * use 'mov eax, imm32' (which zero-extends imm32)
471 /* 'mov rax, imm32' sign extends imm32 */
472 b1
= add_1mod(0x48, dst_reg
);
475 EMIT3_off32(b1
, b2
, add_1reg(b3
, dst_reg
), imm32
);
479 case BPF_ALU
| BPF_MOV
| BPF_K
:
480 /* optimization: if imm32 is zero, use 'xor <dst>,<dst>'
484 if (is_ereg(dst_reg
))
485 EMIT1(add_2mod(0x40, dst_reg
, dst_reg
));
488 EMIT2(b2
, add_2reg(b3
, dst_reg
, dst_reg
));
492 /* mov %eax, imm32 */
493 if (is_ereg(dst_reg
))
494 EMIT1(add_1mod(0x40, dst_reg
));
495 EMIT1_off32(add_1reg(0xB8, dst_reg
), imm32
);
498 case BPF_LD
| BPF_IMM
| BPF_DW
:
499 /* optimization: if imm64 is zero, use 'xor <dst>,<dst>'
502 if (insn
[0].imm
== 0 && insn
[1].imm
== 0) {
503 b1
= add_2mod(0x48, dst_reg
, dst_reg
);
506 EMIT3(b1
, b2
, add_2reg(b3
, dst_reg
, dst_reg
));
513 /* movabsq %rax, imm64 */
514 EMIT2(add_1mod(0x48, dst_reg
), add_1reg(0xB8, dst_reg
));
515 EMIT(insn
[0].imm
, 4);
516 EMIT(insn
[1].imm
, 4);
522 /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
523 case BPF_ALU
| BPF_MOD
| BPF_X
:
524 case BPF_ALU
| BPF_DIV
| BPF_X
:
525 case BPF_ALU
| BPF_MOD
| BPF_K
:
526 case BPF_ALU
| BPF_DIV
| BPF_K
:
527 case BPF_ALU64
| BPF_MOD
| BPF_X
:
528 case BPF_ALU64
| BPF_DIV
| BPF_X
:
529 case BPF_ALU64
| BPF_MOD
| BPF_K
:
530 case BPF_ALU64
| BPF_DIV
| BPF_K
:
531 EMIT1(0x50); /* push rax */
532 EMIT1(0x52); /* push rdx */
534 if (BPF_SRC(insn
->code
) == BPF_X
)
535 /* mov r11, src_reg */
536 EMIT_mov(AUX_REG
, src_reg
);
539 EMIT3_off32(0x49, 0xC7, 0xC3, imm32
);
541 /* mov rax, dst_reg */
542 EMIT_mov(BPF_REG_0
, dst_reg
);
545 * equivalent to 'xor rdx, rdx', but one byte less
549 if (BPF_SRC(insn
->code
) == BPF_X
) {
550 /* if (src_reg == 0) return 0 */
553 EMIT4(0x49, 0x83, 0xFB, 0x00);
555 /* jne .+9 (skip over pop, pop, xor and jmp) */
556 EMIT2(X86_JNE
, 1 + 1 + 2 + 5);
557 EMIT1(0x5A); /* pop rdx */
558 EMIT1(0x58); /* pop rax */
559 EMIT2(0x31, 0xc0); /* xor eax, eax */
562 * addrs[i] - 11, because there are 11 bytes
563 * after this insn: div, mov, pop, pop, mov
565 jmp_offset
= ctx
->cleanup_addr
- (addrs
[i
] - 11);
566 EMIT1_off32(0xE9, jmp_offset
);
569 if (BPF_CLASS(insn
->code
) == BPF_ALU64
)
571 EMIT3(0x49, 0xF7, 0xF3);
574 EMIT3(0x41, 0xF7, 0xF3);
576 if (BPF_OP(insn
->code
) == BPF_MOD
)
578 EMIT3(0x49, 0x89, 0xD3);
581 EMIT3(0x49, 0x89, 0xC3);
583 EMIT1(0x5A); /* pop rdx */
584 EMIT1(0x58); /* pop rax */
586 /* mov dst_reg, r11 */
587 EMIT_mov(dst_reg
, AUX_REG
);
590 case BPF_ALU
| BPF_MUL
| BPF_K
:
591 case BPF_ALU
| BPF_MUL
| BPF_X
:
592 case BPF_ALU64
| BPF_MUL
| BPF_K
:
593 case BPF_ALU64
| BPF_MUL
| BPF_X
:
594 EMIT1(0x50); /* push rax */
595 EMIT1(0x52); /* push rdx */
597 /* mov r11, dst_reg */
598 EMIT_mov(AUX_REG
, dst_reg
);
600 if (BPF_SRC(insn
->code
) == BPF_X
)
601 /* mov rax, src_reg */
602 EMIT_mov(BPF_REG_0
, src_reg
);
605 EMIT3_off32(0x48, 0xC7, 0xC0, imm32
);
607 if (BPF_CLASS(insn
->code
) == BPF_ALU64
)
608 EMIT1(add_1mod(0x48, AUX_REG
));
609 else if (is_ereg(AUX_REG
))
610 EMIT1(add_1mod(0x40, AUX_REG
));
612 EMIT2(0xF7, add_1reg(0xE0, AUX_REG
));
615 EMIT_mov(AUX_REG
, BPF_REG_0
);
617 EMIT1(0x5A); /* pop rdx */
618 EMIT1(0x58); /* pop rax */
620 /* mov dst_reg, r11 */
621 EMIT_mov(dst_reg
, AUX_REG
);
625 case BPF_ALU
| BPF_LSH
| BPF_K
:
626 case BPF_ALU
| BPF_RSH
| BPF_K
:
627 case BPF_ALU
| BPF_ARSH
| BPF_K
:
628 case BPF_ALU64
| BPF_LSH
| BPF_K
:
629 case BPF_ALU64
| BPF_RSH
| BPF_K
:
630 case BPF_ALU64
| BPF_ARSH
| BPF_K
:
631 if (BPF_CLASS(insn
->code
) == BPF_ALU64
)
632 EMIT1(add_1mod(0x48, dst_reg
));
633 else if (is_ereg(dst_reg
))
634 EMIT1(add_1mod(0x40, dst_reg
));
636 switch (BPF_OP(insn
->code
)) {
637 case BPF_LSH
: b3
= 0xE0; break;
638 case BPF_RSH
: b3
= 0xE8; break;
639 case BPF_ARSH
: b3
= 0xF8; break;
641 EMIT3(0xC1, add_1reg(b3
, dst_reg
), imm32
);
644 case BPF_ALU
| BPF_LSH
| BPF_X
:
645 case BPF_ALU
| BPF_RSH
| BPF_X
:
646 case BPF_ALU
| BPF_ARSH
| BPF_X
:
647 case BPF_ALU64
| BPF_LSH
| BPF_X
:
648 case BPF_ALU64
| BPF_RSH
| BPF_X
:
649 case BPF_ALU64
| BPF_ARSH
| BPF_X
:
651 /* check for bad case when dst_reg == rcx */
652 if (dst_reg
== BPF_REG_4
) {
653 /* mov r11, dst_reg */
654 EMIT_mov(AUX_REG
, dst_reg
);
658 if (src_reg
!= BPF_REG_4
) { /* common case */
659 EMIT1(0x51); /* push rcx */
661 /* mov rcx, src_reg */
662 EMIT_mov(BPF_REG_4
, src_reg
);
665 /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
666 if (BPF_CLASS(insn
->code
) == BPF_ALU64
)
667 EMIT1(add_1mod(0x48, dst_reg
));
668 else if (is_ereg(dst_reg
))
669 EMIT1(add_1mod(0x40, dst_reg
));
671 switch (BPF_OP(insn
->code
)) {
672 case BPF_LSH
: b3
= 0xE0; break;
673 case BPF_RSH
: b3
= 0xE8; break;
674 case BPF_ARSH
: b3
= 0xF8; break;
676 EMIT2(0xD3, add_1reg(b3
, dst_reg
));
678 if (src_reg
!= BPF_REG_4
)
679 EMIT1(0x59); /* pop rcx */
681 if (insn
->dst_reg
== BPF_REG_4
)
682 /* mov dst_reg, r11 */
683 EMIT_mov(insn
->dst_reg
, AUX_REG
);
686 case BPF_ALU
| BPF_END
| BPF_FROM_BE
:
689 /* emit 'ror %ax, 8' to swap lower 2 bytes */
691 if (is_ereg(dst_reg
))
693 EMIT3(0xC1, add_1reg(0xC8, dst_reg
), 8);
695 /* emit 'movzwl eax, ax' */
696 if (is_ereg(dst_reg
))
697 EMIT3(0x45, 0x0F, 0xB7);
700 EMIT1(add_2reg(0xC0, dst_reg
, dst_reg
));
703 /* emit 'bswap eax' to swap lower 4 bytes */
704 if (is_ereg(dst_reg
))
708 EMIT1(add_1reg(0xC8, dst_reg
));
711 /* emit 'bswap rax' to swap 8 bytes */
712 EMIT3(add_1mod(0x48, dst_reg
), 0x0F,
713 add_1reg(0xC8, dst_reg
));
718 case BPF_ALU
| BPF_END
| BPF_FROM_LE
:
721 /* emit 'movzwl eax, ax' to zero extend 16-bit
724 if (is_ereg(dst_reg
))
725 EMIT3(0x45, 0x0F, 0xB7);
728 EMIT1(add_2reg(0xC0, dst_reg
, dst_reg
));
731 /* emit 'mov eax, eax' to clear upper 32-bits */
732 if (is_ereg(dst_reg
))
734 EMIT2(0x89, add_2reg(0xC0, dst_reg
, dst_reg
));
742 /* ST: *(u8*)(dst_reg + off) = imm */
743 case BPF_ST
| BPF_MEM
| BPF_B
:
744 if (is_ereg(dst_reg
))
749 case BPF_ST
| BPF_MEM
| BPF_H
:
750 if (is_ereg(dst_reg
))
751 EMIT3(0x66, 0x41, 0xC7);
755 case BPF_ST
| BPF_MEM
| BPF_W
:
756 if (is_ereg(dst_reg
))
761 case BPF_ST
| BPF_MEM
| BPF_DW
:
762 EMIT2(add_1mod(0x48, dst_reg
), 0xC7);
764 st
: if (is_imm8(insn
->off
))
765 EMIT2(add_1reg(0x40, dst_reg
), insn
->off
);
767 EMIT1_off32(add_1reg(0x80, dst_reg
), insn
->off
);
769 EMIT(imm32
, bpf_size_to_x86_bytes(BPF_SIZE(insn
->code
)));
772 /* STX: *(u8*)(dst_reg + off) = src_reg */
773 case BPF_STX
| BPF_MEM
| BPF_B
:
774 /* emit 'mov byte ptr [rax + off], al' */
775 if (is_ereg(dst_reg
) || is_ereg(src_reg
) ||
776 /* have to add extra byte for x86 SIL, DIL regs */
777 src_reg
== BPF_REG_1
|| src_reg
== BPF_REG_2
)
778 EMIT2(add_2mod(0x40, dst_reg
, src_reg
), 0x88);
782 case BPF_STX
| BPF_MEM
| BPF_H
:
783 if (is_ereg(dst_reg
) || is_ereg(src_reg
))
784 EMIT3(0x66, add_2mod(0x40, dst_reg
, src_reg
), 0x89);
788 case BPF_STX
| BPF_MEM
| BPF_W
:
789 if (is_ereg(dst_reg
) || is_ereg(src_reg
))
790 EMIT2(add_2mod(0x40, dst_reg
, src_reg
), 0x89);
794 case BPF_STX
| BPF_MEM
| BPF_DW
:
795 EMIT2(add_2mod(0x48, dst_reg
, src_reg
), 0x89);
796 stx
: if (is_imm8(insn
->off
))
797 EMIT2(add_2reg(0x40, dst_reg
, src_reg
), insn
->off
);
799 EMIT1_off32(add_2reg(0x80, dst_reg
, src_reg
),
803 /* LDX: dst_reg = *(u8*)(src_reg + off) */
804 case BPF_LDX
| BPF_MEM
| BPF_B
:
805 /* emit 'movzx rax, byte ptr [rax + off]' */
806 EMIT3(add_2mod(0x48, src_reg
, dst_reg
), 0x0F, 0xB6);
808 case BPF_LDX
| BPF_MEM
| BPF_H
:
809 /* emit 'movzx rax, word ptr [rax + off]' */
810 EMIT3(add_2mod(0x48, src_reg
, dst_reg
), 0x0F, 0xB7);
812 case BPF_LDX
| BPF_MEM
| BPF_W
:
813 /* emit 'mov eax, dword ptr [rax+0x14]' */
814 if (is_ereg(dst_reg
) || is_ereg(src_reg
))
815 EMIT2(add_2mod(0x40, src_reg
, dst_reg
), 0x8B);
819 case BPF_LDX
| BPF_MEM
| BPF_DW
:
820 /* emit 'mov rax, qword ptr [rax+0x14]' */
821 EMIT2(add_2mod(0x48, src_reg
, dst_reg
), 0x8B);
822 ldx
: /* if insn->off == 0 we can save one extra byte, but
823 * special case of x86 r13 which always needs an offset
824 * is not worth the hassle
826 if (is_imm8(insn
->off
))
827 EMIT2(add_2reg(0x40, src_reg
, dst_reg
), insn
->off
);
829 EMIT1_off32(add_2reg(0x80, src_reg
, dst_reg
),
833 /* STX XADD: lock *(u32*)(dst_reg + off) += src_reg */
834 case BPF_STX
| BPF_XADD
| BPF_W
:
835 /* emit 'lock add dword ptr [rax + off], eax' */
836 if (is_ereg(dst_reg
) || is_ereg(src_reg
))
837 EMIT3(0xF0, add_2mod(0x40, dst_reg
, src_reg
), 0x01);
841 case BPF_STX
| BPF_XADD
| BPF_DW
:
842 EMIT3(0xF0, add_2mod(0x48, dst_reg
, src_reg
), 0x01);
843 xadd
: if (is_imm8(insn
->off
))
844 EMIT2(add_2reg(0x40, dst_reg
, src_reg
), insn
->off
);
846 EMIT1_off32(add_2reg(0x80, dst_reg
, src_reg
),
851 case BPF_JMP
| BPF_CALL
:
852 func
= (u8
*) __bpf_call_base
+ imm32
;
853 jmp_offset
= func
- (image
+ addrs
[i
]);
855 reload_skb_data
= bpf_helper_changes_pkt_data(func
);
856 if (reload_skb_data
) {
857 EMIT1(0x57); /* push %rdi */
858 jmp_offset
+= 22; /* pop, mov, sub, mov */
860 EMIT2(0x41, 0x52); /* push %r10 */
861 EMIT2(0x41, 0x51); /* push %r9 */
862 /* need to adjust jmp offset, since
863 * pop %r9, pop %r10 take 4 bytes after call insn
868 if (!imm32
|| !is_simm32(jmp_offset
)) {
869 pr_err("unsupported bpf func %d addr %p image %p\n",
873 EMIT1_off32(0xE8, jmp_offset
);
875 if (reload_skb_data
) {
876 EMIT1(0x5F); /* pop %rdi */
877 emit_load_skb_data_hlen(&prog
);
879 EMIT2(0x41, 0x59); /* pop %r9 */
880 EMIT2(0x41, 0x5A); /* pop %r10 */
885 case BPF_JMP
| BPF_TAIL_CALL
:
886 emit_bpf_tail_call(&prog
);
890 case BPF_JMP
| BPF_JEQ
| BPF_X
:
891 case BPF_JMP
| BPF_JNE
| BPF_X
:
892 case BPF_JMP
| BPF_JGT
| BPF_X
:
893 case BPF_JMP
| BPF_JLT
| BPF_X
:
894 case BPF_JMP
| BPF_JGE
| BPF_X
:
895 case BPF_JMP
| BPF_JLE
| BPF_X
:
896 case BPF_JMP
| BPF_JSGT
| BPF_X
:
897 case BPF_JMP
| BPF_JSLT
| BPF_X
:
898 case BPF_JMP
| BPF_JSGE
| BPF_X
:
899 case BPF_JMP
| BPF_JSLE
| BPF_X
:
900 /* cmp dst_reg, src_reg */
901 EMIT3(add_2mod(0x48, dst_reg
, src_reg
), 0x39,
902 add_2reg(0xC0, dst_reg
, src_reg
));
905 case BPF_JMP
| BPF_JSET
| BPF_X
:
906 /* test dst_reg, src_reg */
907 EMIT3(add_2mod(0x48, dst_reg
, src_reg
), 0x85,
908 add_2reg(0xC0, dst_reg
, src_reg
));
911 case BPF_JMP
| BPF_JSET
| BPF_K
:
912 /* test dst_reg, imm32 */
913 EMIT1(add_1mod(0x48, dst_reg
));
914 EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg
), imm32
);
917 case BPF_JMP
| BPF_JEQ
| BPF_K
:
918 case BPF_JMP
| BPF_JNE
| BPF_K
:
919 case BPF_JMP
| BPF_JGT
| BPF_K
:
920 case BPF_JMP
| BPF_JLT
| BPF_K
:
921 case BPF_JMP
| BPF_JGE
| BPF_K
:
922 case BPF_JMP
| BPF_JLE
| BPF_K
:
923 case BPF_JMP
| BPF_JSGT
| BPF_K
:
924 case BPF_JMP
| BPF_JSLT
| BPF_K
:
925 case BPF_JMP
| BPF_JSGE
| BPF_K
:
926 case BPF_JMP
| BPF_JSLE
| BPF_K
:
927 /* cmp dst_reg, imm8/32 */
928 EMIT1(add_1mod(0x48, dst_reg
));
931 EMIT3(0x83, add_1reg(0xF8, dst_reg
), imm32
);
933 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg
), imm32
);
935 emit_cond_jmp
: /* convert BPF opcode to x86 */
936 switch (BPF_OP(insn
->code
)) {
945 /* GT is unsigned '>', JA in x86 */
949 /* LT is unsigned '<', JB in x86 */
953 /* GE is unsigned '>=', JAE in x86 */
957 /* LE is unsigned '<=', JBE in x86 */
961 /* signed '>', GT in x86 */
965 /* signed '<', LT in x86 */
969 /* signed '>=', GE in x86 */
973 /* signed '<=', LE in x86 */
976 default: /* to silence gcc warning */
979 jmp_offset
= addrs
[i
+ insn
->off
] - addrs
[i
];
980 if (is_imm8(jmp_offset
)) {
981 EMIT2(jmp_cond
, jmp_offset
);
982 } else if (is_simm32(jmp_offset
)) {
983 EMIT2_off32(0x0F, jmp_cond
+ 0x10, jmp_offset
);
985 pr_err("cond_jmp gen bug %llx\n", jmp_offset
);
991 case BPF_JMP
| BPF_JA
:
992 jmp_offset
= addrs
[i
+ insn
->off
] - addrs
[i
];
994 /* optimize out nop jumps */
997 if (is_imm8(jmp_offset
)) {
998 EMIT2(0xEB, jmp_offset
);
999 } else if (is_simm32(jmp_offset
)) {
1000 EMIT1_off32(0xE9, jmp_offset
);
1002 pr_err("jmp gen bug %llx\n", jmp_offset
);
1007 case BPF_LD
| BPF_IND
| BPF_W
:
1008 func
= sk_load_word
;
1010 case BPF_LD
| BPF_ABS
| BPF_W
:
1011 func
= CHOOSE_LOAD_FUNC(imm32
, sk_load_word
);
1013 ctx
->seen_ld_abs
= seen_ld_abs
= true;
1014 jmp_offset
= func
- (image
+ addrs
[i
]);
1015 if (!func
|| !is_simm32(jmp_offset
)) {
1016 pr_err("unsupported bpf func %d addr %p image %p\n",
1017 imm32
, func
, image
);
1020 if (BPF_MODE(insn
->code
) == BPF_ABS
) {
1021 /* mov %esi, imm32 */
1022 EMIT1_off32(0xBE, imm32
);
1024 /* mov %rsi, src_reg */
1025 EMIT_mov(BPF_REG_2
, src_reg
);
1028 /* add %esi, imm8 */
1029 EMIT3(0x83, 0xC6, imm32
);
1031 /* add %esi, imm32 */
1032 EMIT2_off32(0x81, 0xC6, imm32
);
1035 /* skb pointer is in R6 (%rbx), it will be copied into
1036 * %rdi if skb_copy_bits() call is necessary.
1037 * sk_load_* helpers also use %r10 and %r9d.
1041 /* r10 = skb->data, mov %r10, off32(%rbx) */
1042 EMIT3_off32(0x4c, 0x8b, 0x93,
1043 offsetof(struct sk_buff
, data
));
1044 EMIT1_off32(0xE8, jmp_offset
); /* call */
1047 case BPF_LD
| BPF_IND
| BPF_H
:
1048 func
= sk_load_half
;
1050 case BPF_LD
| BPF_ABS
| BPF_H
:
1051 func
= CHOOSE_LOAD_FUNC(imm32
, sk_load_half
);
1053 case BPF_LD
| BPF_IND
| BPF_B
:
1054 func
= sk_load_byte
;
1056 case BPF_LD
| BPF_ABS
| BPF_B
:
1057 func
= CHOOSE_LOAD_FUNC(imm32
, sk_load_byte
);
1060 case BPF_JMP
| BPF_EXIT
:
1062 jmp_offset
= ctx
->cleanup_addr
- addrs
[i
];
1066 /* update cleanup_addr */
1067 ctx
->cleanup_addr
= proglen
;
1068 /* mov rbx, qword ptr [rbp+0] */
1069 EMIT4(0x48, 0x8B, 0x5D, 0);
1070 /* mov r13, qword ptr [rbp+8] */
1071 EMIT4(0x4C, 0x8B, 0x6D, 8);
1072 /* mov r14, qword ptr [rbp+16] */
1073 EMIT4(0x4C, 0x8B, 0x75, 16);
1074 /* mov r15, qword ptr [rbp+24] */
1075 EMIT4(0x4C, 0x8B, 0x7D, 24);
1077 /* add rbp, AUX_STACK_SPACE */
1078 EMIT4(0x48, 0x83, 0xC5, AUX_STACK_SPACE
);
1079 EMIT1(0xC9); /* leave */
1080 EMIT1(0xC3); /* ret */
1084 /* By design x64 JIT should support all BPF instructions
1085 * This error will be seen if new instruction was added
1086 * to interpreter, but not to JIT
1087 * or if there is junk in bpf_prog
1089 pr_err("bpf_jit: unknown opcode %02x\n", insn
->code
);
1094 if (ilen
> BPF_MAX_INSN_SIZE
) {
1095 pr_err("bpf_jit: fatal insn size error\n");
1100 if (unlikely(proglen
+ ilen
> oldproglen
)) {
1101 pr_err("bpf_jit: fatal error\n");
1104 memcpy(image
+ proglen
, temp
, ilen
);
1113 struct bpf_prog
*bpf_int_jit_compile(struct bpf_prog
*prog
)
1115 struct bpf_binary_header
*header
= NULL
;
1116 struct bpf_prog
*tmp
, *orig_prog
= prog
;
1117 int proglen
, oldproglen
= 0;
1118 struct jit_context ctx
= {};
1119 bool tmp_blinded
= false;
1125 if (!bpf_jit_enable
)
1128 tmp
= bpf_jit_blind_constants(prog
);
1129 /* If blinding was requested and we failed during blinding,
1130 * we must fall back to the interpreter.
1139 addrs
= kmalloc(prog
->len
* sizeof(*addrs
), GFP_KERNEL
);
1145 /* Before first pass, make a rough estimation of addrs[]
1146 * each bpf instruction is translated to less than 64 bytes
1148 for (proglen
= 0, i
= 0; i
< prog
->len
; i
++) {
1152 ctx
.cleanup_addr
= proglen
;
1154 /* JITed image shrinks with every pass and the loop iterates
1155 * until the image stops shrinking. Very large bpf programs
1156 * may converge on the last pass. In such case do one more
1157 * pass to emit the final image
1159 for (pass
= 0; pass
< 20 || image
; pass
++) {
1160 proglen
= do_jit(prog
, addrs
, image
, oldproglen
, &ctx
);
1165 bpf_jit_binary_free(header
);
1170 if (proglen
!= oldproglen
) {
1171 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
1172 proglen
, oldproglen
);
1177 if (proglen
== oldproglen
) {
1178 header
= bpf_jit_binary_alloc(proglen
, &image
,
1185 oldproglen
= proglen
;
1189 if (bpf_jit_enable
> 1)
1190 bpf_jit_dump(prog
->len
, proglen
, pass
+ 1, image
);
1193 bpf_flush_icache(header
, image
+ proglen
);
1194 bpf_jit_binary_lock_ro(header
);
1195 prog
->bpf_func
= (void *)image
;
1197 prog
->jited_len
= proglen
;
1206 bpf_jit_prog_release_other(prog
, prog
== orig_prog
?