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defconfig: exynos9610: Re-add dropped Wi-Fi AP options lost
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "pmu.h"
31 #include "hyperv.h"
32
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
36 #include <linux/fs.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/mem_encrypt.h>
58
59 #include <trace/events/kvm.h>
60
61 #include <asm/debugreg.h>
62 #include <asm/msr.h>
63 #include <asm/desc.h>
64 #include <asm/mce.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70
71 #define CREATE_TRACE_POINTS
72 #include "trace.h"
73
74 #define MAX_IO_MSRS 256
75 #define KVM_MAX_MCE_BANKS 32
76 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
78
79 #define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
82 /* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86 #ifdef CONFIG_X86_64
87 static
88 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
89 #else
90 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
91 #endif
92
93 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
95
96 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
98
99 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
100 static void process_nmi(struct kvm_vcpu *vcpu);
101 static void enter_smm(struct kvm_vcpu *vcpu);
102 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
103
104 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
105 EXPORT_SYMBOL_GPL(kvm_x86_ops);
106
107 static bool __read_mostly ignore_msrs = 0;
108 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
109
110 unsigned int min_timer_period_us = 500;
111 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
112
113 static bool __read_mostly kvmclock_periodic_sync = true;
114 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
115
116 bool __read_mostly kvm_has_tsc_control;
117 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
118 u32 __read_mostly kvm_max_guest_tsc_khz;
119 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
120 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
121 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
122 u64 __read_mostly kvm_max_tsc_scaling_ratio;
123 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
124 u64 __read_mostly kvm_default_tsc_scaling_ratio;
125 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
126
127 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
128 static u32 __read_mostly tsc_tolerance_ppm = 250;
129 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
130
131 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
132 unsigned int __read_mostly lapic_timer_advance_ns = 0;
133 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
134
135 static bool __read_mostly vector_hashing = true;
136 module_param(vector_hashing, bool, S_IRUGO);
137
138 #define KVM_NR_SHARED_MSRS 16
139
140 struct kvm_shared_msrs_global {
141 int nr;
142 u32 msrs[KVM_NR_SHARED_MSRS];
143 };
144
145 struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
152 };
153
154 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
155 static struct kvm_shared_msrs __percpu *shared_msrs;
156
157 struct kvm_stats_debugfs_item debugfs_entries[] = {
158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
168 { "halt_exits", VCPU_STAT(halt_exits) },
169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
173 { "hypercalls", VCPU_STAT(hypercalls) },
174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
181 { "irq_injections", VCPU_STAT(irq_injections) },
182 { "nmi_injections", VCPU_STAT(nmi_injections) },
183 { "req_event", VCPU_STAT(req_event) },
184 { "l1d_flush", VCPU_STAT(l1d_flush) },
185 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
186 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
187 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
188 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
189 { "mmu_flooded", VM_STAT(mmu_flooded) },
190 { "mmu_recycled", VM_STAT(mmu_recycled) },
191 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
192 { "mmu_unsync", VM_STAT(mmu_unsync) },
193 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
194 { "largepages", VM_STAT(lpages) },
195 { "max_mmu_page_hash_collisions",
196 VM_STAT(max_mmu_page_hash_collisions) },
197 { NULL }
198 };
199
200 u64 __read_mostly host_xcr0;
201
202 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
203
204 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
205 {
206 int i;
207 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
208 vcpu->arch.apf.gfns[i] = ~0;
209 }
210
211 static void kvm_on_user_return(struct user_return_notifier *urn)
212 {
213 unsigned slot;
214 struct kvm_shared_msrs *locals
215 = container_of(urn, struct kvm_shared_msrs, urn);
216 struct kvm_shared_msr_values *values;
217 unsigned long flags;
218
219 /*
220 * Disabling irqs at this point since the following code could be
221 * interrupted and executed through kvm_arch_hardware_disable()
222 */
223 local_irq_save(flags);
224 if (locals->registered) {
225 locals->registered = false;
226 user_return_notifier_unregister(urn);
227 }
228 local_irq_restore(flags);
229 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
230 values = &locals->values[slot];
231 if (values->host != values->curr) {
232 wrmsrl(shared_msrs_global.msrs[slot], values->host);
233 values->curr = values->host;
234 }
235 }
236 }
237
238 static void shared_msr_update(unsigned slot, u32 msr)
239 {
240 u64 value;
241 unsigned int cpu = smp_processor_id();
242 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
243
244 /* only read, and nobody should modify it at this time,
245 * so don't need lock */
246 if (slot >= shared_msrs_global.nr) {
247 printk(KERN_ERR "kvm: invalid MSR slot!");
248 return;
249 }
250 rdmsrl_safe(msr, &value);
251 smsr->values[slot].host = value;
252 smsr->values[slot].curr = value;
253 }
254
255 void kvm_define_shared_msr(unsigned slot, u32 msr)
256 {
257 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
258 shared_msrs_global.msrs[slot] = msr;
259 if (slot >= shared_msrs_global.nr)
260 shared_msrs_global.nr = slot + 1;
261 }
262 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
263
264 static void kvm_shared_msr_cpu_online(void)
265 {
266 unsigned i;
267
268 for (i = 0; i < shared_msrs_global.nr; ++i)
269 shared_msr_update(i, shared_msrs_global.msrs[i]);
270 }
271
272 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
273 {
274 unsigned int cpu = smp_processor_id();
275 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
276 int err;
277
278 if (((value ^ smsr->values[slot].curr) & mask) == 0)
279 return 0;
280 smsr->values[slot].curr = value;
281 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
282 if (err)
283 return 1;
284
285 if (!smsr->registered) {
286 smsr->urn.on_user_return = kvm_on_user_return;
287 user_return_notifier_register(&smsr->urn);
288 smsr->registered = true;
289 }
290 return 0;
291 }
292 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
293
294 static void drop_user_return_notifiers(void)
295 {
296 unsigned int cpu = smp_processor_id();
297 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
298
299 if (smsr->registered)
300 kvm_on_user_return(&smsr->urn);
301 }
302
303 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
304 {
305 return vcpu->arch.apic_base;
306 }
307 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
308
309 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
310 {
311 u64 old_state = vcpu->arch.apic_base &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 new_state = msr_info->data &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
316 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
317
318 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
319 return 1;
320 if (!msr_info->host_initiated &&
321 ((new_state == MSR_IA32_APICBASE_ENABLE &&
322 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
323 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
324 old_state == 0)))
325 return 1;
326
327 kvm_lapic_set_base(vcpu, msr_info->data);
328 return 0;
329 }
330 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
331
332 asmlinkage __visible void kvm_spurious_fault(void)
333 {
334 /* Fault while not rebooting. We want the trace. */
335 BUG();
336 }
337 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
338
339 #define EXCPT_BENIGN 0
340 #define EXCPT_CONTRIBUTORY 1
341 #define EXCPT_PF 2
342
343 static int exception_class(int vector)
344 {
345 switch (vector) {
346 case PF_VECTOR:
347 return EXCPT_PF;
348 case DE_VECTOR:
349 case TS_VECTOR:
350 case NP_VECTOR:
351 case SS_VECTOR:
352 case GP_VECTOR:
353 return EXCPT_CONTRIBUTORY;
354 default:
355 break;
356 }
357 return EXCPT_BENIGN;
358 }
359
360 #define EXCPT_FAULT 0
361 #define EXCPT_TRAP 1
362 #define EXCPT_ABORT 2
363 #define EXCPT_INTERRUPT 3
364
365 static int exception_type(int vector)
366 {
367 unsigned int mask;
368
369 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
370 return EXCPT_INTERRUPT;
371
372 mask = 1 << vector;
373
374 /* #DB is trap, as instruction watchpoints are handled elsewhere */
375 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
376 return EXCPT_TRAP;
377
378 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
379 return EXCPT_ABORT;
380
381 /* Reserved exceptions will result in fault */
382 return EXCPT_FAULT;
383 }
384
385 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
386 unsigned nr, bool has_error, u32 error_code,
387 bool reinject)
388 {
389 u32 prev_nr;
390 int class1, class2;
391
392 kvm_make_request(KVM_REQ_EVENT, vcpu);
393
394 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
395 queue:
396 if (has_error && !is_protmode(vcpu))
397 has_error = false;
398 if (reinject) {
399 /*
400 * On vmentry, vcpu->arch.exception.pending is only
401 * true if an event injection was blocked by
402 * nested_run_pending. In that case, however,
403 * vcpu_enter_guest requests an immediate exit,
404 * and the guest shouldn't proceed far enough to
405 * need reinjection.
406 */
407 WARN_ON_ONCE(vcpu->arch.exception.pending);
408 vcpu->arch.exception.injected = true;
409 } else {
410 vcpu->arch.exception.pending = true;
411 vcpu->arch.exception.injected = false;
412 }
413 vcpu->arch.exception.has_error_code = has_error;
414 vcpu->arch.exception.nr = nr;
415 vcpu->arch.exception.error_code = error_code;
416 return;
417 }
418
419 /* to check exception */
420 prev_nr = vcpu->arch.exception.nr;
421 if (prev_nr == DF_VECTOR) {
422 /* triple fault -> shutdown */
423 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
424 return;
425 }
426 class1 = exception_class(prev_nr);
427 class2 = exception_class(nr);
428 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
429 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
430 /*
431 * Generate double fault per SDM Table 5-5. Set
432 * exception.pending = true so that the double fault
433 * can trigger a nested vmexit.
434 */
435 vcpu->arch.exception.pending = true;
436 vcpu->arch.exception.injected = false;
437 vcpu->arch.exception.has_error_code = true;
438 vcpu->arch.exception.nr = DF_VECTOR;
439 vcpu->arch.exception.error_code = 0;
440 } else
441 /* replace previous exception with a new one in a hope
442 that instruction re-execution will regenerate lost
443 exception */
444 goto queue;
445 }
446
447 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
448 {
449 kvm_multiple_exception(vcpu, nr, false, 0, false);
450 }
451 EXPORT_SYMBOL_GPL(kvm_queue_exception);
452
453 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
454 {
455 kvm_multiple_exception(vcpu, nr, false, 0, true);
456 }
457 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
458
459 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
460 {
461 if (err)
462 kvm_inject_gp(vcpu, 0);
463 else
464 return kvm_skip_emulated_instruction(vcpu);
465
466 return 1;
467 }
468 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
469
470 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
471 {
472 ++vcpu->stat.pf_guest;
473 vcpu->arch.exception.nested_apf =
474 is_guest_mode(vcpu) && fault->async_page_fault;
475 if (vcpu->arch.exception.nested_apf)
476 vcpu->arch.apf.nested_apf_token = fault->address;
477 else
478 vcpu->arch.cr2 = fault->address;
479 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
480 }
481 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
482
483 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
484 {
485 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
486 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
487 else
488 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
489
490 return fault->nested_page_fault;
491 }
492
493 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
494 {
495 atomic_inc(&vcpu->arch.nmi_queued);
496 kvm_make_request(KVM_REQ_NMI, vcpu);
497 }
498 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
499
500 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
501 {
502 kvm_multiple_exception(vcpu, nr, true, error_code, false);
503 }
504 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
505
506 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
507 {
508 kvm_multiple_exception(vcpu, nr, true, error_code, true);
509 }
510 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
511
512 /*
513 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
514 * a #GP and return false.
515 */
516 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
517 {
518 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
519 return true;
520 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
521 return false;
522 }
523 EXPORT_SYMBOL_GPL(kvm_require_cpl);
524
525 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
526 {
527 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
528 return true;
529
530 kvm_queue_exception(vcpu, UD_VECTOR);
531 return false;
532 }
533 EXPORT_SYMBOL_GPL(kvm_require_dr);
534
535 /*
536 * This function will be used to read from the physical memory of the currently
537 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
538 * can read from guest physical or from the guest's guest physical memory.
539 */
540 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
541 gfn_t ngfn, void *data, int offset, int len,
542 u32 access)
543 {
544 struct x86_exception exception;
545 gfn_t real_gfn;
546 gpa_t ngpa;
547
548 ngpa = gfn_to_gpa(ngfn);
549 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
550 if (real_gfn == UNMAPPED_GVA)
551 return -EFAULT;
552
553 real_gfn = gpa_to_gfn(real_gfn);
554
555 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
556 }
557 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
558
559 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
560 void *data, int offset, int len, u32 access)
561 {
562 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
563 data, offset, len, access);
564 }
565
566 /*
567 * Load the pae pdptrs. Return true is they are all valid.
568 */
569 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
570 {
571 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
572 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
573 int i;
574 int ret;
575 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
576
577 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
578 offset * sizeof(u64), sizeof(pdpte),
579 PFERR_USER_MASK|PFERR_WRITE_MASK);
580 if (ret < 0) {
581 ret = 0;
582 goto out;
583 }
584 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
585 if ((pdpte[i] & PT_PRESENT_MASK) &&
586 (pdpte[i] &
587 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
588 ret = 0;
589 goto out;
590 }
591 }
592 ret = 1;
593
594 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
595 __set_bit(VCPU_EXREG_PDPTR,
596 (unsigned long *)&vcpu->arch.regs_avail);
597 __set_bit(VCPU_EXREG_PDPTR,
598 (unsigned long *)&vcpu->arch.regs_dirty);
599 out:
600
601 return ret;
602 }
603 EXPORT_SYMBOL_GPL(load_pdptrs);
604
605 bool pdptrs_changed(struct kvm_vcpu *vcpu)
606 {
607 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
608 bool changed = true;
609 int offset;
610 gfn_t gfn;
611 int r;
612
613 if (is_long_mode(vcpu) || !is_pae(vcpu))
614 return false;
615
616 if (!test_bit(VCPU_EXREG_PDPTR,
617 (unsigned long *)&vcpu->arch.regs_avail))
618 return true;
619
620 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
621 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
622 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
623 PFERR_USER_MASK | PFERR_WRITE_MASK);
624 if (r < 0)
625 goto out;
626 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
627 out:
628
629 return changed;
630 }
631 EXPORT_SYMBOL_GPL(pdptrs_changed);
632
633 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
634 {
635 unsigned long old_cr0 = kvm_read_cr0(vcpu);
636 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
637
638 cr0 |= X86_CR0_ET;
639
640 #ifdef CONFIG_X86_64
641 if (cr0 & 0xffffffff00000000UL)
642 return 1;
643 #endif
644
645 cr0 &= ~CR0_RESERVED_BITS;
646
647 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
648 return 1;
649
650 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
651 return 1;
652
653 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
654 #ifdef CONFIG_X86_64
655 if ((vcpu->arch.efer & EFER_LME)) {
656 int cs_db, cs_l;
657
658 if (!is_pae(vcpu))
659 return 1;
660 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
661 if (cs_l)
662 return 1;
663 } else
664 #endif
665 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
666 kvm_read_cr3(vcpu)))
667 return 1;
668 }
669
670 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
671 return 1;
672
673 kvm_x86_ops->set_cr0(vcpu, cr0);
674
675 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
676 kvm_clear_async_pf_completion_queue(vcpu);
677 kvm_async_pf_hash_reset(vcpu);
678 }
679
680 if ((cr0 ^ old_cr0) & update_bits)
681 kvm_mmu_reset_context(vcpu);
682
683 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
684 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
685 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
686 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
687
688 return 0;
689 }
690 EXPORT_SYMBOL_GPL(kvm_set_cr0);
691
692 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
693 {
694 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
695 }
696 EXPORT_SYMBOL_GPL(kvm_lmsw);
697
698 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
699 {
700 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
701 !vcpu->guest_xcr0_loaded) {
702 /* kvm_set_xcr() also depends on this */
703 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
704 vcpu->guest_xcr0_loaded = 1;
705 }
706 }
707
708 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
709 {
710 if (vcpu->guest_xcr0_loaded) {
711 if (vcpu->arch.xcr0 != host_xcr0)
712 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
713 vcpu->guest_xcr0_loaded = 0;
714 }
715 }
716
717 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
718 {
719 u64 xcr0 = xcr;
720 u64 old_xcr0 = vcpu->arch.xcr0;
721 u64 valid_bits;
722
723 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
724 if (index != XCR_XFEATURE_ENABLED_MASK)
725 return 1;
726 if (!(xcr0 & XFEATURE_MASK_FP))
727 return 1;
728 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
729 return 1;
730
731 /*
732 * Do not allow the guest to set bits that we do not support
733 * saving. However, xcr0 bit 0 is always set, even if the
734 * emulated CPU does not support XSAVE (see fx_init).
735 */
736 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
737 if (xcr0 & ~valid_bits)
738 return 1;
739
740 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
741 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
742 return 1;
743
744 if (xcr0 & XFEATURE_MASK_AVX512) {
745 if (!(xcr0 & XFEATURE_MASK_YMM))
746 return 1;
747 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
748 return 1;
749 }
750 vcpu->arch.xcr0 = xcr0;
751
752 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
753 kvm_update_cpuid(vcpu);
754 return 0;
755 }
756
757 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
758 {
759 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
760 __kvm_set_xcr(vcpu, index, xcr)) {
761 kvm_inject_gp(vcpu, 0);
762 return 1;
763 }
764 return 0;
765 }
766 EXPORT_SYMBOL_GPL(kvm_set_xcr);
767
768 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
769 {
770 unsigned long old_cr4 = kvm_read_cr4(vcpu);
771 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
772 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
773
774 if (cr4 & CR4_RESERVED_BITS)
775 return 1;
776
777 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
778 return 1;
779
780 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
781 return 1;
782
783 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
784 return 1;
785
786 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
787 return 1;
788
789 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
790 return 1;
791
792 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
793 return 1;
794
795 if (is_long_mode(vcpu)) {
796 if (!(cr4 & X86_CR4_PAE))
797 return 1;
798 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
799 && ((cr4 ^ old_cr4) & pdptr_bits)
800 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
801 kvm_read_cr3(vcpu)))
802 return 1;
803
804 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
805 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
806 return 1;
807
808 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
809 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
810 return 1;
811 }
812
813 if (kvm_x86_ops->set_cr4(vcpu, cr4))
814 return 1;
815
816 if (((cr4 ^ old_cr4) & pdptr_bits) ||
817 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
818 kvm_mmu_reset_context(vcpu);
819
820 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
821 kvm_update_cpuid(vcpu);
822
823 return 0;
824 }
825 EXPORT_SYMBOL_GPL(kvm_set_cr4);
826
827 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
828 {
829 #ifdef CONFIG_X86_64
830 cr3 &= ~CR3_PCID_INVD;
831 #endif
832
833 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
834 kvm_mmu_sync_roots(vcpu);
835 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
836 return 0;
837 }
838
839 if (is_long_mode(vcpu) &&
840 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
841 return 1;
842 else if (is_pae(vcpu) && is_paging(vcpu) &&
843 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
844 return 1;
845
846 vcpu->arch.cr3 = cr3;
847 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
848 kvm_mmu_new_cr3(vcpu);
849 return 0;
850 }
851 EXPORT_SYMBOL_GPL(kvm_set_cr3);
852
853 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
854 {
855 if (cr8 & CR8_RESERVED_BITS)
856 return 1;
857 if (lapic_in_kernel(vcpu))
858 kvm_lapic_set_tpr(vcpu, cr8);
859 else
860 vcpu->arch.cr8 = cr8;
861 return 0;
862 }
863 EXPORT_SYMBOL_GPL(kvm_set_cr8);
864
865 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
866 {
867 if (lapic_in_kernel(vcpu))
868 return kvm_lapic_get_cr8(vcpu);
869 else
870 return vcpu->arch.cr8;
871 }
872 EXPORT_SYMBOL_GPL(kvm_get_cr8);
873
874 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
875 {
876 int i;
877
878 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
879 for (i = 0; i < KVM_NR_DB_REGS; i++)
880 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
881 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
882 }
883 }
884
885 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
886 {
887 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
888 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
889 }
890
891 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
892 {
893 unsigned long dr7;
894
895 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
896 dr7 = vcpu->arch.guest_debug_dr7;
897 else
898 dr7 = vcpu->arch.dr7;
899 kvm_x86_ops->set_dr7(vcpu, dr7);
900 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
901 if (dr7 & DR7_BP_EN_MASK)
902 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
903 }
904
905 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
906 {
907 u64 fixed = DR6_FIXED_1;
908
909 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
910 fixed |= DR6_RTM;
911 return fixed;
912 }
913
914 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
915 {
916 switch (dr) {
917 case 0 ... 3:
918 vcpu->arch.db[dr] = val;
919 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
920 vcpu->arch.eff_db[dr] = val;
921 break;
922 case 4:
923 /* fall through */
924 case 6:
925 if (val & 0xffffffff00000000ULL)
926 return -1; /* #GP */
927 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
928 kvm_update_dr6(vcpu);
929 break;
930 case 5:
931 /* fall through */
932 default: /* 7 */
933 if (val & 0xffffffff00000000ULL)
934 return -1; /* #GP */
935 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
936 kvm_update_dr7(vcpu);
937 break;
938 }
939
940 return 0;
941 }
942
943 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
944 {
945 if (__kvm_set_dr(vcpu, dr, val)) {
946 kvm_inject_gp(vcpu, 0);
947 return 1;
948 }
949 return 0;
950 }
951 EXPORT_SYMBOL_GPL(kvm_set_dr);
952
953 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
954 {
955 switch (dr) {
956 case 0 ... 3:
957 *val = vcpu->arch.db[dr];
958 break;
959 case 4:
960 /* fall through */
961 case 6:
962 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
963 *val = vcpu->arch.dr6;
964 else
965 *val = kvm_x86_ops->get_dr6(vcpu);
966 break;
967 case 5:
968 /* fall through */
969 default: /* 7 */
970 *val = vcpu->arch.dr7;
971 break;
972 }
973 return 0;
974 }
975 EXPORT_SYMBOL_GPL(kvm_get_dr);
976
977 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
978 {
979 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
980 u64 data;
981 int err;
982
983 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
984 if (err)
985 return err;
986 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
987 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
988 return err;
989 }
990 EXPORT_SYMBOL_GPL(kvm_rdpmc);
991
992 /*
993 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
994 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
995 *
996 * This list is modified at module load time to reflect the
997 * capabilities of the host cpu. This capabilities test skips MSRs that are
998 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
999 * may depend on host virtualization features rather than host cpu features.
1000 */
1001
1002 static u32 msrs_to_save[] = {
1003 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1004 MSR_STAR,
1005 #ifdef CONFIG_X86_64
1006 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1007 #endif
1008 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1009 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1010 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
1011 };
1012
1013 static unsigned num_msrs_to_save;
1014
1015 static u32 emulated_msrs[] = {
1016 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1017 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1018 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1019 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1020 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1021 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1022 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1023 HV_X64_MSR_RESET,
1024 HV_X64_MSR_VP_INDEX,
1025 HV_X64_MSR_VP_RUNTIME,
1026 HV_X64_MSR_SCONTROL,
1027 HV_X64_MSR_STIMER0_CONFIG,
1028 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1029 MSR_KVM_PV_EOI_EN,
1030
1031 MSR_IA32_TSC_ADJUST,
1032 MSR_IA32_TSCDEADLINE,
1033 MSR_IA32_MISC_ENABLE,
1034 MSR_IA32_MCG_STATUS,
1035 MSR_IA32_MCG_CTL,
1036 MSR_IA32_MCG_EXT_CTL,
1037 MSR_IA32_SMBASE,
1038 MSR_PLATFORM_INFO,
1039 MSR_MISC_FEATURES_ENABLES,
1040 MSR_AMD64_VIRT_SPEC_CTRL,
1041 };
1042
1043 static unsigned num_emulated_msrs;
1044
1045 /*
1046 * List of msr numbers which are used to expose MSR-based features that
1047 * can be used by a hypervisor to validate requested CPU features.
1048 */
1049 static u32 msr_based_features[] = {
1050 MSR_F10H_DECFG,
1051 MSR_IA32_UCODE_REV,
1052 MSR_IA32_ARCH_CAPABILITIES,
1053 };
1054
1055 static unsigned int num_msr_based_features;
1056
1057 u64 kvm_get_arch_capabilities(void)
1058 {
1059 u64 data;
1060
1061 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1062
1063 /*
1064 * If we're doing cache flushes (either "always" or "cond")
1065 * we will do one whenever the guest does a vmlaunch/vmresume.
1066 * If an outer hypervisor is doing the cache flush for us
1067 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1068 * capability to the guest too, and if EPT is disabled we're not
1069 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1070 * require a nested hypervisor to do a flush of its own.
1071 */
1072 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1073 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1074
1075 return data;
1076 }
1077 EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1078
1079 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1080 {
1081 switch (msr->index) {
1082 case MSR_IA32_ARCH_CAPABILITIES:
1083 msr->data = kvm_get_arch_capabilities();
1084 break;
1085 case MSR_IA32_UCODE_REV:
1086 rdmsrl_safe(msr->index, &msr->data);
1087 break;
1088 default:
1089 if (kvm_x86_ops->get_msr_feature(msr))
1090 return 1;
1091 }
1092 return 0;
1093 }
1094
1095 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1096 {
1097 struct kvm_msr_entry msr;
1098 int r;
1099
1100 msr.index = index;
1101 r = kvm_get_msr_feature(&msr);
1102 if (r)
1103 return r;
1104
1105 *data = msr.data;
1106
1107 return 0;
1108 }
1109
1110 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1111 {
1112 if (efer & efer_reserved_bits)
1113 return false;
1114
1115 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1116 return false;
1117
1118 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1119 return false;
1120
1121 return true;
1122 }
1123 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1124
1125 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1126 {
1127 u64 old_efer = vcpu->arch.efer;
1128
1129 if (!kvm_valid_efer(vcpu, efer))
1130 return 1;
1131
1132 if (is_paging(vcpu)
1133 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1134 return 1;
1135
1136 efer &= ~EFER_LMA;
1137 efer |= vcpu->arch.efer & EFER_LMA;
1138
1139 kvm_x86_ops->set_efer(vcpu, efer);
1140
1141 /* Update reserved bits */
1142 if ((efer ^ old_efer) & EFER_NX)
1143 kvm_mmu_reset_context(vcpu);
1144
1145 return 0;
1146 }
1147
1148 void kvm_enable_efer_bits(u64 mask)
1149 {
1150 efer_reserved_bits &= ~mask;
1151 }
1152 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1153
1154 /*
1155 * Writes msr value into into the appropriate "register".
1156 * Returns 0 on success, non-0 otherwise.
1157 * Assumes vcpu_load() was already called.
1158 */
1159 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1160 {
1161 switch (msr->index) {
1162 case MSR_FS_BASE:
1163 case MSR_GS_BASE:
1164 case MSR_KERNEL_GS_BASE:
1165 case MSR_CSTAR:
1166 case MSR_LSTAR:
1167 if (is_noncanonical_address(msr->data, vcpu))
1168 return 1;
1169 break;
1170 case MSR_IA32_SYSENTER_EIP:
1171 case MSR_IA32_SYSENTER_ESP:
1172 /*
1173 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1174 * non-canonical address is written on Intel but not on
1175 * AMD (which ignores the top 32-bits, because it does
1176 * not implement 64-bit SYSENTER).
1177 *
1178 * 64-bit code should hence be able to write a non-canonical
1179 * value on AMD. Making the address canonical ensures that
1180 * vmentry does not fail on Intel after writing a non-canonical
1181 * value, and that something deterministic happens if the guest
1182 * invokes 64-bit SYSENTER.
1183 */
1184 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1185 }
1186 return kvm_x86_ops->set_msr(vcpu, msr);
1187 }
1188 EXPORT_SYMBOL_GPL(kvm_set_msr);
1189
1190 /*
1191 * Adapt set_msr() to msr_io()'s calling convention
1192 */
1193 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1194 {
1195 struct msr_data msr;
1196 int r;
1197
1198 msr.index = index;
1199 msr.host_initiated = true;
1200 r = kvm_get_msr(vcpu, &msr);
1201 if (r)
1202 return r;
1203
1204 *data = msr.data;
1205 return 0;
1206 }
1207
1208 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1209 {
1210 struct msr_data msr;
1211
1212 msr.data = *data;
1213 msr.index = index;
1214 msr.host_initiated = true;
1215 return kvm_set_msr(vcpu, &msr);
1216 }
1217
1218 #ifdef CONFIG_X86_64
1219 struct pvclock_gtod_data {
1220 seqcount_t seq;
1221
1222 struct { /* extract of a clocksource struct */
1223 int vclock_mode;
1224 u64 cycle_last;
1225 u64 mask;
1226 u32 mult;
1227 u32 shift;
1228 } clock;
1229
1230 u64 boot_ns;
1231 u64 nsec_base;
1232 u64 wall_time_sec;
1233 };
1234
1235 static struct pvclock_gtod_data pvclock_gtod_data;
1236
1237 static void update_pvclock_gtod(struct timekeeper *tk)
1238 {
1239 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1240 u64 boot_ns;
1241
1242 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1243
1244 write_seqcount_begin(&vdata->seq);
1245
1246 /* copy pvclock gtod data */
1247 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1248 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1249 vdata->clock.mask = tk->tkr_mono.mask;
1250 vdata->clock.mult = tk->tkr_mono.mult;
1251 vdata->clock.shift = tk->tkr_mono.shift;
1252
1253 vdata->boot_ns = boot_ns;
1254 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1255
1256 vdata->wall_time_sec = tk->xtime_sec;
1257
1258 write_seqcount_end(&vdata->seq);
1259 }
1260 #endif
1261
1262 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1263 {
1264 /*
1265 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1266 * vcpu_enter_guest. This function is only called from
1267 * the physical CPU that is running vcpu.
1268 */
1269 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1270 }
1271
1272 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1273 {
1274 int version;
1275 int r;
1276 struct pvclock_wall_clock wc;
1277 struct timespec64 boot;
1278
1279 if (!wall_clock)
1280 return;
1281
1282 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1283 if (r)
1284 return;
1285
1286 if (version & 1)
1287 ++version; /* first time write, random junk */
1288
1289 ++version;
1290
1291 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1292 return;
1293
1294 /*
1295 * The guest calculates current wall clock time by adding
1296 * system time (updated by kvm_guest_time_update below) to the
1297 * wall clock specified here. guest system time equals host
1298 * system time for us, thus we must fill in host boot time here.
1299 */
1300 getboottime64(&boot);
1301
1302 if (kvm->arch.kvmclock_offset) {
1303 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1304 boot = timespec64_sub(boot, ts);
1305 }
1306 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1307 wc.nsec = boot.tv_nsec;
1308 wc.version = version;
1309
1310 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1311
1312 version++;
1313 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1314 }
1315
1316 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1317 {
1318 do_shl32_div32(dividend, divisor);
1319 return dividend;
1320 }
1321
1322 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1323 s8 *pshift, u32 *pmultiplier)
1324 {
1325 uint64_t scaled64;
1326 int32_t shift = 0;
1327 uint64_t tps64;
1328 uint32_t tps32;
1329
1330 tps64 = base_hz;
1331 scaled64 = scaled_hz;
1332 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1333 tps64 >>= 1;
1334 shift--;
1335 }
1336
1337 tps32 = (uint32_t)tps64;
1338 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1339 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1340 scaled64 >>= 1;
1341 else
1342 tps32 <<= 1;
1343 shift++;
1344 }
1345
1346 *pshift = shift;
1347 *pmultiplier = div_frac(scaled64, tps32);
1348
1349 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1350 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1351 }
1352
1353 #ifdef CONFIG_X86_64
1354 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1355 #endif
1356
1357 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1358 static unsigned long max_tsc_khz;
1359
1360 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1361 {
1362 u64 v = (u64)khz * (1000000 + ppm);
1363 do_div(v, 1000000);
1364 return v;
1365 }
1366
1367 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1368 {
1369 u64 ratio;
1370
1371 /* Guest TSC same frequency as host TSC? */
1372 if (!scale) {
1373 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1374 return 0;
1375 }
1376
1377 /* TSC scaling supported? */
1378 if (!kvm_has_tsc_control) {
1379 if (user_tsc_khz > tsc_khz) {
1380 vcpu->arch.tsc_catchup = 1;
1381 vcpu->arch.tsc_always_catchup = 1;
1382 return 0;
1383 } else {
1384 WARN(1, "user requested TSC rate below hardware speed\n");
1385 return -1;
1386 }
1387 }
1388
1389 /* TSC scaling required - calculate ratio */
1390 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1391 user_tsc_khz, tsc_khz);
1392
1393 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1394 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1395 user_tsc_khz);
1396 return -1;
1397 }
1398
1399 vcpu->arch.tsc_scaling_ratio = ratio;
1400 return 0;
1401 }
1402
1403 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1404 {
1405 u32 thresh_lo, thresh_hi;
1406 int use_scaling = 0;
1407
1408 /* tsc_khz can be zero if TSC calibration fails */
1409 if (user_tsc_khz == 0) {
1410 /* set tsc_scaling_ratio to a safe value */
1411 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1412 return -1;
1413 }
1414
1415 /* Compute a scale to convert nanoseconds in TSC cycles */
1416 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1417 &vcpu->arch.virtual_tsc_shift,
1418 &vcpu->arch.virtual_tsc_mult);
1419 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1420
1421 /*
1422 * Compute the variation in TSC rate which is acceptable
1423 * within the range of tolerance and decide if the
1424 * rate being applied is within that bounds of the hardware
1425 * rate. If so, no scaling or compensation need be done.
1426 */
1427 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1428 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1429 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1430 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1431 use_scaling = 1;
1432 }
1433 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1434 }
1435
1436 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1437 {
1438 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1439 vcpu->arch.virtual_tsc_mult,
1440 vcpu->arch.virtual_tsc_shift);
1441 tsc += vcpu->arch.this_tsc_write;
1442 return tsc;
1443 }
1444
1445 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1446 {
1447 #ifdef CONFIG_X86_64
1448 bool vcpus_matched;
1449 struct kvm_arch *ka = &vcpu->kvm->arch;
1450 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1451
1452 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1453 atomic_read(&vcpu->kvm->online_vcpus));
1454
1455 /*
1456 * Once the masterclock is enabled, always perform request in
1457 * order to update it.
1458 *
1459 * In order to enable masterclock, the host clocksource must be TSC
1460 * and the vcpus need to have matched TSCs. When that happens,
1461 * perform request to enable masterclock.
1462 */
1463 if (ka->use_master_clock ||
1464 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1465 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1466
1467 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1468 atomic_read(&vcpu->kvm->online_vcpus),
1469 ka->use_master_clock, gtod->clock.vclock_mode);
1470 #endif
1471 }
1472
1473 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1474 {
1475 u64 curr_offset = vcpu->arch.tsc_offset;
1476 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1477 }
1478
1479 /*
1480 * Multiply tsc by a fixed point number represented by ratio.
1481 *
1482 * The most significant 64-N bits (mult) of ratio represent the
1483 * integral part of the fixed point number; the remaining N bits
1484 * (frac) represent the fractional part, ie. ratio represents a fixed
1485 * point number (mult + frac * 2^(-N)).
1486 *
1487 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1488 */
1489 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1490 {
1491 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1492 }
1493
1494 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1495 {
1496 u64 _tsc = tsc;
1497 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1498
1499 if (ratio != kvm_default_tsc_scaling_ratio)
1500 _tsc = __scale_tsc(ratio, tsc);
1501
1502 return _tsc;
1503 }
1504 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1505
1506 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1507 {
1508 u64 tsc;
1509
1510 tsc = kvm_scale_tsc(vcpu, rdtsc());
1511
1512 return target_tsc - tsc;
1513 }
1514
1515 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1516 {
1517 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1518 }
1519 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1520
1521 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1522 {
1523 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1524 vcpu->arch.tsc_offset = offset;
1525 }
1526
1527 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1528 {
1529 struct kvm *kvm = vcpu->kvm;
1530 u64 offset, ns, elapsed;
1531 unsigned long flags;
1532 bool matched;
1533 bool already_matched;
1534 u64 data = msr->data;
1535 bool synchronizing = false;
1536
1537 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1538 offset = kvm_compute_tsc_offset(vcpu, data);
1539 ns = ktime_get_boot_ns();
1540 elapsed = ns - kvm->arch.last_tsc_nsec;
1541
1542 if (vcpu->arch.virtual_tsc_khz) {
1543 if (data == 0 && msr->host_initiated) {
1544 /*
1545 * detection of vcpu initialization -- need to sync
1546 * with other vCPUs. This particularly helps to keep
1547 * kvm_clock stable after CPU hotplug
1548 */
1549 synchronizing = true;
1550 } else {
1551 u64 tsc_exp = kvm->arch.last_tsc_write +
1552 nsec_to_cycles(vcpu, elapsed);
1553 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1554 /*
1555 * Special case: TSC write with a small delta (1 second)
1556 * of virtual cycle time against real time is
1557 * interpreted as an attempt to synchronize the CPU.
1558 */
1559 synchronizing = data < tsc_exp + tsc_hz &&
1560 data + tsc_hz > tsc_exp;
1561 }
1562 }
1563
1564 /*
1565 * For a reliable TSC, we can match TSC offsets, and for an unstable
1566 * TSC, we add elapsed time in this computation. We could let the
1567 * compensation code attempt to catch up if we fall behind, but
1568 * it's better to try to match offsets from the beginning.
1569 */
1570 if (synchronizing &&
1571 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1572 if (!check_tsc_unstable()) {
1573 offset = kvm->arch.cur_tsc_offset;
1574 pr_debug("kvm: matched tsc offset for %llu\n", data);
1575 } else {
1576 u64 delta = nsec_to_cycles(vcpu, elapsed);
1577 data += delta;
1578 offset = kvm_compute_tsc_offset(vcpu, data);
1579 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1580 }
1581 matched = true;
1582 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1583 } else {
1584 /*
1585 * We split periods of matched TSC writes into generations.
1586 * For each generation, we track the original measured
1587 * nanosecond time, offset, and write, so if TSCs are in
1588 * sync, we can match exact offset, and if not, we can match
1589 * exact software computation in compute_guest_tsc()
1590 *
1591 * These values are tracked in kvm->arch.cur_xxx variables.
1592 */
1593 kvm->arch.cur_tsc_generation++;
1594 kvm->arch.cur_tsc_nsec = ns;
1595 kvm->arch.cur_tsc_write = data;
1596 kvm->arch.cur_tsc_offset = offset;
1597 matched = false;
1598 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1599 kvm->arch.cur_tsc_generation, data);
1600 }
1601
1602 /*
1603 * We also track th most recent recorded KHZ, write and time to
1604 * allow the matching interval to be extended at each write.
1605 */
1606 kvm->arch.last_tsc_nsec = ns;
1607 kvm->arch.last_tsc_write = data;
1608 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1609
1610 vcpu->arch.last_guest_tsc = data;
1611
1612 /* Keep track of which generation this VCPU has synchronized to */
1613 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1614 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1615 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1616
1617 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1618 update_ia32_tsc_adjust_msr(vcpu, offset);
1619
1620 kvm_vcpu_write_tsc_offset(vcpu, offset);
1621 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1622
1623 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1624 if (!matched) {
1625 kvm->arch.nr_vcpus_matched_tsc = 0;
1626 } else if (!already_matched) {
1627 kvm->arch.nr_vcpus_matched_tsc++;
1628 }
1629
1630 kvm_track_tsc_matching(vcpu);
1631 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1632 }
1633
1634 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1635
1636 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1637 s64 adjustment)
1638 {
1639 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1640 }
1641
1642 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1643 {
1644 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1645 WARN_ON(adjustment < 0);
1646 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1647 adjust_tsc_offset_guest(vcpu, adjustment);
1648 }
1649
1650 #ifdef CONFIG_X86_64
1651
1652 static u64 read_tsc(void)
1653 {
1654 u64 ret = (u64)rdtsc_ordered();
1655 u64 last = pvclock_gtod_data.clock.cycle_last;
1656
1657 if (likely(ret >= last))
1658 return ret;
1659
1660 /*
1661 * GCC likes to generate cmov here, but this branch is extremely
1662 * predictable (it's just a function of time and the likely is
1663 * very likely) and there's a data dependence, so force GCC
1664 * to generate a branch instead. I don't barrier() because
1665 * we don't actually need a barrier, and if this function
1666 * ever gets inlined it will generate worse code.
1667 */
1668 asm volatile ("");
1669 return last;
1670 }
1671
1672 static inline u64 vgettsc(u64 *cycle_now)
1673 {
1674 long v;
1675 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1676
1677 *cycle_now = read_tsc();
1678
1679 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1680 return v * gtod->clock.mult;
1681 }
1682
1683 static int do_monotonic_boot(s64 *t, u64 *cycle_now)
1684 {
1685 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1686 unsigned long seq;
1687 int mode;
1688 u64 ns;
1689
1690 do {
1691 seq = read_seqcount_begin(&gtod->seq);
1692 mode = gtod->clock.vclock_mode;
1693 ns = gtod->nsec_base;
1694 ns += vgettsc(cycle_now);
1695 ns >>= gtod->clock.shift;
1696 ns += gtod->boot_ns;
1697 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1698 *t = ns;
1699
1700 return mode;
1701 }
1702
1703 static int do_realtime(struct timespec *ts, u64 *cycle_now)
1704 {
1705 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1706 unsigned long seq;
1707 int mode;
1708 u64 ns;
1709
1710 do {
1711 seq = read_seqcount_begin(&gtod->seq);
1712 mode = gtod->clock.vclock_mode;
1713 ts->tv_sec = gtod->wall_time_sec;
1714 ns = gtod->nsec_base;
1715 ns += vgettsc(cycle_now);
1716 ns >>= gtod->clock.shift;
1717 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1718
1719 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1720 ts->tv_nsec = ns;
1721
1722 return mode;
1723 }
1724
1725 /* returns true if host is using tsc clocksource */
1726 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
1727 {
1728 /* checked again under seqlock below */
1729 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1730 return false;
1731
1732 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1733 }
1734
1735 /* returns true if host is using tsc clocksource */
1736 static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1737 u64 *cycle_now)
1738 {
1739 /* checked again under seqlock below */
1740 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1741 return false;
1742
1743 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1744 }
1745 #endif
1746
1747 /*
1748 *
1749 * Assuming a stable TSC across physical CPUS, and a stable TSC
1750 * across virtual CPUs, the following condition is possible.
1751 * Each numbered line represents an event visible to both
1752 * CPUs at the next numbered event.
1753 *
1754 * "timespecX" represents host monotonic time. "tscX" represents
1755 * RDTSC value.
1756 *
1757 * VCPU0 on CPU0 | VCPU1 on CPU1
1758 *
1759 * 1. read timespec0,tsc0
1760 * 2. | timespec1 = timespec0 + N
1761 * | tsc1 = tsc0 + M
1762 * 3. transition to guest | transition to guest
1763 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1764 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1765 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1766 *
1767 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1768 *
1769 * - ret0 < ret1
1770 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1771 * ...
1772 * - 0 < N - M => M < N
1773 *
1774 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1775 * always the case (the difference between two distinct xtime instances
1776 * might be smaller then the difference between corresponding TSC reads,
1777 * when updating guest vcpus pvclock areas).
1778 *
1779 * To avoid that problem, do not allow visibility of distinct
1780 * system_timestamp/tsc_timestamp values simultaneously: use a master
1781 * copy of host monotonic time values. Update that master copy
1782 * in lockstep.
1783 *
1784 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1785 *
1786 */
1787
1788 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1789 {
1790 #ifdef CONFIG_X86_64
1791 struct kvm_arch *ka = &kvm->arch;
1792 int vclock_mode;
1793 bool host_tsc_clocksource, vcpus_matched;
1794
1795 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1796 atomic_read(&kvm->online_vcpus));
1797
1798 /*
1799 * If the host uses TSC clock, then passthrough TSC as stable
1800 * to the guest.
1801 */
1802 host_tsc_clocksource = kvm_get_time_and_clockread(
1803 &ka->master_kernel_ns,
1804 &ka->master_cycle_now);
1805
1806 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1807 && !ka->backwards_tsc_observed
1808 && !ka->boot_vcpu_runs_old_kvmclock;
1809
1810 if (ka->use_master_clock)
1811 atomic_set(&kvm_guest_has_master_clock, 1);
1812
1813 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1814 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1815 vcpus_matched);
1816 #endif
1817 }
1818
1819 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1820 {
1821 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1822 }
1823
1824 static void kvm_gen_update_masterclock(struct kvm *kvm)
1825 {
1826 #ifdef CONFIG_X86_64
1827 int i;
1828 struct kvm_vcpu *vcpu;
1829 struct kvm_arch *ka = &kvm->arch;
1830
1831 spin_lock(&ka->pvclock_gtod_sync_lock);
1832 kvm_make_mclock_inprogress_request(kvm);
1833 /* no guest entries from this point */
1834 pvclock_update_vm_gtod_copy(kvm);
1835
1836 kvm_for_each_vcpu(i, vcpu, kvm)
1837 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1838
1839 /* guest entries allowed */
1840 kvm_for_each_vcpu(i, vcpu, kvm)
1841 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
1842
1843 spin_unlock(&ka->pvclock_gtod_sync_lock);
1844 #endif
1845 }
1846
1847 u64 get_kvmclock_ns(struct kvm *kvm)
1848 {
1849 struct kvm_arch *ka = &kvm->arch;
1850 struct pvclock_vcpu_time_info hv_clock;
1851 u64 ret;
1852
1853 spin_lock(&ka->pvclock_gtod_sync_lock);
1854 if (!ka->use_master_clock) {
1855 spin_unlock(&ka->pvclock_gtod_sync_lock);
1856 return ktime_get_boot_ns() + ka->kvmclock_offset;
1857 }
1858
1859 hv_clock.tsc_timestamp = ka->master_cycle_now;
1860 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1861 spin_unlock(&ka->pvclock_gtod_sync_lock);
1862
1863 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1864 get_cpu();
1865
1866 if (__this_cpu_read(cpu_tsc_khz)) {
1867 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1868 &hv_clock.tsc_shift,
1869 &hv_clock.tsc_to_system_mul);
1870 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1871 } else
1872 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
1873
1874 put_cpu();
1875
1876 return ret;
1877 }
1878
1879 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1880 {
1881 struct kvm_vcpu_arch *vcpu = &v->arch;
1882 struct pvclock_vcpu_time_info guest_hv_clock;
1883
1884 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1885 &guest_hv_clock, sizeof(guest_hv_clock))))
1886 return;
1887
1888 /* This VCPU is paused, but it's legal for a guest to read another
1889 * VCPU's kvmclock, so we really have to follow the specification where
1890 * it says that version is odd if data is being modified, and even after
1891 * it is consistent.
1892 *
1893 * Version field updates must be kept separate. This is because
1894 * kvm_write_guest_cached might use a "rep movs" instruction, and
1895 * writes within a string instruction are weakly ordered. So there
1896 * are three writes overall.
1897 *
1898 * As a small optimization, only write the version field in the first
1899 * and third write. The vcpu->pv_time cache is still valid, because the
1900 * version field is the first in the struct.
1901 */
1902 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1903
1904 if (guest_hv_clock.version & 1)
1905 ++guest_hv_clock.version; /* first time write, random junk */
1906
1907 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1908 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1909 &vcpu->hv_clock,
1910 sizeof(vcpu->hv_clock.version));
1911
1912 smp_wmb();
1913
1914 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1915 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1916
1917 if (vcpu->pvclock_set_guest_stopped_request) {
1918 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1919 vcpu->pvclock_set_guest_stopped_request = false;
1920 }
1921
1922 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1923
1924 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1925 &vcpu->hv_clock,
1926 sizeof(vcpu->hv_clock));
1927
1928 smp_wmb();
1929
1930 vcpu->hv_clock.version++;
1931 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1932 &vcpu->hv_clock,
1933 sizeof(vcpu->hv_clock.version));
1934 }
1935
1936 static int kvm_guest_time_update(struct kvm_vcpu *v)
1937 {
1938 unsigned long flags, tgt_tsc_khz;
1939 struct kvm_vcpu_arch *vcpu = &v->arch;
1940 struct kvm_arch *ka = &v->kvm->arch;
1941 s64 kernel_ns;
1942 u64 tsc_timestamp, host_tsc;
1943 u8 pvclock_flags;
1944 bool use_master_clock;
1945
1946 kernel_ns = 0;
1947 host_tsc = 0;
1948
1949 /*
1950 * If the host uses TSC clock, then passthrough TSC as stable
1951 * to the guest.
1952 */
1953 spin_lock(&ka->pvclock_gtod_sync_lock);
1954 use_master_clock = ka->use_master_clock;
1955 if (use_master_clock) {
1956 host_tsc = ka->master_cycle_now;
1957 kernel_ns = ka->master_kernel_ns;
1958 }
1959 spin_unlock(&ka->pvclock_gtod_sync_lock);
1960
1961 /* Keep irq disabled to prevent changes to the clock */
1962 local_irq_save(flags);
1963 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1964 if (unlikely(tgt_tsc_khz == 0)) {
1965 local_irq_restore(flags);
1966 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1967 return 1;
1968 }
1969 if (!use_master_clock) {
1970 host_tsc = rdtsc();
1971 kernel_ns = ktime_get_boot_ns();
1972 }
1973
1974 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1975
1976 /*
1977 * We may have to catch up the TSC to match elapsed wall clock
1978 * time for two reasons, even if kvmclock is used.
1979 * 1) CPU could have been running below the maximum TSC rate
1980 * 2) Broken TSC compensation resets the base at each VCPU
1981 * entry to avoid unknown leaps of TSC even when running
1982 * again on the same CPU. This may cause apparent elapsed
1983 * time to disappear, and the guest to stand still or run
1984 * very slowly.
1985 */
1986 if (vcpu->tsc_catchup) {
1987 u64 tsc = compute_guest_tsc(v, kernel_ns);
1988 if (tsc > tsc_timestamp) {
1989 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1990 tsc_timestamp = tsc;
1991 }
1992 }
1993
1994 local_irq_restore(flags);
1995
1996 /* With all the info we got, fill in the values */
1997
1998 if (kvm_has_tsc_control)
1999 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2000
2001 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2002 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2003 &vcpu->hv_clock.tsc_shift,
2004 &vcpu->hv_clock.tsc_to_system_mul);
2005 vcpu->hw_tsc_khz = tgt_tsc_khz;
2006 }
2007
2008 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2009 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2010 vcpu->last_guest_tsc = tsc_timestamp;
2011
2012 /* If the host uses TSC clocksource, then it is stable */
2013 pvclock_flags = 0;
2014 if (use_master_clock)
2015 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2016
2017 vcpu->hv_clock.flags = pvclock_flags;
2018
2019 if (vcpu->pv_time_enabled)
2020 kvm_setup_pvclock_page(v);
2021 if (v == kvm_get_vcpu(v->kvm, 0))
2022 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2023 return 0;
2024 }
2025
2026 /*
2027 * kvmclock updates which are isolated to a given vcpu, such as
2028 * vcpu->cpu migration, should not allow system_timestamp from
2029 * the rest of the vcpus to remain static. Otherwise ntp frequency
2030 * correction applies to one vcpu's system_timestamp but not
2031 * the others.
2032 *
2033 * So in those cases, request a kvmclock update for all vcpus.
2034 * We need to rate-limit these requests though, as they can
2035 * considerably slow guests that have a large number of vcpus.
2036 * The time for a remote vcpu to update its kvmclock is bound
2037 * by the delay we use to rate-limit the updates.
2038 */
2039
2040 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2041
2042 static void kvmclock_update_fn(struct work_struct *work)
2043 {
2044 int i;
2045 struct delayed_work *dwork = to_delayed_work(work);
2046 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2047 kvmclock_update_work);
2048 struct kvm *kvm = container_of(ka, struct kvm, arch);
2049 struct kvm_vcpu *vcpu;
2050
2051 kvm_for_each_vcpu(i, vcpu, kvm) {
2052 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2053 kvm_vcpu_kick(vcpu);
2054 }
2055 }
2056
2057 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2058 {
2059 struct kvm *kvm = v->kvm;
2060
2061 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2062 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2063 KVMCLOCK_UPDATE_DELAY);
2064 }
2065
2066 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2067
2068 static void kvmclock_sync_fn(struct work_struct *work)
2069 {
2070 struct delayed_work *dwork = to_delayed_work(work);
2071 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2072 kvmclock_sync_work);
2073 struct kvm *kvm = container_of(ka, struct kvm, arch);
2074
2075 if (!kvmclock_periodic_sync)
2076 return;
2077
2078 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2079 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2080 KVMCLOCK_SYNC_PERIOD);
2081 }
2082
2083 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2084 {
2085 u64 mcg_cap = vcpu->arch.mcg_cap;
2086 unsigned bank_num = mcg_cap & 0xff;
2087
2088 switch (msr) {
2089 case MSR_IA32_MCG_STATUS:
2090 vcpu->arch.mcg_status = data;
2091 break;
2092 case MSR_IA32_MCG_CTL:
2093 if (!(mcg_cap & MCG_CTL_P))
2094 return 1;
2095 if (data != 0 && data != ~(u64)0)
2096 return -1;
2097 vcpu->arch.mcg_ctl = data;
2098 break;
2099 default:
2100 if (msr >= MSR_IA32_MC0_CTL &&
2101 msr < MSR_IA32_MCx_CTL(bank_num)) {
2102 u32 offset = msr - MSR_IA32_MC0_CTL;
2103 /* only 0 or all 1s can be written to IA32_MCi_CTL
2104 * some Linux kernels though clear bit 10 in bank 4 to
2105 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2106 * this to avoid an uncatched #GP in the guest
2107 */
2108 if ((offset & 0x3) == 0 &&
2109 data != 0 && (data | (1 << 10)) != ~(u64)0)
2110 return -1;
2111 vcpu->arch.mce_banks[offset] = data;
2112 break;
2113 }
2114 return 1;
2115 }
2116 return 0;
2117 }
2118
2119 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2120 {
2121 struct kvm *kvm = vcpu->kvm;
2122 int lm = is_long_mode(vcpu);
2123 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2124 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2125 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2126 : kvm->arch.xen_hvm_config.blob_size_32;
2127 u32 page_num = data & ~PAGE_MASK;
2128 u64 page_addr = data & PAGE_MASK;
2129 u8 *page;
2130 int r;
2131
2132 r = -E2BIG;
2133 if (page_num >= blob_size)
2134 goto out;
2135 r = -ENOMEM;
2136 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2137 if (IS_ERR(page)) {
2138 r = PTR_ERR(page);
2139 goto out;
2140 }
2141 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2142 goto out_free;
2143 r = 0;
2144 out_free:
2145 kfree(page);
2146 out:
2147 return r;
2148 }
2149
2150 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2151 {
2152 gpa_t gpa = data & ~0x3f;
2153
2154 /* Bits 3:5 are reserved, Should be zero */
2155 if (data & 0x38)
2156 return 1;
2157
2158 vcpu->arch.apf.msr_val = data;
2159
2160 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2161 kvm_clear_async_pf_completion_queue(vcpu);
2162 kvm_async_pf_hash_reset(vcpu);
2163 return 0;
2164 }
2165
2166 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2167 sizeof(u32)))
2168 return 1;
2169
2170 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2171 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2172 kvm_async_pf_wakeup_all(vcpu);
2173 return 0;
2174 }
2175
2176 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2177 {
2178 vcpu->arch.pv_time_enabled = false;
2179 }
2180
2181 static void record_steal_time(struct kvm_vcpu *vcpu)
2182 {
2183 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2184 return;
2185
2186 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2187 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2188 return;
2189
2190 vcpu->arch.st.steal.preempted = 0;
2191
2192 if (vcpu->arch.st.steal.version & 1)
2193 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2194
2195 vcpu->arch.st.steal.version += 1;
2196
2197 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2198 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2199
2200 smp_wmb();
2201
2202 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2203 vcpu->arch.st.last_steal;
2204 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2205
2206 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2207 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2208
2209 smp_wmb();
2210
2211 vcpu->arch.st.steal.version += 1;
2212
2213 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2214 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2215 }
2216
2217 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2218 {
2219 bool pr = false;
2220 u32 msr = msr_info->index;
2221 u64 data = msr_info->data;
2222
2223 switch (msr) {
2224 case MSR_AMD64_NB_CFG:
2225 case MSR_IA32_UCODE_WRITE:
2226 case MSR_VM_HSAVE_PA:
2227 case MSR_AMD64_PATCH_LOADER:
2228 case MSR_AMD64_BU_CFG2:
2229 case MSR_AMD64_DC_CFG:
2230 case MSR_F15H_EX_CFG:
2231 break;
2232
2233 case MSR_IA32_UCODE_REV:
2234 if (msr_info->host_initiated)
2235 vcpu->arch.microcode_version = data;
2236 break;
2237 case MSR_IA32_ARCH_CAPABILITIES:
2238 if (!msr_info->host_initiated)
2239 return 1;
2240 vcpu->arch.arch_capabilities = data;
2241 break;
2242 case MSR_EFER:
2243 return set_efer(vcpu, data);
2244 case MSR_K7_HWCR:
2245 data &= ~(u64)0x40; /* ignore flush filter disable */
2246 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2247 data &= ~(u64)0x8; /* ignore TLB cache disable */
2248 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2249 if (data != 0) {
2250 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2251 data);
2252 return 1;
2253 }
2254 break;
2255 case MSR_FAM10H_MMIO_CONF_BASE:
2256 if (data != 0) {
2257 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2258 "0x%llx\n", data);
2259 return 1;
2260 }
2261 break;
2262 case MSR_IA32_DEBUGCTLMSR:
2263 if (!data) {
2264 /* We support the non-activated case already */
2265 break;
2266 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2267 /* Values other than LBR and BTF are vendor-specific,
2268 thus reserved and should throw a #GP */
2269 return 1;
2270 }
2271 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2272 __func__, data);
2273 break;
2274 case 0x200 ... 0x2ff:
2275 return kvm_mtrr_set_msr(vcpu, msr, data);
2276 case MSR_IA32_APICBASE:
2277 return kvm_set_apic_base(vcpu, msr_info);
2278 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2279 return kvm_x2apic_msr_write(vcpu, msr, data);
2280 case MSR_IA32_TSCDEADLINE:
2281 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2282 break;
2283 case MSR_IA32_TSC_ADJUST:
2284 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2285 if (!msr_info->host_initiated) {
2286 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2287 adjust_tsc_offset_guest(vcpu, adj);
2288 }
2289 vcpu->arch.ia32_tsc_adjust_msr = data;
2290 }
2291 break;
2292 case MSR_IA32_MISC_ENABLE:
2293 vcpu->arch.ia32_misc_enable_msr = data;
2294 break;
2295 case MSR_IA32_SMBASE:
2296 if (!msr_info->host_initiated)
2297 return 1;
2298 vcpu->arch.smbase = data;
2299 break;
2300 case MSR_KVM_WALL_CLOCK_NEW:
2301 case MSR_KVM_WALL_CLOCK:
2302 vcpu->kvm->arch.wall_clock = data;
2303 kvm_write_wall_clock(vcpu->kvm, data);
2304 break;
2305 case MSR_KVM_SYSTEM_TIME_NEW:
2306 case MSR_KVM_SYSTEM_TIME: {
2307 struct kvm_arch *ka = &vcpu->kvm->arch;
2308
2309 kvmclock_reset(vcpu);
2310
2311 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2312 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2313
2314 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2315 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2316
2317 ka->boot_vcpu_runs_old_kvmclock = tmp;
2318 }
2319
2320 vcpu->arch.time = data;
2321 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2322
2323 /* we verify if the enable bit is set... */
2324 if (!(data & 1))
2325 break;
2326
2327 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2328 &vcpu->arch.pv_time, data & ~1ULL,
2329 sizeof(struct pvclock_vcpu_time_info)))
2330 vcpu->arch.pv_time_enabled = false;
2331 else
2332 vcpu->arch.pv_time_enabled = true;
2333
2334 break;
2335 }
2336 case MSR_KVM_ASYNC_PF_EN:
2337 if (kvm_pv_enable_async_pf(vcpu, data))
2338 return 1;
2339 break;
2340 case MSR_KVM_STEAL_TIME:
2341
2342 if (unlikely(!sched_info_on()))
2343 return 1;
2344
2345 if (data & KVM_STEAL_RESERVED_MASK)
2346 return 1;
2347
2348 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2349 data & KVM_STEAL_VALID_BITS,
2350 sizeof(struct kvm_steal_time)))
2351 return 1;
2352
2353 vcpu->arch.st.msr_val = data;
2354
2355 if (!(data & KVM_MSR_ENABLED))
2356 break;
2357
2358 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2359
2360 break;
2361 case MSR_KVM_PV_EOI_EN:
2362 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2363 return 1;
2364 break;
2365
2366 case MSR_IA32_MCG_CTL:
2367 case MSR_IA32_MCG_STATUS:
2368 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2369 return set_msr_mce(vcpu, msr, data);
2370
2371 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2372 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2373 pr = true; /* fall through */
2374 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2375 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2376 if (kvm_pmu_is_valid_msr(vcpu, msr))
2377 return kvm_pmu_set_msr(vcpu, msr_info);
2378
2379 if (pr || data != 0)
2380 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2381 "0x%x data 0x%llx\n", msr, data);
2382 break;
2383 case MSR_K7_CLK_CTL:
2384 /*
2385 * Ignore all writes to this no longer documented MSR.
2386 * Writes are only relevant for old K7 processors,
2387 * all pre-dating SVM, but a recommended workaround from
2388 * AMD for these chips. It is possible to specify the
2389 * affected processor models on the command line, hence
2390 * the need to ignore the workaround.
2391 */
2392 break;
2393 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2394 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2395 case HV_X64_MSR_CRASH_CTL:
2396 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2397 return kvm_hv_set_msr_common(vcpu, msr, data,
2398 msr_info->host_initiated);
2399 case MSR_IA32_BBL_CR_CTL3:
2400 /* Drop writes to this legacy MSR -- see rdmsr
2401 * counterpart for further detail.
2402 */
2403 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
2404 break;
2405 case MSR_AMD64_OSVW_ID_LENGTH:
2406 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2407 return 1;
2408 vcpu->arch.osvw.length = data;
2409 break;
2410 case MSR_AMD64_OSVW_STATUS:
2411 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2412 return 1;
2413 vcpu->arch.osvw.status = data;
2414 break;
2415 case MSR_PLATFORM_INFO:
2416 if (!msr_info->host_initiated ||
2417 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2418 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2419 cpuid_fault_enabled(vcpu)))
2420 return 1;
2421 vcpu->arch.msr_platform_info = data;
2422 break;
2423 case MSR_MISC_FEATURES_ENABLES:
2424 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2425 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2426 !supports_cpuid_fault(vcpu)))
2427 return 1;
2428 vcpu->arch.msr_misc_features_enables = data;
2429 break;
2430 default:
2431 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2432 return xen_hvm_config(vcpu, data);
2433 if (kvm_pmu_is_valid_msr(vcpu, msr))
2434 return kvm_pmu_set_msr(vcpu, msr_info);
2435 if (!ignore_msrs) {
2436 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2437 msr, data);
2438 return 1;
2439 } else {
2440 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2441 msr, data);
2442 break;
2443 }
2444 }
2445 return 0;
2446 }
2447 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2448
2449
2450 /*
2451 * Reads an msr value (of 'msr_index') into 'pdata'.
2452 * Returns 0 on success, non-0 otherwise.
2453 * Assumes vcpu_load() was already called.
2454 */
2455 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2456 {
2457 return kvm_x86_ops->get_msr(vcpu, msr);
2458 }
2459 EXPORT_SYMBOL_GPL(kvm_get_msr);
2460
2461 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2462 {
2463 u64 data;
2464 u64 mcg_cap = vcpu->arch.mcg_cap;
2465 unsigned bank_num = mcg_cap & 0xff;
2466
2467 switch (msr) {
2468 case MSR_IA32_P5_MC_ADDR:
2469 case MSR_IA32_P5_MC_TYPE:
2470 data = 0;
2471 break;
2472 case MSR_IA32_MCG_CAP:
2473 data = vcpu->arch.mcg_cap;
2474 break;
2475 case MSR_IA32_MCG_CTL:
2476 if (!(mcg_cap & MCG_CTL_P))
2477 return 1;
2478 data = vcpu->arch.mcg_ctl;
2479 break;
2480 case MSR_IA32_MCG_STATUS:
2481 data = vcpu->arch.mcg_status;
2482 break;
2483 default:
2484 if (msr >= MSR_IA32_MC0_CTL &&
2485 msr < MSR_IA32_MCx_CTL(bank_num)) {
2486 u32 offset = msr - MSR_IA32_MC0_CTL;
2487 data = vcpu->arch.mce_banks[offset];
2488 break;
2489 }
2490 return 1;
2491 }
2492 *pdata = data;
2493 return 0;
2494 }
2495
2496 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2497 {
2498 switch (msr_info->index) {
2499 case MSR_IA32_PLATFORM_ID:
2500 case MSR_IA32_EBL_CR_POWERON:
2501 case MSR_IA32_DEBUGCTLMSR:
2502 case MSR_IA32_LASTBRANCHFROMIP:
2503 case MSR_IA32_LASTBRANCHTOIP:
2504 case MSR_IA32_LASTINTFROMIP:
2505 case MSR_IA32_LASTINTTOIP:
2506 case MSR_K8_SYSCFG:
2507 case MSR_K8_TSEG_ADDR:
2508 case MSR_K8_TSEG_MASK:
2509 case MSR_K7_HWCR:
2510 case MSR_VM_HSAVE_PA:
2511 case MSR_K8_INT_PENDING_MSG:
2512 case MSR_AMD64_NB_CFG:
2513 case MSR_FAM10H_MMIO_CONF_BASE:
2514 case MSR_AMD64_BU_CFG2:
2515 case MSR_IA32_PERF_CTL:
2516 case MSR_AMD64_DC_CFG:
2517 case MSR_F15H_EX_CFG:
2518 msr_info->data = 0;
2519 break;
2520 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2521 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2522 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2523 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2524 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2525 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2526 msr_info->data = 0;
2527 break;
2528 case MSR_IA32_UCODE_REV:
2529 msr_info->data = vcpu->arch.microcode_version;
2530 break;
2531 case MSR_IA32_ARCH_CAPABILITIES:
2532 if (!msr_info->host_initiated &&
2533 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2534 return 1;
2535 msr_info->data = vcpu->arch.arch_capabilities;
2536 break;
2537 case MSR_MTRRcap:
2538 case 0x200 ... 0x2ff:
2539 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2540 case 0xcd: /* fsb frequency */
2541 msr_info->data = 3;
2542 break;
2543 /*
2544 * MSR_EBC_FREQUENCY_ID
2545 * Conservative value valid for even the basic CPU models.
2546 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2547 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2548 * and 266MHz for model 3, or 4. Set Core Clock
2549 * Frequency to System Bus Frequency Ratio to 1 (bits
2550 * 31:24) even though these are only valid for CPU
2551 * models > 2, however guests may end up dividing or
2552 * multiplying by zero otherwise.
2553 */
2554 case MSR_EBC_FREQUENCY_ID:
2555 msr_info->data = 1 << 24;
2556 break;
2557 case MSR_IA32_APICBASE:
2558 msr_info->data = kvm_get_apic_base(vcpu);
2559 break;
2560 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2561 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2562 break;
2563 case MSR_IA32_TSCDEADLINE:
2564 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2565 break;
2566 case MSR_IA32_TSC_ADJUST:
2567 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2568 break;
2569 case MSR_IA32_MISC_ENABLE:
2570 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2571 break;
2572 case MSR_IA32_SMBASE:
2573 if (!msr_info->host_initiated)
2574 return 1;
2575 msr_info->data = vcpu->arch.smbase;
2576 break;
2577 case MSR_IA32_PERF_STATUS:
2578 /* TSC increment by tick */
2579 msr_info->data = 1000ULL;
2580 /* CPU multiplier */
2581 msr_info->data |= (((uint64_t)4ULL) << 40);
2582 break;
2583 case MSR_EFER:
2584 msr_info->data = vcpu->arch.efer;
2585 break;
2586 case MSR_KVM_WALL_CLOCK:
2587 case MSR_KVM_WALL_CLOCK_NEW:
2588 msr_info->data = vcpu->kvm->arch.wall_clock;
2589 break;
2590 case MSR_KVM_SYSTEM_TIME:
2591 case MSR_KVM_SYSTEM_TIME_NEW:
2592 msr_info->data = vcpu->arch.time;
2593 break;
2594 case MSR_KVM_ASYNC_PF_EN:
2595 msr_info->data = vcpu->arch.apf.msr_val;
2596 break;
2597 case MSR_KVM_STEAL_TIME:
2598 msr_info->data = vcpu->arch.st.msr_val;
2599 break;
2600 case MSR_KVM_PV_EOI_EN:
2601 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2602 break;
2603 case MSR_IA32_P5_MC_ADDR:
2604 case MSR_IA32_P5_MC_TYPE:
2605 case MSR_IA32_MCG_CAP:
2606 case MSR_IA32_MCG_CTL:
2607 case MSR_IA32_MCG_STATUS:
2608 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2609 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2610 case MSR_K7_CLK_CTL:
2611 /*
2612 * Provide expected ramp-up count for K7. All other
2613 * are set to zero, indicating minimum divisors for
2614 * every field.
2615 *
2616 * This prevents guest kernels on AMD host with CPU
2617 * type 6, model 8 and higher from exploding due to
2618 * the rdmsr failing.
2619 */
2620 msr_info->data = 0x20000000;
2621 break;
2622 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2623 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2624 case HV_X64_MSR_CRASH_CTL:
2625 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2626 return kvm_hv_get_msr_common(vcpu,
2627 msr_info->index, &msr_info->data);
2628 break;
2629 case MSR_IA32_BBL_CR_CTL3:
2630 /* This legacy MSR exists but isn't fully documented in current
2631 * silicon. It is however accessed by winxp in very narrow
2632 * scenarios where it sets bit #19, itself documented as
2633 * a "reserved" bit. Best effort attempt to source coherent
2634 * read data here should the balance of the register be
2635 * interpreted by the guest:
2636 *
2637 * L2 cache control register 3: 64GB range, 256KB size,
2638 * enabled, latency 0x1, configured
2639 */
2640 msr_info->data = 0xbe702111;
2641 break;
2642 case MSR_AMD64_OSVW_ID_LENGTH:
2643 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2644 return 1;
2645 msr_info->data = vcpu->arch.osvw.length;
2646 break;
2647 case MSR_AMD64_OSVW_STATUS:
2648 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2649 return 1;
2650 msr_info->data = vcpu->arch.osvw.status;
2651 break;
2652 case MSR_PLATFORM_INFO:
2653 msr_info->data = vcpu->arch.msr_platform_info;
2654 break;
2655 case MSR_MISC_FEATURES_ENABLES:
2656 msr_info->data = vcpu->arch.msr_misc_features_enables;
2657 break;
2658 default:
2659 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2660 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2661 if (!ignore_msrs) {
2662 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2663 msr_info->index);
2664 return 1;
2665 } else {
2666 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2667 msr_info->data = 0;
2668 }
2669 break;
2670 }
2671 return 0;
2672 }
2673 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2674
2675 /*
2676 * Read or write a bunch of msrs. All parameters are kernel addresses.
2677 *
2678 * @return number of msrs set successfully.
2679 */
2680 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2681 struct kvm_msr_entry *entries,
2682 int (*do_msr)(struct kvm_vcpu *vcpu,
2683 unsigned index, u64 *data))
2684 {
2685 int i;
2686
2687 for (i = 0; i < msrs->nmsrs; ++i)
2688 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2689 break;
2690
2691 return i;
2692 }
2693
2694 /*
2695 * Read or write a bunch of msrs. Parameters are user addresses.
2696 *
2697 * @return number of msrs set successfully.
2698 */
2699 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2700 int (*do_msr)(struct kvm_vcpu *vcpu,
2701 unsigned index, u64 *data),
2702 int writeback)
2703 {
2704 struct kvm_msrs msrs;
2705 struct kvm_msr_entry *entries;
2706 int r, n;
2707 unsigned size;
2708
2709 r = -EFAULT;
2710 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2711 goto out;
2712
2713 r = -E2BIG;
2714 if (msrs.nmsrs >= MAX_IO_MSRS)
2715 goto out;
2716
2717 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2718 entries = memdup_user(user_msrs->entries, size);
2719 if (IS_ERR(entries)) {
2720 r = PTR_ERR(entries);
2721 goto out;
2722 }
2723
2724 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2725 if (r < 0)
2726 goto out_free;
2727
2728 r = -EFAULT;
2729 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2730 goto out_free;
2731
2732 r = n;
2733
2734 out_free:
2735 kfree(entries);
2736 out:
2737 return r;
2738 }
2739
2740 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2741 {
2742 int r;
2743
2744 switch (ext) {
2745 case KVM_CAP_IRQCHIP:
2746 case KVM_CAP_HLT:
2747 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2748 case KVM_CAP_SET_TSS_ADDR:
2749 case KVM_CAP_EXT_CPUID:
2750 case KVM_CAP_EXT_EMUL_CPUID:
2751 case KVM_CAP_CLOCKSOURCE:
2752 case KVM_CAP_PIT:
2753 case KVM_CAP_NOP_IO_DELAY:
2754 case KVM_CAP_MP_STATE:
2755 case KVM_CAP_SYNC_MMU:
2756 case KVM_CAP_USER_NMI:
2757 case KVM_CAP_REINJECT_CONTROL:
2758 case KVM_CAP_IRQ_INJECT_STATUS:
2759 case KVM_CAP_IOEVENTFD:
2760 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2761 case KVM_CAP_PIT2:
2762 case KVM_CAP_PIT_STATE2:
2763 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2764 case KVM_CAP_XEN_HVM:
2765 case KVM_CAP_VCPU_EVENTS:
2766 case KVM_CAP_HYPERV:
2767 case KVM_CAP_HYPERV_VAPIC:
2768 case KVM_CAP_HYPERV_SPIN:
2769 case KVM_CAP_HYPERV_SYNIC:
2770 case KVM_CAP_HYPERV_SYNIC2:
2771 case KVM_CAP_HYPERV_VP_INDEX:
2772 case KVM_CAP_PCI_SEGMENT:
2773 case KVM_CAP_DEBUGREGS:
2774 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2775 case KVM_CAP_XSAVE:
2776 case KVM_CAP_ASYNC_PF:
2777 case KVM_CAP_GET_TSC_KHZ:
2778 case KVM_CAP_KVMCLOCK_CTRL:
2779 case KVM_CAP_READONLY_MEM:
2780 case KVM_CAP_HYPERV_TIME:
2781 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2782 case KVM_CAP_TSC_DEADLINE_TIMER:
2783 case KVM_CAP_ENABLE_CAP_VM:
2784 case KVM_CAP_DISABLE_QUIRKS:
2785 case KVM_CAP_SET_BOOT_CPU_ID:
2786 case KVM_CAP_SPLIT_IRQCHIP:
2787 case KVM_CAP_IMMEDIATE_EXIT:
2788 case KVM_CAP_GET_MSR_FEATURES:
2789 r = 1;
2790 break;
2791 case KVM_CAP_ADJUST_CLOCK:
2792 r = KVM_CLOCK_TSC_STABLE;
2793 break;
2794 case KVM_CAP_X86_GUEST_MWAIT:
2795 r = kvm_mwait_in_guest();
2796 break;
2797 case KVM_CAP_X86_SMM:
2798 /* SMBASE is usually relocated above 1M on modern chipsets,
2799 * and SMM handlers might indeed rely on 4G segment limits,
2800 * so do not report SMM to be available if real mode is
2801 * emulated via vm86 mode. Still, do not go to great lengths
2802 * to avoid userspace's usage of the feature, because it is a
2803 * fringe case that is not enabled except via specific settings
2804 * of the module parameters.
2805 */
2806 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
2807 break;
2808 case KVM_CAP_VAPIC:
2809 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2810 break;
2811 case KVM_CAP_NR_VCPUS:
2812 r = KVM_SOFT_MAX_VCPUS;
2813 break;
2814 case KVM_CAP_MAX_VCPUS:
2815 r = KVM_MAX_VCPUS;
2816 break;
2817 case KVM_CAP_NR_MEMSLOTS:
2818 r = KVM_USER_MEM_SLOTS;
2819 break;
2820 case KVM_CAP_PV_MMU: /* obsolete */
2821 r = 0;
2822 break;
2823 case KVM_CAP_MCE:
2824 r = KVM_MAX_MCE_BANKS;
2825 break;
2826 case KVM_CAP_XCRS:
2827 r = boot_cpu_has(X86_FEATURE_XSAVE);
2828 break;
2829 case KVM_CAP_TSC_CONTROL:
2830 r = kvm_has_tsc_control;
2831 break;
2832 case KVM_CAP_X2APIC_API:
2833 r = KVM_X2APIC_API_VALID_FLAGS;
2834 break;
2835 default:
2836 r = 0;
2837 break;
2838 }
2839 return r;
2840
2841 }
2842
2843 long kvm_arch_dev_ioctl(struct file *filp,
2844 unsigned int ioctl, unsigned long arg)
2845 {
2846 void __user *argp = (void __user *)arg;
2847 long r;
2848
2849 switch (ioctl) {
2850 case KVM_GET_MSR_INDEX_LIST: {
2851 struct kvm_msr_list __user *user_msr_list = argp;
2852 struct kvm_msr_list msr_list;
2853 unsigned n;
2854
2855 r = -EFAULT;
2856 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2857 goto out;
2858 n = msr_list.nmsrs;
2859 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2860 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2861 goto out;
2862 r = -E2BIG;
2863 if (n < msr_list.nmsrs)
2864 goto out;
2865 r = -EFAULT;
2866 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2867 num_msrs_to_save * sizeof(u32)))
2868 goto out;
2869 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2870 &emulated_msrs,
2871 num_emulated_msrs * sizeof(u32)))
2872 goto out;
2873 r = 0;
2874 break;
2875 }
2876 case KVM_GET_SUPPORTED_CPUID:
2877 case KVM_GET_EMULATED_CPUID: {
2878 struct kvm_cpuid2 __user *cpuid_arg = argp;
2879 struct kvm_cpuid2 cpuid;
2880
2881 r = -EFAULT;
2882 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2883 goto out;
2884
2885 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2886 ioctl);
2887 if (r)
2888 goto out;
2889
2890 r = -EFAULT;
2891 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2892 goto out;
2893 r = 0;
2894 break;
2895 }
2896 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2897 r = -EFAULT;
2898 if (copy_to_user(argp, &kvm_mce_cap_supported,
2899 sizeof(kvm_mce_cap_supported)))
2900 goto out;
2901 r = 0;
2902 break;
2903 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
2904 struct kvm_msr_list __user *user_msr_list = argp;
2905 struct kvm_msr_list msr_list;
2906 unsigned int n;
2907
2908 r = -EFAULT;
2909 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
2910 goto out;
2911 n = msr_list.nmsrs;
2912 msr_list.nmsrs = num_msr_based_features;
2913 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
2914 goto out;
2915 r = -E2BIG;
2916 if (n < msr_list.nmsrs)
2917 goto out;
2918 r = -EFAULT;
2919 if (copy_to_user(user_msr_list->indices, &msr_based_features,
2920 num_msr_based_features * sizeof(u32)))
2921 goto out;
2922 r = 0;
2923 break;
2924 }
2925 case KVM_GET_MSRS:
2926 r = msr_io(NULL, argp, do_get_msr_feature, 1);
2927 break;
2928 }
2929 default:
2930 r = -EINVAL;
2931 }
2932 out:
2933 return r;
2934 }
2935
2936 static void wbinvd_ipi(void *garbage)
2937 {
2938 wbinvd();
2939 }
2940
2941 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2942 {
2943 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2944 }
2945
2946 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2947 {
2948 /* Address WBINVD may be executed by guest */
2949 if (need_emulate_wbinvd(vcpu)) {
2950 if (kvm_x86_ops->has_wbinvd_exit())
2951 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2952 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2953 smp_call_function_single(vcpu->cpu,
2954 wbinvd_ipi, NULL, 1);
2955 }
2956
2957 kvm_x86_ops->vcpu_load(vcpu, cpu);
2958
2959 /* Apply any externally detected TSC adjustments (due to suspend) */
2960 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2961 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2962 vcpu->arch.tsc_offset_adjustment = 0;
2963 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2964 }
2965
2966 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2967 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2968 rdtsc() - vcpu->arch.last_host_tsc;
2969 if (tsc_delta < 0)
2970 mark_tsc_unstable("KVM discovered backwards TSC");
2971
2972 if (check_tsc_unstable()) {
2973 u64 offset = kvm_compute_tsc_offset(vcpu,
2974 vcpu->arch.last_guest_tsc);
2975 kvm_vcpu_write_tsc_offset(vcpu, offset);
2976 vcpu->arch.tsc_catchup = 1;
2977 }
2978
2979 if (kvm_lapic_hv_timer_in_use(vcpu))
2980 kvm_lapic_restart_hv_timer(vcpu);
2981
2982 /*
2983 * On a host with synchronized TSC, there is no need to update
2984 * kvmclock on vcpu->cpu migration
2985 */
2986 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2987 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2988 if (vcpu->cpu != cpu)
2989 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
2990 vcpu->cpu = cpu;
2991 }
2992
2993 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2994 }
2995
2996 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2997 {
2998 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2999 return;
3000
3001 vcpu->arch.st.steal.preempted = 1;
3002
3003 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3004 &vcpu->arch.st.steal.preempted,
3005 offsetof(struct kvm_steal_time, preempted),
3006 sizeof(vcpu->arch.st.steal.preempted));
3007 }
3008
3009 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3010 {
3011 int idx;
3012
3013 if (vcpu->preempted)
3014 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3015
3016 /*
3017 * Disable page faults because we're in atomic context here.
3018 * kvm_write_guest_offset_cached() would call might_fault()
3019 * that relies on pagefault_disable() to tell if there's a
3020 * bug. NOTE: the write to guest memory may not go through if
3021 * during postcopy live migration or if there's heavy guest
3022 * paging.
3023 */
3024 pagefault_disable();
3025 /*
3026 * kvm_memslots() will be called by
3027 * kvm_write_guest_offset_cached() so take the srcu lock.
3028 */
3029 idx = srcu_read_lock(&vcpu->kvm->srcu);
3030 kvm_steal_time_set_preempted(vcpu);
3031 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3032 pagefault_enable();
3033 kvm_x86_ops->vcpu_put(vcpu);
3034 vcpu->arch.last_host_tsc = rdtsc();
3035 /*
3036 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3037 * on every vmexit, but if not, we might have a stale dr6 from the
3038 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3039 */
3040 set_debugreg(0, 6);
3041 }
3042
3043 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3044 struct kvm_lapic_state *s)
3045 {
3046 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
3047 kvm_x86_ops->sync_pir_to_irr(vcpu);
3048
3049 return kvm_apic_get_state(vcpu, s);
3050 }
3051
3052 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3053 struct kvm_lapic_state *s)
3054 {
3055 int r;
3056
3057 r = kvm_apic_set_state(vcpu, s);
3058 if (r)
3059 return r;
3060 update_cr8_intercept(vcpu);
3061
3062 return 0;
3063 }
3064
3065 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3066 {
3067 return (!lapic_in_kernel(vcpu) ||
3068 kvm_apic_accept_pic_intr(vcpu));
3069 }
3070
3071 /*
3072 * if userspace requested an interrupt window, check that the
3073 * interrupt window is open.
3074 *
3075 * No need to exit to userspace if we already have an interrupt queued.
3076 */
3077 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3078 {
3079 return kvm_arch_interrupt_allowed(vcpu) &&
3080 !kvm_cpu_has_interrupt(vcpu) &&
3081 !kvm_event_needs_reinjection(vcpu) &&
3082 kvm_cpu_accept_dm_intr(vcpu);
3083 }
3084
3085 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3086 struct kvm_interrupt *irq)
3087 {
3088 if (irq->irq >= KVM_NR_INTERRUPTS)
3089 return -EINVAL;
3090
3091 if (!irqchip_in_kernel(vcpu->kvm)) {
3092 kvm_queue_interrupt(vcpu, irq->irq, false);
3093 kvm_make_request(KVM_REQ_EVENT, vcpu);
3094 return 0;
3095 }
3096
3097 /*
3098 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3099 * fail for in-kernel 8259.
3100 */
3101 if (pic_in_kernel(vcpu->kvm))
3102 return -ENXIO;
3103
3104 if (vcpu->arch.pending_external_vector != -1)
3105 return -EEXIST;
3106
3107 vcpu->arch.pending_external_vector = irq->irq;
3108 kvm_make_request(KVM_REQ_EVENT, vcpu);
3109 return 0;
3110 }
3111
3112 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3113 {
3114 kvm_inject_nmi(vcpu);
3115
3116 return 0;
3117 }
3118
3119 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3120 {
3121 kvm_make_request(KVM_REQ_SMI, vcpu);
3122
3123 return 0;
3124 }
3125
3126 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3127 struct kvm_tpr_access_ctl *tac)
3128 {
3129 if (tac->flags)
3130 return -EINVAL;
3131 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3132 return 0;
3133 }
3134
3135 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3136 u64 mcg_cap)
3137 {
3138 int r;
3139 unsigned bank_num = mcg_cap & 0xff, bank;
3140
3141 r = -EINVAL;
3142 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3143 goto out;
3144 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3145 goto out;
3146 r = 0;
3147 vcpu->arch.mcg_cap = mcg_cap;
3148 /* Init IA32_MCG_CTL to all 1s */
3149 if (mcg_cap & MCG_CTL_P)
3150 vcpu->arch.mcg_ctl = ~(u64)0;
3151 /* Init IA32_MCi_CTL to all 1s */
3152 for (bank = 0; bank < bank_num; bank++)
3153 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3154
3155 if (kvm_x86_ops->setup_mce)
3156 kvm_x86_ops->setup_mce(vcpu);
3157 out:
3158 return r;
3159 }
3160
3161 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3162 struct kvm_x86_mce *mce)
3163 {
3164 u64 mcg_cap = vcpu->arch.mcg_cap;
3165 unsigned bank_num = mcg_cap & 0xff;
3166 u64 *banks = vcpu->arch.mce_banks;
3167
3168 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3169 return -EINVAL;
3170 /*
3171 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3172 * reporting is disabled
3173 */
3174 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3175 vcpu->arch.mcg_ctl != ~(u64)0)
3176 return 0;
3177 banks += 4 * mce->bank;
3178 /*
3179 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3180 * reporting is disabled for the bank
3181 */
3182 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3183 return 0;
3184 if (mce->status & MCI_STATUS_UC) {
3185 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3186 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3187 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3188 return 0;
3189 }
3190 if (banks[1] & MCI_STATUS_VAL)
3191 mce->status |= MCI_STATUS_OVER;
3192 banks[2] = mce->addr;
3193 banks[3] = mce->misc;
3194 vcpu->arch.mcg_status = mce->mcg_status;
3195 banks[1] = mce->status;
3196 kvm_queue_exception(vcpu, MC_VECTOR);
3197 } else if (!(banks[1] & MCI_STATUS_VAL)
3198 || !(banks[1] & MCI_STATUS_UC)) {
3199 if (banks[1] & MCI_STATUS_VAL)
3200 mce->status |= MCI_STATUS_OVER;
3201 banks[2] = mce->addr;
3202 banks[3] = mce->misc;
3203 banks[1] = mce->status;
3204 } else
3205 banks[1] |= MCI_STATUS_OVER;
3206 return 0;
3207 }
3208
3209 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3210 struct kvm_vcpu_events *events)
3211 {
3212 process_nmi(vcpu);
3213 /*
3214 * FIXME: pass injected and pending separately. This is only
3215 * needed for nested virtualization, whose state cannot be
3216 * migrated yet. For now we can combine them.
3217 */
3218 events->exception.injected =
3219 (vcpu->arch.exception.pending ||
3220 vcpu->arch.exception.injected) &&
3221 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3222 events->exception.nr = vcpu->arch.exception.nr;
3223 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3224 events->exception.pad = 0;
3225 events->exception.error_code = vcpu->arch.exception.error_code;
3226
3227 events->interrupt.injected =
3228 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3229 events->interrupt.nr = vcpu->arch.interrupt.nr;
3230 events->interrupt.soft = 0;
3231 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3232
3233 events->nmi.injected = vcpu->arch.nmi_injected;
3234 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3235 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3236 events->nmi.pad = 0;
3237
3238 events->sipi_vector = 0; /* never valid when reporting to user space */
3239
3240 events->smi.smm = is_smm(vcpu);
3241 events->smi.pending = vcpu->arch.smi_pending;
3242 events->smi.smm_inside_nmi =
3243 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3244 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3245
3246 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3247 | KVM_VCPUEVENT_VALID_SHADOW
3248 | KVM_VCPUEVENT_VALID_SMM);
3249 memset(&events->reserved, 0, sizeof(events->reserved));
3250 }
3251
3252 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3253
3254 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3255 struct kvm_vcpu_events *events)
3256 {
3257 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3258 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3259 | KVM_VCPUEVENT_VALID_SHADOW
3260 | KVM_VCPUEVENT_VALID_SMM))
3261 return -EINVAL;
3262
3263 if (events->exception.injected &&
3264 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3265 is_guest_mode(vcpu)))
3266 return -EINVAL;
3267
3268 /* INITs are latched while in SMM */
3269 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3270 (events->smi.smm || events->smi.pending) &&
3271 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3272 return -EINVAL;
3273
3274 process_nmi(vcpu);
3275 vcpu->arch.exception.injected = false;
3276 vcpu->arch.exception.pending = events->exception.injected;
3277 vcpu->arch.exception.nr = events->exception.nr;
3278 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3279 vcpu->arch.exception.error_code = events->exception.error_code;
3280
3281 vcpu->arch.interrupt.pending = events->interrupt.injected;
3282 vcpu->arch.interrupt.nr = events->interrupt.nr;
3283 vcpu->arch.interrupt.soft = events->interrupt.soft;
3284 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3285 kvm_x86_ops->set_interrupt_shadow(vcpu,
3286 events->interrupt.shadow);
3287
3288 vcpu->arch.nmi_injected = events->nmi.injected;
3289 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3290 vcpu->arch.nmi_pending = events->nmi.pending;
3291 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3292
3293 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3294 lapic_in_kernel(vcpu))
3295 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3296
3297 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3298 u32 hflags = vcpu->arch.hflags;
3299 if (events->smi.smm)
3300 hflags |= HF_SMM_MASK;
3301 else
3302 hflags &= ~HF_SMM_MASK;
3303 kvm_set_hflags(vcpu, hflags);
3304
3305 vcpu->arch.smi_pending = events->smi.pending;
3306
3307 if (events->smi.smm) {
3308 if (events->smi.smm_inside_nmi)
3309 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3310 else
3311 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3312 if (lapic_in_kernel(vcpu)) {
3313 if (events->smi.latched_init)
3314 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3315 else
3316 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3317 }
3318 }
3319 }
3320
3321 kvm_make_request(KVM_REQ_EVENT, vcpu);
3322
3323 return 0;
3324 }
3325
3326 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3327 struct kvm_debugregs *dbgregs)
3328 {
3329 unsigned long val;
3330
3331 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3332 kvm_get_dr(vcpu, 6, &val);
3333 dbgregs->dr6 = val;
3334 dbgregs->dr7 = vcpu->arch.dr7;
3335 dbgregs->flags = 0;
3336 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3337 }
3338
3339 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3340 struct kvm_debugregs *dbgregs)
3341 {
3342 if (dbgregs->flags)
3343 return -EINVAL;
3344
3345 if (dbgregs->dr6 & ~0xffffffffull)
3346 return -EINVAL;
3347 if (dbgregs->dr7 & ~0xffffffffull)
3348 return -EINVAL;
3349
3350 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3351 kvm_update_dr0123(vcpu);
3352 vcpu->arch.dr6 = dbgregs->dr6;
3353 kvm_update_dr6(vcpu);
3354 vcpu->arch.dr7 = dbgregs->dr7;
3355 kvm_update_dr7(vcpu);
3356
3357 return 0;
3358 }
3359
3360 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3361
3362 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3363 {
3364 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3365 u64 xstate_bv = xsave->header.xfeatures;
3366 u64 valid;
3367
3368 /*
3369 * Copy legacy XSAVE area, to avoid complications with CPUID
3370 * leaves 0 and 1 in the loop below.
3371 */
3372 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3373
3374 /* Set XSTATE_BV */
3375 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3376 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3377
3378 /*
3379 * Copy each region from the possibly compacted offset to the
3380 * non-compacted offset.
3381 */
3382 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3383 while (valid) {
3384 u64 feature = valid & -valid;
3385 int index = fls64(feature) - 1;
3386 void *src = get_xsave_addr(xsave, feature);
3387
3388 if (src) {
3389 u32 size, offset, ecx, edx;
3390 cpuid_count(XSTATE_CPUID, index,
3391 &size, &offset, &ecx, &edx);
3392 if (feature == XFEATURE_MASK_PKRU)
3393 memcpy(dest + offset, &vcpu->arch.pkru,
3394 sizeof(vcpu->arch.pkru));
3395 else
3396 memcpy(dest + offset, src, size);
3397
3398 }
3399
3400 valid -= feature;
3401 }
3402 }
3403
3404 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3405 {
3406 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3407 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3408 u64 valid;
3409
3410 /*
3411 * Copy legacy XSAVE area, to avoid complications with CPUID
3412 * leaves 0 and 1 in the loop below.
3413 */
3414 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3415
3416 /* Set XSTATE_BV and possibly XCOMP_BV. */
3417 xsave->header.xfeatures = xstate_bv;
3418 if (boot_cpu_has(X86_FEATURE_XSAVES))
3419 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3420
3421 /*
3422 * Copy each region from the non-compacted offset to the
3423 * possibly compacted offset.
3424 */
3425 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3426 while (valid) {
3427 u64 feature = valid & -valid;
3428 int index = fls64(feature) - 1;
3429 void *dest = get_xsave_addr(xsave, feature);
3430
3431 if (dest) {
3432 u32 size, offset, ecx, edx;
3433 cpuid_count(XSTATE_CPUID, index,
3434 &size, &offset, &ecx, &edx);
3435 if (feature == XFEATURE_MASK_PKRU)
3436 memcpy(&vcpu->arch.pkru, src + offset,
3437 sizeof(vcpu->arch.pkru));
3438 else
3439 memcpy(dest, src + offset, size);
3440 }
3441
3442 valid -= feature;
3443 }
3444 }
3445
3446 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3447 struct kvm_xsave *guest_xsave)
3448 {
3449 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3450 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3451 fill_xsave((u8 *) guest_xsave->region, vcpu);
3452 } else {
3453 memcpy(guest_xsave->region,
3454 &vcpu->arch.guest_fpu.state.fxsave,
3455 sizeof(struct fxregs_state));
3456 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3457 XFEATURE_MASK_FPSSE;
3458 }
3459 }
3460
3461 #define XSAVE_MXCSR_OFFSET 24
3462
3463 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3464 struct kvm_xsave *guest_xsave)
3465 {
3466 u64 xstate_bv =
3467 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3468 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3469
3470 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3471 /*
3472 * Here we allow setting states that are not present in
3473 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3474 * with old userspace.
3475 */
3476 if (xstate_bv & ~kvm_supported_xcr0() ||
3477 mxcsr & ~mxcsr_feature_mask)
3478 return -EINVAL;
3479 load_xsave(vcpu, (u8 *)guest_xsave->region);
3480 } else {
3481 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3482 mxcsr & ~mxcsr_feature_mask)
3483 return -EINVAL;
3484 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3485 guest_xsave->region, sizeof(struct fxregs_state));
3486 }
3487 return 0;
3488 }
3489
3490 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3491 struct kvm_xcrs *guest_xcrs)
3492 {
3493 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3494 guest_xcrs->nr_xcrs = 0;
3495 return;
3496 }
3497
3498 guest_xcrs->nr_xcrs = 1;
3499 guest_xcrs->flags = 0;
3500 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3501 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3502 }
3503
3504 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3505 struct kvm_xcrs *guest_xcrs)
3506 {
3507 int i, r = 0;
3508
3509 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3510 return -EINVAL;
3511
3512 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3513 return -EINVAL;
3514
3515 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3516 /* Only support XCR0 currently */
3517 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3518 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3519 guest_xcrs->xcrs[i].value);
3520 break;
3521 }
3522 if (r)
3523 r = -EINVAL;
3524 return r;
3525 }
3526
3527 /*
3528 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3529 * stopped by the hypervisor. This function will be called from the host only.
3530 * EINVAL is returned when the host attempts to set the flag for a guest that
3531 * does not support pv clocks.
3532 */
3533 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3534 {
3535 if (!vcpu->arch.pv_time_enabled)
3536 return -EINVAL;
3537 vcpu->arch.pvclock_set_guest_stopped_request = true;
3538 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3539 return 0;
3540 }
3541
3542 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3543 struct kvm_enable_cap *cap)
3544 {
3545 if (cap->flags)
3546 return -EINVAL;
3547
3548 switch (cap->cap) {
3549 case KVM_CAP_HYPERV_SYNIC2:
3550 if (cap->args[0])
3551 return -EINVAL;
3552 case KVM_CAP_HYPERV_SYNIC:
3553 if (!irqchip_in_kernel(vcpu->kvm))
3554 return -EINVAL;
3555 return kvm_hv_activate_synic(vcpu, cap->cap ==
3556 KVM_CAP_HYPERV_SYNIC2);
3557 default:
3558 return -EINVAL;
3559 }
3560 }
3561
3562 long kvm_arch_vcpu_ioctl(struct file *filp,
3563 unsigned int ioctl, unsigned long arg)
3564 {
3565 struct kvm_vcpu *vcpu = filp->private_data;
3566 void __user *argp = (void __user *)arg;
3567 int r;
3568 union {
3569 struct kvm_lapic_state *lapic;
3570 struct kvm_xsave *xsave;
3571 struct kvm_xcrs *xcrs;
3572 void *buffer;
3573 } u;
3574
3575 u.buffer = NULL;
3576 switch (ioctl) {
3577 case KVM_GET_LAPIC: {
3578 r = -EINVAL;
3579 if (!lapic_in_kernel(vcpu))
3580 goto out;
3581 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3582
3583 r = -ENOMEM;
3584 if (!u.lapic)
3585 goto out;
3586 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3587 if (r)
3588 goto out;
3589 r = -EFAULT;
3590 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3591 goto out;
3592 r = 0;
3593 break;
3594 }
3595 case KVM_SET_LAPIC: {
3596 r = -EINVAL;
3597 if (!lapic_in_kernel(vcpu))
3598 goto out;
3599 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3600 if (IS_ERR(u.lapic))
3601 return PTR_ERR(u.lapic);
3602
3603 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3604 break;
3605 }
3606 case KVM_INTERRUPT: {
3607 struct kvm_interrupt irq;
3608
3609 r = -EFAULT;
3610 if (copy_from_user(&irq, argp, sizeof irq))
3611 goto out;
3612 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3613 break;
3614 }
3615 case KVM_NMI: {
3616 r = kvm_vcpu_ioctl_nmi(vcpu);
3617 break;
3618 }
3619 case KVM_SMI: {
3620 r = kvm_vcpu_ioctl_smi(vcpu);
3621 break;
3622 }
3623 case KVM_SET_CPUID: {
3624 struct kvm_cpuid __user *cpuid_arg = argp;
3625 struct kvm_cpuid cpuid;
3626
3627 r = -EFAULT;
3628 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3629 goto out;
3630 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3631 break;
3632 }
3633 case KVM_SET_CPUID2: {
3634 struct kvm_cpuid2 __user *cpuid_arg = argp;
3635 struct kvm_cpuid2 cpuid;
3636
3637 r = -EFAULT;
3638 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3639 goto out;
3640 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3641 cpuid_arg->entries);
3642 break;
3643 }
3644 case KVM_GET_CPUID2: {
3645 struct kvm_cpuid2 __user *cpuid_arg = argp;
3646 struct kvm_cpuid2 cpuid;
3647
3648 r = -EFAULT;
3649 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3650 goto out;
3651 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3652 cpuid_arg->entries);
3653 if (r)
3654 goto out;
3655 r = -EFAULT;
3656 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3657 goto out;
3658 r = 0;
3659 break;
3660 }
3661 case KVM_GET_MSRS: {
3662 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3663 r = msr_io(vcpu, argp, do_get_msr, 1);
3664 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3665 break;
3666 }
3667 case KVM_SET_MSRS: {
3668 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3669 r = msr_io(vcpu, argp, do_set_msr, 0);
3670 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3671 break;
3672 }
3673 case KVM_TPR_ACCESS_REPORTING: {
3674 struct kvm_tpr_access_ctl tac;
3675
3676 r = -EFAULT;
3677 if (copy_from_user(&tac, argp, sizeof tac))
3678 goto out;
3679 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3680 if (r)
3681 goto out;
3682 r = -EFAULT;
3683 if (copy_to_user(argp, &tac, sizeof tac))
3684 goto out;
3685 r = 0;
3686 break;
3687 };
3688 case KVM_SET_VAPIC_ADDR: {
3689 struct kvm_vapic_addr va;
3690 int idx;
3691
3692 r = -EINVAL;
3693 if (!lapic_in_kernel(vcpu))
3694 goto out;
3695 r = -EFAULT;
3696 if (copy_from_user(&va, argp, sizeof va))
3697 goto out;
3698 idx = srcu_read_lock(&vcpu->kvm->srcu);
3699 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3700 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3701 break;
3702 }
3703 case KVM_X86_SETUP_MCE: {
3704 u64 mcg_cap;
3705
3706 r = -EFAULT;
3707 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3708 goto out;
3709 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3710 break;
3711 }
3712 case KVM_X86_SET_MCE: {
3713 struct kvm_x86_mce mce;
3714
3715 r = -EFAULT;
3716 if (copy_from_user(&mce, argp, sizeof mce))
3717 goto out;
3718 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3719 break;
3720 }
3721 case KVM_GET_VCPU_EVENTS: {
3722 struct kvm_vcpu_events events;
3723
3724 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3725
3726 r = -EFAULT;
3727 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3728 break;
3729 r = 0;
3730 break;
3731 }
3732 case KVM_SET_VCPU_EVENTS: {
3733 struct kvm_vcpu_events events;
3734
3735 r = -EFAULT;
3736 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3737 break;
3738
3739 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3740 break;
3741 }
3742 case KVM_GET_DEBUGREGS: {
3743 struct kvm_debugregs dbgregs;
3744
3745 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3746
3747 r = -EFAULT;
3748 if (copy_to_user(argp, &dbgregs,
3749 sizeof(struct kvm_debugregs)))
3750 break;
3751 r = 0;
3752 break;
3753 }
3754 case KVM_SET_DEBUGREGS: {
3755 struct kvm_debugregs dbgregs;
3756
3757 r = -EFAULT;
3758 if (copy_from_user(&dbgregs, argp,
3759 sizeof(struct kvm_debugregs)))
3760 break;
3761
3762 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3763 break;
3764 }
3765 case KVM_GET_XSAVE: {
3766 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3767 r = -ENOMEM;
3768 if (!u.xsave)
3769 break;
3770
3771 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3772
3773 r = -EFAULT;
3774 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3775 break;
3776 r = 0;
3777 break;
3778 }
3779 case KVM_SET_XSAVE: {
3780 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3781 if (IS_ERR(u.xsave))
3782 return PTR_ERR(u.xsave);
3783
3784 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3785 break;
3786 }
3787 case KVM_GET_XCRS: {
3788 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3789 r = -ENOMEM;
3790 if (!u.xcrs)
3791 break;
3792
3793 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3794
3795 r = -EFAULT;
3796 if (copy_to_user(argp, u.xcrs,
3797 sizeof(struct kvm_xcrs)))
3798 break;
3799 r = 0;
3800 break;
3801 }
3802 case KVM_SET_XCRS: {
3803 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3804 if (IS_ERR(u.xcrs))
3805 return PTR_ERR(u.xcrs);
3806
3807 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3808 break;
3809 }
3810 case KVM_SET_TSC_KHZ: {
3811 u32 user_tsc_khz;
3812
3813 r = -EINVAL;
3814 user_tsc_khz = (u32)arg;
3815
3816 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3817 goto out;
3818
3819 if (user_tsc_khz == 0)
3820 user_tsc_khz = tsc_khz;
3821
3822 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3823 r = 0;
3824
3825 goto out;
3826 }
3827 case KVM_GET_TSC_KHZ: {
3828 r = vcpu->arch.virtual_tsc_khz;
3829 goto out;
3830 }
3831 case KVM_KVMCLOCK_CTRL: {
3832 r = kvm_set_guest_paused(vcpu);
3833 goto out;
3834 }
3835 case KVM_ENABLE_CAP: {
3836 struct kvm_enable_cap cap;
3837
3838 r = -EFAULT;
3839 if (copy_from_user(&cap, argp, sizeof(cap)))
3840 goto out;
3841 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3842 break;
3843 }
3844 default:
3845 r = -EINVAL;
3846 }
3847 out:
3848 kfree(u.buffer);
3849 return r;
3850 }
3851
3852 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3853 {
3854 return VM_FAULT_SIGBUS;
3855 }
3856
3857 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3858 {
3859 int ret;
3860
3861 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3862 return -EINVAL;
3863 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3864 return ret;
3865 }
3866
3867 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3868 u64 ident_addr)
3869 {
3870 kvm->arch.ept_identity_map_addr = ident_addr;
3871 return 0;
3872 }
3873
3874 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3875 u32 kvm_nr_mmu_pages)
3876 {
3877 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3878 return -EINVAL;
3879
3880 mutex_lock(&kvm->slots_lock);
3881
3882 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3883 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3884
3885 mutex_unlock(&kvm->slots_lock);
3886 return 0;
3887 }
3888
3889 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3890 {
3891 return kvm->arch.n_max_mmu_pages;
3892 }
3893
3894 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3895 {
3896 struct kvm_pic *pic = kvm->arch.vpic;
3897 int r;
3898
3899 r = 0;
3900 switch (chip->chip_id) {
3901 case KVM_IRQCHIP_PIC_MASTER:
3902 memcpy(&chip->chip.pic, &pic->pics[0],
3903 sizeof(struct kvm_pic_state));
3904 break;
3905 case KVM_IRQCHIP_PIC_SLAVE:
3906 memcpy(&chip->chip.pic, &pic->pics[1],
3907 sizeof(struct kvm_pic_state));
3908 break;
3909 case KVM_IRQCHIP_IOAPIC:
3910 kvm_get_ioapic(kvm, &chip->chip.ioapic);
3911 break;
3912 default:
3913 r = -EINVAL;
3914 break;
3915 }
3916 return r;
3917 }
3918
3919 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3920 {
3921 struct kvm_pic *pic = kvm->arch.vpic;
3922 int r;
3923
3924 r = 0;
3925 switch (chip->chip_id) {
3926 case KVM_IRQCHIP_PIC_MASTER:
3927 spin_lock(&pic->lock);
3928 memcpy(&pic->pics[0], &chip->chip.pic,
3929 sizeof(struct kvm_pic_state));
3930 spin_unlock(&pic->lock);
3931 break;
3932 case KVM_IRQCHIP_PIC_SLAVE:
3933 spin_lock(&pic->lock);
3934 memcpy(&pic->pics[1], &chip->chip.pic,
3935 sizeof(struct kvm_pic_state));
3936 spin_unlock(&pic->lock);
3937 break;
3938 case KVM_IRQCHIP_IOAPIC:
3939 kvm_set_ioapic(kvm, &chip->chip.ioapic);
3940 break;
3941 default:
3942 r = -EINVAL;
3943 break;
3944 }
3945 kvm_pic_update_irq(pic);
3946 return r;
3947 }
3948
3949 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3950 {
3951 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3952
3953 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3954
3955 mutex_lock(&kps->lock);
3956 memcpy(ps, &kps->channels, sizeof(*ps));
3957 mutex_unlock(&kps->lock);
3958 return 0;
3959 }
3960
3961 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3962 {
3963 int i;
3964 struct kvm_pit *pit = kvm->arch.vpit;
3965
3966 mutex_lock(&pit->pit_state.lock);
3967 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3968 for (i = 0; i < 3; i++)
3969 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3970 mutex_unlock(&pit->pit_state.lock);
3971 return 0;
3972 }
3973
3974 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3975 {
3976 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3977 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3978 sizeof(ps->channels));
3979 ps->flags = kvm->arch.vpit->pit_state.flags;
3980 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3981 memset(&ps->reserved, 0, sizeof(ps->reserved));
3982 return 0;
3983 }
3984
3985 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3986 {
3987 int start = 0;
3988 int i;
3989 u32 prev_legacy, cur_legacy;
3990 struct kvm_pit *pit = kvm->arch.vpit;
3991
3992 mutex_lock(&pit->pit_state.lock);
3993 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3994 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3995 if (!prev_legacy && cur_legacy)
3996 start = 1;
3997 memcpy(&pit->pit_state.channels, &ps->channels,
3998 sizeof(pit->pit_state.channels));
3999 pit->pit_state.flags = ps->flags;
4000 for (i = 0; i < 3; i++)
4001 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4002 start && i == 0);
4003 mutex_unlock(&pit->pit_state.lock);
4004 return 0;
4005 }
4006
4007 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4008 struct kvm_reinject_control *control)
4009 {
4010 struct kvm_pit *pit = kvm->arch.vpit;
4011
4012 if (!pit)
4013 return -ENXIO;
4014
4015 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4016 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4017 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4018 */
4019 mutex_lock(&pit->pit_state.lock);
4020 kvm_pit_set_reinject(pit, control->pit_reinject);
4021 mutex_unlock(&pit->pit_state.lock);
4022
4023 return 0;
4024 }
4025
4026 /**
4027 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4028 * @kvm: kvm instance
4029 * @log: slot id and address to which we copy the log
4030 *
4031 * Steps 1-4 below provide general overview of dirty page logging. See
4032 * kvm_get_dirty_log_protect() function description for additional details.
4033 *
4034 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4035 * always flush the TLB (step 4) even if previous step failed and the dirty
4036 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4037 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4038 * writes will be marked dirty for next log read.
4039 *
4040 * 1. Take a snapshot of the bit and clear it if needed.
4041 * 2. Write protect the corresponding page.
4042 * 3. Copy the snapshot to the userspace.
4043 * 4. Flush TLB's if needed.
4044 */
4045 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4046 {
4047 bool is_dirty = false;
4048 int r;
4049
4050 mutex_lock(&kvm->slots_lock);
4051
4052 /*
4053 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4054 */
4055 if (kvm_x86_ops->flush_log_dirty)
4056 kvm_x86_ops->flush_log_dirty(kvm);
4057
4058 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
4059
4060 /*
4061 * All the TLBs can be flushed out of mmu lock, see the comments in
4062 * kvm_mmu_slot_remove_write_access().
4063 */
4064 lockdep_assert_held(&kvm->slots_lock);
4065 if (is_dirty)
4066 kvm_flush_remote_tlbs(kvm);
4067
4068 mutex_unlock(&kvm->slots_lock);
4069 return r;
4070 }
4071
4072 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4073 bool line_status)
4074 {
4075 if (!irqchip_in_kernel(kvm))
4076 return -ENXIO;
4077
4078 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4079 irq_event->irq, irq_event->level,
4080 line_status);
4081 return 0;
4082 }
4083
4084 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4085 struct kvm_enable_cap *cap)
4086 {
4087 int r;
4088
4089 if (cap->flags)
4090 return -EINVAL;
4091
4092 switch (cap->cap) {
4093 case KVM_CAP_DISABLE_QUIRKS:
4094 kvm->arch.disabled_quirks = cap->args[0];
4095 r = 0;
4096 break;
4097 case KVM_CAP_SPLIT_IRQCHIP: {
4098 mutex_lock(&kvm->lock);
4099 r = -EINVAL;
4100 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4101 goto split_irqchip_unlock;
4102 r = -EEXIST;
4103 if (irqchip_in_kernel(kvm))
4104 goto split_irqchip_unlock;
4105 if (kvm->created_vcpus)
4106 goto split_irqchip_unlock;
4107 r = kvm_setup_empty_irq_routing(kvm);
4108 if (r)
4109 goto split_irqchip_unlock;
4110 /* Pairs with irqchip_in_kernel. */
4111 smp_wmb();
4112 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4113 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4114 r = 0;
4115 split_irqchip_unlock:
4116 mutex_unlock(&kvm->lock);
4117 break;
4118 }
4119 case KVM_CAP_X2APIC_API:
4120 r = -EINVAL;
4121 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4122 break;
4123
4124 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4125 kvm->arch.x2apic_format = true;
4126 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4127 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4128
4129 r = 0;
4130 break;
4131 default:
4132 r = -EINVAL;
4133 break;
4134 }
4135 return r;
4136 }
4137
4138 long kvm_arch_vm_ioctl(struct file *filp,
4139 unsigned int ioctl, unsigned long arg)
4140 {
4141 struct kvm *kvm = filp->private_data;
4142 void __user *argp = (void __user *)arg;
4143 int r = -ENOTTY;
4144 /*
4145 * This union makes it completely explicit to gcc-3.x
4146 * that these two variables' stack usage should be
4147 * combined, not added together.
4148 */
4149 union {
4150 struct kvm_pit_state ps;
4151 struct kvm_pit_state2 ps2;
4152 struct kvm_pit_config pit_config;
4153 } u;
4154
4155 switch (ioctl) {
4156 case KVM_SET_TSS_ADDR:
4157 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4158 break;
4159 case KVM_SET_IDENTITY_MAP_ADDR: {
4160 u64 ident_addr;
4161
4162 r = -EFAULT;
4163 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4164 goto out;
4165 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4166 break;
4167 }
4168 case KVM_SET_NR_MMU_PAGES:
4169 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4170 break;
4171 case KVM_GET_NR_MMU_PAGES:
4172 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4173 break;
4174 case KVM_CREATE_IRQCHIP: {
4175 mutex_lock(&kvm->lock);
4176
4177 r = -EEXIST;
4178 if (irqchip_in_kernel(kvm))
4179 goto create_irqchip_unlock;
4180
4181 r = -EINVAL;
4182 if (kvm->created_vcpus)
4183 goto create_irqchip_unlock;
4184
4185 r = kvm_pic_init(kvm);
4186 if (r)
4187 goto create_irqchip_unlock;
4188
4189 r = kvm_ioapic_init(kvm);
4190 if (r) {
4191 kvm_pic_destroy(kvm);
4192 goto create_irqchip_unlock;
4193 }
4194
4195 r = kvm_setup_default_irq_routing(kvm);
4196 if (r) {
4197 kvm_ioapic_destroy(kvm);
4198 kvm_pic_destroy(kvm);
4199 goto create_irqchip_unlock;
4200 }
4201 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4202 smp_wmb();
4203 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4204 create_irqchip_unlock:
4205 mutex_unlock(&kvm->lock);
4206 break;
4207 }
4208 case KVM_CREATE_PIT:
4209 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4210 goto create_pit;
4211 case KVM_CREATE_PIT2:
4212 r = -EFAULT;
4213 if (copy_from_user(&u.pit_config, argp,
4214 sizeof(struct kvm_pit_config)))
4215 goto out;
4216 create_pit:
4217 mutex_lock(&kvm->lock);
4218 r = -EEXIST;
4219 if (kvm->arch.vpit)
4220 goto create_pit_unlock;
4221 r = -ENOMEM;
4222 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4223 if (kvm->arch.vpit)
4224 r = 0;
4225 create_pit_unlock:
4226 mutex_unlock(&kvm->lock);
4227 break;
4228 case KVM_GET_IRQCHIP: {
4229 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4230 struct kvm_irqchip *chip;
4231
4232 chip = memdup_user(argp, sizeof(*chip));
4233 if (IS_ERR(chip)) {
4234 r = PTR_ERR(chip);
4235 goto out;
4236 }
4237
4238 r = -ENXIO;
4239 if (!irqchip_kernel(kvm))
4240 goto get_irqchip_out;
4241 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4242 if (r)
4243 goto get_irqchip_out;
4244 r = -EFAULT;
4245 if (copy_to_user(argp, chip, sizeof *chip))
4246 goto get_irqchip_out;
4247 r = 0;
4248 get_irqchip_out:
4249 kfree(chip);
4250 break;
4251 }
4252 case KVM_SET_IRQCHIP: {
4253 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4254 struct kvm_irqchip *chip;
4255
4256 chip = memdup_user(argp, sizeof(*chip));
4257 if (IS_ERR(chip)) {
4258 r = PTR_ERR(chip);
4259 goto out;
4260 }
4261
4262 r = -ENXIO;
4263 if (!irqchip_kernel(kvm))
4264 goto set_irqchip_out;
4265 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4266 if (r)
4267 goto set_irqchip_out;
4268 r = 0;
4269 set_irqchip_out:
4270 kfree(chip);
4271 break;
4272 }
4273 case KVM_GET_PIT: {
4274 r = -EFAULT;
4275 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4276 goto out;
4277 r = -ENXIO;
4278 if (!kvm->arch.vpit)
4279 goto out;
4280 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4281 if (r)
4282 goto out;
4283 r = -EFAULT;
4284 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4285 goto out;
4286 r = 0;
4287 break;
4288 }
4289 case KVM_SET_PIT: {
4290 r = -EFAULT;
4291 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4292 goto out;
4293 r = -ENXIO;
4294 if (!kvm->arch.vpit)
4295 goto out;
4296 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4297 break;
4298 }
4299 case KVM_GET_PIT2: {
4300 r = -ENXIO;
4301 if (!kvm->arch.vpit)
4302 goto out;
4303 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4304 if (r)
4305 goto out;
4306 r = -EFAULT;
4307 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4308 goto out;
4309 r = 0;
4310 break;
4311 }
4312 case KVM_SET_PIT2: {
4313 r = -EFAULT;
4314 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4315 goto out;
4316 r = -ENXIO;
4317 if (!kvm->arch.vpit)
4318 goto out;
4319 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4320 break;
4321 }
4322 case KVM_REINJECT_CONTROL: {
4323 struct kvm_reinject_control control;
4324 r = -EFAULT;
4325 if (copy_from_user(&control, argp, sizeof(control)))
4326 goto out;
4327 r = kvm_vm_ioctl_reinject(kvm, &control);
4328 break;
4329 }
4330 case KVM_SET_BOOT_CPU_ID:
4331 r = 0;
4332 mutex_lock(&kvm->lock);
4333 if (kvm->created_vcpus)
4334 r = -EBUSY;
4335 else
4336 kvm->arch.bsp_vcpu_id = arg;
4337 mutex_unlock(&kvm->lock);
4338 break;
4339 case KVM_XEN_HVM_CONFIG: {
4340 struct kvm_xen_hvm_config xhc;
4341 r = -EFAULT;
4342 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4343 goto out;
4344 r = -EINVAL;
4345 if (xhc.flags)
4346 goto out;
4347 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4348 r = 0;
4349 break;
4350 }
4351 case KVM_SET_CLOCK: {
4352 struct kvm_clock_data user_ns;
4353 u64 now_ns;
4354
4355 r = -EFAULT;
4356 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4357 goto out;
4358
4359 r = -EINVAL;
4360 if (user_ns.flags)
4361 goto out;
4362
4363 r = 0;
4364 /*
4365 * TODO: userspace has to take care of races with VCPU_RUN, so
4366 * kvm_gen_update_masterclock() can be cut down to locked
4367 * pvclock_update_vm_gtod_copy().
4368 */
4369 kvm_gen_update_masterclock(kvm);
4370 now_ns = get_kvmclock_ns(kvm);
4371 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4372 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4373 break;
4374 }
4375 case KVM_GET_CLOCK: {
4376 struct kvm_clock_data user_ns;
4377 u64 now_ns;
4378
4379 now_ns = get_kvmclock_ns(kvm);
4380 user_ns.clock = now_ns;
4381 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4382 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4383
4384 r = -EFAULT;
4385 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4386 goto out;
4387 r = 0;
4388 break;
4389 }
4390 case KVM_ENABLE_CAP: {
4391 struct kvm_enable_cap cap;
4392
4393 r = -EFAULT;
4394 if (copy_from_user(&cap, argp, sizeof(cap)))
4395 goto out;
4396 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4397 break;
4398 }
4399 default:
4400 r = -ENOTTY;
4401 }
4402 out:
4403 return r;
4404 }
4405
4406 static void kvm_init_msr_list(void)
4407 {
4408 u32 dummy[2];
4409 unsigned i, j;
4410
4411 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4412 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4413 continue;
4414
4415 /*
4416 * Even MSRs that are valid in the host may not be exposed
4417 * to the guests in some cases.
4418 */
4419 switch (msrs_to_save[i]) {
4420 case MSR_IA32_BNDCFGS:
4421 if (!kvm_x86_ops->mpx_supported())
4422 continue;
4423 break;
4424 case MSR_TSC_AUX:
4425 if (!kvm_x86_ops->rdtscp_supported())
4426 continue;
4427 break;
4428 default:
4429 break;
4430 }
4431
4432 if (j < i)
4433 msrs_to_save[j] = msrs_to_save[i];
4434 j++;
4435 }
4436 num_msrs_to_save = j;
4437
4438 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4439 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4440 continue;
4441
4442 if (j < i)
4443 emulated_msrs[j] = emulated_msrs[i];
4444 j++;
4445 }
4446 num_emulated_msrs = j;
4447
4448 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4449 struct kvm_msr_entry msr;
4450
4451 msr.index = msr_based_features[i];
4452 if (kvm_get_msr_feature(&msr))
4453 continue;
4454
4455 if (j < i)
4456 msr_based_features[j] = msr_based_features[i];
4457 j++;
4458 }
4459 num_msr_based_features = j;
4460 }
4461
4462 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4463 const void *v)
4464 {
4465 int handled = 0;
4466 int n;
4467
4468 do {
4469 n = min(len, 8);
4470 if (!(lapic_in_kernel(vcpu) &&
4471 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4472 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4473 break;
4474 handled += n;
4475 addr += n;
4476 len -= n;
4477 v += n;
4478 } while (len);
4479
4480 return handled;
4481 }
4482
4483 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4484 {
4485 int handled = 0;
4486 int n;
4487
4488 do {
4489 n = min(len, 8);
4490 if (!(lapic_in_kernel(vcpu) &&
4491 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4492 addr, n, v))
4493 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4494 break;
4495 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
4496 handled += n;
4497 addr += n;
4498 len -= n;
4499 v += n;
4500 } while (len);
4501
4502 return handled;
4503 }
4504
4505 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4506 struct kvm_segment *var, int seg)
4507 {
4508 kvm_x86_ops->set_segment(vcpu, var, seg);
4509 }
4510
4511 void kvm_get_segment(struct kvm_vcpu *vcpu,
4512 struct kvm_segment *var, int seg)
4513 {
4514 kvm_x86_ops->get_segment(vcpu, var, seg);
4515 }
4516
4517 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4518 struct x86_exception *exception)
4519 {
4520 gpa_t t_gpa;
4521
4522 BUG_ON(!mmu_is_nested(vcpu));
4523
4524 /* NPT walks are always user-walks */
4525 access |= PFERR_USER_MASK;
4526 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4527
4528 return t_gpa;
4529 }
4530
4531 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4532 struct x86_exception *exception)
4533 {
4534 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4535 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4536 }
4537
4538 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4539 struct x86_exception *exception)
4540 {
4541 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4542 access |= PFERR_FETCH_MASK;
4543 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4544 }
4545
4546 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4547 struct x86_exception *exception)
4548 {
4549 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4550 access |= PFERR_WRITE_MASK;
4551 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4552 }
4553
4554 /* uses this to access any guest's mapped memory without checking CPL */
4555 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4556 struct x86_exception *exception)
4557 {
4558 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4559 }
4560
4561 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4562 struct kvm_vcpu *vcpu, u32 access,
4563 struct x86_exception *exception)
4564 {
4565 void *data = val;
4566 int r = X86EMUL_CONTINUE;
4567
4568 while (bytes) {
4569 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4570 exception);
4571 unsigned offset = addr & (PAGE_SIZE-1);
4572 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4573 int ret;
4574
4575 if (gpa == UNMAPPED_GVA)
4576 return X86EMUL_PROPAGATE_FAULT;
4577 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4578 offset, toread);
4579 if (ret < 0) {
4580 r = X86EMUL_IO_NEEDED;
4581 goto out;
4582 }
4583
4584 bytes -= toread;
4585 data += toread;
4586 addr += toread;
4587 }
4588 out:
4589 return r;
4590 }
4591
4592 /* used for instruction fetching */
4593 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4594 gva_t addr, void *val, unsigned int bytes,
4595 struct x86_exception *exception)
4596 {
4597 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4598 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4599 unsigned offset;
4600 int ret;
4601
4602 /* Inline kvm_read_guest_virt_helper for speed. */
4603 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4604 exception);
4605 if (unlikely(gpa == UNMAPPED_GVA))
4606 return X86EMUL_PROPAGATE_FAULT;
4607
4608 offset = addr & (PAGE_SIZE-1);
4609 if (WARN_ON(offset + bytes > PAGE_SIZE))
4610 bytes = (unsigned)PAGE_SIZE - offset;
4611 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4612 offset, bytes);
4613 if (unlikely(ret < 0))
4614 return X86EMUL_IO_NEEDED;
4615
4616 return X86EMUL_CONTINUE;
4617 }
4618
4619 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
4620 gva_t addr, void *val, unsigned int bytes,
4621 struct x86_exception *exception)
4622 {
4623 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4624
4625 /*
4626 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
4627 * is returned, but our callers are not ready for that and they blindly
4628 * call kvm_inject_page_fault. Ensure that they at least do not leak
4629 * uninitialized kernel stack memory into cr2 and error code.
4630 */
4631 memset(exception, 0, sizeof(*exception));
4632 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4633 exception);
4634 }
4635 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4636
4637 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
4638 gva_t addr, void *val, unsigned int bytes,
4639 struct x86_exception *exception, bool system)
4640 {
4641 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4642 u32 access = 0;
4643
4644 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4645 access |= PFERR_USER_MASK;
4646
4647 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
4648 }
4649
4650 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4651 unsigned long addr, void *val, unsigned int bytes)
4652 {
4653 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4654 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4655
4656 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4657 }
4658
4659 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4660 struct kvm_vcpu *vcpu, u32 access,
4661 struct x86_exception *exception)
4662 {
4663 void *data = val;
4664 int r = X86EMUL_CONTINUE;
4665
4666 while (bytes) {
4667 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4668 access,
4669 exception);
4670 unsigned offset = addr & (PAGE_SIZE-1);
4671 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4672 int ret;
4673
4674 if (gpa == UNMAPPED_GVA)
4675 return X86EMUL_PROPAGATE_FAULT;
4676 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4677 if (ret < 0) {
4678 r = X86EMUL_IO_NEEDED;
4679 goto out;
4680 }
4681
4682 bytes -= towrite;
4683 data += towrite;
4684 addr += towrite;
4685 }
4686 out:
4687 return r;
4688 }
4689
4690 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
4691 unsigned int bytes, struct x86_exception *exception,
4692 bool system)
4693 {
4694 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4695 u32 access = PFERR_WRITE_MASK;
4696
4697 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4698 access |= PFERR_USER_MASK;
4699
4700 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4701 access, exception);
4702 }
4703
4704 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
4705 unsigned int bytes, struct x86_exception *exception)
4706 {
4707 /* kvm_write_guest_virt_system can pull in tons of pages. */
4708 vcpu->arch.l1tf_flush_l1d = true;
4709
4710 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4711 PFERR_WRITE_MASK, exception);
4712 }
4713 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4714
4715 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4716 gpa_t gpa, bool write)
4717 {
4718 /* For APIC access vmexit */
4719 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4720 return 1;
4721
4722 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4723 trace_vcpu_match_mmio(gva, gpa, write, true);
4724 return 1;
4725 }
4726
4727 return 0;
4728 }
4729
4730 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4731 gpa_t *gpa, struct x86_exception *exception,
4732 bool write)
4733 {
4734 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4735 | (write ? PFERR_WRITE_MASK : 0);
4736
4737 /*
4738 * currently PKRU is only applied to ept enabled guest so
4739 * there is no pkey in EPT page table for L1 guest or EPT
4740 * shadow page table for L2 guest.
4741 */
4742 if (vcpu_match_mmio_gva(vcpu, gva)
4743 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4744 vcpu->arch.access, 0, access)) {
4745 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4746 (gva & (PAGE_SIZE - 1));
4747 trace_vcpu_match_mmio(gva, *gpa, write, false);
4748 return 1;
4749 }
4750
4751 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4752
4753 if (*gpa == UNMAPPED_GVA)
4754 return -1;
4755
4756 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
4757 }
4758
4759 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4760 const void *val, int bytes)
4761 {
4762 int ret;
4763
4764 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4765 if (ret < 0)
4766 return 0;
4767 kvm_page_track_write(vcpu, gpa, val, bytes);
4768 return 1;
4769 }
4770
4771 struct read_write_emulator_ops {
4772 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4773 int bytes);
4774 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4775 void *val, int bytes);
4776 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4777 int bytes, void *val);
4778 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4779 void *val, int bytes);
4780 bool write;
4781 };
4782
4783 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4784 {
4785 if (vcpu->mmio_read_completed) {
4786 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4787 vcpu->mmio_fragments[0].gpa, val);
4788 vcpu->mmio_read_completed = 0;
4789 return 1;
4790 }
4791
4792 return 0;
4793 }
4794
4795 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4796 void *val, int bytes)
4797 {
4798 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4799 }
4800
4801 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4802 void *val, int bytes)
4803 {
4804 return emulator_write_phys(vcpu, gpa, val, bytes);
4805 }
4806
4807 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4808 {
4809 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
4810 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4811 }
4812
4813 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4814 void *val, int bytes)
4815 {
4816 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
4817 return X86EMUL_IO_NEEDED;
4818 }
4819
4820 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4821 void *val, int bytes)
4822 {
4823 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4824
4825 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4826 return X86EMUL_CONTINUE;
4827 }
4828
4829 static const struct read_write_emulator_ops read_emultor = {
4830 .read_write_prepare = read_prepare,
4831 .read_write_emulate = read_emulate,
4832 .read_write_mmio = vcpu_mmio_read,
4833 .read_write_exit_mmio = read_exit_mmio,
4834 };
4835
4836 static const struct read_write_emulator_ops write_emultor = {
4837 .read_write_emulate = write_emulate,
4838 .read_write_mmio = write_mmio,
4839 .read_write_exit_mmio = write_exit_mmio,
4840 .write = true,
4841 };
4842
4843 static int emulator_read_write_onepage(unsigned long addr, void *val,
4844 unsigned int bytes,
4845 struct x86_exception *exception,
4846 struct kvm_vcpu *vcpu,
4847 const struct read_write_emulator_ops *ops)
4848 {
4849 gpa_t gpa;
4850 int handled, ret;
4851 bool write = ops->write;
4852 struct kvm_mmio_fragment *frag;
4853 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4854
4855 /*
4856 * If the exit was due to a NPF we may already have a GPA.
4857 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4858 * Note, this cannot be used on string operations since string
4859 * operation using rep will only have the initial GPA from the NPF
4860 * occurred.
4861 */
4862 if (vcpu->arch.gpa_available &&
4863 emulator_can_use_gpa(ctxt) &&
4864 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4865 gpa = vcpu->arch.gpa_val;
4866 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4867 } else {
4868 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4869 if (ret < 0)
4870 return X86EMUL_PROPAGATE_FAULT;
4871 }
4872
4873 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
4874 return X86EMUL_CONTINUE;
4875
4876 /*
4877 * Is this MMIO handled locally?
4878 */
4879 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4880 if (handled == bytes)
4881 return X86EMUL_CONTINUE;
4882
4883 gpa += handled;
4884 bytes -= handled;
4885 val += handled;
4886
4887 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4888 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4889 frag->gpa = gpa;
4890 frag->data = val;
4891 frag->len = bytes;
4892 return X86EMUL_CONTINUE;
4893 }
4894
4895 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4896 unsigned long addr,
4897 void *val, unsigned int bytes,
4898 struct x86_exception *exception,
4899 const struct read_write_emulator_ops *ops)
4900 {
4901 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4902 gpa_t gpa;
4903 int rc;
4904
4905 if (ops->read_write_prepare &&
4906 ops->read_write_prepare(vcpu, val, bytes))
4907 return X86EMUL_CONTINUE;
4908
4909 vcpu->mmio_nr_fragments = 0;
4910
4911 /* Crossing a page boundary? */
4912 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4913 int now;
4914
4915 now = -addr & ~PAGE_MASK;
4916 rc = emulator_read_write_onepage(addr, val, now, exception,
4917 vcpu, ops);
4918
4919 if (rc != X86EMUL_CONTINUE)
4920 return rc;
4921 addr += now;
4922 if (ctxt->mode != X86EMUL_MODE_PROT64)
4923 addr = (u32)addr;
4924 val += now;
4925 bytes -= now;
4926 }
4927
4928 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4929 vcpu, ops);
4930 if (rc != X86EMUL_CONTINUE)
4931 return rc;
4932
4933 if (!vcpu->mmio_nr_fragments)
4934 return rc;
4935
4936 gpa = vcpu->mmio_fragments[0].gpa;
4937
4938 vcpu->mmio_needed = 1;
4939 vcpu->mmio_cur_fragment = 0;
4940
4941 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4942 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4943 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4944 vcpu->run->mmio.phys_addr = gpa;
4945
4946 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4947 }
4948
4949 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4950 unsigned long addr,
4951 void *val,
4952 unsigned int bytes,
4953 struct x86_exception *exception)
4954 {
4955 return emulator_read_write(ctxt, addr, val, bytes,
4956 exception, &read_emultor);
4957 }
4958
4959 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4960 unsigned long addr,
4961 const void *val,
4962 unsigned int bytes,
4963 struct x86_exception *exception)
4964 {
4965 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4966 exception, &write_emultor);
4967 }
4968
4969 #define CMPXCHG_TYPE(t, ptr, old, new) \
4970 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4971
4972 #ifdef CONFIG_X86_64
4973 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4974 #else
4975 # define CMPXCHG64(ptr, old, new) \
4976 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4977 #endif
4978
4979 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4980 unsigned long addr,
4981 const void *old,
4982 const void *new,
4983 unsigned int bytes,
4984 struct x86_exception *exception)
4985 {
4986 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4987 gpa_t gpa;
4988 struct page *page;
4989 char *kaddr;
4990 bool exchanged;
4991
4992 /* guests cmpxchg8b have to be emulated atomically */
4993 if (bytes > 8 || (bytes & (bytes - 1)))
4994 goto emul_write;
4995
4996 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4997
4998 if (gpa == UNMAPPED_GVA ||
4999 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5000 goto emul_write;
5001
5002 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5003 goto emul_write;
5004
5005 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
5006 if (is_error_page(page))
5007 goto emul_write;
5008
5009 kaddr = kmap_atomic(page);
5010 kaddr += offset_in_page(gpa);
5011 switch (bytes) {
5012 case 1:
5013 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5014 break;
5015 case 2:
5016 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5017 break;
5018 case 4:
5019 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5020 break;
5021 case 8:
5022 exchanged = CMPXCHG64(kaddr, old, new);
5023 break;
5024 default:
5025 BUG();
5026 }
5027 kunmap_atomic(kaddr);
5028 kvm_release_page_dirty(page);
5029
5030 if (!exchanged)
5031 return X86EMUL_CMPXCHG_FAILED;
5032
5033 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5034 kvm_page_track_write(vcpu, gpa, new, bytes);
5035
5036 return X86EMUL_CONTINUE;
5037
5038 emul_write:
5039 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5040
5041 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5042 }
5043
5044 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5045 {
5046 int r = 0, i;
5047
5048 for (i = 0; i < vcpu->arch.pio.count; i++) {
5049 if (vcpu->arch.pio.in)
5050 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5051 vcpu->arch.pio.size, pd);
5052 else
5053 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5054 vcpu->arch.pio.port, vcpu->arch.pio.size,
5055 pd);
5056 if (r)
5057 break;
5058 pd += vcpu->arch.pio.size;
5059 }
5060 return r;
5061 }
5062
5063 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5064 unsigned short port, void *val,
5065 unsigned int count, bool in)
5066 {
5067 vcpu->arch.pio.port = port;
5068 vcpu->arch.pio.in = in;
5069 vcpu->arch.pio.count = count;
5070 vcpu->arch.pio.size = size;
5071
5072 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5073 vcpu->arch.pio.count = 0;
5074 return 1;
5075 }
5076
5077 vcpu->run->exit_reason = KVM_EXIT_IO;
5078 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5079 vcpu->run->io.size = size;
5080 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5081 vcpu->run->io.count = count;
5082 vcpu->run->io.port = port;
5083
5084 return 0;
5085 }
5086
5087 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5088 int size, unsigned short port, void *val,
5089 unsigned int count)
5090 {
5091 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5092 int ret;
5093
5094 if (vcpu->arch.pio.count)
5095 goto data_avail;
5096
5097 memset(vcpu->arch.pio_data, 0, size * count);
5098
5099 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5100 if (ret) {
5101 data_avail:
5102 memcpy(val, vcpu->arch.pio_data, size * count);
5103 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5104 vcpu->arch.pio.count = 0;
5105 return 1;
5106 }
5107
5108 return 0;
5109 }
5110
5111 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5112 int size, unsigned short port,
5113 const void *val, unsigned int count)
5114 {
5115 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5116
5117 memcpy(vcpu->arch.pio_data, val, size * count);
5118 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5119 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5120 }
5121
5122 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5123 {
5124 return kvm_x86_ops->get_segment_base(vcpu, seg);
5125 }
5126
5127 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5128 {
5129 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5130 }
5131
5132 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5133 {
5134 if (!need_emulate_wbinvd(vcpu))
5135 return X86EMUL_CONTINUE;
5136
5137 if (kvm_x86_ops->has_wbinvd_exit()) {
5138 int cpu = get_cpu();
5139
5140 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5141 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5142 wbinvd_ipi, NULL, 1);
5143 put_cpu();
5144 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5145 } else
5146 wbinvd();
5147 return X86EMUL_CONTINUE;
5148 }
5149
5150 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5151 {
5152 kvm_emulate_wbinvd_noskip(vcpu);
5153 return kvm_skip_emulated_instruction(vcpu);
5154 }
5155 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5156
5157
5158
5159 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5160 {
5161 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5162 }
5163
5164 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5165 unsigned long *dest)
5166 {
5167 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5168 }
5169
5170 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5171 unsigned long value)
5172 {
5173
5174 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5175 }
5176
5177 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5178 {
5179 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5180 }
5181
5182 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5183 {
5184 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5185 unsigned long value;
5186
5187 switch (cr) {
5188 case 0:
5189 value = kvm_read_cr0(vcpu);
5190 break;
5191 case 2:
5192 value = vcpu->arch.cr2;
5193 break;
5194 case 3:
5195 value = kvm_read_cr3(vcpu);
5196 break;
5197 case 4:
5198 value = kvm_read_cr4(vcpu);
5199 break;
5200 case 8:
5201 value = kvm_get_cr8(vcpu);
5202 break;
5203 default:
5204 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5205 return 0;
5206 }
5207
5208 return value;
5209 }
5210
5211 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5212 {
5213 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5214 int res = 0;
5215
5216 switch (cr) {
5217 case 0:
5218 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5219 break;
5220 case 2:
5221 vcpu->arch.cr2 = val;
5222 break;
5223 case 3:
5224 res = kvm_set_cr3(vcpu, val);
5225 break;
5226 case 4:
5227 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5228 break;
5229 case 8:
5230 res = kvm_set_cr8(vcpu, val);
5231 break;
5232 default:
5233 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5234 res = -1;
5235 }
5236
5237 return res;
5238 }
5239
5240 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5241 {
5242 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5243 }
5244
5245 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5246 {
5247 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5248 }
5249
5250 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5251 {
5252 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5253 }
5254
5255 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5256 {
5257 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5258 }
5259
5260 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5261 {
5262 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5263 }
5264
5265 static unsigned long emulator_get_cached_segment_base(
5266 struct x86_emulate_ctxt *ctxt, int seg)
5267 {
5268 return get_segment_base(emul_to_vcpu(ctxt), seg);
5269 }
5270
5271 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5272 struct desc_struct *desc, u32 *base3,
5273 int seg)
5274 {
5275 struct kvm_segment var;
5276
5277 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5278 *selector = var.selector;
5279
5280 if (var.unusable) {
5281 memset(desc, 0, sizeof(*desc));
5282 if (base3)
5283 *base3 = 0;
5284 return false;
5285 }
5286
5287 if (var.g)
5288 var.limit >>= 12;
5289 set_desc_limit(desc, var.limit);
5290 set_desc_base(desc, (unsigned long)var.base);
5291 #ifdef CONFIG_X86_64
5292 if (base3)
5293 *base3 = var.base >> 32;
5294 #endif
5295 desc->type = var.type;
5296 desc->s = var.s;
5297 desc->dpl = var.dpl;
5298 desc->p = var.present;
5299 desc->avl = var.avl;
5300 desc->l = var.l;
5301 desc->d = var.db;
5302 desc->g = var.g;
5303
5304 return true;
5305 }
5306
5307 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5308 struct desc_struct *desc, u32 base3,
5309 int seg)
5310 {
5311 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5312 struct kvm_segment var;
5313
5314 var.selector = selector;
5315 var.base = get_desc_base(desc);
5316 #ifdef CONFIG_X86_64
5317 var.base |= ((u64)base3) << 32;
5318 #endif
5319 var.limit = get_desc_limit(desc);
5320 if (desc->g)
5321 var.limit = (var.limit << 12) | 0xfff;
5322 var.type = desc->type;
5323 var.dpl = desc->dpl;
5324 var.db = desc->d;
5325 var.s = desc->s;
5326 var.l = desc->l;
5327 var.g = desc->g;
5328 var.avl = desc->avl;
5329 var.present = desc->p;
5330 var.unusable = !var.present;
5331 var.padding = 0;
5332
5333 kvm_set_segment(vcpu, &var, seg);
5334 return;
5335 }
5336
5337 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5338 u32 msr_index, u64 *pdata)
5339 {
5340 struct msr_data msr;
5341 int r;
5342
5343 msr.index = msr_index;
5344 msr.host_initiated = false;
5345 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5346 if (r)
5347 return r;
5348
5349 *pdata = msr.data;
5350 return 0;
5351 }
5352
5353 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5354 u32 msr_index, u64 data)
5355 {
5356 struct msr_data msr;
5357
5358 msr.data = data;
5359 msr.index = msr_index;
5360 msr.host_initiated = false;
5361 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5362 }
5363
5364 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5365 {
5366 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5367
5368 return vcpu->arch.smbase;
5369 }
5370
5371 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5372 {
5373 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5374
5375 vcpu->arch.smbase = smbase;
5376 }
5377
5378 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5379 u32 pmc)
5380 {
5381 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5382 }
5383
5384 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5385 u32 pmc, u64 *pdata)
5386 {
5387 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5388 }
5389
5390 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5391 {
5392 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5393 }
5394
5395 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5396 {
5397 }
5398
5399 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5400 {
5401 }
5402
5403 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5404 struct x86_instruction_info *info,
5405 enum x86_intercept_stage stage)
5406 {
5407 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5408 }
5409
5410 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5411 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
5412 {
5413 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
5414 }
5415
5416 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5417 {
5418 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5419 }
5420
5421 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5422 {
5423 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5424 }
5425
5426 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5427 {
5428 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5429 }
5430
5431 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5432 {
5433 return emul_to_vcpu(ctxt)->arch.hflags;
5434 }
5435
5436 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5437 {
5438 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5439 }
5440
5441 static const struct x86_emulate_ops emulate_ops = {
5442 .read_gpr = emulator_read_gpr,
5443 .write_gpr = emulator_write_gpr,
5444 .read_std = emulator_read_std,
5445 .write_std = emulator_write_std,
5446 .read_phys = kvm_read_guest_phys_system,
5447 .fetch = kvm_fetch_guest_virt,
5448 .read_emulated = emulator_read_emulated,
5449 .write_emulated = emulator_write_emulated,
5450 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5451 .invlpg = emulator_invlpg,
5452 .pio_in_emulated = emulator_pio_in_emulated,
5453 .pio_out_emulated = emulator_pio_out_emulated,
5454 .get_segment = emulator_get_segment,
5455 .set_segment = emulator_set_segment,
5456 .get_cached_segment_base = emulator_get_cached_segment_base,
5457 .get_gdt = emulator_get_gdt,
5458 .get_idt = emulator_get_idt,
5459 .set_gdt = emulator_set_gdt,
5460 .set_idt = emulator_set_idt,
5461 .get_cr = emulator_get_cr,
5462 .set_cr = emulator_set_cr,
5463 .cpl = emulator_get_cpl,
5464 .get_dr = emulator_get_dr,
5465 .set_dr = emulator_set_dr,
5466 .get_smbase = emulator_get_smbase,
5467 .set_smbase = emulator_set_smbase,
5468 .set_msr = emulator_set_msr,
5469 .get_msr = emulator_get_msr,
5470 .check_pmc = emulator_check_pmc,
5471 .read_pmc = emulator_read_pmc,
5472 .halt = emulator_halt,
5473 .wbinvd = emulator_wbinvd,
5474 .fix_hypercall = emulator_fix_hypercall,
5475 .get_fpu = emulator_get_fpu,
5476 .put_fpu = emulator_put_fpu,
5477 .intercept = emulator_intercept,
5478 .get_cpuid = emulator_get_cpuid,
5479 .set_nmi_mask = emulator_set_nmi_mask,
5480 .get_hflags = emulator_get_hflags,
5481 .set_hflags = emulator_set_hflags,
5482 };
5483
5484 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5485 {
5486 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5487 /*
5488 * an sti; sti; sequence only disable interrupts for the first
5489 * instruction. So, if the last instruction, be it emulated or
5490 * not, left the system with the INT_STI flag enabled, it
5491 * means that the last instruction is an sti. We should not
5492 * leave the flag on in this case. The same goes for mov ss
5493 */
5494 if (int_shadow & mask)
5495 mask = 0;
5496 if (unlikely(int_shadow || mask)) {
5497 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5498 if (!mask)
5499 kvm_make_request(KVM_REQ_EVENT, vcpu);
5500 }
5501 }
5502
5503 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5504 {
5505 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5506 if (ctxt->exception.vector == PF_VECTOR)
5507 return kvm_propagate_fault(vcpu, &ctxt->exception);
5508
5509 if (ctxt->exception.error_code_valid)
5510 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5511 ctxt->exception.error_code);
5512 else
5513 kvm_queue_exception(vcpu, ctxt->exception.vector);
5514 return false;
5515 }
5516
5517 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5518 {
5519 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5520 int cs_db, cs_l;
5521
5522 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5523
5524 ctxt->eflags = kvm_get_rflags(vcpu);
5525 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5526
5527 ctxt->eip = kvm_rip_read(vcpu);
5528 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5529 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5530 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5531 cs_db ? X86EMUL_MODE_PROT32 :
5532 X86EMUL_MODE_PROT16;
5533 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5534 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5535 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5536
5537 init_decode_cache(ctxt);
5538 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5539 }
5540
5541 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5542 {
5543 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5544 int ret;
5545
5546 init_emulate_ctxt(vcpu);
5547
5548 ctxt->op_bytes = 2;
5549 ctxt->ad_bytes = 2;
5550 ctxt->_eip = ctxt->eip + inc_eip;
5551 ret = emulate_int_real(ctxt, irq);
5552
5553 if (ret != X86EMUL_CONTINUE)
5554 return EMULATE_FAIL;
5555
5556 ctxt->eip = ctxt->_eip;
5557 kvm_rip_write(vcpu, ctxt->eip);
5558 kvm_set_rflags(vcpu, ctxt->eflags);
5559
5560 if (irq == NMI_VECTOR)
5561 vcpu->arch.nmi_pending = 0;
5562 else
5563 vcpu->arch.interrupt.pending = false;
5564
5565 return EMULATE_DONE;
5566 }
5567 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5568
5569 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5570 {
5571 int r = EMULATE_DONE;
5572
5573 ++vcpu->stat.insn_emulation_fail;
5574 trace_kvm_emulate_insn_failed(vcpu);
5575 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5576 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5577 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5578 vcpu->run->internal.ndata = 0;
5579 r = EMULATE_USER_EXIT;
5580 }
5581 kvm_queue_exception(vcpu, UD_VECTOR);
5582
5583 return r;
5584 }
5585
5586 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5587 bool write_fault_to_shadow_pgtable,
5588 int emulation_type)
5589 {
5590 gpa_t gpa = cr2;
5591 kvm_pfn_t pfn;
5592
5593 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5594 return false;
5595
5596 if (!vcpu->arch.mmu.direct_map) {
5597 /*
5598 * Write permission should be allowed since only
5599 * write access need to be emulated.
5600 */
5601 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5602
5603 /*
5604 * If the mapping is invalid in guest, let cpu retry
5605 * it to generate fault.
5606 */
5607 if (gpa == UNMAPPED_GVA)
5608 return true;
5609 }
5610
5611 /*
5612 * Do not retry the unhandleable instruction if it faults on the
5613 * readonly host memory, otherwise it will goto a infinite loop:
5614 * retry instruction -> write #PF -> emulation fail -> retry
5615 * instruction -> ...
5616 */
5617 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5618
5619 /*
5620 * If the instruction failed on the error pfn, it can not be fixed,
5621 * report the error to userspace.
5622 */
5623 if (is_error_noslot_pfn(pfn))
5624 return false;
5625
5626 kvm_release_pfn_clean(pfn);
5627
5628 /* The instructions are well-emulated on direct mmu. */
5629 if (vcpu->arch.mmu.direct_map) {
5630 unsigned int indirect_shadow_pages;
5631
5632 spin_lock(&vcpu->kvm->mmu_lock);
5633 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5634 spin_unlock(&vcpu->kvm->mmu_lock);
5635
5636 if (indirect_shadow_pages)
5637 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5638
5639 return true;
5640 }
5641
5642 /*
5643 * if emulation was due to access to shadowed page table
5644 * and it failed try to unshadow page and re-enter the
5645 * guest to let CPU execute the instruction.
5646 */
5647 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5648
5649 /*
5650 * If the access faults on its page table, it can not
5651 * be fixed by unprotecting shadow page and it should
5652 * be reported to userspace.
5653 */
5654 return !write_fault_to_shadow_pgtable;
5655 }
5656
5657 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5658 unsigned long cr2, int emulation_type)
5659 {
5660 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5661 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5662
5663 last_retry_eip = vcpu->arch.last_retry_eip;
5664 last_retry_addr = vcpu->arch.last_retry_addr;
5665
5666 /*
5667 * If the emulation is caused by #PF and it is non-page_table
5668 * writing instruction, it means the VM-EXIT is caused by shadow
5669 * page protected, we can zap the shadow page and retry this
5670 * instruction directly.
5671 *
5672 * Note: if the guest uses a non-page-table modifying instruction
5673 * on the PDE that points to the instruction, then we will unmap
5674 * the instruction and go to an infinite loop. So, we cache the
5675 * last retried eip and the last fault address, if we meet the eip
5676 * and the address again, we can break out of the potential infinite
5677 * loop.
5678 */
5679 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5680
5681 if (!(emulation_type & EMULTYPE_RETRY))
5682 return false;
5683
5684 if (x86_page_table_writing_insn(ctxt))
5685 return false;
5686
5687 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5688 return false;
5689
5690 vcpu->arch.last_retry_eip = ctxt->eip;
5691 vcpu->arch.last_retry_addr = cr2;
5692
5693 if (!vcpu->arch.mmu.direct_map)
5694 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5695
5696 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5697
5698 return true;
5699 }
5700
5701 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5702 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5703
5704 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5705 {
5706 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5707 /* This is a good place to trace that we are exiting SMM. */
5708 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5709
5710 /* Process a latched INIT or SMI, if any. */
5711 kvm_make_request(KVM_REQ_EVENT, vcpu);
5712 }
5713
5714 kvm_mmu_reset_context(vcpu);
5715 }
5716
5717 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5718 {
5719 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5720
5721 vcpu->arch.hflags = emul_flags;
5722
5723 if (changed & HF_SMM_MASK)
5724 kvm_smm_changed(vcpu);
5725 }
5726
5727 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5728 unsigned long *db)
5729 {
5730 u32 dr6 = 0;
5731 int i;
5732 u32 enable, rwlen;
5733
5734 enable = dr7;
5735 rwlen = dr7 >> 16;
5736 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5737 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5738 dr6 |= (1 << i);
5739 return dr6;
5740 }
5741
5742 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
5743 {
5744 struct kvm_run *kvm_run = vcpu->run;
5745
5746 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5747 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5748 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5749 kvm_run->debug.arch.exception = DB_VECTOR;
5750 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5751 *r = EMULATE_USER_EXIT;
5752 } else {
5753 /*
5754 * "Certain debug exceptions may clear bit 0-3. The
5755 * remaining contents of the DR6 register are never
5756 * cleared by the processor".
5757 */
5758 vcpu->arch.dr6 &= ~15;
5759 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5760 kvm_queue_exception(vcpu, DB_VECTOR);
5761 }
5762 }
5763
5764 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5765 {
5766 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5767 int r = EMULATE_DONE;
5768
5769 kvm_x86_ops->skip_emulated_instruction(vcpu);
5770
5771 /*
5772 * rflags is the old, "raw" value of the flags. The new value has
5773 * not been saved yet.
5774 *
5775 * This is correct even for TF set by the guest, because "the
5776 * processor will not generate this exception after the instruction
5777 * that sets the TF flag".
5778 */
5779 if (unlikely(rflags & X86_EFLAGS_TF))
5780 kvm_vcpu_do_singlestep(vcpu, &r);
5781 return r == EMULATE_DONE;
5782 }
5783 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5784
5785 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5786 {
5787 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5788 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5789 struct kvm_run *kvm_run = vcpu->run;
5790 unsigned long eip = kvm_get_linear_rip(vcpu);
5791 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5792 vcpu->arch.guest_debug_dr7,
5793 vcpu->arch.eff_db);
5794
5795 if (dr6 != 0) {
5796 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5797 kvm_run->debug.arch.pc = eip;
5798 kvm_run->debug.arch.exception = DB_VECTOR;
5799 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5800 *r = EMULATE_USER_EXIT;
5801 return true;
5802 }
5803 }
5804
5805 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5806 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5807 unsigned long eip = kvm_get_linear_rip(vcpu);
5808 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5809 vcpu->arch.dr7,
5810 vcpu->arch.db);
5811
5812 if (dr6 != 0) {
5813 vcpu->arch.dr6 &= ~15;
5814 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5815 kvm_queue_exception(vcpu, DB_VECTOR);
5816 *r = EMULATE_DONE;
5817 return true;
5818 }
5819 }
5820
5821 return false;
5822 }
5823
5824 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5825 unsigned long cr2,
5826 int emulation_type,
5827 void *insn,
5828 int insn_len)
5829 {
5830 int r;
5831 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5832 bool writeback = true;
5833 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5834
5835 vcpu->arch.l1tf_flush_l1d = true;
5836
5837 /*
5838 * Clear write_fault_to_shadow_pgtable here to ensure it is
5839 * never reused.
5840 */
5841 vcpu->arch.write_fault_to_shadow_pgtable = false;
5842 kvm_clear_exception_queue(vcpu);
5843
5844 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5845 init_emulate_ctxt(vcpu);
5846
5847 /*
5848 * We will reenter on the same instruction since
5849 * we do not set complete_userspace_io. This does not
5850 * handle watchpoints yet, those would be handled in
5851 * the emulate_ops.
5852 */
5853 if (!(emulation_type & EMULTYPE_SKIP) &&
5854 kvm_vcpu_check_breakpoint(vcpu, &r))
5855 return r;
5856
5857 ctxt->interruptibility = 0;
5858 ctxt->have_exception = false;
5859 ctxt->exception.vector = -1;
5860 ctxt->perm_ok = false;
5861
5862 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5863
5864 r = x86_decode_insn(ctxt, insn, insn_len);
5865
5866 trace_kvm_emulate_insn_start(vcpu);
5867 ++vcpu->stat.insn_emulation;
5868 if (r != EMULATION_OK) {
5869 if (emulation_type & EMULTYPE_TRAP_UD)
5870 return EMULATE_FAIL;
5871 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5872 emulation_type))
5873 return EMULATE_DONE;
5874 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5875 return EMULATE_DONE;
5876 if (emulation_type & EMULTYPE_SKIP)
5877 return EMULATE_FAIL;
5878 return handle_emulation_failure(vcpu);
5879 }
5880 }
5881
5882 if (emulation_type & EMULTYPE_SKIP) {
5883 kvm_rip_write(vcpu, ctxt->_eip);
5884 if (ctxt->eflags & X86_EFLAGS_RF)
5885 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5886 return EMULATE_DONE;
5887 }
5888
5889 if (retry_instruction(ctxt, cr2, emulation_type))
5890 return EMULATE_DONE;
5891
5892 /* this is needed for vmware backdoor interface to work since it
5893 changes registers values during IO operation */
5894 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5895 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5896 emulator_invalidate_register_cache(ctxt);
5897 }
5898
5899 restart:
5900 /* Save the faulting GPA (cr2) in the address field */
5901 ctxt->exception.address = cr2;
5902
5903 r = x86_emulate_insn(ctxt);
5904
5905 if (r == EMULATION_INTERCEPTED)
5906 return EMULATE_DONE;
5907
5908 if (r == EMULATION_FAILED) {
5909 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5910 emulation_type))
5911 return EMULATE_DONE;
5912
5913 return handle_emulation_failure(vcpu);
5914 }
5915
5916 if (ctxt->have_exception) {
5917 r = EMULATE_DONE;
5918 if (inject_emulated_exception(vcpu))
5919 return r;
5920 } else if (vcpu->arch.pio.count) {
5921 if (!vcpu->arch.pio.in) {
5922 /* FIXME: return into emulator if single-stepping. */
5923 vcpu->arch.pio.count = 0;
5924 } else {
5925 writeback = false;
5926 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5927 }
5928 r = EMULATE_USER_EXIT;
5929 } else if (vcpu->mmio_needed) {
5930 if (!vcpu->mmio_is_write)
5931 writeback = false;
5932 r = EMULATE_USER_EXIT;
5933 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5934 } else if (r == EMULATION_RESTART)
5935 goto restart;
5936 else
5937 r = EMULATE_DONE;
5938
5939 if (writeback) {
5940 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5941 toggle_interruptibility(vcpu, ctxt->interruptibility);
5942 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5943 kvm_rip_write(vcpu, ctxt->eip);
5944 if (r == EMULATE_DONE && ctxt->tf)
5945 kvm_vcpu_do_singlestep(vcpu, &r);
5946 if (!ctxt->have_exception ||
5947 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5948 __kvm_set_rflags(vcpu, ctxt->eflags);
5949
5950 /*
5951 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5952 * do nothing, and it will be requested again as soon as
5953 * the shadow expires. But we still need to check here,
5954 * because POPF has no interrupt shadow.
5955 */
5956 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5957 kvm_make_request(KVM_REQ_EVENT, vcpu);
5958 } else
5959 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5960
5961 return r;
5962 }
5963 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5964
5965 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5966 {
5967 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5968 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5969 size, port, &val, 1);
5970 /* do not return to emulator after return from userspace */
5971 vcpu->arch.pio.count = 0;
5972 return ret;
5973 }
5974 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5975
5976 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5977 {
5978 unsigned long val;
5979
5980 /* We should only ever be called with arch.pio.count equal to 1 */
5981 BUG_ON(vcpu->arch.pio.count != 1);
5982
5983 /* For size less than 4 we merge, else we zero extend */
5984 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5985 : 0;
5986
5987 /*
5988 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5989 * the copy and tracing
5990 */
5991 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5992 vcpu->arch.pio.port, &val, 1);
5993 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5994
5995 return 1;
5996 }
5997
5998 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5999 {
6000 unsigned long val;
6001 int ret;
6002
6003 /* For size less than 4 we merge, else we zero extend */
6004 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6005
6006 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6007 &val, 1);
6008 if (ret) {
6009 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6010 return ret;
6011 }
6012
6013 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6014
6015 return 0;
6016 }
6017 EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
6018
6019 static int kvmclock_cpu_down_prep(unsigned int cpu)
6020 {
6021 __this_cpu_write(cpu_tsc_khz, 0);
6022 return 0;
6023 }
6024
6025 static void tsc_khz_changed(void *data)
6026 {
6027 struct cpufreq_freqs *freq = data;
6028 unsigned long khz = 0;
6029
6030 if (data)
6031 khz = freq->new;
6032 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6033 khz = cpufreq_quick_get(raw_smp_processor_id());
6034 if (!khz)
6035 khz = tsc_khz;
6036 __this_cpu_write(cpu_tsc_khz, khz);
6037 }
6038
6039 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6040 void *data)
6041 {
6042 struct cpufreq_freqs *freq = data;
6043 struct kvm *kvm;
6044 struct kvm_vcpu *vcpu;
6045 int i, send_ipi = 0;
6046
6047 /*
6048 * We allow guests to temporarily run on slowing clocks,
6049 * provided we notify them after, or to run on accelerating
6050 * clocks, provided we notify them before. Thus time never
6051 * goes backwards.
6052 *
6053 * However, we have a problem. We can't atomically update
6054 * the frequency of a given CPU from this function; it is
6055 * merely a notifier, which can be called from any CPU.
6056 * Changing the TSC frequency at arbitrary points in time
6057 * requires a recomputation of local variables related to
6058 * the TSC for each VCPU. We must flag these local variables
6059 * to be updated and be sure the update takes place with the
6060 * new frequency before any guests proceed.
6061 *
6062 * Unfortunately, the combination of hotplug CPU and frequency
6063 * change creates an intractable locking scenario; the order
6064 * of when these callouts happen is undefined with respect to
6065 * CPU hotplug, and they can race with each other. As such,
6066 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6067 * undefined; you can actually have a CPU frequency change take
6068 * place in between the computation of X and the setting of the
6069 * variable. To protect against this problem, all updates of
6070 * the per_cpu tsc_khz variable are done in an interrupt
6071 * protected IPI, and all callers wishing to update the value
6072 * must wait for a synchronous IPI to complete (which is trivial
6073 * if the caller is on the CPU already). This establishes the
6074 * necessary total order on variable updates.
6075 *
6076 * Note that because a guest time update may take place
6077 * anytime after the setting of the VCPU's request bit, the
6078 * correct TSC value must be set before the request. However,
6079 * to ensure the update actually makes it to any guest which
6080 * starts running in hardware virtualization between the set
6081 * and the acquisition of the spinlock, we must also ping the
6082 * CPU after setting the request bit.
6083 *
6084 */
6085
6086 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6087 return 0;
6088 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6089 return 0;
6090
6091 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6092
6093 spin_lock(&kvm_lock);
6094 list_for_each_entry(kvm, &vm_list, vm_list) {
6095 kvm_for_each_vcpu(i, vcpu, kvm) {
6096 if (vcpu->cpu != freq->cpu)
6097 continue;
6098 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6099 if (vcpu->cpu != smp_processor_id())
6100 send_ipi = 1;
6101 }
6102 }
6103 spin_unlock(&kvm_lock);
6104
6105 if (freq->old < freq->new && send_ipi) {
6106 /*
6107 * We upscale the frequency. Must make the guest
6108 * doesn't see old kvmclock values while running with
6109 * the new frequency, otherwise we risk the guest sees
6110 * time go backwards.
6111 *
6112 * In case we update the frequency for another cpu
6113 * (which might be in guest context) send an interrupt
6114 * to kick the cpu out of guest context. Next time
6115 * guest context is entered kvmclock will be updated,
6116 * so the guest will not see stale values.
6117 */
6118 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6119 }
6120 return 0;
6121 }
6122
6123 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6124 .notifier_call = kvmclock_cpufreq_notifier
6125 };
6126
6127 static int kvmclock_cpu_online(unsigned int cpu)
6128 {
6129 tsc_khz_changed(NULL);
6130 return 0;
6131 }
6132
6133 static void kvm_timer_init(void)
6134 {
6135 max_tsc_khz = tsc_khz;
6136
6137 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6138 #ifdef CONFIG_CPU_FREQ
6139 struct cpufreq_policy policy;
6140 int cpu;
6141
6142 memset(&policy, 0, sizeof(policy));
6143 cpu = get_cpu();
6144 cpufreq_get_policy(&policy, cpu);
6145 if (policy.cpuinfo.max_freq)
6146 max_tsc_khz = policy.cpuinfo.max_freq;
6147 put_cpu();
6148 #endif
6149 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6150 CPUFREQ_TRANSITION_NOTIFIER);
6151 }
6152 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
6153
6154 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6155 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6156 }
6157
6158 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6159
6160 int kvm_is_in_guest(void)
6161 {
6162 return __this_cpu_read(current_vcpu) != NULL;
6163 }
6164
6165 static int kvm_is_user_mode(void)
6166 {
6167 int user_mode = 3;
6168
6169 if (__this_cpu_read(current_vcpu))
6170 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6171
6172 return user_mode != 0;
6173 }
6174
6175 static unsigned long kvm_get_guest_ip(void)
6176 {
6177 unsigned long ip = 0;
6178
6179 if (__this_cpu_read(current_vcpu))
6180 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6181
6182 return ip;
6183 }
6184
6185 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6186 .is_in_guest = kvm_is_in_guest,
6187 .is_user_mode = kvm_is_user_mode,
6188 .get_guest_ip = kvm_get_guest_ip,
6189 };
6190
6191 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6192 {
6193 __this_cpu_write(current_vcpu, vcpu);
6194 }
6195 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6196
6197 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6198 {
6199 __this_cpu_write(current_vcpu, NULL);
6200 }
6201 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6202
6203 static void kvm_set_mmio_spte_mask(void)
6204 {
6205 u64 mask;
6206 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6207
6208 /*
6209 * Set the reserved bits and the present bit of an paging-structure
6210 * entry to generate page fault with PFER.RSV = 1.
6211 */
6212
6213 /*
6214 * Mask the uppermost physical address bit, which would be reserved as
6215 * long as the supported physical address width is less than 52.
6216 */
6217 mask = 1ull << 51;
6218
6219 /* Set the present bit. */
6220 mask |= 1ull;
6221
6222 /*
6223 * If reserved bit is not supported, clear the present bit to disable
6224 * mmio page fault.
6225 */
6226 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
6227 mask &= ~1ull;
6228
6229 kvm_mmu_set_mmio_spte_mask(mask, mask);
6230 }
6231
6232 #ifdef CONFIG_X86_64
6233 static void pvclock_gtod_update_fn(struct work_struct *work)
6234 {
6235 struct kvm *kvm;
6236
6237 struct kvm_vcpu *vcpu;
6238 int i;
6239
6240 spin_lock(&kvm_lock);
6241 list_for_each_entry(kvm, &vm_list, vm_list)
6242 kvm_for_each_vcpu(i, vcpu, kvm)
6243 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6244 atomic_set(&kvm_guest_has_master_clock, 0);
6245 spin_unlock(&kvm_lock);
6246 }
6247
6248 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6249
6250 /*
6251 * Notification about pvclock gtod data update.
6252 */
6253 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6254 void *priv)
6255 {
6256 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6257 struct timekeeper *tk = priv;
6258
6259 update_pvclock_gtod(tk);
6260
6261 /* disable master clock if host does not trust, or does not
6262 * use, TSC clocksource
6263 */
6264 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6265 atomic_read(&kvm_guest_has_master_clock) != 0)
6266 queue_work(system_long_wq, &pvclock_gtod_work);
6267
6268 return 0;
6269 }
6270
6271 static struct notifier_block pvclock_gtod_notifier = {
6272 .notifier_call = pvclock_gtod_notify,
6273 };
6274 #endif
6275
6276 int kvm_arch_init(void *opaque)
6277 {
6278 int r;
6279 struct kvm_x86_ops *ops = opaque;
6280
6281 if (kvm_x86_ops) {
6282 printk(KERN_ERR "kvm: already loaded the other module\n");
6283 r = -EEXIST;
6284 goto out;
6285 }
6286
6287 if (!ops->cpu_has_kvm_support()) {
6288 printk(KERN_ERR "kvm: no hardware support\n");
6289 r = -EOPNOTSUPP;
6290 goto out;
6291 }
6292 if (ops->disabled_by_bios()) {
6293 printk(KERN_ERR "kvm: disabled by bios\n");
6294 r = -EOPNOTSUPP;
6295 goto out;
6296 }
6297
6298 r = -ENOMEM;
6299 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6300 if (!shared_msrs) {
6301 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6302 goto out;
6303 }
6304
6305 r = kvm_mmu_module_init();
6306 if (r)
6307 goto out_free_percpu;
6308
6309 kvm_set_mmio_spte_mask();
6310
6311 kvm_x86_ops = ops;
6312
6313 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6314 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6315 PT_PRESENT_MASK, 0, sme_me_mask);
6316 kvm_timer_init();
6317
6318 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6319
6320 if (boot_cpu_has(X86_FEATURE_XSAVE))
6321 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6322
6323 kvm_lapic_init();
6324 #ifdef CONFIG_X86_64
6325 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6326 #endif
6327
6328 return 0;
6329
6330 out_free_percpu:
6331 free_percpu(shared_msrs);
6332 out:
6333 return r;
6334 }
6335
6336 void kvm_arch_exit(void)
6337 {
6338 kvm_lapic_exit();
6339 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6340
6341 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6342 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6343 CPUFREQ_TRANSITION_NOTIFIER);
6344 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6345 #ifdef CONFIG_X86_64
6346 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6347 #endif
6348 kvm_x86_ops = NULL;
6349 kvm_mmu_module_exit();
6350 free_percpu(shared_msrs);
6351 }
6352
6353 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6354 {
6355 ++vcpu->stat.halt_exits;
6356 if (lapic_in_kernel(vcpu)) {
6357 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6358 return 1;
6359 } else {
6360 vcpu->run->exit_reason = KVM_EXIT_HLT;
6361 return 0;
6362 }
6363 }
6364 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6365
6366 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6367 {
6368 int ret = kvm_skip_emulated_instruction(vcpu);
6369 /*
6370 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6371 * KVM_EXIT_DEBUG here.
6372 */
6373 return kvm_vcpu_halt(vcpu) && ret;
6374 }
6375 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6376
6377 #ifdef CONFIG_X86_64
6378 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6379 unsigned long clock_type)
6380 {
6381 struct kvm_clock_pairing clock_pairing;
6382 struct timespec ts;
6383 u64 cycle;
6384 int ret;
6385
6386 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6387 return -KVM_EOPNOTSUPP;
6388
6389 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6390 return -KVM_EOPNOTSUPP;
6391
6392 clock_pairing.sec = ts.tv_sec;
6393 clock_pairing.nsec = ts.tv_nsec;
6394 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6395 clock_pairing.flags = 0;
6396 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
6397
6398 ret = 0;
6399 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6400 sizeof(struct kvm_clock_pairing)))
6401 ret = -KVM_EFAULT;
6402
6403 return ret;
6404 }
6405 #endif
6406
6407 /*
6408 * kvm_pv_kick_cpu_op: Kick a vcpu.
6409 *
6410 * @apicid - apicid of vcpu to be kicked.
6411 */
6412 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6413 {
6414 struct kvm_lapic_irq lapic_irq;
6415
6416 lapic_irq.shorthand = 0;
6417 lapic_irq.dest_mode = 0;
6418 lapic_irq.level = 0;
6419 lapic_irq.dest_id = apicid;
6420 lapic_irq.msi_redir_hint = false;
6421
6422 lapic_irq.delivery_mode = APIC_DM_REMRD;
6423 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6424 }
6425
6426 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6427 {
6428 vcpu->arch.apicv_active = false;
6429 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6430 }
6431
6432 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6433 {
6434 unsigned long nr, a0, a1, a2, a3, ret;
6435 int op_64_bit;
6436
6437 if (kvm_hv_hypercall_enabled(vcpu->kvm)) {
6438 if (!kvm_hv_hypercall(vcpu))
6439 return 0;
6440 goto out;
6441 }
6442
6443 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6444 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6445 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6446 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6447 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6448
6449 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6450
6451 op_64_bit = is_64_bit_mode(vcpu);
6452 if (!op_64_bit) {
6453 nr &= 0xFFFFFFFF;
6454 a0 &= 0xFFFFFFFF;
6455 a1 &= 0xFFFFFFFF;
6456 a2 &= 0xFFFFFFFF;
6457 a3 &= 0xFFFFFFFF;
6458 }
6459
6460 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6461 ret = -KVM_EPERM;
6462 goto out_error;
6463 }
6464
6465 switch (nr) {
6466 case KVM_HC_VAPIC_POLL_IRQ:
6467 ret = 0;
6468 break;
6469 case KVM_HC_KICK_CPU:
6470 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6471 ret = 0;
6472 break;
6473 #ifdef CONFIG_X86_64
6474 case KVM_HC_CLOCK_PAIRING:
6475 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6476 break;
6477 #endif
6478 default:
6479 ret = -KVM_ENOSYS;
6480 break;
6481 }
6482 out_error:
6483 if (!op_64_bit)
6484 ret = (u32)ret;
6485 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6486
6487 out:
6488 ++vcpu->stat.hypercalls;
6489 return kvm_skip_emulated_instruction(vcpu);
6490 }
6491 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6492
6493 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6494 {
6495 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6496 char instruction[3];
6497 unsigned long rip = kvm_rip_read(vcpu);
6498
6499 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6500
6501 return emulator_write_emulated(ctxt, rip, instruction, 3,
6502 &ctxt->exception);
6503 }
6504
6505 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6506 {
6507 return vcpu->run->request_interrupt_window &&
6508 likely(!pic_in_kernel(vcpu->kvm));
6509 }
6510
6511 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6512 {
6513 struct kvm_run *kvm_run = vcpu->run;
6514
6515 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6516 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6517 kvm_run->cr8 = kvm_get_cr8(vcpu);
6518 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6519 kvm_run->ready_for_interrupt_injection =
6520 pic_in_kernel(vcpu->kvm) ||
6521 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6522 }
6523
6524 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6525 {
6526 int max_irr, tpr;
6527
6528 if (!kvm_x86_ops->update_cr8_intercept)
6529 return;
6530
6531 if (!lapic_in_kernel(vcpu))
6532 return;
6533
6534 if (vcpu->arch.apicv_active)
6535 return;
6536
6537 if (!vcpu->arch.apic->vapic_addr)
6538 max_irr = kvm_lapic_find_highest_irr(vcpu);
6539 else
6540 max_irr = -1;
6541
6542 if (max_irr != -1)
6543 max_irr >>= 4;
6544
6545 tpr = kvm_lapic_get_cr8(vcpu);
6546
6547 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6548 }
6549
6550 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6551 {
6552 int r;
6553
6554 /* try to reinject previous events if any */
6555 if (vcpu->arch.exception.injected) {
6556 kvm_x86_ops->queue_exception(vcpu);
6557 return 0;
6558 }
6559
6560 /*
6561 * Exceptions must be injected immediately, or the exception
6562 * frame will have the address of the NMI or interrupt handler.
6563 */
6564 if (!vcpu->arch.exception.pending) {
6565 if (vcpu->arch.nmi_injected) {
6566 kvm_x86_ops->set_nmi(vcpu);
6567 return 0;
6568 }
6569
6570 if (vcpu->arch.interrupt.pending) {
6571 kvm_x86_ops->set_irq(vcpu);
6572 return 0;
6573 }
6574 }
6575
6576 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6577 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6578 if (r != 0)
6579 return r;
6580 }
6581
6582 /* try to inject new event if pending */
6583 if (vcpu->arch.exception.pending) {
6584 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6585 vcpu->arch.exception.has_error_code,
6586 vcpu->arch.exception.error_code);
6587
6588 vcpu->arch.exception.pending = false;
6589 vcpu->arch.exception.injected = true;
6590
6591 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6592 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6593 X86_EFLAGS_RF);
6594
6595 if (vcpu->arch.exception.nr == DB_VECTOR &&
6596 (vcpu->arch.dr7 & DR7_GD)) {
6597 vcpu->arch.dr7 &= ~DR7_GD;
6598 kvm_update_dr7(vcpu);
6599 }
6600
6601 kvm_x86_ops->queue_exception(vcpu);
6602 } else if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6603 vcpu->arch.smi_pending = false;
6604 enter_smm(vcpu);
6605 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6606 --vcpu->arch.nmi_pending;
6607 vcpu->arch.nmi_injected = true;
6608 kvm_x86_ops->set_nmi(vcpu);
6609 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6610 /*
6611 * Because interrupts can be injected asynchronously, we are
6612 * calling check_nested_events again here to avoid a race condition.
6613 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6614 * proposal and current concerns. Perhaps we should be setting
6615 * KVM_REQ_EVENT only on certain events and not unconditionally?
6616 */
6617 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6618 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6619 if (r != 0)
6620 return r;
6621 }
6622 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6623 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6624 false);
6625 kvm_x86_ops->set_irq(vcpu);
6626 }
6627 }
6628
6629 return 0;
6630 }
6631
6632 static void process_nmi(struct kvm_vcpu *vcpu)
6633 {
6634 unsigned limit = 2;
6635
6636 /*
6637 * x86 is limited to one NMI running, and one NMI pending after it.
6638 * If an NMI is already in progress, limit further NMIs to just one.
6639 * Otherwise, allow two (and we'll inject the first one immediately).
6640 */
6641 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6642 limit = 1;
6643
6644 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6645 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6646 kvm_make_request(KVM_REQ_EVENT, vcpu);
6647 }
6648
6649 #define put_smstate(type, buf, offset, val) \
6650 *(type *)((buf) + (offset) - 0x7e00) = val
6651
6652 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6653 {
6654 u32 flags = 0;
6655 flags |= seg->g << 23;
6656 flags |= seg->db << 22;
6657 flags |= seg->l << 21;
6658 flags |= seg->avl << 20;
6659 flags |= seg->present << 15;
6660 flags |= seg->dpl << 13;
6661 flags |= seg->s << 12;
6662 flags |= seg->type << 8;
6663 return flags;
6664 }
6665
6666 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6667 {
6668 struct kvm_segment seg;
6669 int offset;
6670
6671 kvm_get_segment(vcpu, &seg, n);
6672 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6673
6674 if (n < 3)
6675 offset = 0x7f84 + n * 12;
6676 else
6677 offset = 0x7f2c + (n - 3) * 12;
6678
6679 put_smstate(u32, buf, offset + 8, seg.base);
6680 put_smstate(u32, buf, offset + 4, seg.limit);
6681 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6682 }
6683
6684 #ifdef CONFIG_X86_64
6685 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6686 {
6687 struct kvm_segment seg;
6688 int offset;
6689 u16 flags;
6690
6691 kvm_get_segment(vcpu, &seg, n);
6692 offset = 0x7e00 + n * 16;
6693
6694 flags = enter_smm_get_segment_flags(&seg) >> 8;
6695 put_smstate(u16, buf, offset, seg.selector);
6696 put_smstate(u16, buf, offset + 2, flags);
6697 put_smstate(u32, buf, offset + 4, seg.limit);
6698 put_smstate(u64, buf, offset + 8, seg.base);
6699 }
6700 #endif
6701
6702 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6703 {
6704 struct desc_ptr dt;
6705 struct kvm_segment seg;
6706 unsigned long val;
6707 int i;
6708
6709 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6710 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6711 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6712 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6713
6714 for (i = 0; i < 8; i++)
6715 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6716
6717 kvm_get_dr(vcpu, 6, &val);
6718 put_smstate(u32, buf, 0x7fcc, (u32)val);
6719 kvm_get_dr(vcpu, 7, &val);
6720 put_smstate(u32, buf, 0x7fc8, (u32)val);
6721
6722 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6723 put_smstate(u32, buf, 0x7fc4, seg.selector);
6724 put_smstate(u32, buf, 0x7f64, seg.base);
6725 put_smstate(u32, buf, 0x7f60, seg.limit);
6726 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6727
6728 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6729 put_smstate(u32, buf, 0x7fc0, seg.selector);
6730 put_smstate(u32, buf, 0x7f80, seg.base);
6731 put_smstate(u32, buf, 0x7f7c, seg.limit);
6732 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6733
6734 kvm_x86_ops->get_gdt(vcpu, &dt);
6735 put_smstate(u32, buf, 0x7f74, dt.address);
6736 put_smstate(u32, buf, 0x7f70, dt.size);
6737
6738 kvm_x86_ops->get_idt(vcpu, &dt);
6739 put_smstate(u32, buf, 0x7f58, dt.address);
6740 put_smstate(u32, buf, 0x7f54, dt.size);
6741
6742 for (i = 0; i < 6; i++)
6743 enter_smm_save_seg_32(vcpu, buf, i);
6744
6745 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6746
6747 /* revision id */
6748 put_smstate(u32, buf, 0x7efc, 0x00020000);
6749 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6750 }
6751
6752 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6753 {
6754 #ifdef CONFIG_X86_64
6755 struct desc_ptr dt;
6756 struct kvm_segment seg;
6757 unsigned long val;
6758 int i;
6759
6760 for (i = 0; i < 16; i++)
6761 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6762
6763 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6764 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6765
6766 kvm_get_dr(vcpu, 6, &val);
6767 put_smstate(u64, buf, 0x7f68, val);
6768 kvm_get_dr(vcpu, 7, &val);
6769 put_smstate(u64, buf, 0x7f60, val);
6770
6771 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6772 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6773 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6774
6775 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6776
6777 /* revision id */
6778 put_smstate(u32, buf, 0x7efc, 0x00020064);
6779
6780 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6781
6782 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6783 put_smstate(u16, buf, 0x7e90, seg.selector);
6784 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6785 put_smstate(u32, buf, 0x7e94, seg.limit);
6786 put_smstate(u64, buf, 0x7e98, seg.base);
6787
6788 kvm_x86_ops->get_idt(vcpu, &dt);
6789 put_smstate(u32, buf, 0x7e84, dt.size);
6790 put_smstate(u64, buf, 0x7e88, dt.address);
6791
6792 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6793 put_smstate(u16, buf, 0x7e70, seg.selector);
6794 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6795 put_smstate(u32, buf, 0x7e74, seg.limit);
6796 put_smstate(u64, buf, 0x7e78, seg.base);
6797
6798 kvm_x86_ops->get_gdt(vcpu, &dt);
6799 put_smstate(u32, buf, 0x7e64, dt.size);
6800 put_smstate(u64, buf, 0x7e68, dt.address);
6801
6802 for (i = 0; i < 6; i++)
6803 enter_smm_save_seg_64(vcpu, buf, i);
6804 #else
6805 WARN_ON_ONCE(1);
6806 #endif
6807 }
6808
6809 static void enter_smm(struct kvm_vcpu *vcpu)
6810 {
6811 struct kvm_segment cs, ds;
6812 struct desc_ptr dt;
6813 char buf[512];
6814 u32 cr0;
6815
6816 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6817 vcpu->arch.hflags |= HF_SMM_MASK;
6818 memset(buf, 0, 512);
6819 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
6820 enter_smm_save_state_64(vcpu, buf);
6821 else
6822 enter_smm_save_state_32(vcpu, buf);
6823
6824 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6825
6826 if (kvm_x86_ops->get_nmi_mask(vcpu))
6827 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6828 else
6829 kvm_x86_ops->set_nmi_mask(vcpu, true);
6830
6831 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6832 kvm_rip_write(vcpu, 0x8000);
6833
6834 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6835 kvm_x86_ops->set_cr0(vcpu, cr0);
6836 vcpu->arch.cr0 = cr0;
6837
6838 kvm_x86_ops->set_cr4(vcpu, 0);
6839
6840 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6841 dt.address = dt.size = 0;
6842 kvm_x86_ops->set_idt(vcpu, &dt);
6843
6844 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6845
6846 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6847 cs.base = vcpu->arch.smbase;
6848
6849 ds.selector = 0;
6850 ds.base = 0;
6851
6852 cs.limit = ds.limit = 0xffffffff;
6853 cs.type = ds.type = 0x3;
6854 cs.dpl = ds.dpl = 0;
6855 cs.db = ds.db = 0;
6856 cs.s = ds.s = 1;
6857 cs.l = ds.l = 0;
6858 cs.g = ds.g = 1;
6859 cs.avl = ds.avl = 0;
6860 cs.present = ds.present = 1;
6861 cs.unusable = ds.unusable = 0;
6862 cs.padding = ds.padding = 0;
6863
6864 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6865 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6866 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6867 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6868 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6869 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6870
6871 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
6872 kvm_x86_ops->set_efer(vcpu, 0);
6873
6874 kvm_update_cpuid(vcpu);
6875 kvm_mmu_reset_context(vcpu);
6876 }
6877
6878 static void process_smi(struct kvm_vcpu *vcpu)
6879 {
6880 vcpu->arch.smi_pending = true;
6881 kvm_make_request(KVM_REQ_EVENT, vcpu);
6882 }
6883
6884 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6885 {
6886 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6887 }
6888
6889 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6890 {
6891 u64 eoi_exit_bitmap[4];
6892
6893 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6894 return;
6895
6896 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6897
6898 if (irqchip_split(vcpu->kvm))
6899 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6900 else {
6901 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6902 kvm_x86_ops->sync_pir_to_irr(vcpu);
6903 if (ioapic_in_kernel(vcpu->kvm))
6904 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6905 }
6906 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6907 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6908 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6909 }
6910
6911 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6912 {
6913 ++vcpu->stat.tlb_flush;
6914 kvm_x86_ops->tlb_flush(vcpu);
6915 }
6916
6917 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6918 unsigned long start, unsigned long end)
6919 {
6920 unsigned long apic_address;
6921
6922 /*
6923 * The physical address of apic access page is stored in the VMCS.
6924 * Update it when it becomes invalid.
6925 */
6926 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6927 if (start <= apic_address && apic_address < end)
6928 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6929 }
6930
6931 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6932 {
6933 struct page *page = NULL;
6934
6935 if (!lapic_in_kernel(vcpu))
6936 return;
6937
6938 if (!kvm_x86_ops->set_apic_access_page_addr)
6939 return;
6940
6941 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6942 if (is_error_page(page))
6943 return;
6944 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6945
6946 /*
6947 * Do not pin apic access page in memory, the MMU notifier
6948 * will call us again if it is migrated or swapped out.
6949 */
6950 put_page(page);
6951 }
6952 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6953
6954 /*
6955 * Returns 1 to let vcpu_run() continue the guest execution loop without
6956 * exiting to the userspace. Otherwise, the value will be returned to the
6957 * userspace.
6958 */
6959 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6960 {
6961 int r;
6962 bool req_int_win =
6963 dm_request_for_irq_injection(vcpu) &&
6964 kvm_cpu_accept_dm_intr(vcpu);
6965
6966 bool req_immediate_exit = false;
6967
6968 if (kvm_request_pending(vcpu)) {
6969 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6970 kvm_mmu_unload(vcpu);
6971 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6972 __kvm_migrate_timers(vcpu);
6973 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6974 kvm_gen_update_masterclock(vcpu->kvm);
6975 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6976 kvm_gen_kvmclock_update(vcpu);
6977 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6978 r = kvm_guest_time_update(vcpu);
6979 if (unlikely(r))
6980 goto out;
6981 }
6982 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6983 kvm_mmu_sync_roots(vcpu);
6984 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6985 kvm_vcpu_flush_tlb(vcpu);
6986 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6987 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6988 r = 0;
6989 goto out;
6990 }
6991 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6992 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6993 vcpu->mmio_needed = 0;
6994 r = 0;
6995 goto out;
6996 }
6997 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6998 /* Page is swapped out. Do synthetic halt */
6999 vcpu->arch.apf.halted = true;
7000 r = 1;
7001 goto out;
7002 }
7003 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7004 record_steal_time(vcpu);
7005 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7006 process_smi(vcpu);
7007 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7008 process_nmi(vcpu);
7009 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7010 kvm_pmu_handle_event(vcpu);
7011 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7012 kvm_pmu_deliver_pmi(vcpu);
7013 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7014 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7015 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7016 vcpu->arch.ioapic_handled_vectors)) {
7017 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7018 vcpu->run->eoi.vector =
7019 vcpu->arch.pending_ioapic_eoi;
7020 r = 0;
7021 goto out;
7022 }
7023 }
7024 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7025 vcpu_scan_ioapic(vcpu);
7026 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7027 kvm_vcpu_reload_apic_access_page(vcpu);
7028 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7029 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7030 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7031 r = 0;
7032 goto out;
7033 }
7034 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7035 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7036 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7037 r = 0;
7038 goto out;
7039 }
7040 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7041 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7042 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7043 r = 0;
7044 goto out;
7045 }
7046
7047 /*
7048 * KVM_REQ_HV_STIMER has to be processed after
7049 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7050 * depend on the guest clock being up-to-date
7051 */
7052 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7053 kvm_hv_process_stimers(vcpu);
7054 }
7055
7056 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7057 ++vcpu->stat.req_event;
7058 kvm_apic_accept_events(vcpu);
7059 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7060 r = 1;
7061 goto out;
7062 }
7063
7064 if (inject_pending_event(vcpu, req_int_win) != 0)
7065 req_immediate_exit = true;
7066 else {
7067 /* Enable NMI/IRQ window open exits if needed.
7068 *
7069 * SMIs have two cases: 1) they can be nested, and
7070 * then there is nothing to do here because RSM will
7071 * cause a vmexit anyway; 2) or the SMI can be pending
7072 * because inject_pending_event has completed the
7073 * injection of an IRQ or NMI from the previous vmexit,
7074 * and then we request an immediate exit to inject the SMI.
7075 */
7076 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7077 req_immediate_exit = true;
7078 if (vcpu->arch.nmi_pending)
7079 kvm_x86_ops->enable_nmi_window(vcpu);
7080 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7081 kvm_x86_ops->enable_irq_window(vcpu);
7082 WARN_ON(vcpu->arch.exception.pending);
7083 }
7084
7085 if (kvm_lapic_enabled(vcpu)) {
7086 update_cr8_intercept(vcpu);
7087 kvm_lapic_sync_to_vapic(vcpu);
7088 }
7089 }
7090
7091 r = kvm_mmu_reload(vcpu);
7092 if (unlikely(r)) {
7093 goto cancel_injection;
7094 }
7095
7096 preempt_disable();
7097
7098 kvm_x86_ops->prepare_guest_switch(vcpu);
7099
7100 /*
7101 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7102 * IPI are then delayed after guest entry, which ensures that they
7103 * result in virtual interrupt delivery.
7104 */
7105 local_irq_disable();
7106 vcpu->mode = IN_GUEST_MODE;
7107
7108 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7109
7110 /*
7111 * 1) We should set ->mode before checking ->requests. Please see
7112 * the comment in kvm_vcpu_exiting_guest_mode().
7113 *
7114 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7115 * pairs with the memory barrier implicit in pi_test_and_set_on
7116 * (see vmx_deliver_posted_interrupt).
7117 *
7118 * 3) This also orders the write to mode from any reads to the page
7119 * tables done while the VCPU is running. Please see the comment
7120 * in kvm_flush_remote_tlbs.
7121 */
7122 smp_mb__after_srcu_read_unlock();
7123
7124 /*
7125 * This handles the case where a posted interrupt was
7126 * notified with kvm_vcpu_kick.
7127 */
7128 if (kvm_lapic_enabled(vcpu)) {
7129 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
7130 kvm_x86_ops->sync_pir_to_irr(vcpu);
7131 }
7132
7133 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7134 || need_resched() || signal_pending(current)) {
7135 vcpu->mode = OUTSIDE_GUEST_MODE;
7136 smp_wmb();
7137 local_irq_enable();
7138 preempt_enable();
7139 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7140 r = 1;
7141 goto cancel_injection;
7142 }
7143
7144 kvm_load_guest_xcr0(vcpu);
7145
7146 if (req_immediate_exit) {
7147 kvm_make_request(KVM_REQ_EVENT, vcpu);
7148 smp_send_reschedule(vcpu->cpu);
7149 }
7150
7151 trace_kvm_entry(vcpu->vcpu_id);
7152 wait_lapic_expire(vcpu);
7153 guest_enter_irqoff();
7154
7155 if (unlikely(vcpu->arch.switch_db_regs)) {
7156 set_debugreg(0, 7);
7157 set_debugreg(vcpu->arch.eff_db[0], 0);
7158 set_debugreg(vcpu->arch.eff_db[1], 1);
7159 set_debugreg(vcpu->arch.eff_db[2], 2);
7160 set_debugreg(vcpu->arch.eff_db[3], 3);
7161 set_debugreg(vcpu->arch.dr6, 6);
7162 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7163 }
7164
7165 kvm_x86_ops->run(vcpu);
7166
7167 /*
7168 * Do this here before restoring debug registers on the host. And
7169 * since we do this before handling the vmexit, a DR access vmexit
7170 * can (a) read the correct value of the debug registers, (b) set
7171 * KVM_DEBUGREG_WONT_EXIT again.
7172 */
7173 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
7174 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7175 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
7176 kvm_update_dr0123(vcpu);
7177 kvm_update_dr6(vcpu);
7178 kvm_update_dr7(vcpu);
7179 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7180 }
7181
7182 /*
7183 * If the guest has used debug registers, at least dr7
7184 * will be disabled while returning to the host.
7185 * If we don't have active breakpoints in the host, we don't
7186 * care about the messed up debug address registers. But if
7187 * we have some of them active, restore the old state.
7188 */
7189 if (hw_breakpoint_active())
7190 hw_breakpoint_restore();
7191
7192 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
7193
7194 vcpu->mode = OUTSIDE_GUEST_MODE;
7195 smp_wmb();
7196
7197 kvm_put_guest_xcr0(vcpu);
7198
7199 kvm_x86_ops->handle_external_intr(vcpu);
7200
7201 ++vcpu->stat.exits;
7202
7203 guest_exit_irqoff();
7204
7205 local_irq_enable();
7206 preempt_enable();
7207
7208 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7209
7210 /*
7211 * Profile KVM exit RIPs:
7212 */
7213 if (unlikely(prof_on == KVM_PROFILING)) {
7214 unsigned long rip = kvm_rip_read(vcpu);
7215 profile_hit(KVM_PROFILING, (void *)rip);
7216 }
7217
7218 if (unlikely(vcpu->arch.tsc_always_catchup))
7219 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7220
7221 if (vcpu->arch.apic_attention)
7222 kvm_lapic_sync_from_vapic(vcpu);
7223
7224 vcpu->arch.gpa_available = false;
7225 r = kvm_x86_ops->handle_exit(vcpu);
7226 return r;
7227
7228 cancel_injection:
7229 kvm_x86_ops->cancel_injection(vcpu);
7230 if (unlikely(vcpu->arch.apic_attention))
7231 kvm_lapic_sync_from_vapic(vcpu);
7232 out:
7233 return r;
7234 }
7235
7236 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7237 {
7238 if (!kvm_arch_vcpu_runnable(vcpu) &&
7239 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
7240 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7241 kvm_vcpu_block(vcpu);
7242 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7243
7244 if (kvm_x86_ops->post_block)
7245 kvm_x86_ops->post_block(vcpu);
7246
7247 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7248 return 1;
7249 }
7250
7251 kvm_apic_accept_events(vcpu);
7252 switch(vcpu->arch.mp_state) {
7253 case KVM_MP_STATE_HALTED:
7254 vcpu->arch.pv.pv_unhalted = false;
7255 vcpu->arch.mp_state =
7256 KVM_MP_STATE_RUNNABLE;
7257 case KVM_MP_STATE_RUNNABLE:
7258 vcpu->arch.apf.halted = false;
7259 break;
7260 case KVM_MP_STATE_INIT_RECEIVED:
7261 break;
7262 default:
7263 return -EINTR;
7264 break;
7265 }
7266 return 1;
7267 }
7268
7269 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7270 {
7271 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7272 kvm_x86_ops->check_nested_events(vcpu, false);
7273
7274 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7275 !vcpu->arch.apf.halted);
7276 }
7277
7278 static int vcpu_run(struct kvm_vcpu *vcpu)
7279 {
7280 int r;
7281 struct kvm *kvm = vcpu->kvm;
7282
7283 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7284 vcpu->arch.l1tf_flush_l1d = true;
7285
7286 for (;;) {
7287 if (kvm_vcpu_running(vcpu)) {
7288 r = vcpu_enter_guest(vcpu);
7289 } else {
7290 r = vcpu_block(kvm, vcpu);
7291 }
7292
7293 if (r <= 0)
7294 break;
7295
7296 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
7297 if (kvm_cpu_has_pending_timer(vcpu))
7298 kvm_inject_pending_timer_irqs(vcpu);
7299
7300 if (dm_request_for_irq_injection(vcpu) &&
7301 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7302 r = 0;
7303 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7304 ++vcpu->stat.request_irq_exits;
7305 break;
7306 }
7307
7308 kvm_check_async_pf_completion(vcpu);
7309
7310 if (signal_pending(current)) {
7311 r = -EINTR;
7312 vcpu->run->exit_reason = KVM_EXIT_INTR;
7313 ++vcpu->stat.signal_exits;
7314 break;
7315 }
7316 if (need_resched()) {
7317 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7318 cond_resched();
7319 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7320 }
7321 }
7322
7323 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7324
7325 return r;
7326 }
7327
7328 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7329 {
7330 int r;
7331 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7332 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7333 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7334 if (r != EMULATE_DONE)
7335 return 0;
7336 return 1;
7337 }
7338
7339 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7340 {
7341 BUG_ON(!vcpu->arch.pio.count);
7342
7343 return complete_emulated_io(vcpu);
7344 }
7345
7346 /*
7347 * Implements the following, as a state machine:
7348 *
7349 * read:
7350 * for each fragment
7351 * for each mmio piece in the fragment
7352 * write gpa, len
7353 * exit
7354 * copy data
7355 * execute insn
7356 *
7357 * write:
7358 * for each fragment
7359 * for each mmio piece in the fragment
7360 * write gpa, len
7361 * copy data
7362 * exit
7363 */
7364 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
7365 {
7366 struct kvm_run *run = vcpu->run;
7367 struct kvm_mmio_fragment *frag;
7368 unsigned len;
7369
7370 BUG_ON(!vcpu->mmio_needed);
7371
7372 /* Complete previous fragment */
7373 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7374 len = min(8u, frag->len);
7375 if (!vcpu->mmio_is_write)
7376 memcpy(frag->data, run->mmio.data, len);
7377
7378 if (frag->len <= 8) {
7379 /* Switch to the next fragment. */
7380 frag++;
7381 vcpu->mmio_cur_fragment++;
7382 } else {
7383 /* Go forward to the next mmio piece. */
7384 frag->data += len;
7385 frag->gpa += len;
7386 frag->len -= len;
7387 }
7388
7389 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
7390 vcpu->mmio_needed = 0;
7391
7392 /* FIXME: return into emulator if single-stepping. */
7393 if (vcpu->mmio_is_write)
7394 return 1;
7395 vcpu->mmio_read_completed = 1;
7396 return complete_emulated_io(vcpu);
7397 }
7398
7399 run->exit_reason = KVM_EXIT_MMIO;
7400 run->mmio.phys_addr = frag->gpa;
7401 if (vcpu->mmio_is_write)
7402 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7403 run->mmio.len = min(8u, frag->len);
7404 run->mmio.is_write = vcpu->mmio_is_write;
7405 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7406 return 0;
7407 }
7408
7409
7410 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7411 {
7412 int r;
7413
7414 kvm_sigset_activate(vcpu);
7415
7416 kvm_load_guest_fpu(vcpu);
7417
7418 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7419 if (kvm_run->immediate_exit) {
7420 r = -EINTR;
7421 goto out;
7422 }
7423 kvm_vcpu_block(vcpu);
7424 kvm_apic_accept_events(vcpu);
7425 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
7426 r = -EAGAIN;
7427 if (signal_pending(current)) {
7428 r = -EINTR;
7429 vcpu->run->exit_reason = KVM_EXIT_INTR;
7430 ++vcpu->stat.signal_exits;
7431 }
7432 goto out;
7433 }
7434
7435 /* re-sync apic's tpr */
7436 if (!lapic_in_kernel(vcpu)) {
7437 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7438 r = -EINVAL;
7439 goto out;
7440 }
7441 }
7442
7443 if (unlikely(vcpu->arch.complete_userspace_io)) {
7444 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7445 vcpu->arch.complete_userspace_io = NULL;
7446 r = cui(vcpu);
7447 if (r <= 0)
7448 goto out;
7449 } else
7450 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7451
7452 if (kvm_run->immediate_exit)
7453 r = -EINTR;
7454 else
7455 r = vcpu_run(vcpu);
7456
7457 out:
7458 kvm_put_guest_fpu(vcpu);
7459 post_kvm_run_save(vcpu);
7460 kvm_sigset_deactivate(vcpu);
7461
7462 return r;
7463 }
7464
7465 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7466 {
7467 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7468 /*
7469 * We are here if userspace calls get_regs() in the middle of
7470 * instruction emulation. Registers state needs to be copied
7471 * back from emulation context to vcpu. Userspace shouldn't do
7472 * that usually, but some bad designed PV devices (vmware
7473 * backdoor interface) need this to work
7474 */
7475 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7476 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7477 }
7478 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7479 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7480 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7481 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7482 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7483 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7484 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7485 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7486 #ifdef CONFIG_X86_64
7487 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7488 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7489 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7490 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7491 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7492 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7493 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7494 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7495 #endif
7496
7497 regs->rip = kvm_rip_read(vcpu);
7498 regs->rflags = kvm_get_rflags(vcpu);
7499
7500 return 0;
7501 }
7502
7503 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7504 {
7505 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7506 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7507
7508 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7509 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7510 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7511 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7512 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7513 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7514 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7515 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7516 #ifdef CONFIG_X86_64
7517 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7518 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7519 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7520 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7521 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7522 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7523 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7524 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7525 #endif
7526
7527 kvm_rip_write(vcpu, regs->rip);
7528 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
7529
7530 vcpu->arch.exception.pending = false;
7531
7532 kvm_make_request(KVM_REQ_EVENT, vcpu);
7533
7534 return 0;
7535 }
7536
7537 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7538 {
7539 struct kvm_segment cs;
7540
7541 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7542 *db = cs.db;
7543 *l = cs.l;
7544 }
7545 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7546
7547 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7548 struct kvm_sregs *sregs)
7549 {
7550 struct desc_ptr dt;
7551
7552 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7553 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7554 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7555 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7556 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7557 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7558
7559 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7560 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7561
7562 kvm_x86_ops->get_idt(vcpu, &dt);
7563 sregs->idt.limit = dt.size;
7564 sregs->idt.base = dt.address;
7565 kvm_x86_ops->get_gdt(vcpu, &dt);
7566 sregs->gdt.limit = dt.size;
7567 sregs->gdt.base = dt.address;
7568
7569 sregs->cr0 = kvm_read_cr0(vcpu);
7570 sregs->cr2 = vcpu->arch.cr2;
7571 sregs->cr3 = kvm_read_cr3(vcpu);
7572 sregs->cr4 = kvm_read_cr4(vcpu);
7573 sregs->cr8 = kvm_get_cr8(vcpu);
7574 sregs->efer = vcpu->arch.efer;
7575 sregs->apic_base = kvm_get_apic_base(vcpu);
7576
7577 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7578
7579 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7580 set_bit(vcpu->arch.interrupt.nr,
7581 (unsigned long *)sregs->interrupt_bitmap);
7582
7583 return 0;
7584 }
7585
7586 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7587 struct kvm_mp_state *mp_state)
7588 {
7589 kvm_apic_accept_events(vcpu);
7590 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7591 vcpu->arch.pv.pv_unhalted)
7592 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7593 else
7594 mp_state->mp_state = vcpu->arch.mp_state;
7595
7596 return 0;
7597 }
7598
7599 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7600 struct kvm_mp_state *mp_state)
7601 {
7602 if (!lapic_in_kernel(vcpu) &&
7603 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7604 return -EINVAL;
7605
7606 /* INITs are latched while in SMM */
7607 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7608 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7609 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7610 return -EINVAL;
7611
7612 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7613 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7614 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7615 } else
7616 vcpu->arch.mp_state = mp_state->mp_state;
7617 kvm_make_request(KVM_REQ_EVENT, vcpu);
7618 return 0;
7619 }
7620
7621 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7622 int reason, bool has_error_code, u32 error_code)
7623 {
7624 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7625 int ret;
7626
7627 init_emulate_ctxt(vcpu);
7628
7629 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7630 has_error_code, error_code);
7631
7632 if (ret)
7633 return EMULATE_FAIL;
7634
7635 kvm_rip_write(vcpu, ctxt->eip);
7636 kvm_set_rflags(vcpu, ctxt->eflags);
7637 kvm_make_request(KVM_REQ_EVENT, vcpu);
7638 return EMULATE_DONE;
7639 }
7640 EXPORT_SYMBOL_GPL(kvm_task_switch);
7641
7642 int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7643 {
7644 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
7645 /*
7646 * When EFER.LME and CR0.PG are set, the processor is in
7647 * 64-bit mode (though maybe in a 32-bit code segment).
7648 * CR4.PAE and EFER.LMA must be set.
7649 */
7650 if (!(sregs->cr4 & X86_CR4_PAE)
7651 || !(sregs->efer & EFER_LMA))
7652 return -EINVAL;
7653 } else {
7654 /*
7655 * Not in 64-bit mode: EFER.LMA is clear and the code
7656 * segment cannot be 64-bit.
7657 */
7658 if (sregs->efer & EFER_LMA || sregs->cs.l)
7659 return -EINVAL;
7660 }
7661
7662 return 0;
7663 }
7664
7665 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7666 struct kvm_sregs *sregs)
7667 {
7668 struct msr_data apic_base_msr;
7669 int mmu_reset_needed = 0;
7670 int cpuid_update_needed = 0;
7671 int pending_vec, max_bits, idx;
7672 struct desc_ptr dt;
7673
7674 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7675 (sregs->cr4 & X86_CR4_OSXSAVE))
7676 return -EINVAL;
7677
7678 if (kvm_valid_sregs(vcpu, sregs))
7679 return -EINVAL;
7680
7681 apic_base_msr.data = sregs->apic_base;
7682 apic_base_msr.host_initiated = true;
7683 if (kvm_set_apic_base(vcpu, &apic_base_msr))
7684 return -EINVAL;
7685
7686 dt.size = sregs->idt.limit;
7687 dt.address = sregs->idt.base;
7688 kvm_x86_ops->set_idt(vcpu, &dt);
7689 dt.size = sregs->gdt.limit;
7690 dt.address = sregs->gdt.base;
7691 kvm_x86_ops->set_gdt(vcpu, &dt);
7692
7693 vcpu->arch.cr2 = sregs->cr2;
7694 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7695 vcpu->arch.cr3 = sregs->cr3;
7696 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7697
7698 kvm_set_cr8(vcpu, sregs->cr8);
7699
7700 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7701 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7702
7703 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7704 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7705 vcpu->arch.cr0 = sregs->cr0;
7706
7707 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7708 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
7709 (X86_CR4_OSXSAVE | X86_CR4_PKE));
7710 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7711 if (cpuid_update_needed)
7712 kvm_update_cpuid(vcpu);
7713
7714 idx = srcu_read_lock(&vcpu->kvm->srcu);
7715 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7716 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7717 mmu_reset_needed = 1;
7718 }
7719 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7720
7721 if (mmu_reset_needed)
7722 kvm_mmu_reset_context(vcpu);
7723
7724 max_bits = KVM_NR_INTERRUPTS;
7725 pending_vec = find_first_bit(
7726 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7727 if (pending_vec < max_bits) {
7728 kvm_queue_interrupt(vcpu, pending_vec, false);
7729 pr_debug("Set back pending irq %d\n", pending_vec);
7730 }
7731
7732 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7733 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7734 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7735 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7736 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7737 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7738
7739 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7740 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7741
7742 update_cr8_intercept(vcpu);
7743
7744 /* Older userspace won't unhalt the vcpu on reset. */
7745 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7746 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7747 !is_protmode(vcpu))
7748 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7749
7750 kvm_make_request(KVM_REQ_EVENT, vcpu);
7751
7752 return 0;
7753 }
7754
7755 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7756 struct kvm_guest_debug *dbg)
7757 {
7758 unsigned long rflags;
7759 int i, r;
7760
7761 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7762 r = -EBUSY;
7763 if (vcpu->arch.exception.pending)
7764 goto out;
7765 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7766 kvm_queue_exception(vcpu, DB_VECTOR);
7767 else
7768 kvm_queue_exception(vcpu, BP_VECTOR);
7769 }
7770
7771 /*
7772 * Read rflags as long as potentially injected trace flags are still
7773 * filtered out.
7774 */
7775 rflags = kvm_get_rflags(vcpu);
7776
7777 vcpu->guest_debug = dbg->control;
7778 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7779 vcpu->guest_debug = 0;
7780
7781 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7782 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7783 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7784 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7785 } else {
7786 for (i = 0; i < KVM_NR_DB_REGS; i++)
7787 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7788 }
7789 kvm_update_dr7(vcpu);
7790
7791 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7792 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7793 get_segment_base(vcpu, VCPU_SREG_CS);
7794
7795 /*
7796 * Trigger an rflags update that will inject or remove the trace
7797 * flags.
7798 */
7799 kvm_set_rflags(vcpu, rflags);
7800
7801 kvm_x86_ops->update_bp_intercept(vcpu);
7802
7803 r = 0;
7804
7805 out:
7806
7807 return r;
7808 }
7809
7810 /*
7811 * Translate a guest virtual address to a guest physical address.
7812 */
7813 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7814 struct kvm_translation *tr)
7815 {
7816 unsigned long vaddr = tr->linear_address;
7817 gpa_t gpa;
7818 int idx;
7819
7820 idx = srcu_read_lock(&vcpu->kvm->srcu);
7821 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7822 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7823 tr->physical_address = gpa;
7824 tr->valid = gpa != UNMAPPED_GVA;
7825 tr->writeable = 1;
7826 tr->usermode = 0;
7827
7828 return 0;
7829 }
7830
7831 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7832 {
7833 struct fxregs_state *fxsave =
7834 &vcpu->arch.guest_fpu.state.fxsave;
7835
7836 memcpy(fpu->fpr, fxsave->st_space, 128);
7837 fpu->fcw = fxsave->cwd;
7838 fpu->fsw = fxsave->swd;
7839 fpu->ftwx = fxsave->twd;
7840 fpu->last_opcode = fxsave->fop;
7841 fpu->last_ip = fxsave->rip;
7842 fpu->last_dp = fxsave->rdp;
7843 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7844
7845 return 0;
7846 }
7847
7848 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7849 {
7850 struct fxregs_state *fxsave =
7851 &vcpu->arch.guest_fpu.state.fxsave;
7852
7853 memcpy(fxsave->st_space, fpu->fpr, 128);
7854 fxsave->cwd = fpu->fcw;
7855 fxsave->swd = fpu->fsw;
7856 fxsave->twd = fpu->ftwx;
7857 fxsave->fop = fpu->last_opcode;
7858 fxsave->rip = fpu->last_ip;
7859 fxsave->rdp = fpu->last_dp;
7860 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7861
7862 return 0;
7863 }
7864
7865 static void fx_init(struct kvm_vcpu *vcpu)
7866 {
7867 fpstate_init(&vcpu->arch.guest_fpu.state);
7868 if (boot_cpu_has(X86_FEATURE_XSAVES))
7869 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7870 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7871
7872 /*
7873 * Ensure guest xcr0 is valid for loading
7874 */
7875 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7876
7877 vcpu->arch.cr0 |= X86_CR0_ET;
7878 }
7879
7880 /* Swap (qemu) user FPU context for the guest FPU context. */
7881 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7882 {
7883 preempt_disable();
7884 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
7885 /* PKRU is separately restored in kvm_x86_ops->run. */
7886 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7887 ~XFEATURE_MASK_PKRU);
7888 preempt_enable();
7889 trace_kvm_fpu(1);
7890 }
7891
7892 /* When vcpu_run ends, restore user space FPU context. */
7893 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7894 {
7895 preempt_disable();
7896 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7897 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7898 preempt_enable();
7899 ++vcpu->stat.fpu_reload;
7900 trace_kvm_fpu(0);
7901 }
7902
7903 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7904 {
7905 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7906
7907 kvmclock_reset(vcpu);
7908
7909 kvm_x86_ops->vcpu_free(vcpu);
7910 free_cpumask_var(wbinvd_dirty_mask);
7911 }
7912
7913 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7914 unsigned int id)
7915 {
7916 struct kvm_vcpu *vcpu;
7917
7918 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7919 printk_once(KERN_WARNING
7920 "kvm: SMP vm created on host with unstable TSC; "
7921 "guest TSC will not be reliable\n");
7922
7923 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7924
7925 return vcpu;
7926 }
7927
7928 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7929 {
7930 int r;
7931
7932 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
7933 kvm_vcpu_mtrr_init(vcpu);
7934 r = vcpu_load(vcpu);
7935 if (r)
7936 return r;
7937 kvm_vcpu_reset(vcpu, false);
7938 kvm_mmu_setup(vcpu);
7939 vcpu_put(vcpu);
7940 return r;
7941 }
7942
7943 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7944 {
7945 struct msr_data msr;
7946 struct kvm *kvm = vcpu->kvm;
7947
7948 kvm_hv_vcpu_postcreate(vcpu);
7949
7950 if (vcpu_load(vcpu))
7951 return;
7952 msr.data = 0x0;
7953 msr.index = MSR_IA32_TSC;
7954 msr.host_initiated = true;
7955 kvm_write_tsc(vcpu, &msr);
7956 vcpu_put(vcpu);
7957
7958 if (!kvmclock_periodic_sync)
7959 return;
7960
7961 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7962 KVMCLOCK_SYNC_PERIOD);
7963 }
7964
7965 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7966 {
7967 int r;
7968 vcpu->arch.apf.msr_val = 0;
7969
7970 r = vcpu_load(vcpu);
7971 BUG_ON(r);
7972 kvm_mmu_unload(vcpu);
7973 vcpu_put(vcpu);
7974
7975 kvm_x86_ops->vcpu_free(vcpu);
7976 }
7977
7978 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7979 {
7980 kvm_lapic_reset(vcpu, init_event);
7981
7982 vcpu->arch.hflags = 0;
7983
7984 vcpu->arch.smi_pending = 0;
7985 atomic_set(&vcpu->arch.nmi_queued, 0);
7986 vcpu->arch.nmi_pending = 0;
7987 vcpu->arch.nmi_injected = false;
7988 kvm_clear_interrupt_queue(vcpu);
7989 kvm_clear_exception_queue(vcpu);
7990 vcpu->arch.exception.pending = false;
7991
7992 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7993 kvm_update_dr0123(vcpu);
7994 vcpu->arch.dr6 = DR6_INIT;
7995 kvm_update_dr6(vcpu);
7996 vcpu->arch.dr7 = DR7_FIXED_1;
7997 kvm_update_dr7(vcpu);
7998
7999 vcpu->arch.cr2 = 0;
8000
8001 kvm_make_request(KVM_REQ_EVENT, vcpu);
8002 vcpu->arch.apf.msr_val = 0;
8003 vcpu->arch.st.msr_val = 0;
8004
8005 kvmclock_reset(vcpu);
8006
8007 kvm_clear_async_pf_completion_queue(vcpu);
8008 kvm_async_pf_hash_reset(vcpu);
8009 vcpu->arch.apf.halted = false;
8010
8011 if (!init_event) {
8012 kvm_pmu_reset(vcpu);
8013 vcpu->arch.smbase = 0x30000;
8014
8015 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8016 vcpu->arch.msr_misc_features_enables = 0;
8017 }
8018
8019 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8020 vcpu->arch.regs_avail = ~0;
8021 vcpu->arch.regs_dirty = ~0;
8022
8023 kvm_x86_ops->vcpu_reset(vcpu, init_event);
8024 }
8025
8026 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
8027 {
8028 struct kvm_segment cs;
8029
8030 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8031 cs.selector = vector << 8;
8032 cs.base = vector << 12;
8033 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8034 kvm_rip_write(vcpu, 0);
8035 }
8036
8037 int kvm_arch_hardware_enable(void)
8038 {
8039 struct kvm *kvm;
8040 struct kvm_vcpu *vcpu;
8041 int i;
8042 int ret;
8043 u64 local_tsc;
8044 u64 max_tsc = 0;
8045 bool stable, backwards_tsc = false;
8046
8047 kvm_shared_msr_cpu_online();
8048 ret = kvm_x86_ops->hardware_enable();
8049 if (ret != 0)
8050 return ret;
8051
8052 local_tsc = rdtsc();
8053 stable = !check_tsc_unstable();
8054 list_for_each_entry(kvm, &vm_list, vm_list) {
8055 kvm_for_each_vcpu(i, vcpu, kvm) {
8056 if (!stable && vcpu->cpu == smp_processor_id())
8057 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8058 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8059 backwards_tsc = true;
8060 if (vcpu->arch.last_host_tsc > max_tsc)
8061 max_tsc = vcpu->arch.last_host_tsc;
8062 }
8063 }
8064 }
8065
8066 /*
8067 * Sometimes, even reliable TSCs go backwards. This happens on
8068 * platforms that reset TSC during suspend or hibernate actions, but
8069 * maintain synchronization. We must compensate. Fortunately, we can
8070 * detect that condition here, which happens early in CPU bringup,
8071 * before any KVM threads can be running. Unfortunately, we can't
8072 * bring the TSCs fully up to date with real time, as we aren't yet far
8073 * enough into CPU bringup that we know how much real time has actually
8074 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
8075 * variables that haven't been updated yet.
8076 *
8077 * So we simply find the maximum observed TSC above, then record the
8078 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8079 * the adjustment will be applied. Note that we accumulate
8080 * adjustments, in case multiple suspend cycles happen before some VCPU
8081 * gets a chance to run again. In the event that no KVM threads get a
8082 * chance to run, we will miss the entire elapsed period, as we'll have
8083 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8084 * loose cycle time. This isn't too big a deal, since the loss will be
8085 * uniform across all VCPUs (not to mention the scenario is extremely
8086 * unlikely). It is possible that a second hibernate recovery happens
8087 * much faster than a first, causing the observed TSC here to be
8088 * smaller; this would require additional padding adjustment, which is
8089 * why we set last_host_tsc to the local tsc observed here.
8090 *
8091 * N.B. - this code below runs only on platforms with reliable TSC,
8092 * as that is the only way backwards_tsc is set above. Also note
8093 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8094 * have the same delta_cyc adjustment applied if backwards_tsc
8095 * is detected. Note further, this adjustment is only done once,
8096 * as we reset last_host_tsc on all VCPUs to stop this from being
8097 * called multiple times (one for each physical CPU bringup).
8098 *
8099 * Platforms with unreliable TSCs don't have to deal with this, they
8100 * will be compensated by the logic in vcpu_load, which sets the TSC to
8101 * catchup mode. This will catchup all VCPUs to real time, but cannot
8102 * guarantee that they stay in perfect synchronization.
8103 */
8104 if (backwards_tsc) {
8105 u64 delta_cyc = max_tsc - local_tsc;
8106 list_for_each_entry(kvm, &vm_list, vm_list) {
8107 kvm->arch.backwards_tsc_observed = true;
8108 kvm_for_each_vcpu(i, vcpu, kvm) {
8109 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8110 vcpu->arch.last_host_tsc = local_tsc;
8111 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
8112 }
8113
8114 /*
8115 * We have to disable TSC offset matching.. if you were
8116 * booting a VM while issuing an S4 host suspend....
8117 * you may have some problem. Solving this issue is
8118 * left as an exercise to the reader.
8119 */
8120 kvm->arch.last_tsc_nsec = 0;
8121 kvm->arch.last_tsc_write = 0;
8122 }
8123
8124 }
8125 return 0;
8126 }
8127
8128 void kvm_arch_hardware_disable(void)
8129 {
8130 kvm_x86_ops->hardware_disable();
8131 drop_user_return_notifiers();
8132 }
8133
8134 int kvm_arch_hardware_setup(void)
8135 {
8136 int r;
8137
8138 r = kvm_x86_ops->hardware_setup();
8139 if (r != 0)
8140 return r;
8141
8142 if (kvm_has_tsc_control) {
8143 /*
8144 * Make sure the user can only configure tsc_khz values that
8145 * fit into a signed integer.
8146 * A min value is not calculated needed because it will always
8147 * be 1 on all machines.
8148 */
8149 u64 max = min(0x7fffffffULL,
8150 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8151 kvm_max_guest_tsc_khz = max;
8152
8153 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
8154 }
8155
8156 kvm_init_msr_list();
8157 return 0;
8158 }
8159
8160 void kvm_arch_hardware_unsetup(void)
8161 {
8162 kvm_x86_ops->hardware_unsetup();
8163 }
8164
8165 void kvm_arch_check_processor_compat(void *rtn)
8166 {
8167 kvm_x86_ops->check_processor_compatibility(rtn);
8168 }
8169
8170 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8171 {
8172 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8173 }
8174 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8175
8176 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8177 {
8178 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
8179 }
8180
8181 struct static_key kvm_no_apic_vcpu __read_mostly;
8182 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
8183
8184 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8185 {
8186 struct page *page;
8187 struct kvm *kvm;
8188 int r;
8189
8190 BUG_ON(vcpu->kvm == NULL);
8191 kvm = vcpu->kvm;
8192
8193 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
8194 vcpu->arch.pv.pv_unhalted = false;
8195 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
8196 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
8197 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8198 else
8199 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
8200
8201 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8202 if (!page) {
8203 r = -ENOMEM;
8204 goto fail;
8205 }
8206 vcpu->arch.pio_data = page_address(page);
8207
8208 kvm_set_tsc_khz(vcpu, max_tsc_khz);
8209
8210 r = kvm_mmu_create(vcpu);
8211 if (r < 0)
8212 goto fail_free_pio_data;
8213
8214 if (irqchip_in_kernel(kvm)) {
8215 r = kvm_create_lapic(vcpu);
8216 if (r < 0)
8217 goto fail_mmu_destroy;
8218 } else
8219 static_key_slow_inc(&kvm_no_apic_vcpu);
8220
8221 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8222 GFP_KERNEL);
8223 if (!vcpu->arch.mce_banks) {
8224 r = -ENOMEM;
8225 goto fail_free_lapic;
8226 }
8227 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8228
8229 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8230 r = -ENOMEM;
8231 goto fail_free_mce_banks;
8232 }
8233
8234 fx_init(vcpu);
8235
8236 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
8237 vcpu->arch.pv_time_enabled = false;
8238
8239 vcpu->arch.guest_supported_xcr0 = 0;
8240 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
8241
8242 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8243
8244 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8245
8246 kvm_async_pf_hash_reset(vcpu);
8247 kvm_pmu_init(vcpu);
8248
8249 vcpu->arch.pending_external_vector = -1;
8250 vcpu->arch.preempted_in_kernel = false;
8251
8252 kvm_hv_vcpu_init(vcpu);
8253
8254 return 0;
8255
8256 fail_free_mce_banks:
8257 kfree(vcpu->arch.mce_banks);
8258 fail_free_lapic:
8259 kvm_free_lapic(vcpu);
8260 fail_mmu_destroy:
8261 kvm_mmu_destroy(vcpu);
8262 fail_free_pio_data:
8263 free_page((unsigned long)vcpu->arch.pio_data);
8264 fail:
8265 return r;
8266 }
8267
8268 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8269 {
8270 int idx;
8271
8272 kvm_hv_vcpu_uninit(vcpu);
8273 kvm_pmu_destroy(vcpu);
8274 kfree(vcpu->arch.mce_banks);
8275 kvm_free_lapic(vcpu);
8276 idx = srcu_read_lock(&vcpu->kvm->srcu);
8277 kvm_mmu_destroy(vcpu);
8278 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8279 free_page((unsigned long)vcpu->arch.pio_data);
8280 if (!lapic_in_kernel(vcpu))
8281 static_key_slow_dec(&kvm_no_apic_vcpu);
8282 }
8283
8284 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8285 {
8286 vcpu->arch.l1tf_flush_l1d = true;
8287 kvm_x86_ops->sched_in(vcpu, cpu);
8288 }
8289
8290 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
8291 {
8292 if (type)
8293 return -EINVAL;
8294
8295 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
8296 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
8297 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
8298 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
8299 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
8300
8301 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8302 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
8303 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8304 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8305 &kvm->arch.irq_sources_bitmap);
8306
8307 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
8308 mutex_init(&kvm->arch.apic_map_lock);
8309 mutex_init(&kvm->arch.hyperv.hv_lock);
8310 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8311
8312 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
8313 pvclock_update_vm_gtod_copy(kvm);
8314
8315 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
8316 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
8317
8318 kvm_page_track_init(kvm);
8319 kvm_mmu_init_vm(kvm);
8320
8321 if (kvm_x86_ops->vm_init)
8322 return kvm_x86_ops->vm_init(kvm);
8323
8324 return 0;
8325 }
8326
8327 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8328 {
8329 int r;
8330 r = vcpu_load(vcpu);
8331 BUG_ON(r);
8332 kvm_mmu_unload(vcpu);
8333 vcpu_put(vcpu);
8334 }
8335
8336 static void kvm_free_vcpus(struct kvm *kvm)
8337 {
8338 unsigned int i;
8339 struct kvm_vcpu *vcpu;
8340
8341 /*
8342 * Unpin any mmu pages first.
8343 */
8344 kvm_for_each_vcpu(i, vcpu, kvm) {
8345 kvm_clear_async_pf_completion_queue(vcpu);
8346 kvm_unload_vcpu_mmu(vcpu);
8347 }
8348 kvm_for_each_vcpu(i, vcpu, kvm)
8349 kvm_arch_vcpu_free(vcpu);
8350
8351 mutex_lock(&kvm->lock);
8352 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8353 kvm->vcpus[i] = NULL;
8354
8355 atomic_set(&kvm->online_vcpus, 0);
8356 mutex_unlock(&kvm->lock);
8357 }
8358
8359 void kvm_arch_sync_events(struct kvm *kvm)
8360 {
8361 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
8362 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
8363 kvm_free_pit(kvm);
8364 }
8365
8366 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8367 {
8368 int i, r;
8369 unsigned long hva;
8370 struct kvm_memslots *slots = kvm_memslots(kvm);
8371 struct kvm_memory_slot *slot, old;
8372
8373 /* Called with kvm->slots_lock held. */
8374 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8375 return -EINVAL;
8376
8377 slot = id_to_memslot(slots, id);
8378 if (size) {
8379 if (slot->npages)
8380 return -EEXIST;
8381
8382 /*
8383 * MAP_SHARED to prevent internal slot pages from being moved
8384 * by fork()/COW.
8385 */
8386 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8387 MAP_SHARED | MAP_ANONYMOUS, 0);
8388 if (IS_ERR((void *)hva))
8389 return PTR_ERR((void *)hva);
8390 } else {
8391 if (!slot->npages)
8392 return 0;
8393
8394 hva = 0;
8395 }
8396
8397 old = *slot;
8398 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
8399 struct kvm_userspace_memory_region m;
8400
8401 m.slot = id | (i << 16);
8402 m.flags = 0;
8403 m.guest_phys_addr = gpa;
8404 m.userspace_addr = hva;
8405 m.memory_size = size;
8406 r = __kvm_set_memory_region(kvm, &m);
8407 if (r < 0)
8408 return r;
8409 }
8410
8411 if (!size)
8412 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8413
8414 return 0;
8415 }
8416 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8417
8418 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8419 {
8420 int r;
8421
8422 mutex_lock(&kvm->slots_lock);
8423 r = __x86_set_memory_region(kvm, id, gpa, size);
8424 mutex_unlock(&kvm->slots_lock);
8425
8426 return r;
8427 }
8428 EXPORT_SYMBOL_GPL(x86_set_memory_region);
8429
8430 void kvm_arch_destroy_vm(struct kvm *kvm)
8431 {
8432 if (current->mm == kvm->mm) {
8433 /*
8434 * Free memory regions allocated on behalf of userspace,
8435 * unless the the memory map has changed due to process exit
8436 * or fd copying.
8437 */
8438 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8439 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8440 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8441 }
8442 if (kvm_x86_ops->vm_destroy)
8443 kvm_x86_ops->vm_destroy(kvm);
8444 kvm_pic_destroy(kvm);
8445 kvm_ioapic_destroy(kvm);
8446 kvm_free_vcpus(kvm);
8447 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8448 kvm_mmu_uninit_vm(kvm);
8449 kvm_page_track_cleanup(kvm);
8450 }
8451
8452 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8453 struct kvm_memory_slot *dont)
8454 {
8455 int i;
8456
8457 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8458 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8459 kvfree(free->arch.rmap[i]);
8460 free->arch.rmap[i] = NULL;
8461 }
8462 if (i == 0)
8463 continue;
8464
8465 if (!dont || free->arch.lpage_info[i - 1] !=
8466 dont->arch.lpage_info[i - 1]) {
8467 kvfree(free->arch.lpage_info[i - 1]);
8468 free->arch.lpage_info[i - 1] = NULL;
8469 }
8470 }
8471
8472 kvm_page_track_free_memslot(free, dont);
8473 }
8474
8475 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8476 unsigned long npages)
8477 {
8478 int i;
8479
8480 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8481 struct kvm_lpage_info *linfo;
8482 unsigned long ugfn;
8483 int lpages;
8484 int level = i + 1;
8485
8486 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8487 slot->base_gfn, level) + 1;
8488
8489 slot->arch.rmap[i] =
8490 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
8491 if (!slot->arch.rmap[i])
8492 goto out_free;
8493 if (i == 0)
8494 continue;
8495
8496 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
8497 if (!linfo)
8498 goto out_free;
8499
8500 slot->arch.lpage_info[i - 1] = linfo;
8501
8502 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8503 linfo[0].disallow_lpage = 1;
8504 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8505 linfo[lpages - 1].disallow_lpage = 1;
8506 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8507 /*
8508 * If the gfn and userspace address are not aligned wrt each
8509 * other, or if explicitly asked to, disable large page
8510 * support for this slot
8511 */
8512 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8513 !kvm_largepages_enabled()) {
8514 unsigned long j;
8515
8516 for (j = 0; j < lpages; ++j)
8517 linfo[j].disallow_lpage = 1;
8518 }
8519 }
8520
8521 if (kvm_page_track_create_memslot(slot, npages))
8522 goto out_free;
8523
8524 return 0;
8525
8526 out_free:
8527 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8528 kvfree(slot->arch.rmap[i]);
8529 slot->arch.rmap[i] = NULL;
8530 if (i == 0)
8531 continue;
8532
8533 kvfree(slot->arch.lpage_info[i - 1]);
8534 slot->arch.lpage_info[i - 1] = NULL;
8535 }
8536 return -ENOMEM;
8537 }
8538
8539 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
8540 {
8541 /*
8542 * memslots->generation has been incremented.
8543 * mmio generation may have reached its maximum value.
8544 */
8545 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
8546 }
8547
8548 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8549 struct kvm_memory_slot *memslot,
8550 const struct kvm_userspace_memory_region *mem,
8551 enum kvm_mr_change change)
8552 {
8553 return 0;
8554 }
8555
8556 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8557 struct kvm_memory_slot *new)
8558 {
8559 /* Still write protect RO slot */
8560 if (new->flags & KVM_MEM_READONLY) {
8561 kvm_mmu_slot_remove_write_access(kvm, new);
8562 return;
8563 }
8564
8565 /*
8566 * Call kvm_x86_ops dirty logging hooks when they are valid.
8567 *
8568 * kvm_x86_ops->slot_disable_log_dirty is called when:
8569 *
8570 * - KVM_MR_CREATE with dirty logging is disabled
8571 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8572 *
8573 * The reason is, in case of PML, we need to set D-bit for any slots
8574 * with dirty logging disabled in order to eliminate unnecessary GPA
8575 * logging in PML buffer (and potential PML buffer full VMEXT). This
8576 * guarantees leaving PML enabled during guest's lifetime won't have
8577 * any additonal overhead from PML when guest is running with dirty
8578 * logging disabled for memory slots.
8579 *
8580 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8581 * to dirty logging mode.
8582 *
8583 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8584 *
8585 * In case of write protect:
8586 *
8587 * Write protect all pages for dirty logging.
8588 *
8589 * All the sptes including the large sptes which point to this
8590 * slot are set to readonly. We can not create any new large
8591 * spte on this slot until the end of the logging.
8592 *
8593 * See the comments in fast_page_fault().
8594 */
8595 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8596 if (kvm_x86_ops->slot_enable_log_dirty)
8597 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8598 else
8599 kvm_mmu_slot_remove_write_access(kvm, new);
8600 } else {
8601 if (kvm_x86_ops->slot_disable_log_dirty)
8602 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8603 }
8604 }
8605
8606 void kvm_arch_commit_memory_region(struct kvm *kvm,
8607 const struct kvm_userspace_memory_region *mem,
8608 const struct kvm_memory_slot *old,
8609 const struct kvm_memory_slot *new,
8610 enum kvm_mr_change change)
8611 {
8612 int nr_mmu_pages = 0;
8613
8614 if (!kvm->arch.n_requested_mmu_pages)
8615 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8616
8617 if (nr_mmu_pages)
8618 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8619
8620 /*
8621 * Dirty logging tracks sptes in 4k granularity, meaning that large
8622 * sptes have to be split. If live migration is successful, the guest
8623 * in the source machine will be destroyed and large sptes will be
8624 * created in the destination. However, if the guest continues to run
8625 * in the source machine (for example if live migration fails), small
8626 * sptes will remain around and cause bad performance.
8627 *
8628 * Scan sptes if dirty logging has been stopped, dropping those
8629 * which can be collapsed into a single large-page spte. Later
8630 * page faults will create the large-page sptes.
8631 */
8632 if ((change != KVM_MR_DELETE) &&
8633 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8634 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8635 kvm_mmu_zap_collapsible_sptes(kvm, new);
8636
8637 /*
8638 * Set up write protection and/or dirty logging for the new slot.
8639 *
8640 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8641 * been zapped so no dirty logging staff is needed for old slot. For
8642 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8643 * new and it's also covered when dealing with the new slot.
8644 *
8645 * FIXME: const-ify all uses of struct kvm_memory_slot.
8646 */
8647 if (change != KVM_MR_DELETE)
8648 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8649 }
8650
8651 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8652 {
8653 kvm_mmu_invalidate_zap_all_pages(kvm);
8654 }
8655
8656 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8657 struct kvm_memory_slot *slot)
8658 {
8659 kvm_page_track_flush_slot(kvm, slot);
8660 }
8661
8662 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8663 {
8664 if (!list_empty_careful(&vcpu->async_pf.done))
8665 return true;
8666
8667 if (kvm_apic_has_events(vcpu))
8668 return true;
8669
8670 if (vcpu->arch.pv.pv_unhalted)
8671 return true;
8672
8673 if (vcpu->arch.exception.pending)
8674 return true;
8675
8676 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8677 (vcpu->arch.nmi_pending &&
8678 kvm_x86_ops->nmi_allowed(vcpu)))
8679 return true;
8680
8681 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8682 (vcpu->arch.smi_pending && !is_smm(vcpu)))
8683 return true;
8684
8685 if (kvm_arch_interrupt_allowed(vcpu) &&
8686 kvm_cpu_has_interrupt(vcpu))
8687 return true;
8688
8689 if (kvm_hv_has_stimer_pending(vcpu))
8690 return true;
8691
8692 return false;
8693 }
8694
8695 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8696 {
8697 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8698 }
8699
8700 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8701 {
8702 return vcpu->arch.preempted_in_kernel;
8703 }
8704
8705 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8706 {
8707 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8708 }
8709
8710 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8711 {
8712 return kvm_x86_ops->interrupt_allowed(vcpu);
8713 }
8714
8715 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8716 {
8717 if (is_64_bit_mode(vcpu))
8718 return kvm_rip_read(vcpu);
8719 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8720 kvm_rip_read(vcpu));
8721 }
8722 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8723
8724 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8725 {
8726 return kvm_get_linear_rip(vcpu) == linear_rip;
8727 }
8728 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8729
8730 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8731 {
8732 unsigned long rflags;
8733
8734 rflags = kvm_x86_ops->get_rflags(vcpu);
8735 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8736 rflags &= ~X86_EFLAGS_TF;
8737 return rflags;
8738 }
8739 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8740
8741 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8742 {
8743 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8744 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8745 rflags |= X86_EFLAGS_TF;
8746 kvm_x86_ops->set_rflags(vcpu, rflags);
8747 }
8748
8749 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8750 {
8751 __kvm_set_rflags(vcpu, rflags);
8752 kvm_make_request(KVM_REQ_EVENT, vcpu);
8753 }
8754 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8755
8756 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8757 {
8758 int r;
8759
8760 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8761 work->wakeup_all)
8762 return;
8763
8764 r = kvm_mmu_reload(vcpu);
8765 if (unlikely(r))
8766 return;
8767
8768 if (!vcpu->arch.mmu.direct_map &&
8769 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8770 return;
8771
8772 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8773 }
8774
8775 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8776 {
8777 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8778 }
8779
8780 static inline u32 kvm_async_pf_next_probe(u32 key)
8781 {
8782 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8783 }
8784
8785 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8786 {
8787 u32 key = kvm_async_pf_hash_fn(gfn);
8788
8789 while (vcpu->arch.apf.gfns[key] != ~0)
8790 key = kvm_async_pf_next_probe(key);
8791
8792 vcpu->arch.apf.gfns[key] = gfn;
8793 }
8794
8795 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8796 {
8797 int i;
8798 u32 key = kvm_async_pf_hash_fn(gfn);
8799
8800 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8801 (vcpu->arch.apf.gfns[key] != gfn &&
8802 vcpu->arch.apf.gfns[key] != ~0); i++)
8803 key = kvm_async_pf_next_probe(key);
8804
8805 return key;
8806 }
8807
8808 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8809 {
8810 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8811 }
8812
8813 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8814 {
8815 u32 i, j, k;
8816
8817 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8818 while (true) {
8819 vcpu->arch.apf.gfns[i] = ~0;
8820 do {
8821 j = kvm_async_pf_next_probe(j);
8822 if (vcpu->arch.apf.gfns[j] == ~0)
8823 return;
8824 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8825 /*
8826 * k lies cyclically in ]i,j]
8827 * | i.k.j |
8828 * |....j i.k.| or |.k..j i...|
8829 */
8830 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8831 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8832 i = j;
8833 }
8834 }
8835
8836 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8837 {
8838
8839 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8840 sizeof(val));
8841 }
8842
8843 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8844 {
8845
8846 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8847 sizeof(u32));
8848 }
8849
8850 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8851 struct kvm_async_pf *work)
8852 {
8853 struct x86_exception fault;
8854
8855 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8856 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8857
8858 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8859 (vcpu->arch.apf.send_user_only &&
8860 kvm_x86_ops->get_cpl(vcpu) == 0))
8861 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8862 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8863 fault.vector = PF_VECTOR;
8864 fault.error_code_valid = true;
8865 fault.error_code = 0;
8866 fault.nested_page_fault = false;
8867 fault.address = work->arch.token;
8868 fault.async_page_fault = true;
8869 kvm_inject_page_fault(vcpu, &fault);
8870 }
8871 }
8872
8873 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8874 struct kvm_async_pf *work)
8875 {
8876 struct x86_exception fault;
8877 u32 val;
8878
8879 if (work->wakeup_all)
8880 work->arch.token = ~0; /* broadcast wakeup */
8881 else
8882 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8883 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8884
8885 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8886 !apf_get_user(vcpu, &val)) {
8887 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8888 vcpu->arch.exception.pending &&
8889 vcpu->arch.exception.nr == PF_VECTOR &&
8890 !apf_put_user(vcpu, 0)) {
8891 vcpu->arch.exception.injected = false;
8892 vcpu->arch.exception.pending = false;
8893 vcpu->arch.exception.nr = 0;
8894 vcpu->arch.exception.has_error_code = false;
8895 vcpu->arch.exception.error_code = 0;
8896 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8897 fault.vector = PF_VECTOR;
8898 fault.error_code_valid = true;
8899 fault.error_code = 0;
8900 fault.nested_page_fault = false;
8901 fault.address = work->arch.token;
8902 fault.async_page_fault = true;
8903 kvm_inject_page_fault(vcpu, &fault);
8904 }
8905 }
8906 vcpu->arch.apf.halted = false;
8907 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8908 }
8909
8910 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8911 {
8912 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8913 return true;
8914 else
8915 return kvm_can_do_async_pf(vcpu);
8916 }
8917
8918 void kvm_arch_start_assignment(struct kvm *kvm)
8919 {
8920 atomic_inc(&kvm->arch.assigned_device_count);
8921 }
8922 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8923
8924 void kvm_arch_end_assignment(struct kvm *kvm)
8925 {
8926 atomic_dec(&kvm->arch.assigned_device_count);
8927 }
8928 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8929
8930 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8931 {
8932 return atomic_read(&kvm->arch.assigned_device_count);
8933 }
8934 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8935
8936 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8937 {
8938 atomic_inc(&kvm->arch.noncoherent_dma_count);
8939 }
8940 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8941
8942 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8943 {
8944 atomic_dec(&kvm->arch.noncoherent_dma_count);
8945 }
8946 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8947
8948 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8949 {
8950 return atomic_read(&kvm->arch.noncoherent_dma_count);
8951 }
8952 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8953
8954 bool kvm_arch_has_irq_bypass(void)
8955 {
8956 return kvm_x86_ops->update_pi_irte != NULL;
8957 }
8958
8959 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8960 struct irq_bypass_producer *prod)
8961 {
8962 struct kvm_kernel_irqfd *irqfd =
8963 container_of(cons, struct kvm_kernel_irqfd, consumer);
8964
8965 irqfd->producer = prod;
8966
8967 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8968 prod->irq, irqfd->gsi, 1);
8969 }
8970
8971 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8972 struct irq_bypass_producer *prod)
8973 {
8974 int ret;
8975 struct kvm_kernel_irqfd *irqfd =
8976 container_of(cons, struct kvm_kernel_irqfd, consumer);
8977
8978 WARN_ON(irqfd->producer != prod);
8979 irqfd->producer = NULL;
8980
8981 /*
8982 * When producer of consumer is unregistered, we change back to
8983 * remapped mode, so we can re-use the current implementation
8984 * when the irq is masked/disabled or the consumer side (KVM
8985 * int this case doesn't want to receive the interrupts.
8986 */
8987 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8988 if (ret)
8989 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8990 " fails: %d\n", irqfd->consumer.token, ret);
8991 }
8992
8993 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8994 uint32_t guest_irq, bool set)
8995 {
8996 if (!kvm_x86_ops->update_pi_irte)
8997 return -EINVAL;
8998
8999 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9000 }
9001
9002 bool kvm_vector_hashing_enabled(void)
9003 {
9004 return vector_hashing;
9005 }
9006 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9007
9008 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
9009 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
9010 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9011 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9012 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9013 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
9014 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
9015 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
9016 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
9017 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
9018 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
9019 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
9020 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
9021 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
9022 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
9023 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
9024 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
9025 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9026 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);