2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id
[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
66 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
68 static bool __read_mostly enable_vpid
= 1;
69 module_param_named(vpid
, enable_vpid
, bool, 0444);
71 static bool __read_mostly flexpriority_enabled
= 1;
72 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
74 static bool __read_mostly enable_ept
= 1;
75 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
77 static bool __read_mostly enable_unrestricted_guest
= 1;
78 module_param_named(unrestricted_guest
,
79 enable_unrestricted_guest
, bool, S_IRUGO
);
81 static bool __read_mostly enable_ept_ad_bits
= 1;
82 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
84 static bool __read_mostly emulate_invalid_guest_state
= true;
85 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
87 static bool __read_mostly fasteoi
= 1;
88 module_param(fasteoi
, bool, S_IRUGO
);
90 static bool __read_mostly enable_apicv
= 1;
91 module_param(enable_apicv
, bool, S_IRUGO
);
93 static bool __read_mostly enable_shadow_vmcs
= 1;
94 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
100 static bool __read_mostly nested
= 0;
101 module_param(nested
, bool, S_IRUGO
);
103 static u64 __read_mostly host_xss
;
105 static bool __read_mostly enable_pml
= 1;
106 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
108 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
110 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
111 static int __read_mostly cpu_preemption_timer_multi
;
112 static bool __read_mostly enable_preemption_timer
= 1;
114 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
117 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
118 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
119 #define KVM_VM_CR0_ALWAYS_ON \
120 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
121 #define KVM_CR4_GUEST_OWNED_BITS \
122 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
123 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
125 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
126 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
128 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
130 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
133 * Hyper-V requires all of these, so mark them as supported even though
134 * they are just treated the same as all-context.
136 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
137 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
138 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
139 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
140 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
143 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
144 * ple_gap: upper bound on the amount of time between two successive
145 * executions of PAUSE in a loop. Also indicate if ple enabled.
146 * According to test, this time is usually smaller than 128 cycles.
147 * ple_window: upper bound on the amount of time a guest is allowed to execute
148 * in a PAUSE loop. Tests indicate that most spinlocks are held for
149 * less than 2^12 cycles
150 * Time is measured based on a counter that runs at the same rate as the TSC,
151 * refer SDM volume 3b section 21.6.13 & 22.1.3.
153 #define KVM_VMX_DEFAULT_PLE_GAP 128
154 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
155 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
156 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
157 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
158 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
160 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
161 module_param(ple_gap
, int, S_IRUGO
);
163 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
164 module_param(ple_window
, int, S_IRUGO
);
166 /* Default doubles per-vcpu window every exit. */
167 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
168 module_param(ple_window_grow
, int, S_IRUGO
);
170 /* Default resets per-vcpu window every exit to ple_window. */
171 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
172 module_param(ple_window_shrink
, int, S_IRUGO
);
174 /* Default is to compute the maximum so we can never overflow. */
175 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
176 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
177 module_param(ple_window_max
, int, S_IRUGO
);
179 extern const ulong vmx_return
;
181 #define NR_AUTOLOAD_MSRS 8
182 #define VMCS02_POOL_SIZE 1
191 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
192 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
193 * loaded on this CPU (so we can clear them if the CPU goes down).
197 struct vmcs
*shadow_vmcs
;
200 struct list_head loaded_vmcss_on_cpu_link
;
203 struct shared_msr_entry
{
210 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
211 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
212 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
213 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
214 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
215 * More than one of these structures may exist, if L1 runs multiple L2 guests.
216 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
217 * underlying hardware which will be used to run L2.
218 * This structure is packed to ensure that its layout is identical across
219 * machines (necessary for live migration).
220 * If there are changes in this struct, VMCS12_REVISION must be changed.
222 typedef u64 natural_width
;
223 struct __packed vmcs12
{
224 /* According to the Intel spec, a VMCS region must start with the
225 * following two fields. Then follow implementation-specific data.
230 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
231 u32 padding
[7]; /* room for future expansion */
236 u64 vm_exit_msr_store_addr
;
237 u64 vm_exit_msr_load_addr
;
238 u64 vm_entry_msr_load_addr
;
240 u64 virtual_apic_page_addr
;
241 u64 apic_access_addr
;
242 u64 posted_intr_desc_addr
;
244 u64 eoi_exit_bitmap0
;
245 u64 eoi_exit_bitmap1
;
246 u64 eoi_exit_bitmap2
;
247 u64 eoi_exit_bitmap3
;
249 u64 guest_physical_address
;
250 u64 vmcs_link_pointer
;
252 u64 guest_ia32_debugctl
;
255 u64 guest_ia32_perf_global_ctrl
;
263 u64 host_ia32_perf_global_ctrl
;
264 u64 padding64
[8]; /* room for future expansion */
266 * To allow migration of L1 (complete with its L2 guests) between
267 * machines of different natural widths (32 or 64 bit), we cannot have
268 * unsigned long fields with no explict size. We use u64 (aliased
269 * natural_width) instead. Luckily, x86 is little-endian.
271 natural_width cr0_guest_host_mask
;
272 natural_width cr4_guest_host_mask
;
273 natural_width cr0_read_shadow
;
274 natural_width cr4_read_shadow
;
275 natural_width cr3_target_value0
;
276 natural_width cr3_target_value1
;
277 natural_width cr3_target_value2
;
278 natural_width cr3_target_value3
;
279 natural_width exit_qualification
;
280 natural_width guest_linear_address
;
281 natural_width guest_cr0
;
282 natural_width guest_cr3
;
283 natural_width guest_cr4
;
284 natural_width guest_es_base
;
285 natural_width guest_cs_base
;
286 natural_width guest_ss_base
;
287 natural_width guest_ds_base
;
288 natural_width guest_fs_base
;
289 natural_width guest_gs_base
;
290 natural_width guest_ldtr_base
;
291 natural_width guest_tr_base
;
292 natural_width guest_gdtr_base
;
293 natural_width guest_idtr_base
;
294 natural_width guest_dr7
;
295 natural_width guest_rsp
;
296 natural_width guest_rip
;
297 natural_width guest_rflags
;
298 natural_width guest_pending_dbg_exceptions
;
299 natural_width guest_sysenter_esp
;
300 natural_width guest_sysenter_eip
;
301 natural_width host_cr0
;
302 natural_width host_cr3
;
303 natural_width host_cr4
;
304 natural_width host_fs_base
;
305 natural_width host_gs_base
;
306 natural_width host_tr_base
;
307 natural_width host_gdtr_base
;
308 natural_width host_idtr_base
;
309 natural_width host_ia32_sysenter_esp
;
310 natural_width host_ia32_sysenter_eip
;
311 natural_width host_rsp
;
312 natural_width host_rip
;
313 natural_width paddingl
[8]; /* room for future expansion */
314 u32 pin_based_vm_exec_control
;
315 u32 cpu_based_vm_exec_control
;
316 u32 exception_bitmap
;
317 u32 page_fault_error_code_mask
;
318 u32 page_fault_error_code_match
;
319 u32 cr3_target_count
;
320 u32 vm_exit_controls
;
321 u32 vm_exit_msr_store_count
;
322 u32 vm_exit_msr_load_count
;
323 u32 vm_entry_controls
;
324 u32 vm_entry_msr_load_count
;
325 u32 vm_entry_intr_info_field
;
326 u32 vm_entry_exception_error_code
;
327 u32 vm_entry_instruction_len
;
329 u32 secondary_vm_exec_control
;
330 u32 vm_instruction_error
;
332 u32 vm_exit_intr_info
;
333 u32 vm_exit_intr_error_code
;
334 u32 idt_vectoring_info_field
;
335 u32 idt_vectoring_error_code
;
336 u32 vm_exit_instruction_len
;
337 u32 vmx_instruction_info
;
344 u32 guest_ldtr_limit
;
346 u32 guest_gdtr_limit
;
347 u32 guest_idtr_limit
;
348 u32 guest_es_ar_bytes
;
349 u32 guest_cs_ar_bytes
;
350 u32 guest_ss_ar_bytes
;
351 u32 guest_ds_ar_bytes
;
352 u32 guest_fs_ar_bytes
;
353 u32 guest_gs_ar_bytes
;
354 u32 guest_ldtr_ar_bytes
;
355 u32 guest_tr_ar_bytes
;
356 u32 guest_interruptibility_info
;
357 u32 guest_activity_state
;
358 u32 guest_sysenter_cs
;
359 u32 host_ia32_sysenter_cs
;
360 u32 vmx_preemption_timer_value
;
361 u32 padding32
[7]; /* room for future expansion */
362 u16 virtual_processor_id
;
364 u16 guest_es_selector
;
365 u16 guest_cs_selector
;
366 u16 guest_ss_selector
;
367 u16 guest_ds_selector
;
368 u16 guest_fs_selector
;
369 u16 guest_gs_selector
;
370 u16 guest_ldtr_selector
;
371 u16 guest_tr_selector
;
372 u16 guest_intr_status
;
374 u16 host_es_selector
;
375 u16 host_cs_selector
;
376 u16 host_ss_selector
;
377 u16 host_ds_selector
;
378 u16 host_fs_selector
;
379 u16 host_gs_selector
;
380 u16 host_tr_selector
;
384 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
385 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
386 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
388 #define VMCS12_REVISION 0x11e57ed0
391 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
392 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
393 * current implementation, 4K are reserved to avoid future complications.
395 #define VMCS12_SIZE 0x1000
397 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
399 struct list_head list
;
401 struct loaded_vmcs vmcs02
;
405 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
406 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
409 /* Has the level1 guest done vmxon? */
414 /* The guest-physical address of the current VMCS L1 keeps for L2 */
416 /* The host-usable pointer to the above */
417 struct page
*current_vmcs12_page
;
418 struct vmcs12
*current_vmcs12
;
420 * Cache of the guest's VMCS, existing outside of guest memory.
421 * Loaded from guest memory during VMPTRLD. Flushed to guest
422 * memory during VMXOFF, VMCLEAR, VMPTRLD.
424 struct vmcs12
*cached_vmcs12
;
426 * Indicates if the shadow vmcs must be updated with the
427 * data hold by vmcs12
429 bool sync_shadow_vmcs
;
431 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
432 struct list_head vmcs02_pool
;
434 bool change_vmcs01_virtual_x2apic_mode
;
435 /* L2 must run next, and mustn't decide to exit to L1. */
436 bool nested_run_pending
;
438 * Guest pages referred to in vmcs02 with host-physical pointers, so
439 * we must keep them pinned while L2 runs.
441 struct page
*apic_access_page
;
442 struct page
*virtual_apic_page
;
443 struct page
*pi_desc_page
;
444 struct pi_desc
*pi_desc
;
448 unsigned long *msr_bitmap
;
450 struct hrtimer preemption_timer
;
451 bool preemption_timer_expired
;
453 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
460 * We only store the "true" versions of the VMX capability MSRs. We
461 * generate the "non-true" versions by setting the must-be-1 bits
462 * according to the SDM.
464 u32 nested_vmx_procbased_ctls_low
;
465 u32 nested_vmx_procbased_ctls_high
;
466 u32 nested_vmx_secondary_ctls_low
;
467 u32 nested_vmx_secondary_ctls_high
;
468 u32 nested_vmx_pinbased_ctls_low
;
469 u32 nested_vmx_pinbased_ctls_high
;
470 u32 nested_vmx_exit_ctls_low
;
471 u32 nested_vmx_exit_ctls_high
;
472 u32 nested_vmx_entry_ctls_low
;
473 u32 nested_vmx_entry_ctls_high
;
474 u32 nested_vmx_misc_low
;
475 u32 nested_vmx_misc_high
;
476 u32 nested_vmx_ept_caps
;
477 u32 nested_vmx_vpid_caps
;
478 u64 nested_vmx_basic
;
479 u64 nested_vmx_cr0_fixed0
;
480 u64 nested_vmx_cr0_fixed1
;
481 u64 nested_vmx_cr4_fixed0
;
482 u64 nested_vmx_cr4_fixed1
;
483 u64 nested_vmx_vmcs_enum
;
486 #define POSTED_INTR_ON 0
487 #define POSTED_INTR_SN 1
489 /* Posted-Interrupt Descriptor */
491 u32 pir
[8]; /* Posted interrupt requested */
494 /* bit 256 - Outstanding Notification */
496 /* bit 257 - Suppress Notification */
498 /* bit 271:258 - Reserved */
500 /* bit 279:272 - Notification Vector */
502 /* bit 287:280 - Reserved */
504 /* bit 319:288 - Notification Destination */
512 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
514 return test_and_set_bit(POSTED_INTR_ON
,
515 (unsigned long *)&pi_desc
->control
);
518 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
520 return test_and_clear_bit(POSTED_INTR_ON
,
521 (unsigned long *)&pi_desc
->control
);
524 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
526 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
529 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
531 return clear_bit(POSTED_INTR_SN
,
532 (unsigned long *)&pi_desc
->control
);
535 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
537 return set_bit(POSTED_INTR_SN
,
538 (unsigned long *)&pi_desc
->control
);
541 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
543 clear_bit(POSTED_INTR_ON
,
544 (unsigned long *)&pi_desc
->control
);
547 static inline int pi_test_on(struct pi_desc
*pi_desc
)
549 return test_bit(POSTED_INTR_ON
,
550 (unsigned long *)&pi_desc
->control
);
553 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
555 return test_bit(POSTED_INTR_SN
,
556 (unsigned long *)&pi_desc
->control
);
560 struct kvm_vcpu vcpu
;
561 unsigned long host_rsp
;
563 bool nmi_known_unmasked
;
565 u32 idt_vectoring_info
;
567 struct shared_msr_entry
*guest_msrs
;
570 unsigned long host_idt_base
;
572 u64 msr_host_kernel_gs_base
;
573 u64 msr_guest_kernel_gs_base
;
575 u32 vm_entry_controls_shadow
;
576 u32 vm_exit_controls_shadow
;
578 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
579 * non-nested (L1) guest, it always points to vmcs01. For a nested
580 * guest (L2), it points to a different VMCS.
582 struct loaded_vmcs vmcs01
;
583 struct loaded_vmcs
*loaded_vmcs
;
584 bool __launched
; /* temporary, used in vmx_vcpu_run */
585 struct msr_autoload
{
587 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
588 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
592 u16 fs_sel
, gs_sel
, ldt_sel
;
596 int gs_ldt_reload_needed
;
597 int fs_reload_needed
;
598 u64 msr_host_bndcfgs
;
599 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
604 struct kvm_segment segs
[8];
607 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
608 struct kvm_save_segment
{
616 bool emulation_required
;
620 /* Posted interrupt descriptor */
621 struct pi_desc pi_desc
;
623 /* Support for a guest hypervisor (nested VMX) */
624 struct nested_vmx nested
;
626 /* Dynamic PLE window. */
628 bool ple_window_dirty
;
630 /* Support for PML */
631 #define PML_ENTITY_NUM 512
634 /* apic deadline value in host tsc */
637 u64 current_tsc_ratio
;
639 bool guest_pkru_valid
;
644 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
645 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
646 * in msr_ia32_feature_control_valid_bits.
648 u64 msr_ia32_feature_control
;
649 u64 msr_ia32_feature_control_valid_bits
;
652 enum segment_cache_field
{
661 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
663 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
666 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
668 return &(to_vmx(vcpu
)->pi_desc
);
671 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
672 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
673 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
674 [number##_HIGH] = VMCS12_OFFSET(name)+4
677 static unsigned long shadow_read_only_fields
[] = {
679 * We do NOT shadow fields that are modified when L0
680 * traps and emulates any vmx instruction (e.g. VMPTRLD,
681 * VMXON...) executed by L1.
682 * For example, VM_INSTRUCTION_ERROR is read
683 * by L1 if a vmx instruction fails (part of the error path).
684 * Note the code assumes this logic. If for some reason
685 * we start shadowing these fields then we need to
686 * force a shadow sync when L0 emulates vmx instructions
687 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
688 * by nested_vmx_failValid)
692 VM_EXIT_INSTRUCTION_LEN
,
693 IDT_VECTORING_INFO_FIELD
,
694 IDT_VECTORING_ERROR_CODE
,
695 VM_EXIT_INTR_ERROR_CODE
,
697 GUEST_LINEAR_ADDRESS
,
698 GUEST_PHYSICAL_ADDRESS
700 static int max_shadow_read_only_fields
=
701 ARRAY_SIZE(shadow_read_only_fields
);
703 static unsigned long shadow_read_write_fields
[] = {
710 GUEST_INTERRUPTIBILITY_INFO
,
723 CPU_BASED_VM_EXEC_CONTROL
,
724 VM_ENTRY_EXCEPTION_ERROR_CODE
,
725 VM_ENTRY_INTR_INFO_FIELD
,
726 VM_ENTRY_INSTRUCTION_LEN
,
727 VM_ENTRY_EXCEPTION_ERROR_CODE
,
733 static int max_shadow_read_write_fields
=
734 ARRAY_SIZE(shadow_read_write_fields
);
736 static const unsigned short vmcs_field_to_offset_table
[] = {
737 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
738 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
739 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
740 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
741 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
742 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
743 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
744 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
745 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
746 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
747 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
748 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
749 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
750 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
751 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
752 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
753 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
754 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
755 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
756 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
757 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
758 FIELD64(MSR_BITMAP
, msr_bitmap
),
759 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
760 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
761 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
762 FIELD64(TSC_OFFSET
, tsc_offset
),
763 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
764 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
765 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
766 FIELD64(EPT_POINTER
, ept_pointer
),
767 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
768 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
769 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
770 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
771 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
772 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
773 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
774 FIELD64(PML_ADDRESS
, pml_address
),
775 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
776 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
777 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
778 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
779 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
780 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
781 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
782 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
783 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
784 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
785 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
786 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
787 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
788 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
789 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
790 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
791 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
792 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
793 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
794 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
795 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
796 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
797 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
798 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
799 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
800 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
801 FIELD(TPR_THRESHOLD
, tpr_threshold
),
802 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
803 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
804 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
805 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
806 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
807 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
808 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
809 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
810 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
811 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
812 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
813 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
814 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
815 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
816 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
817 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
818 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
819 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
820 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
821 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
822 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
823 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
824 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
825 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
826 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
827 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
828 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
829 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
830 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
831 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
832 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
833 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
834 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
835 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
836 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
837 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
838 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
839 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
840 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
841 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
842 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
843 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
844 FIELD(GUEST_CR0
, guest_cr0
),
845 FIELD(GUEST_CR3
, guest_cr3
),
846 FIELD(GUEST_CR4
, guest_cr4
),
847 FIELD(GUEST_ES_BASE
, guest_es_base
),
848 FIELD(GUEST_CS_BASE
, guest_cs_base
),
849 FIELD(GUEST_SS_BASE
, guest_ss_base
),
850 FIELD(GUEST_DS_BASE
, guest_ds_base
),
851 FIELD(GUEST_FS_BASE
, guest_fs_base
),
852 FIELD(GUEST_GS_BASE
, guest_gs_base
),
853 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
854 FIELD(GUEST_TR_BASE
, guest_tr_base
),
855 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
856 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
857 FIELD(GUEST_DR7
, guest_dr7
),
858 FIELD(GUEST_RSP
, guest_rsp
),
859 FIELD(GUEST_RIP
, guest_rip
),
860 FIELD(GUEST_RFLAGS
, guest_rflags
),
861 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
862 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
863 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
864 FIELD(HOST_CR0
, host_cr0
),
865 FIELD(HOST_CR3
, host_cr3
),
866 FIELD(HOST_CR4
, host_cr4
),
867 FIELD(HOST_FS_BASE
, host_fs_base
),
868 FIELD(HOST_GS_BASE
, host_gs_base
),
869 FIELD(HOST_TR_BASE
, host_tr_base
),
870 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
871 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
872 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
873 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
874 FIELD(HOST_RSP
, host_rsp
),
875 FIELD(HOST_RIP
, host_rip
),
878 static inline short vmcs_field_to_offset(unsigned long field
)
880 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
882 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
883 vmcs_field_to_offset_table
[field
] == 0)
886 return vmcs_field_to_offset_table
[field
];
889 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
891 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
894 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
896 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
897 if (is_error_page(page
))
903 static void nested_release_page(struct page
*page
)
905 kvm_release_page_dirty(page
);
908 static void nested_release_page_clean(struct page
*page
)
910 kvm_release_page_clean(page
);
913 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
914 static u64
construct_eptp(unsigned long root_hpa
);
915 static bool vmx_xsaves_supported(void);
916 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
917 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
918 struct kvm_segment
*var
, int seg
);
919 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
920 struct kvm_segment
*var
, int seg
);
921 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
922 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
923 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
924 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
925 static int alloc_identity_pagetable(struct kvm
*kvm
);
927 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
928 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
930 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
931 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
933 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
936 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
937 * can find which vCPU should be waken up.
939 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
940 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
945 VMX_MSR_BITMAP_LEGACY
,
946 VMX_MSR_BITMAP_LONGMODE
,
947 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
948 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
949 VMX_MSR_BITMAP_LEGACY_X2APIC
,
950 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
956 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
958 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
959 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
960 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
961 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
962 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
963 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
964 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
965 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
966 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
967 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
969 static bool cpu_has_load_ia32_efer
;
970 static bool cpu_has_load_perf_global_ctrl
;
972 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
973 static DEFINE_SPINLOCK(vmx_vpid_lock
);
975 static struct vmcs_config
{
980 u32 pin_based_exec_ctrl
;
981 u32 cpu_based_exec_ctrl
;
982 u32 cpu_based_2nd_exec_ctrl
;
987 static struct vmx_capability
{
992 #define VMX_SEGMENT_FIELD(seg) \
993 [VCPU_SREG_##seg] = { \
994 .selector = GUEST_##seg##_SELECTOR, \
995 .base = GUEST_##seg##_BASE, \
996 .limit = GUEST_##seg##_LIMIT, \
997 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1000 static const struct kvm_vmx_segment_field
{
1005 } kvm_vmx_segment_fields
[] = {
1006 VMX_SEGMENT_FIELD(CS
),
1007 VMX_SEGMENT_FIELD(DS
),
1008 VMX_SEGMENT_FIELD(ES
),
1009 VMX_SEGMENT_FIELD(FS
),
1010 VMX_SEGMENT_FIELD(GS
),
1011 VMX_SEGMENT_FIELD(SS
),
1012 VMX_SEGMENT_FIELD(TR
),
1013 VMX_SEGMENT_FIELD(LDTR
),
1016 static u64 host_efer
;
1018 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1021 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1022 * away by decrementing the array size.
1024 static const u32 vmx_msr_index
[] = {
1025 #ifdef CONFIG_X86_64
1026 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1028 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1031 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1033 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1034 INTR_INFO_VALID_MASK
)) ==
1035 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1038 static inline bool is_debug(u32 intr_info
)
1040 return is_exception_n(intr_info
, DB_VECTOR
);
1043 static inline bool is_breakpoint(u32 intr_info
)
1045 return is_exception_n(intr_info
, BP_VECTOR
);
1048 static inline bool is_page_fault(u32 intr_info
)
1050 return is_exception_n(intr_info
, PF_VECTOR
);
1053 static inline bool is_no_device(u32 intr_info
)
1055 return is_exception_n(intr_info
, NM_VECTOR
);
1058 static inline bool is_invalid_opcode(u32 intr_info
)
1060 return is_exception_n(intr_info
, UD_VECTOR
);
1063 static inline bool is_external_interrupt(u32 intr_info
)
1065 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1066 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1069 static inline bool is_machine_check(u32 intr_info
)
1071 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1072 INTR_INFO_VALID_MASK
)) ==
1073 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1076 static inline bool cpu_has_vmx_msr_bitmap(void)
1078 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1081 static inline bool cpu_has_vmx_tpr_shadow(void)
1083 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1086 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1088 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1091 static inline bool cpu_has_secondary_exec_ctrls(void)
1093 return vmcs_config
.cpu_based_exec_ctrl
&
1094 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1097 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1099 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1100 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1103 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1105 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1106 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1109 static inline bool cpu_has_vmx_apic_register_virt(void)
1111 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1112 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1115 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1117 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1118 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1122 * Comment's format: document - errata name - stepping - processor name.
1124 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1126 static u32 vmx_preemption_cpu_tfms
[] = {
1127 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1129 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1130 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1131 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1133 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1135 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1136 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1138 * 320767.pdf - AAP86 - B1 -
1139 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1142 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1144 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1146 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1148 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1149 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1150 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1154 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1156 u32 eax
= cpuid_eax(0x00000001), i
;
1158 /* Clear the reserved bits */
1159 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1160 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1161 if (eax
== vmx_preemption_cpu_tfms
[i
])
1167 static inline bool cpu_has_vmx_preemption_timer(void)
1169 return vmcs_config
.pin_based_exec_ctrl
&
1170 PIN_BASED_VMX_PREEMPTION_TIMER
;
1173 static inline bool cpu_has_vmx_posted_intr(void)
1175 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1176 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1179 static inline bool cpu_has_vmx_apicv(void)
1181 return cpu_has_vmx_apic_register_virt() &&
1182 cpu_has_vmx_virtual_intr_delivery() &&
1183 cpu_has_vmx_posted_intr();
1186 static inline bool cpu_has_vmx_flexpriority(void)
1188 return cpu_has_vmx_tpr_shadow() &&
1189 cpu_has_vmx_virtualize_apic_accesses();
1192 static inline bool cpu_has_vmx_ept_execute_only(void)
1194 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1197 static inline bool cpu_has_vmx_ept_2m_page(void)
1199 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1202 static inline bool cpu_has_vmx_ept_1g_page(void)
1204 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1207 static inline bool cpu_has_vmx_ept_4levels(void)
1209 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1212 static inline bool cpu_has_vmx_ept_ad_bits(void)
1214 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1217 static inline bool cpu_has_vmx_invept_context(void)
1219 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1222 static inline bool cpu_has_vmx_invept_global(void)
1224 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1227 static inline bool cpu_has_vmx_invvpid_single(void)
1229 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1232 static inline bool cpu_has_vmx_invvpid_global(void)
1234 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1237 static inline bool cpu_has_vmx_invvpid(void)
1239 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1242 static inline bool cpu_has_vmx_ept(void)
1244 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1245 SECONDARY_EXEC_ENABLE_EPT
;
1248 static inline bool cpu_has_vmx_unrestricted_guest(void)
1250 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1251 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1254 static inline bool cpu_has_vmx_ple(void)
1256 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1257 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1260 static inline bool cpu_has_vmx_basic_inout(void)
1262 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1265 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1267 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1270 static inline bool cpu_has_vmx_vpid(void)
1272 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1273 SECONDARY_EXEC_ENABLE_VPID
;
1276 static inline bool cpu_has_vmx_rdtscp(void)
1278 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1279 SECONDARY_EXEC_RDTSCP
;
1282 static inline bool cpu_has_vmx_invpcid(void)
1284 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1285 SECONDARY_EXEC_ENABLE_INVPCID
;
1288 static inline bool cpu_has_vmx_wbinvd_exit(void)
1290 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1291 SECONDARY_EXEC_WBINVD_EXITING
;
1294 static inline bool cpu_has_vmx_shadow_vmcs(void)
1297 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1298 /* check if the cpu supports writing r/o exit information fields */
1299 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1302 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1303 SECONDARY_EXEC_SHADOW_VMCS
;
1306 static inline bool cpu_has_vmx_pml(void)
1308 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1311 static inline bool cpu_has_vmx_tsc_scaling(void)
1313 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1314 SECONDARY_EXEC_TSC_SCALING
;
1317 static inline bool report_flexpriority(void)
1319 return flexpriority_enabled
;
1322 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1324 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1327 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1329 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1332 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1334 return (vmcs12
->cpu_based_vm_exec_control
&
1335 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1336 (vmcs12
->secondary_vm_exec_control
& bit
);
1339 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1341 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1344 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1346 return vmcs12
->pin_based_vm_exec_control
&
1347 PIN_BASED_VMX_PREEMPTION_TIMER
;
1350 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1352 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1355 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1357 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1358 vmx_xsaves_supported();
1361 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1363 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1366 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1368 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1371 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1373 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1376 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1378 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1381 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1383 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1386 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1388 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1391 static inline bool is_nmi(u32 intr_info
)
1393 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1394 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1397 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1399 unsigned long exit_qualification
);
1400 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1401 struct vmcs12
*vmcs12
,
1402 u32 reason
, unsigned long qualification
);
1404 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1408 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1409 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1414 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1420 } operand
= { vpid
, 0, gva
};
1422 asm volatile (__ex(ASM_VMX_INVVPID
)
1423 /* CF==1 or ZF==1 --> rc = -1 */
1424 "; ja 1f ; ud2 ; 1:"
1425 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1428 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1432 } operand
= {eptp
, gpa
};
1434 asm volatile (__ex(ASM_VMX_INVEPT
)
1435 /* CF==1 or ZF==1 --> rc = -1 */
1436 "; ja 1f ; ud2 ; 1:\n"
1437 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1440 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1444 i
= __find_msr_index(vmx
, msr
);
1446 return &vmx
->guest_msrs
[i
];
1450 static void vmcs_clear(struct vmcs
*vmcs
)
1452 u64 phys_addr
= __pa(vmcs
);
1455 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1456 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1459 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1463 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1465 vmcs_clear(loaded_vmcs
->vmcs
);
1466 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1467 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1468 loaded_vmcs
->cpu
= -1;
1469 loaded_vmcs
->launched
= 0;
1472 static void vmcs_load(struct vmcs
*vmcs
)
1474 u64 phys_addr
= __pa(vmcs
);
1477 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1478 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1481 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1485 #ifdef CONFIG_KEXEC_CORE
1487 * This bitmap is used to indicate whether the vmclear
1488 * operation is enabled on all cpus. All disabled by
1491 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1493 static inline void crash_enable_local_vmclear(int cpu
)
1495 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1498 static inline void crash_disable_local_vmclear(int cpu
)
1500 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1503 static inline int crash_local_vmclear_enabled(int cpu
)
1505 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1508 static void crash_vmclear_local_loaded_vmcss(void)
1510 int cpu
= raw_smp_processor_id();
1511 struct loaded_vmcs
*v
;
1513 if (!crash_local_vmclear_enabled(cpu
))
1516 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1517 loaded_vmcss_on_cpu_link
)
1518 vmcs_clear(v
->vmcs
);
1521 static inline void crash_enable_local_vmclear(int cpu
) { }
1522 static inline void crash_disable_local_vmclear(int cpu
) { }
1523 #endif /* CONFIG_KEXEC_CORE */
1525 static void __loaded_vmcs_clear(void *arg
)
1527 struct loaded_vmcs
*loaded_vmcs
= arg
;
1528 int cpu
= raw_smp_processor_id();
1530 if (loaded_vmcs
->cpu
!= cpu
)
1531 return; /* vcpu migration can race with cpu offline */
1532 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1533 per_cpu(current_vmcs
, cpu
) = NULL
;
1534 crash_disable_local_vmclear(cpu
);
1535 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1538 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1539 * is before setting loaded_vmcs->vcpu to -1 which is done in
1540 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1541 * then adds the vmcs into percpu list before it is deleted.
1545 loaded_vmcs_init(loaded_vmcs
);
1546 crash_enable_local_vmclear(cpu
);
1549 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1551 int cpu
= loaded_vmcs
->cpu
;
1554 smp_call_function_single(cpu
,
1555 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1558 static inline void vpid_sync_vcpu_single(int vpid
)
1563 if (cpu_has_vmx_invvpid_single())
1564 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1567 static inline void vpid_sync_vcpu_global(void)
1569 if (cpu_has_vmx_invvpid_global())
1570 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1573 static inline void vpid_sync_context(int vpid
)
1575 if (cpu_has_vmx_invvpid_single())
1576 vpid_sync_vcpu_single(vpid
);
1578 vpid_sync_vcpu_global();
1581 static inline void ept_sync_global(void)
1583 if (cpu_has_vmx_invept_global())
1584 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1587 static inline void ept_sync_context(u64 eptp
)
1590 if (cpu_has_vmx_invept_context())
1591 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1597 static __always_inline
void vmcs_check16(unsigned long field
)
1599 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1600 "16-bit accessor invalid for 64-bit field");
1601 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1602 "16-bit accessor invalid for 64-bit high field");
1603 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1604 "16-bit accessor invalid for 32-bit high field");
1605 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1606 "16-bit accessor invalid for natural width field");
1609 static __always_inline
void vmcs_check32(unsigned long field
)
1611 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1612 "32-bit accessor invalid for 16-bit field");
1613 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1614 "32-bit accessor invalid for natural width field");
1617 static __always_inline
void vmcs_check64(unsigned long field
)
1619 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1620 "64-bit accessor invalid for 16-bit field");
1621 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1622 "64-bit accessor invalid for 64-bit high field");
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1624 "64-bit accessor invalid for 32-bit field");
1625 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1626 "64-bit accessor invalid for natural width field");
1629 static __always_inline
void vmcs_checkl(unsigned long field
)
1631 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1632 "Natural width accessor invalid for 16-bit field");
1633 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1634 "Natural width accessor invalid for 64-bit field");
1635 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1636 "Natural width accessor invalid for 64-bit high field");
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1638 "Natural width accessor invalid for 32-bit field");
1641 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1643 unsigned long value
;
1645 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1646 : "=a"(value
) : "d"(field
) : "cc");
1650 static __always_inline u16
vmcs_read16(unsigned long field
)
1652 vmcs_check16(field
);
1653 return __vmcs_readl(field
);
1656 static __always_inline u32
vmcs_read32(unsigned long field
)
1658 vmcs_check32(field
);
1659 return __vmcs_readl(field
);
1662 static __always_inline u64
vmcs_read64(unsigned long field
)
1664 vmcs_check64(field
);
1665 #ifdef CONFIG_X86_64
1666 return __vmcs_readl(field
);
1668 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1672 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1675 return __vmcs_readl(field
);
1678 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1680 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1681 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1685 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1689 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1690 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1691 if (unlikely(error
))
1692 vmwrite_error(field
, value
);
1695 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1697 vmcs_check16(field
);
1698 __vmcs_writel(field
, value
);
1701 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1703 vmcs_check32(field
);
1704 __vmcs_writel(field
, value
);
1707 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1709 vmcs_check64(field
);
1710 __vmcs_writel(field
, value
);
1711 #ifndef CONFIG_X86_64
1713 __vmcs_writel(field
+1, value
>> 32);
1717 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1720 __vmcs_writel(field
, value
);
1723 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1725 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1726 "vmcs_clear_bits does not support 64-bit fields");
1727 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1730 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1732 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1733 "vmcs_set_bits does not support 64-bit fields");
1734 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1737 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1739 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1742 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1744 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1745 vmx
->vm_entry_controls_shadow
= val
;
1748 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1750 if (vmx
->vm_entry_controls_shadow
!= val
)
1751 vm_entry_controls_init(vmx
, val
);
1754 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1756 return vmx
->vm_entry_controls_shadow
;
1760 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1762 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1765 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1767 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1770 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1772 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1775 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1777 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1778 vmx
->vm_exit_controls_shadow
= val
;
1781 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1783 if (vmx
->vm_exit_controls_shadow
!= val
)
1784 vm_exit_controls_init(vmx
, val
);
1787 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1789 return vmx
->vm_exit_controls_shadow
;
1793 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1795 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1798 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1800 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1803 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1805 vmx
->segment_cache
.bitmask
= 0;
1808 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1812 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1814 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1815 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1816 vmx
->segment_cache
.bitmask
= 0;
1818 ret
= vmx
->segment_cache
.bitmask
& mask
;
1819 vmx
->segment_cache
.bitmask
|= mask
;
1823 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1825 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1827 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1828 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1832 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1834 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1836 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1837 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1841 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1843 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1845 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1846 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1850 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1852 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1854 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1855 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1859 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1863 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1864 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1865 if ((vcpu
->guest_debug
&
1866 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1867 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1868 eb
|= 1u << BP_VECTOR
;
1869 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1872 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1874 /* When we are running a nested L2 guest and L1 specified for it a
1875 * certain exception bitmap, we must trap the same exceptions and pass
1876 * them to L1. When running L2, we will only handle the exceptions
1877 * specified above if L1 did not want them.
1879 if (is_guest_mode(vcpu
))
1880 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1882 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1885 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1886 unsigned long entry
, unsigned long exit
)
1888 vm_entry_controls_clearbit(vmx
, entry
);
1889 vm_exit_controls_clearbit(vmx
, exit
);
1892 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1895 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1899 if (cpu_has_load_ia32_efer
) {
1900 clear_atomic_switch_msr_special(vmx
,
1901 VM_ENTRY_LOAD_IA32_EFER
,
1902 VM_EXIT_LOAD_IA32_EFER
);
1906 case MSR_CORE_PERF_GLOBAL_CTRL
:
1907 if (cpu_has_load_perf_global_ctrl
) {
1908 clear_atomic_switch_msr_special(vmx
,
1909 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1910 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1916 for (i
= 0; i
< m
->nr
; ++i
)
1917 if (m
->guest
[i
].index
== msr
)
1923 m
->guest
[i
] = m
->guest
[m
->nr
];
1924 m
->host
[i
] = m
->host
[m
->nr
];
1925 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1926 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1929 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1930 unsigned long entry
, unsigned long exit
,
1931 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1932 u64 guest_val
, u64 host_val
)
1934 vmcs_write64(guest_val_vmcs
, guest_val
);
1935 vmcs_write64(host_val_vmcs
, host_val
);
1936 vm_entry_controls_setbit(vmx
, entry
);
1937 vm_exit_controls_setbit(vmx
, exit
);
1940 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1941 u64 guest_val
, u64 host_val
)
1944 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1948 if (cpu_has_load_ia32_efer
) {
1949 add_atomic_switch_msr_special(vmx
,
1950 VM_ENTRY_LOAD_IA32_EFER
,
1951 VM_EXIT_LOAD_IA32_EFER
,
1954 guest_val
, host_val
);
1958 case MSR_CORE_PERF_GLOBAL_CTRL
:
1959 if (cpu_has_load_perf_global_ctrl
) {
1960 add_atomic_switch_msr_special(vmx
,
1961 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1962 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1963 GUEST_IA32_PERF_GLOBAL_CTRL
,
1964 HOST_IA32_PERF_GLOBAL_CTRL
,
1965 guest_val
, host_val
);
1969 case MSR_IA32_PEBS_ENABLE
:
1970 /* PEBS needs a quiescent period after being disabled (to write
1971 * a record). Disabling PEBS through VMX MSR swapping doesn't
1972 * provide that period, so a CPU could write host's record into
1975 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1978 for (i
= 0; i
< m
->nr
; ++i
)
1979 if (m
->guest
[i
].index
== msr
)
1982 if (i
== NR_AUTOLOAD_MSRS
) {
1983 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1984 "Can't add msr %x\n", msr
);
1986 } else if (i
== m
->nr
) {
1988 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1989 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1992 m
->guest
[i
].index
= msr
;
1993 m
->guest
[i
].value
= guest_val
;
1994 m
->host
[i
].index
= msr
;
1995 m
->host
[i
].value
= host_val
;
1998 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2000 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2001 u64 ignore_bits
= 0;
2005 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2006 * host CPUID is more efficient than testing guest CPUID
2007 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2009 if (boot_cpu_has(X86_FEATURE_SMEP
))
2010 guest_efer
|= EFER_NX
;
2011 else if (!(guest_efer
& EFER_NX
))
2012 ignore_bits
|= EFER_NX
;
2016 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2018 ignore_bits
|= EFER_SCE
;
2019 #ifdef CONFIG_X86_64
2020 ignore_bits
|= EFER_LMA
| EFER_LME
;
2021 /* SCE is meaningful only in long mode on Intel */
2022 if (guest_efer
& EFER_LMA
)
2023 ignore_bits
&= ~(u64
)EFER_SCE
;
2026 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2029 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2030 * On CPUs that support "load IA32_EFER", always switch EFER
2031 * atomically, since it's faster than switching it manually.
2033 if (cpu_has_load_ia32_efer
||
2034 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2035 if (!(guest_efer
& EFER_LMA
))
2036 guest_efer
&= ~EFER_LME
;
2037 if (guest_efer
!= host_efer
)
2038 add_atomic_switch_msr(vmx
, MSR_EFER
,
2039 guest_efer
, host_efer
);
2042 guest_efer
&= ~ignore_bits
;
2043 guest_efer
|= host_efer
& ignore_bits
;
2045 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2046 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2052 #ifdef CONFIG_X86_32
2054 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2055 * VMCS rather than the segment table. KVM uses this helper to figure
2056 * out the current bases to poke them into the VMCS before entry.
2058 static unsigned long segment_base(u16 selector
)
2060 struct desc_struct
*table
;
2063 if (!(selector
& ~SEGMENT_RPL_MASK
))
2066 table
= get_current_gdt_ro();
2068 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2069 u16 ldt_selector
= kvm_read_ldt();
2071 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2074 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2076 v
= get_desc_base(&table
[selector
>> 3]);
2081 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2083 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2086 if (vmx
->host_state
.loaded
)
2089 vmx
->host_state
.loaded
= 1;
2091 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2092 * allow segment selectors with cpl > 0 or ti == 1.
2094 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2095 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2096 savesegment(fs
, vmx
->host_state
.fs_sel
);
2097 if (!(vmx
->host_state
.fs_sel
& 7)) {
2098 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2099 vmx
->host_state
.fs_reload_needed
= 0;
2101 vmcs_write16(HOST_FS_SELECTOR
, 0);
2102 vmx
->host_state
.fs_reload_needed
= 1;
2104 savesegment(gs
, vmx
->host_state
.gs_sel
);
2105 if (!(vmx
->host_state
.gs_sel
& 7))
2106 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2108 vmcs_write16(HOST_GS_SELECTOR
, 0);
2109 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2112 #ifdef CONFIG_X86_64
2113 savesegment(ds
, vmx
->host_state
.ds_sel
);
2114 savesegment(es
, vmx
->host_state
.es_sel
);
2117 #ifdef CONFIG_X86_64
2118 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2119 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2121 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2122 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2125 #ifdef CONFIG_X86_64
2126 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2127 if (is_long_mode(&vmx
->vcpu
))
2128 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2130 if (boot_cpu_has(X86_FEATURE_MPX
))
2131 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2132 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2133 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2134 vmx
->guest_msrs
[i
].data
,
2135 vmx
->guest_msrs
[i
].mask
);
2138 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2140 if (!vmx
->host_state
.loaded
)
2143 ++vmx
->vcpu
.stat
.host_state_reload
;
2144 vmx
->host_state
.loaded
= 0;
2145 #ifdef CONFIG_X86_64
2146 if (is_long_mode(&vmx
->vcpu
))
2147 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2149 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2150 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2151 #ifdef CONFIG_X86_64
2152 load_gs_index(vmx
->host_state
.gs_sel
);
2154 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2157 if (vmx
->host_state
.fs_reload_needed
)
2158 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2159 #ifdef CONFIG_X86_64
2160 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2161 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2162 loadsegment(es
, vmx
->host_state
.es_sel
);
2165 invalidate_tss_limit();
2166 #ifdef CONFIG_X86_64
2167 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2169 if (vmx
->host_state
.msr_host_bndcfgs
)
2170 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2171 load_fixmap_gdt(raw_smp_processor_id());
2174 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2177 __vmx_load_host_state(vmx
);
2181 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2183 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2184 struct pi_desc old
, new;
2187 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2188 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2189 !kvm_vcpu_apicv_active(vcpu
))
2193 old
.control
= new.control
= pi_desc
->control
;
2196 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2197 * are two possible cases:
2198 * 1. After running 'pre_block', context switch
2199 * happened. For this case, 'sn' was set in
2200 * vmx_vcpu_put(), so we need to clear it here.
2201 * 2. After running 'pre_block', we were blocked,
2202 * and woken up by some other guy. For this case,
2203 * we don't need to do anything, 'pi_post_block'
2204 * will do everything for us. However, we cannot
2205 * check whether it is case #1 or case #2 here
2206 * (maybe, not needed), so we also clear sn here,
2207 * I think it is not a big deal.
2209 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2210 if (vcpu
->cpu
!= cpu
) {
2211 dest
= cpu_physical_id(cpu
);
2213 if (x2apic_enabled())
2216 new.ndst
= (dest
<< 8) & 0xFF00;
2219 /* set 'NV' to 'notification vector' */
2220 new.nv
= POSTED_INTR_VECTOR
;
2223 /* Allow posting non-urgent interrupts */
2225 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2226 new.control
) != old
.control
);
2229 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2231 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2232 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2236 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2237 * vcpu mutex is already taken.
2239 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2241 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2242 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2244 if (!already_loaded
) {
2245 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2246 local_irq_disable();
2247 crash_disable_local_vmclear(cpu
);
2250 * Read loaded_vmcs->cpu should be before fetching
2251 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2252 * See the comments in __loaded_vmcs_clear().
2256 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2257 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2258 crash_enable_local_vmclear(cpu
);
2262 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2263 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2264 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2267 if (!already_loaded
) {
2268 void *gdt
= get_current_gdt_ro();
2269 unsigned long sysenter_esp
;
2271 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2274 * Linux uses per-cpu TSS and GDT, so set these when switching
2275 * processors. See 22.2.4.
2277 vmcs_writel(HOST_TR_BASE
,
2278 (unsigned long)this_cpu_ptr(&cpu_tss
));
2279 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2282 * VM exits change the host TR limit to 0x67 after a VM
2283 * exit. This is okay, since 0x67 covers everything except
2284 * the IO bitmap and have have code to handle the IO bitmap
2285 * being lost after a VM exit.
2287 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2289 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2290 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2292 vmx
->loaded_vmcs
->cpu
= cpu
;
2295 /* Setup TSC multiplier */
2296 if (kvm_has_tsc_control
&&
2297 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2298 decache_tsc_multiplier(vmx
);
2300 vmx_vcpu_pi_load(vcpu
, cpu
);
2301 vmx
->host_pkru
= read_pkru();
2304 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2306 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2308 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2309 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2310 !kvm_vcpu_apicv_active(vcpu
))
2313 /* Set SN when the vCPU is preempted */
2314 if (vcpu
->preempted
)
2318 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2320 vmx_vcpu_pi_put(vcpu
);
2322 __vmx_load_host_state(to_vmx(vcpu
));
2325 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2328 * Return the cr0 value that a nested guest would read. This is a combination
2329 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2330 * its hypervisor (cr0_read_shadow).
2332 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2334 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2335 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2337 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2339 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2340 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2343 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2345 unsigned long rflags
, save_rflags
;
2347 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2348 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2349 rflags
= vmcs_readl(GUEST_RFLAGS
);
2350 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2351 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2352 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2353 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2355 to_vmx(vcpu
)->rflags
= rflags
;
2357 return to_vmx(vcpu
)->rflags
;
2360 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2362 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2363 to_vmx(vcpu
)->rflags
= rflags
;
2364 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2365 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2366 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2368 vmcs_writel(GUEST_RFLAGS
, rflags
);
2371 static u32
vmx_get_pkru(struct kvm_vcpu
*vcpu
)
2373 return to_vmx(vcpu
)->guest_pkru
;
2376 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2378 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2381 if (interruptibility
& GUEST_INTR_STATE_STI
)
2382 ret
|= KVM_X86_SHADOW_INT_STI
;
2383 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2384 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2389 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2391 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2392 u32 interruptibility
= interruptibility_old
;
2394 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2396 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2397 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2398 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2399 interruptibility
|= GUEST_INTR_STATE_STI
;
2401 if ((interruptibility
!= interruptibility_old
))
2402 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2405 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2409 rip
= kvm_rip_read(vcpu
);
2410 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2411 kvm_rip_write(vcpu
, rip
);
2413 /* skipping an emulated instruction also counts */
2414 vmx_set_interrupt_shadow(vcpu
, 0);
2418 * KVM wants to inject page-faults which it got to the guest. This function
2419 * checks whether in a nested guest, we need to inject them to L1 or L2.
2421 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2423 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2425 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2428 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2429 vmcs_read32(VM_EXIT_INTR_INFO
),
2430 vmcs_readl(EXIT_QUALIFICATION
));
2434 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2435 bool has_error_code
, u32 error_code
,
2438 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2439 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2441 if (!reinject
&& is_guest_mode(vcpu
) &&
2442 nested_vmx_check_exception(vcpu
, nr
))
2445 if (has_error_code
) {
2446 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2447 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2450 if (vmx
->rmode
.vm86_active
) {
2452 if (kvm_exception_is_soft(nr
))
2453 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2454 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2455 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2459 if (kvm_exception_is_soft(nr
)) {
2460 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2461 vmx
->vcpu
.arch
.event_exit_inst_len
);
2462 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2464 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2466 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2469 static bool vmx_rdtscp_supported(void)
2471 return cpu_has_vmx_rdtscp();
2474 static bool vmx_invpcid_supported(void)
2476 return cpu_has_vmx_invpcid() && enable_ept
;
2480 * Swap MSR entry in host/guest MSR entry array.
2482 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2484 struct shared_msr_entry tmp
;
2486 tmp
= vmx
->guest_msrs
[to
];
2487 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2488 vmx
->guest_msrs
[from
] = tmp
;
2491 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2493 unsigned long *msr_bitmap
;
2495 if (is_guest_mode(vcpu
))
2496 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2497 else if (cpu_has_secondary_exec_ctrls() &&
2498 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2499 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2500 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2501 if (is_long_mode(vcpu
))
2502 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2504 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2506 if (is_long_mode(vcpu
))
2507 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2509 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2512 if (is_long_mode(vcpu
))
2513 msr_bitmap
= vmx_msr_bitmap_longmode
;
2515 msr_bitmap
= vmx_msr_bitmap_legacy
;
2518 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2522 * Set up the vmcs to automatically save and restore system
2523 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2524 * mode, as fiddling with msrs is very expensive.
2526 static void setup_msrs(struct vcpu_vmx
*vmx
)
2528 int save_nmsrs
, index
;
2531 #ifdef CONFIG_X86_64
2532 if (is_long_mode(&vmx
->vcpu
)) {
2533 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2535 move_msr_up(vmx
, index
, save_nmsrs
++);
2536 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2538 move_msr_up(vmx
, index
, save_nmsrs
++);
2539 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2541 move_msr_up(vmx
, index
, save_nmsrs
++);
2542 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2543 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2544 move_msr_up(vmx
, index
, save_nmsrs
++);
2546 * MSR_STAR is only needed on long mode guests, and only
2547 * if efer.sce is enabled.
2549 index
= __find_msr_index(vmx
, MSR_STAR
);
2550 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2551 move_msr_up(vmx
, index
, save_nmsrs
++);
2554 index
= __find_msr_index(vmx
, MSR_EFER
);
2555 if (index
>= 0 && update_transition_efer(vmx
, index
))
2556 move_msr_up(vmx
, index
, save_nmsrs
++);
2558 vmx
->save_nmsrs
= save_nmsrs
;
2560 if (cpu_has_vmx_msr_bitmap())
2561 vmx_set_msr_bitmap(&vmx
->vcpu
);
2565 * reads and returns guest's timestamp counter "register"
2566 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2567 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2569 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2571 u64 host_tsc
, tsc_offset
;
2574 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2575 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2579 * writes 'offset' into guest's timestamp counter offset register
2581 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2583 if (is_guest_mode(vcpu
)) {
2585 * We're here if L1 chose not to trap WRMSR to TSC. According
2586 * to the spec, this should set L1's TSC; The offset that L1
2587 * set for L2 remains unchanged, and still needs to be added
2588 * to the newly set TSC to get L2's TSC.
2590 struct vmcs12
*vmcs12
;
2591 /* recalculate vmcs02.TSC_OFFSET: */
2592 vmcs12
= get_vmcs12(vcpu
);
2593 vmcs_write64(TSC_OFFSET
, offset
+
2594 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2595 vmcs12
->tsc_offset
: 0));
2597 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2598 vmcs_read64(TSC_OFFSET
), offset
);
2599 vmcs_write64(TSC_OFFSET
, offset
);
2603 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2605 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2606 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2610 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2611 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2612 * all guests if the "nested" module option is off, and can also be disabled
2613 * for a single guest by disabling its VMX cpuid bit.
2615 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2617 return nested
&& guest_cpuid_has_vmx(vcpu
);
2621 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2622 * returned for the various VMX controls MSRs when nested VMX is enabled.
2623 * The same values should also be used to verify that vmcs12 control fields are
2624 * valid during nested entry from L1 to L2.
2625 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2626 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2627 * bit in the high half is on if the corresponding bit in the control field
2628 * may be on. See also vmx_control_verify().
2630 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2633 * Note that as a general rule, the high half of the MSRs (bits in
2634 * the control fields which may be 1) should be initialized by the
2635 * intersection of the underlying hardware's MSR (i.e., features which
2636 * can be supported) and the list of features we want to expose -
2637 * because they are known to be properly supported in our code.
2638 * Also, usually, the low half of the MSRs (bits which must be 1) can
2639 * be set to 0, meaning that L1 may turn off any of these bits. The
2640 * reason is that if one of these bits is necessary, it will appear
2641 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2642 * fields of vmcs01 and vmcs02, will turn these bits off - and
2643 * nested_vmx_exit_handled() will not pass related exits to L1.
2644 * These rules have exceptions below.
2647 /* pin-based controls */
2648 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2649 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2650 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2651 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2652 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2653 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2654 PIN_BASED_EXT_INTR_MASK
|
2655 PIN_BASED_NMI_EXITING
|
2656 PIN_BASED_VIRTUAL_NMIS
;
2657 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2658 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2659 PIN_BASED_VMX_PREEMPTION_TIMER
;
2660 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2661 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2662 PIN_BASED_POSTED_INTR
;
2665 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2666 vmx
->nested
.nested_vmx_exit_ctls_low
,
2667 vmx
->nested
.nested_vmx_exit_ctls_high
);
2668 vmx
->nested
.nested_vmx_exit_ctls_low
=
2669 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2671 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2672 #ifdef CONFIG_X86_64
2673 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2675 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2676 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2677 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2678 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2679 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2681 if (kvm_mpx_supported())
2682 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2684 /* We support free control of debug control saving. */
2685 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2687 /* entry controls */
2688 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2689 vmx
->nested
.nested_vmx_entry_ctls_low
,
2690 vmx
->nested
.nested_vmx_entry_ctls_high
);
2691 vmx
->nested
.nested_vmx_entry_ctls_low
=
2692 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2693 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2694 #ifdef CONFIG_X86_64
2695 VM_ENTRY_IA32E_MODE
|
2697 VM_ENTRY_LOAD_IA32_PAT
;
2698 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2699 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2700 if (kvm_mpx_supported())
2701 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2703 /* We support free control of debug control loading. */
2704 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2706 /* cpu-based controls */
2707 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2708 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2709 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2710 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2711 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2712 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2713 CPU_BASED_VIRTUAL_INTR_PENDING
|
2714 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2715 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2716 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2717 CPU_BASED_CR3_STORE_EXITING
|
2718 #ifdef CONFIG_X86_64
2719 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2721 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2722 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2723 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2724 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2725 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2727 * We can allow some features even when not supported by the
2728 * hardware. For example, L1 can specify an MSR bitmap - and we
2729 * can use it to avoid exits to L1 - even when L0 runs L2
2730 * without MSR bitmaps.
2732 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2733 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2734 CPU_BASED_USE_MSR_BITMAPS
;
2736 /* We support free control of CR3 access interception. */
2737 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2738 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2740 /* secondary cpu-based controls */
2741 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2742 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2743 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2744 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2745 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2746 SECONDARY_EXEC_RDRAND
| SECONDARY_EXEC_RDSEED
|
2747 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2748 SECONDARY_EXEC_RDTSCP
|
2749 SECONDARY_EXEC_DESC
|
2750 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2751 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2752 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2753 SECONDARY_EXEC_WBINVD_EXITING
|
2754 SECONDARY_EXEC_XSAVES
;
2757 /* nested EPT: emulate EPT also to L1 */
2758 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2759 SECONDARY_EXEC_ENABLE_EPT
;
2760 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2761 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2762 if (cpu_has_vmx_ept_execute_only())
2763 vmx
->nested
.nested_vmx_ept_caps
|=
2764 VMX_EPT_EXECUTE_ONLY_BIT
;
2765 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2766 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2767 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2768 VMX_EPT_1GB_PAGE_BIT
;
2769 if (enable_ept_ad_bits
) {
2770 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2771 SECONDARY_EXEC_ENABLE_PML
;
2772 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2775 vmx
->nested
.nested_vmx_ept_caps
= 0;
2778 * Old versions of KVM use the single-context version without
2779 * checking for support, so declare that it is supported even
2780 * though it is treated as global context. The alternative is
2781 * not failing the single-context invvpid, and it is worse.
2784 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2785 SECONDARY_EXEC_ENABLE_VPID
;
2786 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2787 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2789 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2791 if (enable_unrestricted_guest
)
2792 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2793 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2795 /* miscellaneous data */
2796 rdmsr(MSR_IA32_VMX_MISC
,
2797 vmx
->nested
.nested_vmx_misc_low
,
2798 vmx
->nested
.nested_vmx_misc_high
);
2799 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2800 vmx
->nested
.nested_vmx_misc_low
|=
2801 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2802 VMX_MISC_ACTIVITY_HLT
;
2803 vmx
->nested
.nested_vmx_misc_high
= 0;
2806 * This MSR reports some information about VMX support. We
2807 * should return information about the VMX we emulate for the
2808 * guest, and the VMCS structure we give it - not about the
2809 * VMX support of the underlying hardware.
2811 vmx
->nested
.nested_vmx_basic
=
2813 VMX_BASIC_TRUE_CTLS
|
2814 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2815 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2817 if (cpu_has_vmx_basic_inout())
2818 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2821 * These MSRs specify bits which the guest must keep fixed on
2822 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2823 * We picked the standard core2 setting.
2825 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2826 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2827 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2828 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2830 /* These MSRs specify bits which the guest must keep fixed off. */
2831 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2832 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2834 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2835 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2839 * if fixed0[i] == 1: val[i] must be 1
2840 * if fixed1[i] == 0: val[i] must be 0
2842 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2844 return ((val
& fixed1
) | fixed0
) == val
;
2847 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2849 return fixed_bits_valid(control
, low
, high
);
2852 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2854 return low
| ((u64
)high
<< 32);
2857 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2862 return (superset
| subset
) == superset
;
2865 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2867 const u64 feature_and_reserved
=
2868 /* feature (except bit 48; see below) */
2869 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2871 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2872 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2874 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2878 * KVM does not emulate a version of VMX that constrains physical
2879 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2881 if (data
& BIT_ULL(48))
2884 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2885 vmx_basic_vmcs_revision_id(data
))
2888 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2891 vmx
->nested
.nested_vmx_basic
= data
;
2896 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2901 switch (msr_index
) {
2902 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2903 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2904 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2906 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2907 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2908 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2910 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2911 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2912 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2914 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2915 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2916 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2918 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2919 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2920 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
2926 supported
= vmx_control_msr(*lowp
, *highp
);
2928 /* Check must-be-1 bits are still 1. */
2929 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
2932 /* Check must-be-0 bits are still 0. */
2933 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
2937 *highp
= data
>> 32;
2941 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
2943 const u64 feature_and_reserved_bits
=
2945 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2946 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2948 GENMASK_ULL(13, 9) | BIT_ULL(31);
2951 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
2952 vmx
->nested
.nested_vmx_misc_high
);
2954 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
2957 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
2958 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
2959 vmx_misc_preemption_timer_rate(data
) !=
2960 vmx_misc_preemption_timer_rate(vmx_misc
))
2963 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
2966 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
2969 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
2972 vmx
->nested
.nested_vmx_misc_low
= data
;
2973 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
2977 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
2979 u64 vmx_ept_vpid_cap
;
2981 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
2982 vmx
->nested
.nested_vmx_vpid_caps
);
2984 /* Every bit is either reserved or a feature bit. */
2985 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
2988 vmx
->nested
.nested_vmx_ept_caps
= data
;
2989 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
2993 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2997 switch (msr_index
) {
2998 case MSR_IA32_VMX_CR0_FIXED0
:
2999 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3001 case MSR_IA32_VMX_CR4_FIXED0
:
3002 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3009 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3010 * must be 1 in the restored value.
3012 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3020 * Called when userspace is restoring VMX MSRs.
3022 * Returns 0 on success, non-0 otherwise.
3024 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3026 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3028 switch (msr_index
) {
3029 case MSR_IA32_VMX_BASIC
:
3030 return vmx_restore_vmx_basic(vmx
, data
);
3031 case MSR_IA32_VMX_PINBASED_CTLS
:
3032 case MSR_IA32_VMX_PROCBASED_CTLS
:
3033 case MSR_IA32_VMX_EXIT_CTLS
:
3034 case MSR_IA32_VMX_ENTRY_CTLS
:
3036 * The "non-true" VMX capability MSRs are generated from the
3037 * "true" MSRs, so we do not support restoring them directly.
3039 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3040 * should restore the "true" MSRs with the must-be-1 bits
3041 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3042 * DEFAULT SETTINGS".
3045 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3046 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3047 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3048 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3049 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3050 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3051 case MSR_IA32_VMX_MISC
:
3052 return vmx_restore_vmx_misc(vmx
, data
);
3053 case MSR_IA32_VMX_CR0_FIXED0
:
3054 case MSR_IA32_VMX_CR4_FIXED0
:
3055 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3056 case MSR_IA32_VMX_CR0_FIXED1
:
3057 case MSR_IA32_VMX_CR4_FIXED1
:
3059 * These MSRs are generated based on the vCPU's CPUID, so we
3060 * do not support restoring them directly.
3063 case MSR_IA32_VMX_EPT_VPID_CAP
:
3064 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3065 case MSR_IA32_VMX_VMCS_ENUM
:
3066 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3070 * The rest of the VMX capability MSRs do not support restore.
3076 /* Returns 0 on success, non-0 otherwise. */
3077 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3079 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3081 switch (msr_index
) {
3082 case MSR_IA32_VMX_BASIC
:
3083 *pdata
= vmx
->nested
.nested_vmx_basic
;
3085 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3086 case MSR_IA32_VMX_PINBASED_CTLS
:
3087 *pdata
= vmx_control_msr(
3088 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3089 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3090 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3091 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3093 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3094 case MSR_IA32_VMX_PROCBASED_CTLS
:
3095 *pdata
= vmx_control_msr(
3096 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3097 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3098 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3099 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3101 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3102 case MSR_IA32_VMX_EXIT_CTLS
:
3103 *pdata
= vmx_control_msr(
3104 vmx
->nested
.nested_vmx_exit_ctls_low
,
3105 vmx
->nested
.nested_vmx_exit_ctls_high
);
3106 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3107 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3109 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3110 case MSR_IA32_VMX_ENTRY_CTLS
:
3111 *pdata
= vmx_control_msr(
3112 vmx
->nested
.nested_vmx_entry_ctls_low
,
3113 vmx
->nested
.nested_vmx_entry_ctls_high
);
3114 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3115 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3117 case MSR_IA32_VMX_MISC
:
3118 *pdata
= vmx_control_msr(
3119 vmx
->nested
.nested_vmx_misc_low
,
3120 vmx
->nested
.nested_vmx_misc_high
);
3122 case MSR_IA32_VMX_CR0_FIXED0
:
3123 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3125 case MSR_IA32_VMX_CR0_FIXED1
:
3126 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3128 case MSR_IA32_VMX_CR4_FIXED0
:
3129 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3131 case MSR_IA32_VMX_CR4_FIXED1
:
3132 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3134 case MSR_IA32_VMX_VMCS_ENUM
:
3135 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3137 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3138 *pdata
= vmx_control_msr(
3139 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3140 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3142 case MSR_IA32_VMX_EPT_VPID_CAP
:
3143 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3144 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3153 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3156 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3158 return !(val
& ~valid_bits
);
3162 * Reads an msr value (of 'msr_index') into 'pdata'.
3163 * Returns 0 on success, non-0 otherwise.
3164 * Assumes vcpu_load() was already called.
3166 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3168 struct shared_msr_entry
*msr
;
3170 switch (msr_info
->index
) {
3171 #ifdef CONFIG_X86_64
3173 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3176 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3178 case MSR_KERNEL_GS_BASE
:
3179 vmx_load_host_state(to_vmx(vcpu
));
3180 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3184 return kvm_get_msr_common(vcpu
, msr_info
);
3186 msr_info
->data
= guest_read_tsc(vcpu
);
3188 case MSR_IA32_SYSENTER_CS
:
3189 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3191 case MSR_IA32_SYSENTER_EIP
:
3192 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3194 case MSR_IA32_SYSENTER_ESP
:
3195 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3197 case MSR_IA32_BNDCFGS
:
3198 if (!kvm_mpx_supported())
3200 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3202 case MSR_IA32_MCG_EXT_CTL
:
3203 if (!msr_info
->host_initiated
&&
3204 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3205 FEATURE_CONTROL_LMCE
))
3207 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3209 case MSR_IA32_FEATURE_CONTROL
:
3210 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3212 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3213 if (!nested_vmx_allowed(vcpu
))
3215 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3217 if (!vmx_xsaves_supported())
3219 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3222 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3224 /* Otherwise falls through */
3226 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3228 msr_info
->data
= msr
->data
;
3231 return kvm_get_msr_common(vcpu
, msr_info
);
3237 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3240 * Writes msr value into into the appropriate "register".
3241 * Returns 0 on success, non-0 otherwise.
3242 * Assumes vcpu_load() was already called.
3244 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3246 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3247 struct shared_msr_entry
*msr
;
3249 u32 msr_index
= msr_info
->index
;
3250 u64 data
= msr_info
->data
;
3252 switch (msr_index
) {
3254 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3256 #ifdef CONFIG_X86_64
3258 vmx_segment_cache_clear(vmx
);
3259 vmcs_writel(GUEST_FS_BASE
, data
);
3262 vmx_segment_cache_clear(vmx
);
3263 vmcs_writel(GUEST_GS_BASE
, data
);
3265 case MSR_KERNEL_GS_BASE
:
3266 vmx_load_host_state(vmx
);
3267 vmx
->msr_guest_kernel_gs_base
= data
;
3270 case MSR_IA32_SYSENTER_CS
:
3271 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3273 case MSR_IA32_SYSENTER_EIP
:
3274 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3276 case MSR_IA32_SYSENTER_ESP
:
3277 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3279 case MSR_IA32_BNDCFGS
:
3280 if (!kvm_mpx_supported())
3282 vmcs_write64(GUEST_BNDCFGS
, data
);
3285 kvm_write_tsc(vcpu
, msr_info
);
3287 case MSR_IA32_CR_PAT
:
3288 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3289 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3291 vmcs_write64(GUEST_IA32_PAT
, data
);
3292 vcpu
->arch
.pat
= data
;
3295 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3297 case MSR_IA32_TSC_ADJUST
:
3298 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3300 case MSR_IA32_MCG_EXT_CTL
:
3301 if ((!msr_info
->host_initiated
&&
3302 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3303 FEATURE_CONTROL_LMCE
)) ||
3304 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3306 vcpu
->arch
.mcg_ext_ctl
= data
;
3308 case MSR_IA32_FEATURE_CONTROL
:
3309 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3310 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3311 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3313 vmx
->msr_ia32_feature_control
= data
;
3314 if (msr_info
->host_initiated
&& data
== 0)
3315 vmx_leave_nested(vcpu
);
3317 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3318 if (!msr_info
->host_initiated
)
3319 return 1; /* they are read-only */
3320 if (!nested_vmx_allowed(vcpu
))
3322 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3324 if (!vmx_xsaves_supported())
3327 * The only supported bit as of Skylake is bit 8, but
3328 * it is not supported on KVM.
3332 vcpu
->arch
.ia32_xss
= data
;
3333 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3334 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3335 vcpu
->arch
.ia32_xss
, host_xss
);
3337 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3340 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3342 /* Check reserved bit, higher 32 bits should be zero */
3343 if ((data
>> 32) != 0)
3345 /* Otherwise falls through */
3347 msr
= find_msr_entry(vmx
, msr_index
);
3349 u64 old_msr_data
= msr
->data
;
3351 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3353 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3357 msr
->data
= old_msr_data
;
3361 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3367 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3369 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3372 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3375 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3377 case VCPU_EXREG_PDPTR
:
3379 ept_save_pdptrs(vcpu
);
3386 static __init
int cpu_has_kvm_support(void)
3388 return cpu_has_vmx();
3391 static __init
int vmx_disabled_by_bios(void)
3395 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3396 if (msr
& FEATURE_CONTROL_LOCKED
) {
3397 /* launched w/ TXT and VMX disabled */
3398 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3401 /* launched w/o TXT and VMX only enabled w/ TXT */
3402 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3403 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3404 && !tboot_enabled()) {
3405 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3406 "activate TXT before enabling KVM\n");
3409 /* launched w/o TXT and VMX disabled */
3410 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3411 && !tboot_enabled())
3418 static void kvm_cpu_vmxon(u64 addr
)
3420 cr4_set_bits(X86_CR4_VMXE
);
3421 intel_pt_handle_vmx(1);
3423 asm volatile (ASM_VMX_VMXON_RAX
3424 : : "a"(&addr
), "m"(addr
)
3428 static int hardware_enable(void)
3430 int cpu
= raw_smp_processor_id();
3431 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3434 if (cr4_read_shadow() & X86_CR4_VMXE
)
3437 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3438 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3439 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3442 * Now we can enable the vmclear operation in kdump
3443 * since the loaded_vmcss_on_cpu list on this cpu
3444 * has been initialized.
3446 * Though the cpu is not in VMX operation now, there
3447 * is no problem to enable the vmclear operation
3448 * for the loaded_vmcss_on_cpu list is empty!
3450 crash_enable_local_vmclear(cpu
);
3452 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3454 test_bits
= FEATURE_CONTROL_LOCKED
;
3455 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3456 if (tboot_enabled())
3457 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3459 if ((old
& test_bits
) != test_bits
) {
3460 /* enable and lock */
3461 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3463 kvm_cpu_vmxon(phys_addr
);
3469 static void vmclear_local_loaded_vmcss(void)
3471 int cpu
= raw_smp_processor_id();
3472 struct loaded_vmcs
*v
, *n
;
3474 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3475 loaded_vmcss_on_cpu_link
)
3476 __loaded_vmcs_clear(v
);
3480 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3483 static void kvm_cpu_vmxoff(void)
3485 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3487 intel_pt_handle_vmx(0);
3488 cr4_clear_bits(X86_CR4_VMXE
);
3491 static void hardware_disable(void)
3493 vmclear_local_loaded_vmcss();
3497 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3498 u32 msr
, u32
*result
)
3500 u32 vmx_msr_low
, vmx_msr_high
;
3501 u32 ctl
= ctl_min
| ctl_opt
;
3503 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3505 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3506 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3508 /* Ensure minimum (required) set of control bits are supported. */
3516 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3518 u32 vmx_msr_low
, vmx_msr_high
;
3520 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3521 return vmx_msr_high
& ctl
;
3524 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3526 u32 vmx_msr_low
, vmx_msr_high
;
3527 u32 min
, opt
, min2
, opt2
;
3528 u32 _pin_based_exec_control
= 0;
3529 u32 _cpu_based_exec_control
= 0;
3530 u32 _cpu_based_2nd_exec_control
= 0;
3531 u32 _vmexit_control
= 0;
3532 u32 _vmentry_control
= 0;
3534 min
= CPU_BASED_HLT_EXITING
|
3535 #ifdef CONFIG_X86_64
3536 CPU_BASED_CR8_LOAD_EXITING
|
3537 CPU_BASED_CR8_STORE_EXITING
|
3539 CPU_BASED_CR3_LOAD_EXITING
|
3540 CPU_BASED_CR3_STORE_EXITING
|
3541 CPU_BASED_USE_IO_BITMAPS
|
3542 CPU_BASED_MOV_DR_EXITING
|
3543 CPU_BASED_USE_TSC_OFFSETING
|
3544 CPU_BASED_INVLPG_EXITING
|
3545 CPU_BASED_RDPMC_EXITING
;
3547 if (!kvm_mwait_in_guest())
3548 min
|= CPU_BASED_MWAIT_EXITING
|
3549 CPU_BASED_MONITOR_EXITING
;
3551 opt
= CPU_BASED_TPR_SHADOW
|
3552 CPU_BASED_USE_MSR_BITMAPS
|
3553 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3554 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3555 &_cpu_based_exec_control
) < 0)
3557 #ifdef CONFIG_X86_64
3558 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3559 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3560 ~CPU_BASED_CR8_STORE_EXITING
;
3562 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3564 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3565 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3566 SECONDARY_EXEC_WBINVD_EXITING
|
3567 SECONDARY_EXEC_ENABLE_VPID
|
3568 SECONDARY_EXEC_ENABLE_EPT
|
3569 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3570 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3571 SECONDARY_EXEC_RDTSCP
|
3572 SECONDARY_EXEC_ENABLE_INVPCID
|
3573 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3574 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3575 SECONDARY_EXEC_SHADOW_VMCS
|
3576 SECONDARY_EXEC_XSAVES
|
3577 SECONDARY_EXEC_ENABLE_PML
|
3578 SECONDARY_EXEC_TSC_SCALING
;
3579 if (adjust_vmx_controls(min2
, opt2
,
3580 MSR_IA32_VMX_PROCBASED_CTLS2
,
3581 &_cpu_based_2nd_exec_control
) < 0)
3584 #ifndef CONFIG_X86_64
3585 if (!(_cpu_based_2nd_exec_control
&
3586 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3587 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3590 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3591 _cpu_based_2nd_exec_control
&= ~(
3592 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3593 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3594 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3596 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3597 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3599 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3600 CPU_BASED_CR3_STORE_EXITING
|
3601 CPU_BASED_INVLPG_EXITING
);
3602 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3603 vmx_capability
.ept
, vmx_capability
.vpid
);
3606 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3607 #ifdef CONFIG_X86_64
3608 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3610 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3611 VM_EXIT_CLEAR_BNDCFGS
;
3612 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3613 &_vmexit_control
) < 0)
3616 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
3617 PIN_BASED_VIRTUAL_NMIS
;
3618 opt
= PIN_BASED_POSTED_INTR
| PIN_BASED_VMX_PREEMPTION_TIMER
;
3619 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3620 &_pin_based_exec_control
) < 0)
3623 if (cpu_has_broken_vmx_preemption_timer())
3624 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3625 if (!(_cpu_based_2nd_exec_control
&
3626 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3627 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3629 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3630 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3631 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3632 &_vmentry_control
) < 0)
3635 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3637 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3638 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3641 #ifdef CONFIG_X86_64
3642 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3643 if (vmx_msr_high
& (1u<<16))
3647 /* Require Write-Back (WB) memory type for VMCS accesses. */
3648 if (((vmx_msr_high
>> 18) & 15) != 6)
3651 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3652 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3653 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3654 vmcs_conf
->revision_id
= vmx_msr_low
;
3656 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3657 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3658 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3659 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3660 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3662 cpu_has_load_ia32_efer
=
3663 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3664 VM_ENTRY_LOAD_IA32_EFER
)
3665 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3666 VM_EXIT_LOAD_IA32_EFER
);
3668 cpu_has_load_perf_global_ctrl
=
3669 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3670 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3671 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3672 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3675 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3676 * but due to errata below it can't be used. Workaround is to use
3677 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3679 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3684 * BC86,AAY89,BD102 (model 44)
3688 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3689 switch (boot_cpu_data
.x86_model
) {
3695 cpu_has_load_perf_global_ctrl
= false;
3696 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3697 "does not work properly. Using workaround\n");
3704 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3705 rdmsrl(MSR_IA32_XSS
, host_xss
);
3710 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3712 int node
= cpu_to_node(cpu
);
3716 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3719 vmcs
= page_address(pages
);
3720 memset(vmcs
, 0, vmcs_config
.size
);
3721 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3725 static struct vmcs
*alloc_vmcs(void)
3727 return alloc_vmcs_cpu(raw_smp_processor_id());
3730 static void free_vmcs(struct vmcs
*vmcs
)
3732 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3736 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3738 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3740 if (!loaded_vmcs
->vmcs
)
3742 loaded_vmcs_clear(loaded_vmcs
);
3743 free_vmcs(loaded_vmcs
->vmcs
);
3744 loaded_vmcs
->vmcs
= NULL
;
3745 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3748 static void free_kvm_area(void)
3752 for_each_possible_cpu(cpu
) {
3753 free_vmcs(per_cpu(vmxarea
, cpu
));
3754 per_cpu(vmxarea
, cpu
) = NULL
;
3758 static void init_vmcs_shadow_fields(void)
3762 /* No checks for read only fields yet */
3764 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3765 switch (shadow_read_write_fields
[i
]) {
3767 if (!kvm_mpx_supported())
3775 shadow_read_write_fields
[j
] =
3776 shadow_read_write_fields
[i
];
3779 max_shadow_read_write_fields
= j
;
3781 /* shadowed fields guest access without vmexit */
3782 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3783 clear_bit(shadow_read_write_fields
[i
],
3784 vmx_vmwrite_bitmap
);
3785 clear_bit(shadow_read_write_fields
[i
],
3788 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3789 clear_bit(shadow_read_only_fields
[i
],
3793 static __init
int alloc_kvm_area(void)
3797 for_each_possible_cpu(cpu
) {
3800 vmcs
= alloc_vmcs_cpu(cpu
);
3806 per_cpu(vmxarea
, cpu
) = vmcs
;
3811 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3813 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3816 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3817 struct kvm_segment
*save
)
3819 if (!emulate_invalid_guest_state
) {
3821 * CS and SS RPL should be equal during guest entry according
3822 * to VMX spec, but in reality it is not always so. Since vcpu
3823 * is in the middle of the transition from real mode to
3824 * protected mode it is safe to assume that RPL 0 is a good
3827 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3828 save
->selector
&= ~SEGMENT_RPL_MASK
;
3829 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3832 vmx_set_segment(vcpu
, save
, seg
);
3835 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3837 unsigned long flags
;
3838 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3841 * Update real mode segment cache. It may be not up-to-date if sement
3842 * register was written while vcpu was in a guest mode.
3844 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3845 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3846 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3847 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3848 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3849 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3851 vmx
->rmode
.vm86_active
= 0;
3853 vmx_segment_cache_clear(vmx
);
3855 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3857 flags
= vmcs_readl(GUEST_RFLAGS
);
3858 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3859 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3860 vmcs_writel(GUEST_RFLAGS
, flags
);
3862 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3863 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3865 update_exception_bitmap(vcpu
);
3867 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3868 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3869 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3870 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3871 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3872 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3875 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3877 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3878 struct kvm_segment var
= *save
;
3881 if (seg
== VCPU_SREG_CS
)
3884 if (!emulate_invalid_guest_state
) {
3885 var
.selector
= var
.base
>> 4;
3886 var
.base
= var
.base
& 0xffff0;
3896 if (save
->base
& 0xf)
3897 printk_once(KERN_WARNING
"kvm: segment base is not "
3898 "paragraph aligned when entering "
3899 "protected mode (seg=%d)", seg
);
3902 vmcs_write16(sf
->selector
, var
.selector
);
3903 vmcs_writel(sf
->base
, var
.base
);
3904 vmcs_write32(sf
->limit
, var
.limit
);
3905 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3908 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3910 unsigned long flags
;
3911 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3913 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3914 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3915 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3916 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3917 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3918 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3919 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3921 vmx
->rmode
.vm86_active
= 1;
3924 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3925 * vcpu. Warn the user that an update is overdue.
3927 if (!vcpu
->kvm
->arch
.tss_addr
)
3928 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3929 "called before entering vcpu\n");
3931 vmx_segment_cache_clear(vmx
);
3933 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3934 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3935 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3937 flags
= vmcs_readl(GUEST_RFLAGS
);
3938 vmx
->rmode
.save_rflags
= flags
;
3940 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3942 vmcs_writel(GUEST_RFLAGS
, flags
);
3943 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3944 update_exception_bitmap(vcpu
);
3946 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3947 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3948 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3949 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3950 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3951 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3953 kvm_mmu_reset_context(vcpu
);
3956 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3958 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3959 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3965 * Force kernel_gs_base reloading before EFER changes, as control
3966 * of this msr depends on is_long_mode().
3968 vmx_load_host_state(to_vmx(vcpu
));
3969 vcpu
->arch
.efer
= efer
;
3970 if (efer
& EFER_LMA
) {
3971 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3974 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3976 msr
->data
= efer
& ~EFER_LME
;
3981 #ifdef CONFIG_X86_64
3983 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3987 vmx_segment_cache_clear(to_vmx(vcpu
));
3989 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3990 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3991 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3993 vmcs_write32(GUEST_TR_AR_BYTES
,
3994 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3995 | VMX_AR_TYPE_BUSY_64_TSS
);
3997 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4000 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4002 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4003 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4008 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4011 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4013 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
4015 vpid_sync_context(vpid
);
4019 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4021 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4024 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4027 vmx_flush_tlb(vcpu
);
4030 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4032 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4034 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4035 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4038 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4040 if (enable_ept
&& is_paging(vcpu
))
4041 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4042 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4045 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4047 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4049 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4050 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4053 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4055 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4057 if (!test_bit(VCPU_EXREG_PDPTR
,
4058 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4061 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4062 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4063 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4064 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4065 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4069 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4071 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4073 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4074 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4075 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4076 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4077 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4080 __set_bit(VCPU_EXREG_PDPTR
,
4081 (unsigned long *)&vcpu
->arch
.regs_avail
);
4082 __set_bit(VCPU_EXREG_PDPTR
,
4083 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4086 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4088 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4089 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4090 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4092 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4093 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4094 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4095 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4097 return fixed_bits_valid(val
, fixed0
, fixed1
);
4100 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4102 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4103 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4105 return fixed_bits_valid(val
, fixed0
, fixed1
);
4108 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4110 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4111 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4113 return fixed_bits_valid(val
, fixed0
, fixed1
);
4116 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4117 #define nested_guest_cr4_valid nested_cr4_valid
4118 #define nested_host_cr4_valid nested_cr4_valid
4120 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4122 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4124 struct kvm_vcpu
*vcpu
)
4126 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4127 vmx_decache_cr3(vcpu
);
4128 if (!(cr0
& X86_CR0_PG
)) {
4129 /* From paging/starting to nonpaging */
4130 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4131 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4132 (CPU_BASED_CR3_LOAD_EXITING
|
4133 CPU_BASED_CR3_STORE_EXITING
));
4134 vcpu
->arch
.cr0
= cr0
;
4135 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4136 } else if (!is_paging(vcpu
)) {
4137 /* From nonpaging to paging */
4138 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4139 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4140 ~(CPU_BASED_CR3_LOAD_EXITING
|
4141 CPU_BASED_CR3_STORE_EXITING
));
4142 vcpu
->arch
.cr0
= cr0
;
4143 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4146 if (!(cr0
& X86_CR0_WP
))
4147 *hw_cr0
&= ~X86_CR0_WP
;
4150 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4152 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4153 unsigned long hw_cr0
;
4155 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4156 if (enable_unrestricted_guest
)
4157 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4159 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4161 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4164 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4168 #ifdef CONFIG_X86_64
4169 if (vcpu
->arch
.efer
& EFER_LME
) {
4170 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4172 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4178 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4180 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4181 vmcs_writel(GUEST_CR0
, hw_cr0
);
4182 vcpu
->arch
.cr0
= cr0
;
4184 /* depends on vcpu->arch.cr0 to be set to a new value */
4185 vmx
->emulation_required
= emulation_required(vcpu
);
4188 static u64
construct_eptp(unsigned long root_hpa
)
4192 /* TODO write the value reading from MSR */
4193 eptp
= VMX_EPT_DEFAULT_MT
|
4194 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
4195 if (enable_ept_ad_bits
)
4196 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
4197 eptp
|= (root_hpa
& PAGE_MASK
);
4202 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4204 unsigned long guest_cr3
;
4209 eptp
= construct_eptp(cr3
);
4210 vmcs_write64(EPT_POINTER
, eptp
);
4211 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4212 guest_cr3
= kvm_read_cr3(vcpu
);
4214 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4215 ept_load_pdptrs(vcpu
);
4218 vmx_flush_tlb(vcpu
);
4219 vmcs_writel(GUEST_CR3
, guest_cr3
);
4222 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4225 * Pass through host's Machine Check Enable value to hw_cr4, which
4226 * is in force while we are in guest mode. Do not let guests control
4227 * this bit, even if host CR4.MCE == 0.
4229 unsigned long hw_cr4
=
4230 (cr4_read_shadow() & X86_CR4_MCE
) |
4231 (cr4
& ~X86_CR4_MCE
) |
4232 (to_vmx(vcpu
)->rmode
.vm86_active
?
4233 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4235 if (cr4
& X86_CR4_VMXE
) {
4237 * To use VMXON (and later other VMX instructions), a guest
4238 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4239 * So basically the check on whether to allow nested VMX
4242 if (!nested_vmx_allowed(vcpu
))
4246 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4249 vcpu
->arch
.cr4
= cr4
;
4251 if (!is_paging(vcpu
)) {
4252 hw_cr4
&= ~X86_CR4_PAE
;
4253 hw_cr4
|= X86_CR4_PSE
;
4254 } else if (!(cr4
& X86_CR4_PAE
)) {
4255 hw_cr4
&= ~X86_CR4_PAE
;
4259 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4261 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4262 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4263 * to be manually disabled when guest switches to non-paging
4266 * If !enable_unrestricted_guest, the CPU is always running
4267 * with CR0.PG=1 and CR4 needs to be modified.
4268 * If enable_unrestricted_guest, the CPU automatically
4269 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4271 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4273 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4274 vmcs_writel(GUEST_CR4
, hw_cr4
);
4278 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4279 struct kvm_segment
*var
, int seg
)
4281 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4284 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4285 *var
= vmx
->rmode
.segs
[seg
];
4286 if (seg
== VCPU_SREG_TR
4287 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4289 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4290 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4293 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4294 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4295 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4296 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4297 var
->unusable
= (ar
>> 16) & 1;
4298 var
->type
= ar
& 15;
4299 var
->s
= (ar
>> 4) & 1;
4300 var
->dpl
= (ar
>> 5) & 3;
4302 * Some userspaces do not preserve unusable property. Since usable
4303 * segment has to be present according to VMX spec we can use present
4304 * property to amend userspace bug by making unusable segment always
4305 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4306 * segment as unusable.
4308 var
->present
= !var
->unusable
;
4309 var
->avl
= (ar
>> 12) & 1;
4310 var
->l
= (ar
>> 13) & 1;
4311 var
->db
= (ar
>> 14) & 1;
4312 var
->g
= (ar
>> 15) & 1;
4315 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4317 struct kvm_segment s
;
4319 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4320 vmx_get_segment(vcpu
, &s
, seg
);
4323 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4326 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4328 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4330 if (unlikely(vmx
->rmode
.vm86_active
))
4333 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4334 return VMX_AR_DPL(ar
);
4338 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4342 if (var
->unusable
|| !var
->present
)
4345 ar
= var
->type
& 15;
4346 ar
|= (var
->s
& 1) << 4;
4347 ar
|= (var
->dpl
& 3) << 5;
4348 ar
|= (var
->present
& 1) << 7;
4349 ar
|= (var
->avl
& 1) << 12;
4350 ar
|= (var
->l
& 1) << 13;
4351 ar
|= (var
->db
& 1) << 14;
4352 ar
|= (var
->g
& 1) << 15;
4358 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4359 struct kvm_segment
*var
, int seg
)
4361 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4362 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4364 vmx_segment_cache_clear(vmx
);
4366 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4367 vmx
->rmode
.segs
[seg
] = *var
;
4368 if (seg
== VCPU_SREG_TR
)
4369 vmcs_write16(sf
->selector
, var
->selector
);
4371 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4375 vmcs_writel(sf
->base
, var
->base
);
4376 vmcs_write32(sf
->limit
, var
->limit
);
4377 vmcs_write16(sf
->selector
, var
->selector
);
4380 * Fix the "Accessed" bit in AR field of segment registers for older
4382 * IA32 arch specifies that at the time of processor reset the
4383 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4384 * is setting it to 0 in the userland code. This causes invalid guest
4385 * state vmexit when "unrestricted guest" mode is turned on.
4386 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4387 * tree. Newer qemu binaries with that qemu fix would not need this
4390 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4391 var
->type
|= 0x1; /* Accessed */
4393 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4396 vmx
->emulation_required
= emulation_required(vcpu
);
4399 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4401 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4403 *db
= (ar
>> 14) & 1;
4404 *l
= (ar
>> 13) & 1;
4407 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4409 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4410 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4413 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4415 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4416 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4419 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4421 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4422 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4425 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4427 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4428 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4431 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4433 struct kvm_segment var
;
4436 vmx_get_segment(vcpu
, &var
, seg
);
4438 if (seg
== VCPU_SREG_CS
)
4440 ar
= vmx_segment_access_rights(&var
);
4442 if (var
.base
!= (var
.selector
<< 4))
4444 if (var
.limit
!= 0xffff)
4452 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4454 struct kvm_segment cs
;
4455 unsigned int cs_rpl
;
4457 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4458 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4462 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4466 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4467 if (cs
.dpl
> cs_rpl
)
4470 if (cs
.dpl
!= cs_rpl
)
4476 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4480 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4482 struct kvm_segment ss
;
4483 unsigned int ss_rpl
;
4485 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4486 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4490 if (ss
.type
!= 3 && ss
.type
!= 7)
4494 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4502 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4504 struct kvm_segment var
;
4507 vmx_get_segment(vcpu
, &var
, seg
);
4508 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4516 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4517 if (var
.dpl
< rpl
) /* DPL < RPL */
4521 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4527 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4529 struct kvm_segment tr
;
4531 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4535 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4537 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4545 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4547 struct kvm_segment ldtr
;
4549 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4553 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4563 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4565 struct kvm_segment cs
, ss
;
4567 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4568 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4570 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4571 (ss
.selector
& SEGMENT_RPL_MASK
));
4575 * Check if guest state is valid. Returns true if valid, false if
4577 * We assume that registers are always usable
4579 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4581 if (enable_unrestricted_guest
)
4584 /* real mode guest state checks */
4585 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4586 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4588 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4590 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4592 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4594 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4596 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4599 /* protected mode guest state checks */
4600 if (!cs_ss_rpl_check(vcpu
))
4602 if (!code_segment_valid(vcpu
))
4604 if (!stack_segment_valid(vcpu
))
4606 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4608 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4610 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4612 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4614 if (!tr_valid(vcpu
))
4616 if (!ldtr_valid(vcpu
))
4620 * - Add checks on RIP
4621 * - Add checks on RFLAGS
4627 static int init_rmode_tss(struct kvm
*kvm
)
4633 idx
= srcu_read_lock(&kvm
->srcu
);
4634 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4635 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4638 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4639 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4640 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4643 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4646 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4650 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4651 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4654 srcu_read_unlock(&kvm
->srcu
, idx
);
4658 static int init_rmode_identity_map(struct kvm
*kvm
)
4661 kvm_pfn_t identity_map_pfn
;
4667 /* Protect kvm->arch.ept_identity_pagetable_done. */
4668 mutex_lock(&kvm
->slots_lock
);
4670 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4673 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4675 r
= alloc_identity_pagetable(kvm
);
4679 idx
= srcu_read_lock(&kvm
->srcu
);
4680 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4683 /* Set up identity-mapping pagetable for EPT in real mode */
4684 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4685 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4686 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4687 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4688 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4692 kvm
->arch
.ept_identity_pagetable_done
= true;
4695 srcu_read_unlock(&kvm
->srcu
, idx
);
4698 mutex_unlock(&kvm
->slots_lock
);
4702 static void seg_setup(int seg
)
4704 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4707 vmcs_write16(sf
->selector
, 0);
4708 vmcs_writel(sf
->base
, 0);
4709 vmcs_write32(sf
->limit
, 0xffff);
4711 if (seg
== VCPU_SREG_CS
)
4712 ar
|= 0x08; /* code segment */
4714 vmcs_write32(sf
->ar_bytes
, ar
);
4717 static int alloc_apic_access_page(struct kvm
*kvm
)
4722 mutex_lock(&kvm
->slots_lock
);
4723 if (kvm
->arch
.apic_access_page_done
)
4725 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4726 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4730 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4731 if (is_error_page(page
)) {
4737 * Do not pin the page in memory, so that memory hot-unplug
4738 * is able to migrate it.
4741 kvm
->arch
.apic_access_page_done
= true;
4743 mutex_unlock(&kvm
->slots_lock
);
4747 static int alloc_identity_pagetable(struct kvm
*kvm
)
4749 /* Called with kvm->slots_lock held. */
4753 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4755 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4756 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4761 static int allocate_vpid(void)
4767 spin_lock(&vmx_vpid_lock
);
4768 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4769 if (vpid
< VMX_NR_VPIDS
)
4770 __set_bit(vpid
, vmx_vpid_bitmap
);
4773 spin_unlock(&vmx_vpid_lock
);
4777 static void free_vpid(int vpid
)
4779 if (!enable_vpid
|| vpid
== 0)
4781 spin_lock(&vmx_vpid_lock
);
4782 __clear_bit(vpid
, vmx_vpid_bitmap
);
4783 spin_unlock(&vmx_vpid_lock
);
4786 #define MSR_TYPE_R 1
4787 #define MSR_TYPE_W 2
4788 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4791 int f
= sizeof(unsigned long);
4793 if (!cpu_has_vmx_msr_bitmap())
4797 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4798 * have the write-low and read-high bitmap offsets the wrong way round.
4799 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4801 if (msr
<= 0x1fff) {
4802 if (type
& MSR_TYPE_R
)
4804 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4806 if (type
& MSR_TYPE_W
)
4808 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4810 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4812 if (type
& MSR_TYPE_R
)
4814 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4816 if (type
& MSR_TYPE_W
)
4818 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4824 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4825 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4827 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4828 unsigned long *msr_bitmap_nested
,
4831 int f
= sizeof(unsigned long);
4833 if (!cpu_has_vmx_msr_bitmap()) {
4839 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4840 * have the write-low and read-high bitmap offsets the wrong way round.
4841 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4843 if (msr
<= 0x1fff) {
4844 if (type
& MSR_TYPE_R
&&
4845 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4847 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4849 if (type
& MSR_TYPE_W
&&
4850 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4852 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4854 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4856 if (type
& MSR_TYPE_R
&&
4857 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4859 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4861 if (type
& MSR_TYPE_W
&&
4862 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4864 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4869 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4872 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4873 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4874 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4875 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4878 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
4881 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
4883 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
4886 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4888 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4893 static bool vmx_get_enable_apicv(void)
4895 return enable_apicv
;
4898 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4900 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4905 if (vmx
->nested
.pi_desc
&&
4906 vmx
->nested
.pi_pending
) {
4907 vmx
->nested
.pi_pending
= false;
4908 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4911 max_irr
= find_last_bit(
4912 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4917 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4918 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4919 kunmap(vmx
->nested
.virtual_apic_page
);
4921 status
= vmcs_read16(GUEST_INTR_STATUS
);
4922 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4924 status
|= (u8
)max_irr
;
4925 vmcs_write16(GUEST_INTR_STATUS
, status
);
4930 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4933 if (vcpu
->mode
== IN_GUEST_MODE
) {
4934 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4937 * Currently, we don't support urgent interrupt,
4938 * all interrupts are recognized as non-urgent
4939 * interrupt, so we cannot post interrupts when
4942 * If the vcpu is in guest mode, it means it is
4943 * running instead of being scheduled out and
4944 * waiting in the run queue, and that's the only
4945 * case when 'SN' is set currently, warning if
4948 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4950 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4951 POSTED_INTR_VECTOR
);
4958 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4961 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4963 if (is_guest_mode(vcpu
) &&
4964 vector
== vmx
->nested
.posted_intr_nv
) {
4965 /* the PIR and ON have been set by L1. */
4966 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4968 * If a posted intr is not recognized by hardware,
4969 * we will accomplish it in the next vmentry.
4971 vmx
->nested
.pi_pending
= true;
4972 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4978 * Send interrupt to vcpu via posted interrupt way.
4979 * 1. If target vcpu is running(non-root mode), send posted interrupt
4980 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4981 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4982 * interrupt from PIR in next vmentry.
4984 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4986 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4989 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4993 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4996 /* If a previous notification has sent the IPI, nothing to do. */
4997 if (pi_test_and_set_on(&vmx
->pi_desc
))
5000 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
))
5001 kvm_vcpu_kick(vcpu
);
5005 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5006 * will not change in the lifetime of the guest.
5007 * Note that host-state that does change is set elsewhere. E.g., host-state
5008 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5010 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5015 unsigned long cr0
, cr4
;
5018 WARN_ON(cr0
& X86_CR0_TS
);
5019 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5020 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
5022 /* Save the most likely value for this task's CR4 in the VMCS. */
5023 cr4
= cr4_read_shadow();
5024 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5025 vmx
->host_state
.vmcs_host_cr4
= cr4
;
5027 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5028 #ifdef CONFIG_X86_64
5030 * Load null selectors, so we can avoid reloading them in
5031 * __vmx_load_host_state(), in case userspace uses the null selectors
5032 * too (the expected case).
5034 vmcs_write16(HOST_DS_SELECTOR
, 0);
5035 vmcs_write16(HOST_ES_SELECTOR
, 0);
5037 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5038 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5040 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5041 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5043 native_store_idt(&dt
);
5044 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5045 vmx
->host_idt_base
= dt
.address
;
5047 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5049 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5050 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5051 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5052 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5054 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5055 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5056 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5060 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5062 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5064 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5065 if (is_guest_mode(&vmx
->vcpu
))
5066 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5067 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5068 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5071 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5073 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5075 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5076 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5077 /* Enable the preemption timer dynamically */
5078 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5079 return pin_based_exec_ctrl
;
5082 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5084 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5086 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5087 if (cpu_has_secondary_exec_ctrls()) {
5088 if (kvm_vcpu_apicv_active(vcpu
))
5089 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5090 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5091 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5093 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5094 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5095 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5098 if (cpu_has_vmx_msr_bitmap())
5099 vmx_set_msr_bitmap(vcpu
);
5102 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5104 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5106 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5107 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5109 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5110 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5111 #ifdef CONFIG_X86_64
5112 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5113 CPU_BASED_CR8_LOAD_EXITING
;
5117 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5118 CPU_BASED_CR3_LOAD_EXITING
|
5119 CPU_BASED_INVLPG_EXITING
;
5120 return exec_control
;
5123 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
5125 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5126 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
5127 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5129 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5131 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5132 enable_unrestricted_guest
= 0;
5133 /* Enable INVPCID for non-ept guests may cause performance regression. */
5134 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5136 if (!enable_unrestricted_guest
)
5137 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5139 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5140 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5141 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5142 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5143 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5144 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5146 We can NOT enable shadow_vmcs here because we don't have yet
5149 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5152 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5154 return exec_control
;
5157 static void ept_set_mmio_spte_mask(void)
5160 * EPT Misconfigurations can be generated if the value of bits 2:0
5161 * of an EPT paging-structure entry is 110b (write/execute).
5163 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE
);
5166 #define VMX_XSS_EXIT_BITMAP 0
5168 * Sets up the vmcs for emulated real mode.
5170 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5172 #ifdef CONFIG_X86_64
5178 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5179 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5181 if (enable_shadow_vmcs
) {
5182 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5183 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5185 if (cpu_has_vmx_msr_bitmap())
5186 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5188 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5191 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5192 vmx
->hv_deadline_tsc
= -1;
5194 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5196 if (cpu_has_secondary_exec_ctrls()) {
5197 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5198 vmx_secondary_exec_control(vmx
));
5201 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5202 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5203 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5204 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5205 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5207 vmcs_write16(GUEST_INTR_STATUS
, 0);
5209 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5210 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5214 vmcs_write32(PLE_GAP
, ple_gap
);
5215 vmx
->ple_window
= ple_window
;
5216 vmx
->ple_window_dirty
= true;
5219 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5220 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5221 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5223 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5224 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5225 vmx_set_constant_host_state(vmx
);
5226 #ifdef CONFIG_X86_64
5227 rdmsrl(MSR_FS_BASE
, a
);
5228 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5229 rdmsrl(MSR_GS_BASE
, a
);
5230 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5232 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5233 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5236 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5237 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5238 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5239 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5240 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5242 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5243 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5245 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5246 u32 index
= vmx_msr_index
[i
];
5247 u32 data_low
, data_high
;
5250 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5252 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5254 vmx
->guest_msrs
[j
].index
= i
;
5255 vmx
->guest_msrs
[j
].data
= 0;
5256 vmx
->guest_msrs
[j
].mask
= -1ull;
5261 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5263 /* 22.2.1, 20.8.1 */
5264 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5266 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5267 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5269 set_cr4_guest_host_mask(vmx
);
5271 if (vmx_xsaves_supported())
5272 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5275 ASSERT(vmx
->pml_pg
);
5276 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5277 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5283 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5285 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5286 struct msr_data apic_base_msr
;
5289 vmx
->rmode
.vm86_active
= 0;
5291 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5292 kvm_set_cr8(vcpu
, 0);
5295 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5296 MSR_IA32_APICBASE_ENABLE
;
5297 if (kvm_vcpu_is_reset_bsp(vcpu
))
5298 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5299 apic_base_msr
.host_initiated
= true;
5300 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5303 vmx_segment_cache_clear(vmx
);
5305 seg_setup(VCPU_SREG_CS
);
5306 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5307 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5309 seg_setup(VCPU_SREG_DS
);
5310 seg_setup(VCPU_SREG_ES
);
5311 seg_setup(VCPU_SREG_FS
);
5312 seg_setup(VCPU_SREG_GS
);
5313 seg_setup(VCPU_SREG_SS
);
5315 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5316 vmcs_writel(GUEST_TR_BASE
, 0);
5317 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5318 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5320 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5321 vmcs_writel(GUEST_LDTR_BASE
, 0);
5322 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5323 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5326 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5327 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5328 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5329 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5332 vmcs_writel(GUEST_RFLAGS
, 0x02);
5333 kvm_rip_write(vcpu
, 0xfff0);
5335 vmcs_writel(GUEST_GDTR_BASE
, 0);
5336 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5338 vmcs_writel(GUEST_IDTR_BASE
, 0);
5339 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5341 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5342 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5343 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5347 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5349 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5350 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5351 if (cpu_need_tpr_shadow(vcpu
))
5352 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5353 __pa(vcpu
->arch
.apic
->regs
));
5354 vmcs_write32(TPR_THRESHOLD
, 0);
5357 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5359 if (kvm_vcpu_apicv_active(vcpu
))
5360 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5363 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5365 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5366 vmx
->vcpu
.arch
.cr0
= cr0
;
5367 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5368 vmx_set_cr4(vcpu
, 0);
5369 vmx_set_efer(vcpu
, 0);
5371 update_exception_bitmap(vcpu
);
5373 vpid_sync_context(vmx
->vpid
);
5377 * In nested virtualization, check if L1 asked to exit on external interrupts.
5378 * For most existing hypervisors, this will always return true.
5380 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5382 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5383 PIN_BASED_EXT_INTR_MASK
;
5387 * In nested virtualization, check if L1 has set
5388 * VM_EXIT_ACK_INTR_ON_EXIT
5390 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5392 return get_vmcs12(vcpu
)->vm_exit_controls
&
5393 VM_EXIT_ACK_INTR_ON_EXIT
;
5396 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5398 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5399 PIN_BASED_NMI_EXITING
;
5402 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5404 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5405 CPU_BASED_VIRTUAL_INTR_PENDING
);
5408 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5410 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5411 enable_irq_window(vcpu
);
5415 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5416 CPU_BASED_VIRTUAL_NMI_PENDING
);
5419 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5421 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5423 int irq
= vcpu
->arch
.interrupt
.nr
;
5425 trace_kvm_inj_virq(irq
);
5427 ++vcpu
->stat
.irq_injections
;
5428 if (vmx
->rmode
.vm86_active
) {
5430 if (vcpu
->arch
.interrupt
.soft
)
5431 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5432 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5433 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5436 intr
= irq
| INTR_INFO_VALID_MASK
;
5437 if (vcpu
->arch
.interrupt
.soft
) {
5438 intr
|= INTR_TYPE_SOFT_INTR
;
5439 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5440 vmx
->vcpu
.arch
.event_exit_inst_len
);
5442 intr
|= INTR_TYPE_EXT_INTR
;
5443 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5446 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5448 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5450 if (!is_guest_mode(vcpu
)) {
5451 ++vcpu
->stat
.nmi_injections
;
5452 vmx
->nmi_known_unmasked
= false;
5455 if (vmx
->rmode
.vm86_active
) {
5456 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5457 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5461 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5462 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5465 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5467 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5469 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5472 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5474 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5476 vmx
->nmi_known_unmasked
= !masked
;
5478 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5479 GUEST_INTR_STATE_NMI
);
5481 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5482 GUEST_INTR_STATE_NMI
);
5485 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5487 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5490 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5491 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5492 | GUEST_INTR_STATE_NMI
));
5495 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5497 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5498 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5499 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5500 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5503 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5507 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5511 kvm
->arch
.tss_addr
= addr
;
5512 return init_rmode_tss(kvm
);
5515 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5520 * Update instruction length as we may reinject the exception
5521 * from user space while in guest debugging mode.
5523 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5524 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5525 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5529 if (vcpu
->guest_debug
&
5530 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5547 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5548 int vec
, u32 err_code
)
5551 * Instruction with address size override prefix opcode 0x67
5552 * Cause the #SS fault with 0 error code in VM86 mode.
5554 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5555 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5556 if (vcpu
->arch
.halt_request
) {
5557 vcpu
->arch
.halt_request
= 0;
5558 return kvm_vcpu_halt(vcpu
);
5566 * Forward all other exceptions that are valid in real mode.
5567 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5568 * the required debugging infrastructure rework.
5570 kvm_queue_exception(vcpu
, vec
);
5575 * Trigger machine check on the host. We assume all the MSRs are already set up
5576 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5577 * We pass a fake environment to the machine check handler because we want
5578 * the guest to be always treated like user space, no matter what context
5579 * it used internally.
5581 static void kvm_machine_check(void)
5583 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5584 struct pt_regs regs
= {
5585 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5586 .flags
= X86_EFLAGS_IF
,
5589 do_machine_check(®s
, 0);
5593 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5595 /* already handled by vcpu_run */
5599 static int handle_exception(struct kvm_vcpu
*vcpu
)
5601 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5602 struct kvm_run
*kvm_run
= vcpu
->run
;
5603 u32 intr_info
, ex_no
, error_code
;
5604 unsigned long cr2
, rip
, dr6
;
5606 enum emulation_result er
;
5608 vect_info
= vmx
->idt_vectoring_info
;
5609 intr_info
= vmx
->exit_intr_info
;
5611 if (is_machine_check(intr_info
))
5612 return handle_machine_check(vcpu
);
5614 if (is_nmi(intr_info
))
5615 return 1; /* already handled by vmx_vcpu_run() */
5617 if (is_invalid_opcode(intr_info
)) {
5618 if (is_guest_mode(vcpu
)) {
5619 kvm_queue_exception(vcpu
, UD_VECTOR
);
5622 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5623 if (er
!= EMULATE_DONE
)
5624 kvm_queue_exception(vcpu
, UD_VECTOR
);
5629 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5630 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5633 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5634 * MMIO, it is better to report an internal error.
5635 * See the comments in vmx_handle_exit.
5637 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5638 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5639 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5640 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5641 vcpu
->run
->internal
.ndata
= 3;
5642 vcpu
->run
->internal
.data
[0] = vect_info
;
5643 vcpu
->run
->internal
.data
[1] = intr_info
;
5644 vcpu
->run
->internal
.data
[2] = error_code
;
5648 if (is_page_fault(intr_info
)) {
5649 /* EPT won't cause page fault directly */
5651 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5652 trace_kvm_page_fault(cr2
, error_code
);
5654 if (kvm_event_needs_reinjection(vcpu
))
5655 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5656 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5659 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5661 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5662 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5666 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5669 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5670 if (!(vcpu
->guest_debug
&
5671 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5672 vcpu
->arch
.dr6
&= ~15;
5673 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5674 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5675 skip_emulated_instruction(vcpu
);
5677 kvm_queue_exception(vcpu
, DB_VECTOR
);
5680 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5681 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5685 * Update instruction length as we may reinject #BP from
5686 * user space while in guest debugging mode. Reading it for
5687 * #DB as well causes no harm, it is not used in that case.
5689 vmx
->vcpu
.arch
.event_exit_inst_len
=
5690 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5691 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5692 rip
= kvm_rip_read(vcpu
);
5693 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5694 kvm_run
->debug
.arch
.exception
= ex_no
;
5697 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5698 kvm_run
->ex
.exception
= ex_no
;
5699 kvm_run
->ex
.error_code
= error_code
;
5705 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5707 ++vcpu
->stat
.irq_exits
;
5711 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5713 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5717 static int handle_io(struct kvm_vcpu
*vcpu
)
5719 unsigned long exit_qualification
;
5720 int size
, in
, string
, ret
;
5723 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5724 string
= (exit_qualification
& 16) != 0;
5725 in
= (exit_qualification
& 8) != 0;
5727 ++vcpu
->stat
.io_exits
;
5730 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5732 port
= exit_qualification
>> 16;
5733 size
= (exit_qualification
& 7) + 1;
5735 ret
= kvm_skip_emulated_instruction(vcpu
);
5738 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5739 * KVM_EXIT_DEBUG here.
5741 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
5745 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5748 * Patch in the VMCALL instruction:
5750 hypercall
[0] = 0x0f;
5751 hypercall
[1] = 0x01;
5752 hypercall
[2] = 0xc1;
5755 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5756 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5758 if (is_guest_mode(vcpu
)) {
5759 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5760 unsigned long orig_val
= val
;
5763 * We get here when L2 changed cr0 in a way that did not change
5764 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5765 * but did change L0 shadowed bits. So we first calculate the
5766 * effective cr0 value that L1 would like to write into the
5767 * hardware. It consists of the L2-owned bits from the new
5768 * value combined with the L1-owned bits from L1's guest_cr0.
5770 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5771 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5773 if (!nested_guest_cr0_valid(vcpu
, val
))
5776 if (kvm_set_cr0(vcpu
, val
))
5778 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5781 if (to_vmx(vcpu
)->nested
.vmxon
&&
5782 !nested_host_cr0_valid(vcpu
, val
))
5785 return kvm_set_cr0(vcpu
, val
);
5789 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5791 if (is_guest_mode(vcpu
)) {
5792 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5793 unsigned long orig_val
= val
;
5795 /* analogously to handle_set_cr0 */
5796 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5797 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5798 if (kvm_set_cr4(vcpu
, val
))
5800 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5803 return kvm_set_cr4(vcpu
, val
);
5806 static int handle_cr(struct kvm_vcpu
*vcpu
)
5808 unsigned long exit_qualification
, val
;
5814 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5815 cr
= exit_qualification
& 15;
5816 reg
= (exit_qualification
>> 8) & 15;
5817 switch ((exit_qualification
>> 4) & 3) {
5818 case 0: /* mov to cr */
5819 val
= kvm_register_readl(vcpu
, reg
);
5820 trace_kvm_cr_write(cr
, val
);
5823 err
= handle_set_cr0(vcpu
, val
);
5824 return kvm_complete_insn_gp(vcpu
, err
);
5826 err
= kvm_set_cr3(vcpu
, val
);
5827 return kvm_complete_insn_gp(vcpu
, err
);
5829 err
= handle_set_cr4(vcpu
, val
);
5830 return kvm_complete_insn_gp(vcpu
, err
);
5832 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5834 err
= kvm_set_cr8(vcpu
, cr8
);
5835 ret
= kvm_complete_insn_gp(vcpu
, err
);
5836 if (lapic_in_kernel(vcpu
))
5838 if (cr8_prev
<= cr8
)
5841 * TODO: we might be squashing a
5842 * KVM_GUESTDBG_SINGLESTEP-triggered
5843 * KVM_EXIT_DEBUG here.
5845 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5851 WARN_ONCE(1, "Guest should always own CR0.TS");
5852 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5853 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5854 return kvm_skip_emulated_instruction(vcpu
);
5855 case 1: /*mov from cr*/
5858 val
= kvm_read_cr3(vcpu
);
5859 kvm_register_write(vcpu
, reg
, val
);
5860 trace_kvm_cr_read(cr
, val
);
5861 return kvm_skip_emulated_instruction(vcpu
);
5863 val
= kvm_get_cr8(vcpu
);
5864 kvm_register_write(vcpu
, reg
, val
);
5865 trace_kvm_cr_read(cr
, val
);
5866 return kvm_skip_emulated_instruction(vcpu
);
5870 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5871 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5872 kvm_lmsw(vcpu
, val
);
5874 return kvm_skip_emulated_instruction(vcpu
);
5878 vcpu
->run
->exit_reason
= 0;
5879 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5880 (int)(exit_qualification
>> 4) & 3, cr
);
5884 static int handle_dr(struct kvm_vcpu
*vcpu
)
5886 unsigned long exit_qualification
;
5889 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5890 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5892 /* First, if DR does not exist, trigger UD */
5893 if (!kvm_require_dr(vcpu
, dr
))
5896 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5897 if (!kvm_require_cpl(vcpu
, 0))
5899 dr7
= vmcs_readl(GUEST_DR7
);
5902 * As the vm-exit takes precedence over the debug trap, we
5903 * need to emulate the latter, either for the host or the
5904 * guest debugging itself.
5906 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5907 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5908 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5909 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5910 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5911 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5914 vcpu
->arch
.dr6
&= ~15;
5915 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5916 kvm_queue_exception(vcpu
, DB_VECTOR
);
5921 if (vcpu
->guest_debug
== 0) {
5922 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
5923 CPU_BASED_MOV_DR_EXITING
);
5926 * No more DR vmexits; force a reload of the debug registers
5927 * and reenter on this instruction. The next vmexit will
5928 * retrieve the full state of the debug registers.
5930 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5934 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5935 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5938 if (kvm_get_dr(vcpu
, dr
, &val
))
5940 kvm_register_write(vcpu
, reg
, val
);
5942 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5945 return kvm_skip_emulated_instruction(vcpu
);
5948 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5950 return vcpu
->arch
.dr6
;
5953 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5957 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5959 get_debugreg(vcpu
->arch
.db
[0], 0);
5960 get_debugreg(vcpu
->arch
.db
[1], 1);
5961 get_debugreg(vcpu
->arch
.db
[2], 2);
5962 get_debugreg(vcpu
->arch
.db
[3], 3);
5963 get_debugreg(vcpu
->arch
.dr6
, 6);
5964 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5966 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5967 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
5970 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5972 vmcs_writel(GUEST_DR7
, val
);
5975 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5977 return kvm_emulate_cpuid(vcpu
);
5980 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5982 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5983 struct msr_data msr_info
;
5985 msr_info
.index
= ecx
;
5986 msr_info
.host_initiated
= false;
5987 if (vmx_get_msr(vcpu
, &msr_info
)) {
5988 trace_kvm_msr_read_ex(ecx
);
5989 kvm_inject_gp(vcpu
, 0);
5993 trace_kvm_msr_read(ecx
, msr_info
.data
);
5995 /* FIXME: handling of bits 32:63 of rax, rdx */
5996 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5997 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5998 return kvm_skip_emulated_instruction(vcpu
);
6001 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6003 struct msr_data msr
;
6004 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6005 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6006 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6010 msr
.host_initiated
= false;
6011 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6012 trace_kvm_msr_write_ex(ecx
, data
);
6013 kvm_inject_gp(vcpu
, 0);
6017 trace_kvm_msr_write(ecx
, data
);
6018 return kvm_skip_emulated_instruction(vcpu
);
6021 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6023 kvm_apic_update_ppr(vcpu
);
6027 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6029 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6030 CPU_BASED_VIRTUAL_INTR_PENDING
);
6032 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6034 ++vcpu
->stat
.irq_window_exits
;
6038 static int handle_halt(struct kvm_vcpu
*vcpu
)
6040 return kvm_emulate_halt(vcpu
);
6043 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6045 return kvm_emulate_hypercall(vcpu
);
6048 static int handle_invd(struct kvm_vcpu
*vcpu
)
6050 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6053 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6055 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6057 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6058 return kvm_skip_emulated_instruction(vcpu
);
6061 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6065 err
= kvm_rdpmc(vcpu
);
6066 return kvm_complete_insn_gp(vcpu
, err
);
6069 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6071 return kvm_emulate_wbinvd(vcpu
);
6074 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6076 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6077 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6079 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6080 return kvm_skip_emulated_instruction(vcpu
);
6084 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6086 kvm_skip_emulated_instruction(vcpu
);
6087 WARN(1, "this should never happen\n");
6091 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6093 kvm_skip_emulated_instruction(vcpu
);
6094 WARN(1, "this should never happen\n");
6098 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6100 if (likely(fasteoi
)) {
6101 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6102 int access_type
, offset
;
6104 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6105 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6107 * Sane guest uses MOV to write EOI, with written value
6108 * not cared. So make a short-circuit here by avoiding
6109 * heavy instruction emulation.
6111 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6112 (offset
== APIC_EOI
)) {
6113 kvm_lapic_set_eoi(vcpu
);
6114 return kvm_skip_emulated_instruction(vcpu
);
6117 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6120 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6122 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6123 int vector
= exit_qualification
& 0xff;
6125 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6126 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6130 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6132 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6133 u32 offset
= exit_qualification
& 0xfff;
6135 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6136 kvm_apic_write_nodecode(vcpu
, offset
);
6140 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6142 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6143 unsigned long exit_qualification
;
6144 bool has_error_code
= false;
6147 int reason
, type
, idt_v
, idt_index
;
6149 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6150 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6151 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6153 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6155 reason
= (u32
)exit_qualification
>> 30;
6156 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6158 case INTR_TYPE_NMI_INTR
:
6159 vcpu
->arch
.nmi_injected
= false;
6160 vmx_set_nmi_mask(vcpu
, true);
6162 case INTR_TYPE_EXT_INTR
:
6163 case INTR_TYPE_SOFT_INTR
:
6164 kvm_clear_interrupt_queue(vcpu
);
6166 case INTR_TYPE_HARD_EXCEPTION
:
6167 if (vmx
->idt_vectoring_info
&
6168 VECTORING_INFO_DELIVER_CODE_MASK
) {
6169 has_error_code
= true;
6171 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6174 case INTR_TYPE_SOFT_EXCEPTION
:
6175 kvm_clear_exception_queue(vcpu
);
6181 tss_selector
= exit_qualification
;
6183 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6184 type
!= INTR_TYPE_EXT_INTR
&&
6185 type
!= INTR_TYPE_NMI_INTR
))
6186 skip_emulated_instruction(vcpu
);
6188 if (kvm_task_switch(vcpu
, tss_selector
,
6189 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6190 has_error_code
, error_code
) == EMULATE_FAIL
) {
6191 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6192 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6193 vcpu
->run
->internal
.ndata
= 0;
6198 * TODO: What about debug traps on tss switch?
6199 * Are we supposed to inject them and update dr6?
6205 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6207 unsigned long exit_qualification
;
6211 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6213 if (is_guest_mode(vcpu
)
6214 && !(exit_qualification
& EPT_VIOLATION_GVA_TRANSLATED
)) {
6216 * Fix up exit_qualification according to whether guest
6217 * page table accesses are reads or writes.
6219 u64 eptp
= nested_ept_get_cr3(vcpu
);
6220 if (!(eptp
& VMX_EPT_AD_ENABLE_BIT
))
6221 exit_qualification
&= ~EPT_VIOLATION_ACC_WRITE
;
6225 * EPT violation happened while executing iret from NMI,
6226 * "blocked by NMI" bit has to be set before next VM entry.
6227 * There are errata that may cause this bit to not be set:
6230 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6231 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6232 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6234 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6235 trace_kvm_page_fault(gpa
, exit_qualification
);
6237 /* Is it a read fault? */
6238 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6239 ? PFERR_USER_MASK
: 0;
6240 /* Is it a write fault? */
6241 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6242 ? PFERR_WRITE_MASK
: 0;
6243 /* Is it a fetch fault? */
6244 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6245 ? PFERR_FETCH_MASK
: 0;
6246 /* ept page table entry is present? */
6247 error_code
|= (exit_qualification
&
6248 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6249 EPT_VIOLATION_EXECUTABLE
))
6250 ? PFERR_PRESENT_MASK
: 0;
6252 vcpu
->arch
.gpa_available
= true;
6253 vcpu
->arch
.exit_qualification
= exit_qualification
;
6255 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6258 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6263 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6264 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6265 trace_kvm_fast_mmio(gpa
);
6266 return kvm_skip_emulated_instruction(vcpu
);
6269 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6270 vcpu
->arch
.gpa_available
= true;
6271 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6272 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6275 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6276 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6278 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6281 /* It is the real ept misconfig */
6284 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6285 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6290 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6292 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6293 CPU_BASED_VIRTUAL_NMI_PENDING
);
6294 ++vcpu
->stat
.nmi_window_exits
;
6295 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6300 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6302 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6303 enum emulation_result err
= EMULATE_DONE
;
6306 bool intr_window_requested
;
6307 unsigned count
= 130;
6309 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6310 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6312 while (vmx
->emulation_required
&& count
-- != 0) {
6313 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6314 return handle_interrupt_window(&vmx
->vcpu
);
6316 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6319 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6321 if (err
== EMULATE_USER_EXIT
) {
6322 ++vcpu
->stat
.mmio_exits
;
6327 if (err
!= EMULATE_DONE
) {
6328 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6329 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6330 vcpu
->run
->internal
.ndata
= 0;
6334 if (vcpu
->arch
.halt_request
) {
6335 vcpu
->arch
.halt_request
= 0;
6336 ret
= kvm_vcpu_halt(vcpu
);
6340 if (signal_pending(current
))
6350 static int __grow_ple_window(int val
)
6352 if (ple_window_grow
< 1)
6355 val
= min(val
, ple_window_actual_max
);
6357 if (ple_window_grow
< ple_window
)
6358 val
*= ple_window_grow
;
6360 val
+= ple_window_grow
;
6365 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6370 if (modifier
< ple_window
)
6375 return max(val
, minimum
);
6378 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6380 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6381 int old
= vmx
->ple_window
;
6383 vmx
->ple_window
= __grow_ple_window(old
);
6385 if (vmx
->ple_window
!= old
)
6386 vmx
->ple_window_dirty
= true;
6388 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6391 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6393 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6394 int old
= vmx
->ple_window
;
6396 vmx
->ple_window
= __shrink_ple_window(old
,
6397 ple_window_shrink
, ple_window
);
6399 if (vmx
->ple_window
!= old
)
6400 vmx
->ple_window_dirty
= true;
6402 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6406 * ple_window_actual_max is computed to be one grow_ple_window() below
6407 * ple_window_max. (See __grow_ple_window for the reason.)
6408 * This prevents overflows, because ple_window_max is int.
6409 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6411 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6413 static void update_ple_window_actual_max(void)
6415 ple_window_actual_max
=
6416 __shrink_ple_window(max(ple_window_max
, ple_window
),
6417 ple_window_grow
, INT_MIN
);
6421 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6423 static void wakeup_handler(void)
6425 struct kvm_vcpu
*vcpu
;
6426 int cpu
= smp_processor_id();
6428 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6429 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6430 blocked_vcpu_list
) {
6431 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6433 if (pi_test_on(pi_desc
) == 1)
6434 kvm_vcpu_kick(vcpu
);
6436 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6439 void vmx_enable_tdp(void)
6441 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6442 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6443 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6444 0ull, VMX_EPT_EXECUTABLE_MASK
,
6445 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6446 enable_ept_ad_bits
? 0ull : VMX_EPT_RWX_MASK
);
6448 ept_set_mmio_spte_mask();
6452 static __init
int hardware_setup(void)
6454 int r
= -ENOMEM
, i
, msr
;
6456 rdmsrl_safe(MSR_EFER
, &host_efer
);
6458 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6459 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6461 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6462 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6467 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6468 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6469 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6472 * Allow direct access to the PC debug port (it is often used for I/O
6473 * delays, but the vmexits simply slow things down).
6475 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6476 clear_bit(0x80, vmx_io_bitmap_a
);
6478 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6480 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6481 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6483 if (setup_vmcs_config(&vmcs_config
) < 0) {
6488 if (boot_cpu_has(X86_FEATURE_NX
))
6489 kvm_enable_efer_bits(EFER_NX
);
6491 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6492 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6495 if (!cpu_has_vmx_shadow_vmcs())
6496 enable_shadow_vmcs
= 0;
6497 if (enable_shadow_vmcs
)
6498 init_vmcs_shadow_fields();
6500 if (!cpu_has_vmx_ept() ||
6501 !cpu_has_vmx_ept_4levels()) {
6503 enable_unrestricted_guest
= 0;
6504 enable_ept_ad_bits
= 0;
6507 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
6508 enable_ept_ad_bits
= 0;
6510 if (!cpu_has_vmx_unrestricted_guest())
6511 enable_unrestricted_guest
= 0;
6513 if (!cpu_has_vmx_flexpriority())
6514 flexpriority_enabled
= 0;
6517 * set_apic_access_page_addr() is used to reload apic access
6518 * page upon invalidation. No need to do anything if not
6519 * using the APIC_ACCESS_ADDR VMCS field.
6521 if (!flexpriority_enabled
)
6522 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6524 if (!cpu_has_vmx_tpr_shadow())
6525 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6527 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6528 kvm_disable_largepages();
6530 if (!cpu_has_vmx_ple())
6533 if (!cpu_has_vmx_apicv()) {
6535 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6538 if (cpu_has_vmx_tsc_scaling()) {
6539 kvm_has_tsc_control
= true;
6540 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6541 kvm_tsc_scaling_ratio_frac_bits
= 48;
6544 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6545 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6546 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6547 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6548 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6549 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6550 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6552 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6553 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6554 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6555 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6556 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6557 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6558 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6559 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6561 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6563 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6564 if (msr
== 0x839 /* TMCCT */)
6566 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6570 * TPR reads and writes can be virtualized even if virtual interrupt
6571 * delivery is not in use.
6573 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6574 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6577 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6579 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6586 update_ple_window_actual_max();
6589 * Only enable PML when hardware supports PML feature, and both EPT
6590 * and EPT A/D bit features are enabled -- PML depends on them to work.
6592 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6596 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6597 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6598 kvm_x86_ops
->flush_log_dirty
= NULL
;
6599 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6602 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6605 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6606 cpu_preemption_timer_multi
=
6607 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6609 kvm_x86_ops
->set_hv_timer
= NULL
;
6610 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6613 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6615 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6617 return alloc_kvm_area();
6620 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6621 free_page((unsigned long)vmx_bitmap
[i
]);
6626 static __exit
void hardware_unsetup(void)
6630 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6631 free_page((unsigned long)vmx_bitmap
[i
]);
6637 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6638 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6640 static int handle_pause(struct kvm_vcpu
*vcpu
)
6643 grow_ple_window(vcpu
);
6645 kvm_vcpu_on_spin(vcpu
);
6646 return kvm_skip_emulated_instruction(vcpu
);
6649 static int handle_nop(struct kvm_vcpu
*vcpu
)
6651 return kvm_skip_emulated_instruction(vcpu
);
6654 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6656 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6657 return handle_nop(vcpu
);
6660 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6665 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6667 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6668 return handle_nop(vcpu
);
6672 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6673 * We could reuse a single VMCS for all the L2 guests, but we also want the
6674 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6675 * allows keeping them loaded on the processor, and in the future will allow
6676 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6677 * every entry if they never change.
6678 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6679 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6681 * The following functions allocate and free a vmcs02 in this pool.
6684 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6685 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6687 struct vmcs02_list
*item
;
6688 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6689 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6690 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6691 return &item
->vmcs02
;
6694 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6695 /* Recycle the least recently used VMCS. */
6696 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6697 struct vmcs02_list
, list
);
6698 item
->vmptr
= vmx
->nested
.current_vmptr
;
6699 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6700 return &item
->vmcs02
;
6703 /* Create a new VMCS */
6704 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6707 item
->vmcs02
.vmcs
= alloc_vmcs();
6708 item
->vmcs02
.shadow_vmcs
= NULL
;
6709 if (!item
->vmcs02
.vmcs
) {
6713 loaded_vmcs_init(&item
->vmcs02
);
6714 item
->vmptr
= vmx
->nested
.current_vmptr
;
6715 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6716 vmx
->nested
.vmcs02_num
++;
6717 return &item
->vmcs02
;
6720 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6721 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6723 struct vmcs02_list
*item
;
6724 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6725 if (item
->vmptr
== vmptr
) {
6726 free_loaded_vmcs(&item
->vmcs02
);
6727 list_del(&item
->list
);
6729 vmx
->nested
.vmcs02_num
--;
6735 * Free all VMCSs saved for this vcpu, except the one pointed by
6736 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6737 * must be &vmx->vmcs01.
6739 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6741 struct vmcs02_list
*item
, *n
;
6743 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6744 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6746 * Something will leak if the above WARN triggers. Better than
6749 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6752 free_loaded_vmcs(&item
->vmcs02
);
6753 list_del(&item
->list
);
6755 vmx
->nested
.vmcs02_num
--;
6760 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6761 * set the success or error code of an emulated VMX instruction, as specified
6762 * by Vol 2B, VMX Instruction Reference, "Conventions".
6764 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6766 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6767 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6768 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6771 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6773 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6774 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6775 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6779 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6780 u32 vm_instruction_error
)
6782 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6784 * failValid writes the error number to the current VMCS, which
6785 * can't be done there isn't a current VMCS.
6787 nested_vmx_failInvalid(vcpu
);
6790 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6791 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6792 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6794 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6796 * We don't need to force a shadow sync because
6797 * VM_INSTRUCTION_ERROR is not shadowed
6801 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6803 /* TODO: not to reset guest simply here. */
6804 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6805 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
6808 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6810 struct vcpu_vmx
*vmx
=
6811 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6813 vmx
->nested
.preemption_timer_expired
= true;
6814 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6815 kvm_vcpu_kick(&vmx
->vcpu
);
6817 return HRTIMER_NORESTART
;
6821 * Decode the memory-address operand of a vmx instruction, as recorded on an
6822 * exit caused by such an instruction (run by a guest hypervisor).
6823 * On success, returns 0. When the operand is invalid, returns 1 and throws
6826 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6827 unsigned long exit_qualification
,
6828 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6832 struct kvm_segment s
;
6835 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6836 * Execution", on an exit, vmx_instruction_info holds most of the
6837 * addressing components of the operand. Only the displacement part
6838 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6839 * For how an actual address is calculated from all these components,
6840 * refer to Vol. 1, "Operand Addressing".
6842 int scaling
= vmx_instruction_info
& 3;
6843 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6844 bool is_reg
= vmx_instruction_info
& (1u << 10);
6845 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6846 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6847 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6848 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6849 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6852 kvm_queue_exception(vcpu
, UD_VECTOR
);
6856 /* Addr = segment_base + offset */
6857 /* offset = base + [index * scale] + displacement */
6858 off
= exit_qualification
; /* holds the displacement */
6860 off
+= kvm_register_read(vcpu
, base_reg
);
6862 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6863 vmx_get_segment(vcpu
, &s
, seg_reg
);
6864 *ret
= s
.base
+ off
;
6866 if (addr_size
== 1) /* 32 bit */
6869 /* Checks for #GP/#SS exceptions. */
6871 if (is_long_mode(vcpu
)) {
6872 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6873 * non-canonical form. This is the only check on the memory
6874 * destination for long mode!
6876 exn
= is_noncanonical_address(*ret
);
6877 } else if (is_protmode(vcpu
)) {
6878 /* Protected mode: apply checks for segment validity in the
6880 * - segment type check (#GP(0) may be thrown)
6881 * - usability check (#GP(0)/#SS(0))
6882 * - limit check (#GP(0)/#SS(0))
6885 /* #GP(0) if the destination operand is located in a
6886 * read-only data segment or any code segment.
6888 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6890 /* #GP(0) if the source operand is located in an
6891 * execute-only code segment
6893 exn
= ((s
.type
& 0xa) == 8);
6895 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6898 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6900 exn
= (s
.unusable
!= 0);
6901 /* Protected mode: #GP(0)/#SS(0) if the memory
6902 * operand is outside the segment limit.
6904 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6907 kvm_queue_exception_e(vcpu
,
6908 seg_reg
== VCPU_SREG_SS
?
6909 SS_VECTOR
: GP_VECTOR
,
6917 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
6920 struct x86_exception e
;
6922 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6923 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6926 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
6927 sizeof(*vmpointer
), &e
)) {
6928 kvm_inject_page_fault(vcpu
, &e
);
6935 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
6937 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6938 struct vmcs
*shadow_vmcs
;
6940 if (cpu_has_vmx_msr_bitmap()) {
6941 vmx
->nested
.msr_bitmap
=
6942 (unsigned long *)__get_free_page(GFP_KERNEL
);
6943 if (!vmx
->nested
.msr_bitmap
)
6944 goto out_msr_bitmap
;
6947 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
6948 if (!vmx
->nested
.cached_vmcs12
)
6949 goto out_cached_vmcs12
;
6951 if (enable_shadow_vmcs
) {
6952 shadow_vmcs
= alloc_vmcs();
6954 goto out_shadow_vmcs
;
6955 /* mark vmcs as shadow */
6956 shadow_vmcs
->revision_id
|= (1u << 31);
6957 /* init shadow vmcs */
6958 vmcs_clear(shadow_vmcs
);
6959 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
6962 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6963 vmx
->nested
.vmcs02_num
= 0;
6965 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6966 HRTIMER_MODE_REL_PINNED
);
6967 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6969 vmx
->nested
.vmxon
= true;
6973 kfree(vmx
->nested
.cached_vmcs12
);
6976 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
6983 * Emulate the VMXON instruction.
6984 * Currently, we just remember that VMX is active, and do not save or even
6985 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6986 * do not currently need to store anything in that guest-allocated memory
6987 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6988 * argument is different from the VMXON pointer (which the spec says they do).
6990 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6995 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6996 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6997 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7000 * The Intel VMX Instruction Reference lists a bunch of bits that are
7001 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7002 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7003 * Otherwise, we should fail with #UD. But most faulting conditions
7004 * have already been checked by hardware, prior to the VM-exit for
7005 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7006 * that bit set to 1 in non-root mode.
7008 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7009 kvm_queue_exception(vcpu
, UD_VECTOR
);
7013 if (vmx
->nested
.vmxon
) {
7014 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7015 return kvm_skip_emulated_instruction(vcpu
);
7018 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7019 != VMXON_NEEDED_FEATURES
) {
7020 kvm_inject_gp(vcpu
, 0);
7024 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7029 * The first 4 bytes of VMXON region contain the supported
7030 * VMCS revision identifier
7032 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7033 * which replaces physical address width with 32
7035 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7036 nested_vmx_failInvalid(vcpu
);
7037 return kvm_skip_emulated_instruction(vcpu
);
7040 page
= nested_get_page(vcpu
, vmptr
);
7042 nested_vmx_failInvalid(vcpu
);
7043 return kvm_skip_emulated_instruction(vcpu
);
7045 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7047 nested_release_page_clean(page
);
7048 nested_vmx_failInvalid(vcpu
);
7049 return kvm_skip_emulated_instruction(vcpu
);
7052 nested_release_page_clean(page
);
7054 vmx
->nested
.vmxon_ptr
= vmptr
;
7055 ret
= enter_vmx_operation(vcpu
);
7059 nested_vmx_succeed(vcpu
);
7060 return kvm_skip_emulated_instruction(vcpu
);
7064 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7065 * for running VMX instructions (except VMXON, whose prerequisites are
7066 * slightly different). It also specifies what exception to inject otherwise.
7067 * Note that many of these exceptions have priority over VM exits, so they
7068 * don't have to be checked again here.
7070 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7072 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7073 kvm_queue_exception(vcpu
, UD_VECTOR
);
7079 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7081 if (vmx
->nested
.current_vmptr
== -1ull)
7084 /* current_vmptr and current_vmcs12 are always set/reset together */
7085 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
7088 if (enable_shadow_vmcs
) {
7089 /* copy to memory all shadowed fields in case
7090 they were modified */
7091 copy_shadow_to_vmcs12(vmx
);
7092 vmx
->nested
.sync_shadow_vmcs
= false;
7093 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
7094 SECONDARY_EXEC_SHADOW_VMCS
);
7095 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7097 vmx
->nested
.posted_intr_nv
= -1;
7099 /* Flush VMCS12 to guest memory */
7100 memcpy(vmx
->nested
.current_vmcs12
, vmx
->nested
.cached_vmcs12
,
7103 kunmap(vmx
->nested
.current_vmcs12_page
);
7104 nested_release_page(vmx
->nested
.current_vmcs12_page
);
7105 vmx
->nested
.current_vmptr
= -1ull;
7106 vmx
->nested
.current_vmcs12
= NULL
;
7110 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7111 * just stops using VMX.
7113 static void free_nested(struct vcpu_vmx
*vmx
)
7115 if (!vmx
->nested
.vmxon
)
7118 vmx
->nested
.vmxon
= false;
7119 free_vpid(vmx
->nested
.vpid02
);
7120 nested_release_vmcs12(vmx
);
7121 if (vmx
->nested
.msr_bitmap
) {
7122 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7123 vmx
->nested
.msr_bitmap
= NULL
;
7125 if (enable_shadow_vmcs
) {
7126 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7127 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7128 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7130 kfree(vmx
->nested
.cached_vmcs12
);
7131 /* Unpin physical memory we referred to in current vmcs02 */
7132 if (vmx
->nested
.apic_access_page
) {
7133 nested_release_page(vmx
->nested
.apic_access_page
);
7134 vmx
->nested
.apic_access_page
= NULL
;
7136 if (vmx
->nested
.virtual_apic_page
) {
7137 nested_release_page(vmx
->nested
.virtual_apic_page
);
7138 vmx
->nested
.virtual_apic_page
= NULL
;
7140 if (vmx
->nested
.pi_desc_page
) {
7141 kunmap(vmx
->nested
.pi_desc_page
);
7142 nested_release_page(vmx
->nested
.pi_desc_page
);
7143 vmx
->nested
.pi_desc_page
= NULL
;
7144 vmx
->nested
.pi_desc
= NULL
;
7147 nested_free_all_saved_vmcss(vmx
);
7150 /* Emulate the VMXOFF instruction */
7151 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7153 if (!nested_vmx_check_permission(vcpu
))
7155 free_nested(to_vmx(vcpu
));
7156 nested_vmx_succeed(vcpu
);
7157 return kvm_skip_emulated_instruction(vcpu
);
7160 /* Emulate the VMCLEAR instruction */
7161 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7163 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7167 if (!nested_vmx_check_permission(vcpu
))
7170 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7173 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7174 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7175 return kvm_skip_emulated_instruction(vcpu
);
7178 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7179 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7180 return kvm_skip_emulated_instruction(vcpu
);
7183 if (vmptr
== vmx
->nested
.current_vmptr
)
7184 nested_release_vmcs12(vmx
);
7186 kvm_vcpu_write_guest(vcpu
,
7187 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7188 &zero
, sizeof(zero
));
7190 nested_free_vmcs02(vmx
, vmptr
);
7192 nested_vmx_succeed(vcpu
);
7193 return kvm_skip_emulated_instruction(vcpu
);
7196 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7198 /* Emulate the VMLAUNCH instruction */
7199 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7201 return nested_vmx_run(vcpu
, true);
7204 /* Emulate the VMRESUME instruction */
7205 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7208 return nested_vmx_run(vcpu
, false);
7211 enum vmcs_field_type
{
7212 VMCS_FIELD_TYPE_U16
= 0,
7213 VMCS_FIELD_TYPE_U64
= 1,
7214 VMCS_FIELD_TYPE_U32
= 2,
7215 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
7218 static inline int vmcs_field_type(unsigned long field
)
7220 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
7221 return VMCS_FIELD_TYPE_U32
;
7222 return (field
>> 13) & 0x3 ;
7225 static inline int vmcs_field_readonly(unsigned long field
)
7227 return (((field
>> 10) & 0x3) == 1);
7231 * Read a vmcs12 field. Since these can have varying lengths and we return
7232 * one type, we chose the biggest type (u64) and zero-extend the return value
7233 * to that size. Note that the caller, handle_vmread, might need to use only
7234 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7235 * 64-bit fields are to be returned).
7237 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7238 unsigned long field
, u64
*ret
)
7240 short offset
= vmcs_field_to_offset(field
);
7246 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7248 switch (vmcs_field_type(field
)) {
7249 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7250 *ret
= *((natural_width
*)p
);
7252 case VMCS_FIELD_TYPE_U16
:
7255 case VMCS_FIELD_TYPE_U32
:
7258 case VMCS_FIELD_TYPE_U64
:
7268 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7269 unsigned long field
, u64 field_value
){
7270 short offset
= vmcs_field_to_offset(field
);
7271 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7275 switch (vmcs_field_type(field
)) {
7276 case VMCS_FIELD_TYPE_U16
:
7277 *(u16
*)p
= field_value
;
7279 case VMCS_FIELD_TYPE_U32
:
7280 *(u32
*)p
= field_value
;
7282 case VMCS_FIELD_TYPE_U64
:
7283 *(u64
*)p
= field_value
;
7285 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7286 *(natural_width
*)p
= field_value
;
7295 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7298 unsigned long field
;
7300 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7301 const unsigned long *fields
= shadow_read_write_fields
;
7302 const int num_fields
= max_shadow_read_write_fields
;
7306 vmcs_load(shadow_vmcs
);
7308 for (i
= 0; i
< num_fields
; i
++) {
7310 switch (vmcs_field_type(field
)) {
7311 case VMCS_FIELD_TYPE_U16
:
7312 field_value
= vmcs_read16(field
);
7314 case VMCS_FIELD_TYPE_U32
:
7315 field_value
= vmcs_read32(field
);
7317 case VMCS_FIELD_TYPE_U64
:
7318 field_value
= vmcs_read64(field
);
7320 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7321 field_value
= vmcs_readl(field
);
7327 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7330 vmcs_clear(shadow_vmcs
);
7331 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7336 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7338 const unsigned long *fields
[] = {
7339 shadow_read_write_fields
,
7340 shadow_read_only_fields
7342 const int max_fields
[] = {
7343 max_shadow_read_write_fields
,
7344 max_shadow_read_only_fields
7347 unsigned long field
;
7348 u64 field_value
= 0;
7349 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7351 vmcs_load(shadow_vmcs
);
7353 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7354 for (i
= 0; i
< max_fields
[q
]; i
++) {
7355 field
= fields
[q
][i
];
7356 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7358 switch (vmcs_field_type(field
)) {
7359 case VMCS_FIELD_TYPE_U16
:
7360 vmcs_write16(field
, (u16
)field_value
);
7362 case VMCS_FIELD_TYPE_U32
:
7363 vmcs_write32(field
, (u32
)field_value
);
7365 case VMCS_FIELD_TYPE_U64
:
7366 vmcs_write64(field
, (u64
)field_value
);
7368 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7369 vmcs_writel(field
, (long)field_value
);
7378 vmcs_clear(shadow_vmcs
);
7379 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7383 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7384 * used before) all generate the same failure when it is missing.
7386 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7388 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7389 if (vmx
->nested
.current_vmptr
== -1ull) {
7390 nested_vmx_failInvalid(vcpu
);
7396 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7398 unsigned long field
;
7400 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7401 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7404 if (!nested_vmx_check_permission(vcpu
))
7407 if (!nested_vmx_check_vmcs12(vcpu
))
7408 return kvm_skip_emulated_instruction(vcpu
);
7410 /* Decode instruction info and find the field to read */
7411 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7412 /* Read the field, zero-extended to a u64 field_value */
7413 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7414 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7415 return kvm_skip_emulated_instruction(vcpu
);
7418 * Now copy part of this value to register or memory, as requested.
7419 * Note that the number of bits actually copied is 32 or 64 depending
7420 * on the guest's mode (32 or 64 bit), not on the given field's length.
7422 if (vmx_instruction_info
& (1u << 10)) {
7423 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7426 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7427 vmx_instruction_info
, true, &gva
))
7429 /* _system ok, as hardware has verified cpl=0 */
7430 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7431 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7434 nested_vmx_succeed(vcpu
);
7435 return kvm_skip_emulated_instruction(vcpu
);
7439 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7441 unsigned long field
;
7443 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7444 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7445 /* The value to write might be 32 or 64 bits, depending on L1's long
7446 * mode, and eventually we need to write that into a field of several
7447 * possible lengths. The code below first zero-extends the value to 64
7448 * bit (field_value), and then copies only the appropriate number of
7449 * bits into the vmcs12 field.
7451 u64 field_value
= 0;
7452 struct x86_exception e
;
7454 if (!nested_vmx_check_permission(vcpu
))
7457 if (!nested_vmx_check_vmcs12(vcpu
))
7458 return kvm_skip_emulated_instruction(vcpu
);
7460 if (vmx_instruction_info
& (1u << 10))
7461 field_value
= kvm_register_readl(vcpu
,
7462 (((vmx_instruction_info
) >> 3) & 0xf));
7464 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7465 vmx_instruction_info
, false, &gva
))
7467 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7468 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7469 kvm_inject_page_fault(vcpu
, &e
);
7475 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7476 if (vmcs_field_readonly(field
)) {
7477 nested_vmx_failValid(vcpu
,
7478 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7479 return kvm_skip_emulated_instruction(vcpu
);
7482 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7483 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7484 return kvm_skip_emulated_instruction(vcpu
);
7487 nested_vmx_succeed(vcpu
);
7488 return kvm_skip_emulated_instruction(vcpu
);
7491 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7493 vmx
->nested
.current_vmptr
= vmptr
;
7494 if (enable_shadow_vmcs
) {
7495 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7496 SECONDARY_EXEC_SHADOW_VMCS
);
7497 vmcs_write64(VMCS_LINK_POINTER
,
7498 __pa(vmx
->vmcs01
.shadow_vmcs
));
7499 vmx
->nested
.sync_shadow_vmcs
= true;
7503 /* Emulate the VMPTRLD instruction */
7504 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7506 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7509 if (!nested_vmx_check_permission(vcpu
))
7512 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7515 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7516 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7517 return kvm_skip_emulated_instruction(vcpu
);
7520 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7521 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7522 return kvm_skip_emulated_instruction(vcpu
);
7525 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7526 struct vmcs12
*new_vmcs12
;
7528 page
= nested_get_page(vcpu
, vmptr
);
7530 nested_vmx_failInvalid(vcpu
);
7531 return kvm_skip_emulated_instruction(vcpu
);
7533 new_vmcs12
= kmap(page
);
7534 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7536 nested_release_page_clean(page
);
7537 nested_vmx_failValid(vcpu
,
7538 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7539 return kvm_skip_emulated_instruction(vcpu
);
7542 nested_release_vmcs12(vmx
);
7543 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7544 vmx
->nested
.current_vmcs12_page
= page
;
7546 * Load VMCS12 from guest memory since it is not already
7549 memcpy(vmx
->nested
.cached_vmcs12
,
7550 vmx
->nested
.current_vmcs12
, VMCS12_SIZE
);
7551 set_current_vmptr(vmx
, vmptr
);
7554 nested_vmx_succeed(vcpu
);
7555 return kvm_skip_emulated_instruction(vcpu
);
7558 /* Emulate the VMPTRST instruction */
7559 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7561 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7562 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7564 struct x86_exception e
;
7566 if (!nested_vmx_check_permission(vcpu
))
7569 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7570 vmx_instruction_info
, true, &vmcs_gva
))
7572 /* ok to use *_system, as hardware has verified cpl=0 */
7573 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7574 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7576 kvm_inject_page_fault(vcpu
, &e
);
7579 nested_vmx_succeed(vcpu
);
7580 return kvm_skip_emulated_instruction(vcpu
);
7583 /* Emulate the INVEPT instruction */
7584 static int handle_invept(struct kvm_vcpu
*vcpu
)
7586 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7587 u32 vmx_instruction_info
, types
;
7590 struct x86_exception e
;
7595 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7596 SECONDARY_EXEC_ENABLE_EPT
) ||
7597 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7598 kvm_queue_exception(vcpu
, UD_VECTOR
);
7602 if (!nested_vmx_check_permission(vcpu
))
7605 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7606 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7608 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7610 if (type
>= 32 || !(types
& (1 << type
))) {
7611 nested_vmx_failValid(vcpu
,
7612 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7613 return kvm_skip_emulated_instruction(vcpu
);
7616 /* According to the Intel VMX instruction reference, the memory
7617 * operand is read even if it isn't needed (e.g., for type==global)
7619 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7620 vmx_instruction_info
, false, &gva
))
7622 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7623 sizeof(operand
), &e
)) {
7624 kvm_inject_page_fault(vcpu
, &e
);
7629 case VMX_EPT_EXTENT_GLOBAL
:
7631 * TODO: track mappings and invalidate
7632 * single context requests appropriately
7634 case VMX_EPT_EXTENT_CONTEXT
:
7635 kvm_mmu_sync_roots(vcpu
);
7636 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7637 nested_vmx_succeed(vcpu
);
7644 return kvm_skip_emulated_instruction(vcpu
);
7647 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7649 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7650 u32 vmx_instruction_info
;
7651 unsigned long type
, types
;
7653 struct x86_exception e
;
7656 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7657 SECONDARY_EXEC_ENABLE_VPID
) ||
7658 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7659 kvm_queue_exception(vcpu
, UD_VECTOR
);
7663 if (!nested_vmx_check_permission(vcpu
))
7666 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7667 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7669 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7670 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7672 if (type
>= 32 || !(types
& (1 << type
))) {
7673 nested_vmx_failValid(vcpu
,
7674 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7675 return kvm_skip_emulated_instruction(vcpu
);
7678 /* according to the intel vmx instruction reference, the memory
7679 * operand is read even if it isn't needed (e.g., for type==global)
7681 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7682 vmx_instruction_info
, false, &gva
))
7684 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vpid
,
7686 kvm_inject_page_fault(vcpu
, &e
);
7691 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7692 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7693 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7695 nested_vmx_failValid(vcpu
,
7696 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7697 return kvm_skip_emulated_instruction(vcpu
);
7700 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7704 return kvm_skip_emulated_instruction(vcpu
);
7707 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7708 nested_vmx_succeed(vcpu
);
7710 return kvm_skip_emulated_instruction(vcpu
);
7713 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7715 unsigned long exit_qualification
;
7717 trace_kvm_pml_full(vcpu
->vcpu_id
);
7719 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7722 * PML buffer FULL happened while executing iret from NMI,
7723 * "blocked by NMI" bit has to be set before next VM entry.
7725 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7726 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7727 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7728 GUEST_INTR_STATE_NMI
);
7731 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7732 * here.., and there's no userspace involvement needed for PML.
7737 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7739 kvm_lapic_expired_hv_timer(vcpu
);
7744 * The exit handlers return 1 if the exit was handled fully and guest execution
7745 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7746 * to be done to userspace and return 0.
7748 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7749 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7750 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7751 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7752 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7753 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7754 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7755 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7756 [EXIT_REASON_CPUID
] = handle_cpuid
,
7757 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7758 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7759 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7760 [EXIT_REASON_HLT
] = handle_halt
,
7761 [EXIT_REASON_INVD
] = handle_invd
,
7762 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7763 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7764 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7765 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7766 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7767 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7768 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7769 [EXIT_REASON_VMREAD
] = handle_vmread
,
7770 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7771 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7772 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7773 [EXIT_REASON_VMON
] = handle_vmon
,
7774 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7775 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7776 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7777 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7778 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7779 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7780 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7781 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7782 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7783 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7784 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7785 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7786 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7787 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7788 [EXIT_REASON_INVEPT
] = handle_invept
,
7789 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7790 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7791 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7792 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7793 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
7796 static const int kvm_vmx_max_exit_handlers
=
7797 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7799 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7800 struct vmcs12
*vmcs12
)
7802 unsigned long exit_qualification
;
7803 gpa_t bitmap
, last_bitmap
;
7808 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7809 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7811 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7813 port
= exit_qualification
>> 16;
7814 size
= (exit_qualification
& 7) + 1;
7816 last_bitmap
= (gpa_t
)-1;
7821 bitmap
= vmcs12
->io_bitmap_a
;
7822 else if (port
< 0x10000)
7823 bitmap
= vmcs12
->io_bitmap_b
;
7826 bitmap
+= (port
& 0x7fff) / 8;
7828 if (last_bitmap
!= bitmap
)
7829 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7831 if (b
& (1 << (port
& 7)))
7836 last_bitmap
= bitmap
;
7843 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7844 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7845 * disinterest in the current event (read or write a specific MSR) by using an
7846 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7848 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7849 struct vmcs12
*vmcs12
, u32 exit_reason
)
7851 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7854 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7858 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7859 * for the four combinations of read/write and low/high MSR numbers.
7860 * First we need to figure out which of the four to use:
7862 bitmap
= vmcs12
->msr_bitmap
;
7863 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7865 if (msr_index
>= 0xc0000000) {
7866 msr_index
-= 0xc0000000;
7870 /* Then read the msr_index'th bit from this bitmap: */
7871 if (msr_index
< 1024*8) {
7873 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7875 return 1 & (b
>> (msr_index
& 7));
7877 return true; /* let L1 handle the wrong parameter */
7881 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7882 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7883 * intercept (via guest_host_mask etc.) the current event.
7885 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7886 struct vmcs12
*vmcs12
)
7888 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7889 int cr
= exit_qualification
& 15;
7893 switch ((exit_qualification
>> 4) & 3) {
7894 case 0: /* mov to cr */
7895 reg
= (exit_qualification
>> 8) & 15;
7896 val
= kvm_register_readl(vcpu
, reg
);
7899 if (vmcs12
->cr0_guest_host_mask
&
7900 (val
^ vmcs12
->cr0_read_shadow
))
7904 if ((vmcs12
->cr3_target_count
>= 1 &&
7905 vmcs12
->cr3_target_value0
== val
) ||
7906 (vmcs12
->cr3_target_count
>= 2 &&
7907 vmcs12
->cr3_target_value1
== val
) ||
7908 (vmcs12
->cr3_target_count
>= 3 &&
7909 vmcs12
->cr3_target_value2
== val
) ||
7910 (vmcs12
->cr3_target_count
>= 4 &&
7911 vmcs12
->cr3_target_value3
== val
))
7913 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7917 if (vmcs12
->cr4_guest_host_mask
&
7918 (vmcs12
->cr4_read_shadow
^ val
))
7922 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7928 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7929 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7932 case 1: /* mov from cr */
7935 if (vmcs12
->cpu_based_vm_exec_control
&
7936 CPU_BASED_CR3_STORE_EXITING
)
7940 if (vmcs12
->cpu_based_vm_exec_control
&
7941 CPU_BASED_CR8_STORE_EXITING
)
7948 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7949 * cr0. Other attempted changes are ignored, with no exit.
7951 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
7952 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7953 (val
^ vmcs12
->cr0_read_shadow
))
7955 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7956 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7965 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7966 * should handle it ourselves in L0 (and then continue L2). Only call this
7967 * when in is_guest_mode (L2).
7969 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7971 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7972 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7973 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7974 u32 exit_reason
= vmx
->exit_reason
;
7976 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7977 vmcs_readl(EXIT_QUALIFICATION
),
7978 vmx
->idt_vectoring_info
,
7980 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7983 if (vmx
->nested
.nested_run_pending
)
7986 if (unlikely(vmx
->fail
)) {
7987 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7988 vmcs_read32(VM_INSTRUCTION_ERROR
));
7992 switch (exit_reason
) {
7993 case EXIT_REASON_EXCEPTION_NMI
:
7994 if (is_nmi(intr_info
))
7996 else if (is_page_fault(intr_info
))
7998 else if (is_no_device(intr_info
) &&
7999 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8001 else if (is_debug(intr_info
) &&
8003 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8005 else if (is_breakpoint(intr_info
) &&
8006 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8008 return vmcs12
->exception_bitmap
&
8009 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8010 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8012 case EXIT_REASON_TRIPLE_FAULT
:
8014 case EXIT_REASON_PENDING_INTERRUPT
:
8015 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8016 case EXIT_REASON_NMI_WINDOW
:
8017 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8018 case EXIT_REASON_TASK_SWITCH
:
8020 case EXIT_REASON_CPUID
:
8022 case EXIT_REASON_HLT
:
8023 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8024 case EXIT_REASON_INVD
:
8026 case EXIT_REASON_INVLPG
:
8027 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8028 case EXIT_REASON_RDPMC
:
8029 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8030 case EXIT_REASON_RDRAND
:
8031 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND
);
8032 case EXIT_REASON_RDSEED
:
8033 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED
);
8034 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8035 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8036 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8037 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8038 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8039 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8040 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8041 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8043 * VMX instructions trap unconditionally. This allows L1 to
8044 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8047 case EXIT_REASON_CR_ACCESS
:
8048 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8049 case EXIT_REASON_DR_ACCESS
:
8050 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8051 case EXIT_REASON_IO_INSTRUCTION
:
8052 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8053 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8054 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8055 case EXIT_REASON_MSR_READ
:
8056 case EXIT_REASON_MSR_WRITE
:
8057 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8058 case EXIT_REASON_INVALID_STATE
:
8060 case EXIT_REASON_MWAIT_INSTRUCTION
:
8061 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8062 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8063 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8064 case EXIT_REASON_MONITOR_INSTRUCTION
:
8065 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8066 case EXIT_REASON_PAUSE_INSTRUCTION
:
8067 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8068 nested_cpu_has2(vmcs12
,
8069 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8070 case EXIT_REASON_MCE_DURING_VMENTRY
:
8072 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8073 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8074 case EXIT_REASON_APIC_ACCESS
:
8075 return nested_cpu_has2(vmcs12
,
8076 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8077 case EXIT_REASON_APIC_WRITE
:
8078 case EXIT_REASON_EOI_INDUCED
:
8079 /* apic_write and eoi_induced should exit unconditionally. */
8081 case EXIT_REASON_EPT_VIOLATION
:
8083 * L0 always deals with the EPT violation. If nested EPT is
8084 * used, and the nested mmu code discovers that the address is
8085 * missing in the guest EPT table (EPT12), the EPT violation
8086 * will be injected with nested_ept_inject_page_fault()
8089 case EXIT_REASON_EPT_MISCONFIG
:
8091 * L2 never uses directly L1's EPT, but rather L0's own EPT
8092 * table (shadow on EPT) or a merged EPT table that L0 built
8093 * (EPT on EPT). So any problems with the structure of the
8094 * table is L0's fault.
8097 case EXIT_REASON_WBINVD
:
8098 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8099 case EXIT_REASON_XSETBV
:
8101 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8103 * This should never happen, since it is not possible to
8104 * set XSS to a non-zero value---neither in L1 nor in L2.
8105 * If if it were, XSS would have to be checked against
8106 * the XSS exit bitmap in vmcs12.
8108 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8109 case EXIT_REASON_PREEMPTION_TIMER
:
8111 case EXIT_REASON_PML_FULL
:
8112 /* We emulate PML support to L1. */
8119 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8121 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8122 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8125 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8128 __free_page(vmx
->pml_pg
);
8133 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8135 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8139 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8141 /* Do nothing if PML buffer is empty */
8142 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8145 /* PML index always points to next available PML buffer entity */
8146 if (pml_idx
>= PML_ENTITY_NUM
)
8151 pml_buf
= page_address(vmx
->pml_pg
);
8152 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8155 gpa
= pml_buf
[pml_idx
];
8156 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8157 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8160 /* reset PML index */
8161 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8165 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8166 * Called before reporting dirty_bitmap to userspace.
8168 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8171 struct kvm_vcpu
*vcpu
;
8173 * We only need to kick vcpu out of guest mode here, as PML buffer
8174 * is flushed at beginning of all VMEXITs, and it's obvious that only
8175 * vcpus running in guest are possible to have unflushed GPAs in PML
8178 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8179 kvm_vcpu_kick(vcpu
);
8182 static void vmx_dump_sel(char *name
, uint32_t sel
)
8184 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8185 name
, vmcs_read16(sel
),
8186 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8187 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8188 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8191 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8193 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8194 name
, vmcs_read32(limit
),
8195 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8198 static void dump_vmcs(void)
8200 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8201 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8202 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8203 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8204 u32 secondary_exec_control
= 0;
8205 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8206 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8209 if (cpu_has_secondary_exec_ctrls())
8210 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8212 pr_err("*** Guest State ***\n");
8213 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8214 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8215 vmcs_readl(CR0_GUEST_HOST_MASK
));
8216 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8217 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8218 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8219 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8220 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8222 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8223 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8224 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8225 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8227 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8228 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8229 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8230 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8231 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8232 vmcs_readl(GUEST_SYSENTER_ESP
),
8233 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8234 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8235 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8236 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8237 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8238 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8239 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8240 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8241 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8242 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8243 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8244 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8245 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8246 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8247 efer
, vmcs_read64(GUEST_IA32_PAT
));
8248 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8249 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8250 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8251 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8252 pr_err("PerfGlobCtl = 0x%016llx\n",
8253 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8254 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8255 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8256 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8257 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8258 vmcs_read32(GUEST_ACTIVITY_STATE
));
8259 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8260 pr_err("InterruptStatus = %04x\n",
8261 vmcs_read16(GUEST_INTR_STATUS
));
8263 pr_err("*** Host State ***\n");
8264 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8265 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8266 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8267 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8268 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8269 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8270 vmcs_read16(HOST_TR_SELECTOR
));
8271 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8272 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8273 vmcs_readl(HOST_TR_BASE
));
8274 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8275 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8276 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8277 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8278 vmcs_readl(HOST_CR4
));
8279 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8280 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8281 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8282 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8283 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8284 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8285 vmcs_read64(HOST_IA32_EFER
),
8286 vmcs_read64(HOST_IA32_PAT
));
8287 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8288 pr_err("PerfGlobCtl = 0x%016llx\n",
8289 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8291 pr_err("*** Control State ***\n");
8292 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8293 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8294 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8295 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8296 vmcs_read32(EXCEPTION_BITMAP
),
8297 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8298 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8299 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8300 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8301 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8302 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8303 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8304 vmcs_read32(VM_EXIT_INTR_INFO
),
8305 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8306 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8307 pr_err(" reason=%08x qualification=%016lx\n",
8308 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8309 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8310 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8311 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8312 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8313 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8314 pr_err("TSC Multiplier = 0x%016llx\n",
8315 vmcs_read64(TSC_MULTIPLIER
));
8316 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8317 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8318 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8319 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8320 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8321 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8322 n
= vmcs_read32(CR3_TARGET_COUNT
);
8323 for (i
= 0; i
+ 1 < n
; i
+= 4)
8324 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8325 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8326 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8328 pr_err("CR3 target%u=%016lx\n",
8329 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8330 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8331 pr_err("PLE Gap=%08x Window=%08x\n",
8332 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8333 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8334 pr_err("Virtual processor ID = 0x%04x\n",
8335 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8339 * The guest has exited. See if we can fix it or if we need userspace
8342 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8344 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8345 u32 exit_reason
= vmx
->exit_reason
;
8346 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8348 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8349 vcpu
->arch
.gpa_available
= false;
8352 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8353 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8354 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8355 * mode as if vcpus is in root mode, the PML buffer must has been
8359 vmx_flush_pml_buffer(vcpu
);
8361 /* If guest state is invalid, start emulating */
8362 if (vmx
->emulation_required
)
8363 return handle_invalid_guest_state(vcpu
);
8365 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
8366 nested_vmx_vmexit(vcpu
, exit_reason
,
8367 vmcs_read32(VM_EXIT_INTR_INFO
),
8368 vmcs_readl(EXIT_QUALIFICATION
));
8372 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8374 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8375 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8380 if (unlikely(vmx
->fail
)) {
8381 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8382 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8383 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8389 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8390 * delivery event since it indicates guest is accessing MMIO.
8391 * The vm-exit can be triggered again after return to guest that
8392 * will cause infinite loop.
8394 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8395 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8396 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8397 exit_reason
!= EXIT_REASON_PML_FULL
&&
8398 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8399 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8400 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8401 vcpu
->run
->internal
.ndata
= 2;
8402 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8403 vcpu
->run
->internal
.data
[1] = exit_reason
;
8407 if (exit_reason
< kvm_vmx_max_exit_handlers
8408 && kvm_vmx_exit_handlers
[exit_reason
])
8409 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8411 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8413 kvm_queue_exception(vcpu
, UD_VECTOR
);
8418 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8420 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8422 if (is_guest_mode(vcpu
) &&
8423 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8426 if (irr
== -1 || tpr
< irr
) {
8427 vmcs_write32(TPR_THRESHOLD
, 0);
8431 vmcs_write32(TPR_THRESHOLD
, irr
);
8434 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8436 u32 sec_exec_control
;
8438 /* Postpone execution until vmcs01 is the current VMCS. */
8439 if (is_guest_mode(vcpu
)) {
8440 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8444 if (!cpu_has_vmx_virtualize_x2apic_mode())
8447 if (!cpu_need_tpr_shadow(vcpu
))
8450 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8453 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8454 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8456 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8457 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8458 vmx_flush_tlb_ept_only(vcpu
);
8460 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8462 vmx_set_msr_bitmap(vcpu
);
8465 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8467 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8470 * Currently we do not handle the nested case where L2 has an
8471 * APIC access page of its own; that page is still pinned.
8472 * Hence, we skip the case where the VCPU is in guest mode _and_
8473 * L1 prepared an APIC access page for L2.
8475 * For the case where L1 and L2 share the same APIC access page
8476 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8477 * in the vmcs12), this function will only update either the vmcs01
8478 * or the vmcs02. If the former, the vmcs02 will be updated by
8479 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8480 * the next L2->L1 exit.
8482 if (!is_guest_mode(vcpu
) ||
8483 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8484 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8485 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8486 vmx_flush_tlb_ept_only(vcpu
);
8490 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8498 status
= vmcs_read16(GUEST_INTR_STATUS
);
8500 if (max_isr
!= old
) {
8502 status
|= max_isr
<< 8;
8503 vmcs_write16(GUEST_INTR_STATUS
, status
);
8507 static void vmx_set_rvi(int vector
)
8515 status
= vmcs_read16(GUEST_INTR_STATUS
);
8516 old
= (u8
)status
& 0xff;
8517 if ((u8
)vector
!= old
) {
8519 status
|= (u8
)vector
;
8520 vmcs_write16(GUEST_INTR_STATUS
, status
);
8524 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8526 if (!is_guest_mode(vcpu
)) {
8527 vmx_set_rvi(max_irr
);
8535 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8538 if (nested_exit_on_intr(vcpu
))
8542 * Else, fall back to pre-APICv interrupt injection since L2
8543 * is run without virtual interrupt delivery.
8545 if (!kvm_event_needs_reinjection(vcpu
) &&
8546 vmx_interrupt_allowed(vcpu
)) {
8547 kvm_queue_interrupt(vcpu
, max_irr
, false);
8548 vmx_inject_irq(vcpu
);
8552 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8554 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8557 WARN_ON(!vcpu
->arch
.apicv_active
);
8558 if (pi_test_on(&vmx
->pi_desc
)) {
8559 pi_clear_on(&vmx
->pi_desc
);
8561 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8562 * But on x86 this is just a compiler barrier anyway.
8564 smp_mb__after_atomic();
8565 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8567 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8569 vmx_hwapic_irr_update(vcpu
, max_irr
);
8573 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8575 if (!kvm_vcpu_apicv_active(vcpu
))
8578 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8579 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8580 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8581 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8584 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
8586 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8588 pi_clear_on(&vmx
->pi_desc
);
8589 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
8592 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8596 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8597 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8600 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8601 exit_intr_info
= vmx
->exit_intr_info
;
8603 /* Handle machine checks before interrupts are enabled */
8604 if (is_machine_check(exit_intr_info
))
8605 kvm_machine_check();
8607 /* We need to handle NMIs before interrupts are enabled */
8608 if (is_nmi(exit_intr_info
)) {
8609 kvm_before_handle_nmi(&vmx
->vcpu
);
8611 kvm_after_handle_nmi(&vmx
->vcpu
);
8615 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8617 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8618 register void *__sp
asm(_ASM_SP
);
8620 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8621 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8622 unsigned int vector
;
8623 unsigned long entry
;
8625 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8626 #ifdef CONFIG_X86_64
8630 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8631 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8632 entry
= gate_offset(*desc
);
8634 #ifdef CONFIG_X86_64
8635 "mov %%" _ASM_SP
", %[sp]\n\t"
8636 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8641 __ASM_SIZE(push
) " $%c[cs]\n\t"
8642 "call *%[entry]\n\t"
8644 #ifdef CONFIG_X86_64
8650 [ss
]"i"(__KERNEL_DS
),
8651 [cs
]"i"(__KERNEL_CS
)
8656 static bool vmx_has_high_real_mode_segbase(void)
8658 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8661 static bool vmx_mpx_supported(void)
8663 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8664 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8667 static bool vmx_xsaves_supported(void)
8669 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8670 SECONDARY_EXEC_XSAVES
;
8673 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8678 bool idtv_info_valid
;
8680 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8682 if (vmx
->nmi_known_unmasked
)
8685 * Can't use vmx->exit_intr_info since we're not sure what
8686 * the exit reason is.
8688 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8689 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8690 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8692 * SDM 3: 27.7.1.2 (September 2008)
8693 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8694 * a guest IRET fault.
8695 * SDM 3: 23.2.2 (September 2008)
8696 * Bit 12 is undefined in any of the following cases:
8697 * If the VM exit sets the valid bit in the IDT-vectoring
8698 * information field.
8699 * If the VM exit is due to a double fault.
8701 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8702 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8703 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8704 GUEST_INTR_STATE_NMI
);
8706 vmx
->nmi_known_unmasked
=
8707 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8708 & GUEST_INTR_STATE_NMI
);
8711 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8712 u32 idt_vectoring_info
,
8713 int instr_len_field
,
8714 int error_code_field
)
8718 bool idtv_info_valid
;
8720 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8722 vcpu
->arch
.nmi_injected
= false;
8723 kvm_clear_exception_queue(vcpu
);
8724 kvm_clear_interrupt_queue(vcpu
);
8726 if (!idtv_info_valid
)
8729 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8731 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8732 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8735 case INTR_TYPE_NMI_INTR
:
8736 vcpu
->arch
.nmi_injected
= true;
8738 * SDM 3: 27.7.1.2 (September 2008)
8739 * Clear bit "block by NMI" before VM entry if a NMI
8742 vmx_set_nmi_mask(vcpu
, false);
8744 case INTR_TYPE_SOFT_EXCEPTION
:
8745 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8747 case INTR_TYPE_HARD_EXCEPTION
:
8748 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8749 u32 err
= vmcs_read32(error_code_field
);
8750 kvm_requeue_exception_e(vcpu
, vector
, err
);
8752 kvm_requeue_exception(vcpu
, vector
);
8754 case INTR_TYPE_SOFT_INTR
:
8755 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8757 case INTR_TYPE_EXT_INTR
:
8758 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8765 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8767 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8768 VM_EXIT_INSTRUCTION_LEN
,
8769 IDT_VECTORING_ERROR_CODE
);
8772 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8774 __vmx_complete_interrupts(vcpu
,
8775 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8776 VM_ENTRY_INSTRUCTION_LEN
,
8777 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8779 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8782 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8785 struct perf_guest_switch_msr
*msrs
;
8787 msrs
= perf_guest_get_msrs(&nr_msrs
);
8792 for (i
= 0; i
< nr_msrs
; i
++)
8793 if (msrs
[i
].host
== msrs
[i
].guest
)
8794 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8796 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8800 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
8802 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8806 if (vmx
->hv_deadline_tsc
== -1)
8810 if (vmx
->hv_deadline_tsc
> tscl
)
8811 /* sure to be 32 bit only because checked on set_hv_timer */
8812 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
8813 cpu_preemption_timer_multi
);
8817 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
8820 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8822 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8823 unsigned long debugctlmsr
, cr4
;
8825 /* Don't enter VMX if guest state is invalid, let the exit handler
8826 start emulation until we arrive back to a valid state */
8827 if (vmx
->emulation_required
)
8830 if (vmx
->ple_window_dirty
) {
8831 vmx
->ple_window_dirty
= false;
8832 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8835 if (vmx
->nested
.sync_shadow_vmcs
) {
8836 copy_vmcs12_to_shadow(vmx
);
8837 vmx
->nested
.sync_shadow_vmcs
= false;
8840 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8841 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8842 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8843 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8845 cr4
= cr4_read_shadow();
8846 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8847 vmcs_writel(HOST_CR4
, cr4
);
8848 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8851 /* When single-stepping over STI and MOV SS, we must clear the
8852 * corresponding interruptibility bits in the guest state. Otherwise
8853 * vmentry fails as it then expects bit 14 (BS) in pending debug
8854 * exceptions being set, but that's not correct for the guest debugging
8856 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8857 vmx_set_interrupt_shadow(vcpu
, 0);
8859 if (vmx
->guest_pkru_valid
)
8860 __write_pkru(vmx
->guest_pkru
);
8862 atomic_switch_perf_msrs(vmx
);
8863 debugctlmsr
= get_debugctlmsr();
8865 vmx_arm_hv_timer(vcpu
);
8867 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8869 /* Store host registers */
8870 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8871 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8872 "push %%" _ASM_CX
" \n\t"
8873 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8875 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8876 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8878 /* Reload cr2 if changed */
8879 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8880 "mov %%cr2, %%" _ASM_DX
" \n\t"
8881 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8883 "mov %%" _ASM_AX
", %%cr2 \n\t"
8885 /* Check if vmlaunch of vmresume is needed */
8886 "cmpl $0, %c[launched](%0) \n\t"
8887 /* Load guest registers. Don't clobber flags. */
8888 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8889 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8890 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8891 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8892 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8893 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8894 #ifdef CONFIG_X86_64
8895 "mov %c[r8](%0), %%r8 \n\t"
8896 "mov %c[r9](%0), %%r9 \n\t"
8897 "mov %c[r10](%0), %%r10 \n\t"
8898 "mov %c[r11](%0), %%r11 \n\t"
8899 "mov %c[r12](%0), %%r12 \n\t"
8900 "mov %c[r13](%0), %%r13 \n\t"
8901 "mov %c[r14](%0), %%r14 \n\t"
8902 "mov %c[r15](%0), %%r15 \n\t"
8904 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8906 /* Enter guest mode */
8908 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8910 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8912 /* Save guest registers, load host registers, keep flags */
8913 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8915 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8916 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8917 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8918 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8919 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8920 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8921 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8922 #ifdef CONFIG_X86_64
8923 "mov %%r8, %c[r8](%0) \n\t"
8924 "mov %%r9, %c[r9](%0) \n\t"
8925 "mov %%r10, %c[r10](%0) \n\t"
8926 "mov %%r11, %c[r11](%0) \n\t"
8927 "mov %%r12, %c[r12](%0) \n\t"
8928 "mov %%r13, %c[r13](%0) \n\t"
8929 "mov %%r14, %c[r14](%0) \n\t"
8930 "mov %%r15, %c[r15](%0) \n\t"
8932 "mov %%cr2, %%" _ASM_AX
" \n\t"
8933 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8935 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8936 "setbe %c[fail](%0) \n\t"
8937 ".pushsection .rodata \n\t"
8938 ".global vmx_return \n\t"
8939 "vmx_return: " _ASM_PTR
" 2b \n\t"
8941 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8942 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8943 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8944 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8945 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8946 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8947 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8948 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8949 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8950 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8951 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8952 #ifdef CONFIG_X86_64
8953 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8954 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8955 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8956 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8957 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8958 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8959 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8960 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8962 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8963 [wordsize
]"i"(sizeof(ulong
))
8965 #ifdef CONFIG_X86_64
8966 , "rax", "rbx", "rdi", "rsi"
8967 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8969 , "eax", "ebx", "edi", "esi"
8973 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8975 update_debugctlmsr(debugctlmsr
);
8977 #ifndef CONFIG_X86_64
8979 * The sysexit path does not restore ds/es, so we must set them to
8980 * a reasonable value ourselves.
8982 * We can't defer this to vmx_load_host_state() since that function
8983 * may be executed in interrupt context, which saves and restore segments
8984 * around it, nullifying its effect.
8986 loadsegment(ds
, __USER_DS
);
8987 loadsegment(es
, __USER_DS
);
8990 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8991 | (1 << VCPU_EXREG_RFLAGS
)
8992 | (1 << VCPU_EXREG_PDPTR
)
8993 | (1 << VCPU_EXREG_SEGMENTS
)
8994 | (1 << VCPU_EXREG_CR3
));
8995 vcpu
->arch
.regs_dirty
= 0;
8997 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8999 vmx
->loaded_vmcs
->launched
= 1;
9001 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
9004 * eager fpu is enabled if PKEY is supported and CR4 is switched
9005 * back on host, so it is safe to read guest PKRU from current
9008 if (boot_cpu_has(X86_FEATURE_OSPKE
)) {
9009 vmx
->guest_pkru
= __read_pkru();
9010 if (vmx
->guest_pkru
!= vmx
->host_pkru
) {
9011 vmx
->guest_pkru_valid
= true;
9012 __write_pkru(vmx
->host_pkru
);
9014 vmx
->guest_pkru_valid
= false;
9018 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9019 * we did not inject a still-pending event to L1 now because of
9020 * nested_run_pending, we need to re-enable this bit.
9022 if (vmx
->nested
.nested_run_pending
)
9023 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9025 vmx
->nested
.nested_run_pending
= 0;
9027 vmx_complete_atomic_exit(vmx
);
9028 vmx_recover_nmi_blocking(vmx
);
9029 vmx_complete_interrupts(vmx
);
9032 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9034 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9037 if (vmx
->loaded_vmcs
== vmcs
)
9041 vmx
->loaded_vmcs
= vmcs
;
9043 vmx_vcpu_load(vcpu
, cpu
);
9049 * Ensure that the current vmcs of the logical processor is the
9050 * vmcs01 of the vcpu before calling free_nested().
9052 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9054 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9057 r
= vcpu_load(vcpu
);
9059 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9064 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9066 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9069 vmx_destroy_pml_buffer(vmx
);
9070 free_vpid(vmx
->vpid
);
9071 leave_guest_mode(vcpu
);
9072 vmx_free_vcpu_nested(vcpu
);
9073 free_loaded_vmcs(vmx
->loaded_vmcs
);
9074 kfree(vmx
->guest_msrs
);
9075 kvm_vcpu_uninit(vcpu
);
9076 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9079 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9082 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9086 return ERR_PTR(-ENOMEM
);
9088 vmx
->vpid
= allocate_vpid();
9090 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9097 * If PML is turned on, failure on enabling PML just results in failure
9098 * of creating the vcpu, therefore we can simplify PML logic (by
9099 * avoiding dealing with cases, such as enabling PML partially on vcpus
9100 * for the guest, etc.
9103 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9108 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9109 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9112 if (!vmx
->guest_msrs
)
9115 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9116 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9117 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9118 if (!vmx
->loaded_vmcs
->vmcs
)
9120 loaded_vmcs_init(vmx
->loaded_vmcs
);
9123 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9124 vmx
->vcpu
.cpu
= cpu
;
9125 err
= vmx_vcpu_setup(vmx
);
9126 vmx_vcpu_put(&vmx
->vcpu
);
9130 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9131 err
= alloc_apic_access_page(kvm
);
9137 if (!kvm
->arch
.ept_identity_map_addr
)
9138 kvm
->arch
.ept_identity_map_addr
=
9139 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9140 err
= init_rmode_identity_map(kvm
);
9146 nested_vmx_setup_ctls_msrs(vmx
);
9147 vmx
->nested
.vpid02
= allocate_vpid();
9150 vmx
->nested
.posted_intr_nv
= -1;
9151 vmx
->nested
.current_vmptr
= -1ull;
9152 vmx
->nested
.current_vmcs12
= NULL
;
9154 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9159 free_vpid(vmx
->nested
.vpid02
);
9160 free_loaded_vmcs(vmx
->loaded_vmcs
);
9162 kfree(vmx
->guest_msrs
);
9164 vmx_destroy_pml_buffer(vmx
);
9166 kvm_vcpu_uninit(&vmx
->vcpu
);
9168 free_vpid(vmx
->vpid
);
9169 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9170 return ERR_PTR(err
);
9173 static void __init
vmx_check_processor_compat(void *rtn
)
9175 struct vmcs_config vmcs_conf
;
9178 if (setup_vmcs_config(&vmcs_conf
) < 0)
9180 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9181 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9182 smp_processor_id());
9187 static int get_ept_level(void)
9189 return VMX_EPT_DEFAULT_GAW
+ 1;
9192 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9197 /* For VT-d and EPT combination
9198 * 1. MMIO: always map as UC
9200 * a. VT-d without snooping control feature: can't guarantee the
9201 * result, try to trust guest.
9202 * b. VT-d with snooping control feature: snooping control feature of
9203 * VT-d engine can guarantee the cache correctness. Just set it
9204 * to WB to keep consistent with host. So the same as item 3.
9205 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9206 * consistent with host MTRR
9209 cache
= MTRR_TYPE_UNCACHABLE
;
9213 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9214 ipat
= VMX_EPT_IPAT_BIT
;
9215 cache
= MTRR_TYPE_WRBACK
;
9219 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9220 ipat
= VMX_EPT_IPAT_BIT
;
9221 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9222 cache
= MTRR_TYPE_WRBACK
;
9224 cache
= MTRR_TYPE_UNCACHABLE
;
9228 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9231 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9234 static int vmx_get_lpage_level(void)
9236 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9237 return PT_DIRECTORY_LEVEL
;
9239 /* For shadow and EPT supported 1GB page */
9240 return PT_PDPE_LEVEL
;
9243 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9246 * These bits in the secondary execution controls field
9247 * are dynamic, the others are mostly based on the hypervisor
9248 * architecture and the guest's CPUID. Do not touch the
9252 SECONDARY_EXEC_SHADOW_VMCS
|
9253 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9254 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9256 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9258 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9259 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9263 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9264 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9266 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9268 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9269 struct kvm_cpuid_entry2
*entry
;
9271 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9272 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9274 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9275 if (entry && (entry->_reg & (_cpuid_mask))) \
9276 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9279 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9280 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9281 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9282 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9283 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9284 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9285 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9286 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9287 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9288 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9289 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9290 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9291 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9292 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9293 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9295 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9296 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9297 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9298 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9299 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9300 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9301 cr4_fixed1_update(bit(11), ecx
, bit(2));
9303 #undef cr4_fixed1_update
9306 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9308 struct kvm_cpuid_entry2
*best
;
9309 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9310 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9312 if (vmx_rdtscp_supported()) {
9313 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9314 if (!rdtscp_enabled
)
9315 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9319 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9320 SECONDARY_EXEC_RDTSCP
;
9322 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9323 ~SECONDARY_EXEC_RDTSCP
;
9327 /* Exposing INVPCID only when PCID is exposed */
9328 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9329 if (vmx_invpcid_supported() &&
9330 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9331 !guest_cpuid_has_pcid(vcpu
))) {
9332 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9335 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9338 if (cpu_has_secondary_exec_ctrls())
9339 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9341 if (nested_vmx_allowed(vcpu
))
9342 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9343 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9345 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9346 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9348 if (nested_vmx_allowed(vcpu
))
9349 nested_vmx_cr_fixed1_bits_update(vcpu
);
9352 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9354 if (func
== 1 && nested
)
9355 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9358 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9359 struct x86_exception
*fault
)
9361 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9362 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9364 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9366 if (vmx
->nested
.pml_full
) {
9367 exit_reason
= EXIT_REASON_PML_FULL
;
9368 vmx
->nested
.pml_full
= false;
9369 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9370 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9371 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9373 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9375 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9376 vmcs12
->guest_physical_address
= fault
->address
;
9379 /* Callbacks for nested_ept_init_mmu_context: */
9381 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9383 /* return the page table to be shadowed - in our case, EPT12 */
9384 return get_vmcs12(vcpu
)->ept_pointer
;
9387 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9391 WARN_ON(mmu_is_nested(vcpu
));
9392 eptp
= nested_ept_get_cr3(vcpu
);
9393 if ((eptp
& VMX_EPT_AD_ENABLE_BIT
) && !enable_ept_ad_bits
)
9396 kvm_mmu_unload(vcpu
);
9397 kvm_init_shadow_ept_mmu(vcpu
,
9398 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9399 VMX_EPT_EXECUTE_ONLY_BIT
,
9400 eptp
& VMX_EPT_AD_ENABLE_BIT
);
9401 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9402 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9403 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9405 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9409 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9411 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9414 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9417 bool inequality
, bit
;
9419 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9421 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9422 vmcs12
->page_fault_error_code_match
;
9423 return inequality
^ bit
;
9426 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9427 struct x86_exception
*fault
)
9429 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9431 WARN_ON(!is_guest_mode(vcpu
));
9433 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
9434 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
9435 vmcs_read32(VM_EXIT_INTR_INFO
),
9436 vmcs_readl(EXIT_QUALIFICATION
));
9438 kvm_inject_page_fault(vcpu
, fault
);
9441 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9442 struct vmcs12
*vmcs12
);
9444 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9445 struct vmcs12
*vmcs12
)
9447 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9450 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9452 * Translate L1 physical address to host physical
9453 * address for vmcs02. Keep the page pinned, so this
9454 * physical address remains valid. We keep a reference
9455 * to it so we can release it later.
9457 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9458 nested_release_page(vmx
->nested
.apic_access_page
);
9459 vmx
->nested
.apic_access_page
=
9460 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9462 * If translation failed, no matter: This feature asks
9463 * to exit when accessing the given address, and if it
9464 * can never be accessed, this feature won't do
9467 if (vmx
->nested
.apic_access_page
) {
9468 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9469 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9471 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9472 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9474 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9475 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9476 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9477 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9478 kvm_vcpu_reload_apic_access_page(vcpu
);
9481 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9482 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9483 nested_release_page(vmx
->nested
.virtual_apic_page
);
9484 vmx
->nested
.virtual_apic_page
=
9485 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9488 * If translation failed, VM entry will fail because
9489 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9490 * Failing the vm entry is _not_ what the processor
9491 * does but it's basically the only possibility we
9492 * have. We could still enter the guest if CR8 load
9493 * exits are enabled, CR8 store exits are enabled, and
9494 * virtualize APIC access is disabled; in this case
9495 * the processor would never use the TPR shadow and we
9496 * could simply clear the bit from the execution
9497 * control. But such a configuration is useless, so
9498 * let's keep the code simple.
9500 if (vmx
->nested
.virtual_apic_page
) {
9501 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9502 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9506 if (nested_cpu_has_posted_intr(vmcs12
)) {
9507 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9508 kunmap(vmx
->nested
.pi_desc_page
);
9509 nested_release_page(vmx
->nested
.pi_desc_page
);
9511 vmx
->nested
.pi_desc_page
=
9512 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9513 vmx
->nested
.pi_desc
=
9514 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9515 if (!vmx
->nested
.pi_desc
) {
9516 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9519 vmx
->nested
.pi_desc
=
9520 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9521 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9523 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9524 page_to_phys(vmx
->nested
.pi_desc_page
) +
9525 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9528 if (cpu_has_vmx_msr_bitmap() &&
9529 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9530 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9533 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9534 CPU_BASED_USE_MSR_BITMAPS
);
9537 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9539 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9540 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9542 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9545 /* Make sure short timeouts reliably trigger an immediate vmexit.
9546 * hrtimer_start does not guarantee this. */
9547 if (preemption_timeout
<= 1) {
9548 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9552 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9553 preemption_timeout
*= 1000000;
9554 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9555 hrtimer_start(&vmx
->nested
.preemption_timer
,
9556 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9559 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9560 struct vmcs12
*vmcs12
)
9565 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9568 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9572 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9574 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9575 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9582 * Merge L0's and L1's MSR bitmap, return false to indicate that
9583 * we do not use the hardware.
9585 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9586 struct vmcs12
*vmcs12
)
9590 unsigned long *msr_bitmap_l1
;
9591 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
9593 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9594 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9597 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9600 msr_bitmap_l1
= (unsigned long *)kmap(page
);
9602 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
9604 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9605 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9606 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9607 nested_vmx_disable_intercept_for_msr(
9608 msr_bitmap_l1
, msr_bitmap_l0
,
9611 nested_vmx_disable_intercept_for_msr(
9612 msr_bitmap_l1
, msr_bitmap_l0
,
9613 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9614 MSR_TYPE_R
| MSR_TYPE_W
);
9616 if (nested_cpu_has_vid(vmcs12
)) {
9617 nested_vmx_disable_intercept_for_msr(
9618 msr_bitmap_l1
, msr_bitmap_l0
,
9619 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9621 nested_vmx_disable_intercept_for_msr(
9622 msr_bitmap_l1
, msr_bitmap_l0
,
9623 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9628 nested_release_page_clean(page
);
9633 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9634 struct vmcs12
*vmcs12
)
9636 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9637 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9638 !nested_cpu_has_vid(vmcs12
) &&
9639 !nested_cpu_has_posted_intr(vmcs12
))
9643 * If virtualize x2apic mode is enabled,
9644 * virtualize apic access must be disabled.
9646 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9647 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9651 * If virtual interrupt delivery is enabled,
9652 * we must exit on external interrupts.
9654 if (nested_cpu_has_vid(vmcs12
) &&
9655 !nested_exit_on_intr(vcpu
))
9659 * bits 15:8 should be zero in posted_intr_nv,
9660 * the descriptor address has been already checked
9661 * in nested_get_vmcs12_pages.
9663 if (nested_cpu_has_posted_intr(vmcs12
) &&
9664 (!nested_cpu_has_vid(vmcs12
) ||
9665 !nested_exit_intr_ack_set(vcpu
) ||
9666 vmcs12
->posted_intr_nv
& 0xff00))
9669 /* tpr shadow is needed by all apicv features. */
9670 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9676 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9677 unsigned long count_field
,
9678 unsigned long addr_field
)
9683 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9684 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9690 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9691 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9692 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9693 pr_debug_ratelimited(
9694 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9695 addr_field
, maxphyaddr
, count
, addr
);
9701 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9702 struct vmcs12
*vmcs12
)
9704 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9705 vmcs12
->vm_exit_msr_store_count
== 0 &&
9706 vmcs12
->vm_entry_msr_load_count
== 0)
9707 return 0; /* Fast path */
9708 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9709 VM_EXIT_MSR_LOAD_ADDR
) ||
9710 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9711 VM_EXIT_MSR_STORE_ADDR
) ||
9712 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9713 VM_ENTRY_MSR_LOAD_ADDR
))
9718 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
9719 struct vmcs12
*vmcs12
)
9721 u64 address
= vmcs12
->pml_address
;
9722 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9724 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
9725 if (!nested_cpu_has_ept(vmcs12
) ||
9726 !IS_ALIGNED(address
, 4096) ||
9727 address
>> maxphyaddr
)
9734 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9735 struct vmx_msr_entry
*e
)
9737 /* x2APIC MSR accesses are not allowed */
9738 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9740 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9741 e
->index
== MSR_IA32_UCODE_REV
)
9743 if (e
->reserved
!= 0)
9748 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9749 struct vmx_msr_entry
*e
)
9751 if (e
->index
== MSR_FS_BASE
||
9752 e
->index
== MSR_GS_BASE
||
9753 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9754 nested_vmx_msr_check_common(vcpu
, e
))
9759 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9760 struct vmx_msr_entry
*e
)
9762 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9763 nested_vmx_msr_check_common(vcpu
, e
))
9769 * Load guest's/host's msr at nested entry/exit.
9770 * return 0 for success, entry index for failure.
9772 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9775 struct vmx_msr_entry e
;
9776 struct msr_data msr
;
9778 msr
.host_initiated
= false;
9779 for (i
= 0; i
< count
; i
++) {
9780 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9782 pr_debug_ratelimited(
9783 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9784 __func__
, i
, gpa
+ i
* sizeof(e
));
9787 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9788 pr_debug_ratelimited(
9789 "%s check failed (%u, 0x%x, 0x%x)\n",
9790 __func__
, i
, e
.index
, e
.reserved
);
9793 msr
.index
= e
.index
;
9795 if (kvm_set_msr(vcpu
, &msr
)) {
9796 pr_debug_ratelimited(
9797 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9798 __func__
, i
, e
.index
, e
.value
);
9807 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9810 struct vmx_msr_entry e
;
9812 for (i
= 0; i
< count
; i
++) {
9813 struct msr_data msr_info
;
9814 if (kvm_vcpu_read_guest(vcpu
,
9815 gpa
+ i
* sizeof(e
),
9816 &e
, 2 * sizeof(u32
))) {
9817 pr_debug_ratelimited(
9818 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9819 __func__
, i
, gpa
+ i
* sizeof(e
));
9822 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9823 pr_debug_ratelimited(
9824 "%s check failed (%u, 0x%x, 0x%x)\n",
9825 __func__
, i
, e
.index
, e
.reserved
);
9828 msr_info
.host_initiated
= false;
9829 msr_info
.index
= e
.index
;
9830 if (kvm_get_msr(vcpu
, &msr_info
)) {
9831 pr_debug_ratelimited(
9832 "%s cannot read MSR (%u, 0x%x)\n",
9833 __func__
, i
, e
.index
);
9836 if (kvm_vcpu_write_guest(vcpu
,
9837 gpa
+ i
* sizeof(e
) +
9838 offsetof(struct vmx_msr_entry
, value
),
9839 &msr_info
.data
, sizeof(msr_info
.data
))) {
9840 pr_debug_ratelimited(
9841 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9842 __func__
, i
, e
.index
, msr_info
.data
);
9849 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
9851 unsigned long invalid_mask
;
9853 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
9854 return (val
& invalid_mask
) == 0;
9858 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9859 * emulating VM entry into a guest with EPT enabled.
9860 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9861 * is assigned to entry_failure_code on failure.
9863 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
9864 u32
*entry_failure_code
)
9866 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
9867 if (!nested_cr3_valid(vcpu
, cr3
)) {
9868 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
9873 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9874 * must not be dereferenced.
9876 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
9878 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
9879 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
9884 vcpu
->arch
.cr3
= cr3
;
9885 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
9888 kvm_mmu_reset_context(vcpu
);
9893 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9894 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9895 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9896 * guest in a way that will both be appropriate to L1's requests, and our
9897 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9898 * function also has additional necessary side-effects, like setting various
9899 * vcpu->arch fields.
9900 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9901 * is assigned to entry_failure_code on failure.
9903 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
9904 bool from_vmentry
, u32
*entry_failure_code
)
9906 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9907 u32 exec_control
, vmcs12_exec_ctrl
;
9909 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9910 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9911 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9912 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9913 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9914 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9915 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9916 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9917 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9918 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9919 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9920 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9921 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9922 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9923 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9924 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9925 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9926 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9927 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9928 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9929 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9930 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9931 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9932 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9933 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9934 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9935 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9936 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9937 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9938 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9939 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9940 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9941 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9942 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9943 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9944 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9947 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
9948 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9949 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9951 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9952 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9955 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9956 vmcs12
->vm_entry_intr_info_field
);
9957 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9958 vmcs12
->vm_entry_exception_error_code
);
9959 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9960 vmcs12
->vm_entry_instruction_len
);
9961 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9962 vmcs12
->guest_interruptibility_info
);
9964 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9966 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9967 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9968 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9969 vmcs12
->guest_pending_dbg_exceptions
);
9970 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9971 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9973 if (nested_cpu_has_xsaves(vmcs12
))
9974 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9975 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9977 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9979 /* Preemption timer setting is only taken from vmcs01. */
9980 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9981 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9982 if (vmx
->hv_deadline_tsc
== -1)
9983 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9985 /* Posted interrupts setting is only taken from vmcs12. */
9986 if (nested_cpu_has_posted_intr(vmcs12
)) {
9988 * Note that we use L0's vector here and in
9989 * vmx_deliver_nested_posted_interrupt.
9991 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9992 vmx
->nested
.pi_pending
= false;
9993 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9995 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9998 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10000 vmx
->nested
.preemption_timer_expired
= false;
10001 if (nested_cpu_has_preemption_timer(vmcs12
))
10002 vmx_start_preemption_timer(vcpu
);
10005 * Whether page-faults are trapped is determined by a combination of
10006 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10007 * If enable_ept, L0 doesn't care about page faults and we should
10008 * set all of these to L1's desires. However, if !enable_ept, L0 does
10009 * care about (at least some) page faults, and because it is not easy
10010 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10011 * to exit on each and every L2 page fault. This is done by setting
10012 * MASK=MATCH=0 and (see below) EB.PF=1.
10013 * Note that below we don't need special code to set EB.PF beyond the
10014 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10015 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10016 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10018 * A problem with this approach (when !enable_ept) is that L1 may be
10019 * injected with more page faults than it asked for. This could have
10020 * caused problems, but in practice existing hypervisors don't care.
10021 * To fix this, we will need to emulate the PFEC checking (on the L1
10022 * page tables), using walk_addr(), when injecting PFs to L1.
10024 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10025 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10026 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10027 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10029 if (cpu_has_secondary_exec_ctrls()) {
10030 exec_control
= vmx_secondary_exec_control(vmx
);
10032 /* Take the following fields only from vmcs12 */
10033 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10034 SECONDARY_EXEC_RDTSCP
|
10035 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10036 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
10037 if (nested_cpu_has(vmcs12
,
10038 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10039 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10040 ~SECONDARY_EXEC_ENABLE_PML
;
10041 exec_control
|= vmcs12_exec_ctrl
;
10044 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10045 vmcs_write64(EOI_EXIT_BITMAP0
,
10046 vmcs12
->eoi_exit_bitmap0
);
10047 vmcs_write64(EOI_EXIT_BITMAP1
,
10048 vmcs12
->eoi_exit_bitmap1
);
10049 vmcs_write64(EOI_EXIT_BITMAP2
,
10050 vmcs12
->eoi_exit_bitmap2
);
10051 vmcs_write64(EOI_EXIT_BITMAP3
,
10052 vmcs12
->eoi_exit_bitmap3
);
10053 vmcs_write16(GUEST_INTR_STATUS
,
10054 vmcs12
->guest_intr_status
);
10058 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10059 * nested_get_vmcs12_pages will either fix it up or
10060 * remove the VM execution control.
10062 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10063 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10065 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10070 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10071 * Some constant fields are set here by vmx_set_constant_host_state().
10072 * Other fields are different per CPU, and will be set later when
10073 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10075 vmx_set_constant_host_state(vmx
);
10078 * Set the MSR load/store lists to match L0's settings.
10080 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10081 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10082 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10083 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10084 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10087 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10088 * entry, but only if the current (host) sp changed from the value
10089 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10090 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10091 * here we just force the write to happen on entry.
10095 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10096 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10097 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10098 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10099 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10102 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10103 * nested_get_vmcs12_pages can't fix it up, the illegal value
10104 * will result in a VM entry failure.
10106 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10107 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10108 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10112 * Merging of IO bitmap not currently supported.
10113 * Rather, exit every time.
10115 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10116 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10118 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10120 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10121 * bitwise-or of what L1 wants to trap for L2, and what we want to
10122 * trap. Note that CR0.TS also needs updating - we do this later.
10124 update_exception_bitmap(vcpu
);
10125 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10126 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10128 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10129 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10130 * bits are further modified by vmx_set_efer() below.
10132 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10134 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10135 * emulated by vmx_set_efer(), below.
10137 vm_entry_controls_init(vmx
,
10138 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10139 ~VM_ENTRY_IA32E_MODE
) |
10140 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10142 if (from_vmentry
&&
10143 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10144 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10145 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10146 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10147 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10150 set_cr4_guest_host_mask(vmx
);
10152 if (from_vmentry
&&
10153 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10154 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10156 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10157 vmcs_write64(TSC_OFFSET
,
10158 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10160 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10161 if (kvm_has_tsc_control
)
10162 decache_tsc_multiplier(vmx
);
10166 * There is no direct mapping between vpid02 and vpid12, the
10167 * vpid02 is per-vCPU for L0 and reused while the value of
10168 * vpid12 is changed w/ one invvpid during nested vmentry.
10169 * The vpid12 is allocated by L1 for L2, so it will not
10170 * influence global bitmap(for vpid01 and vpid02 allocation)
10171 * even if spawn a lot of nested vCPUs.
10173 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10174 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10175 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10176 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10177 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10180 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10181 vmx_flush_tlb(vcpu
);
10188 * Conceptually we want to copy the PML address and index from
10189 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10190 * since we always flush the log on each vmexit, this happens
10191 * to be equivalent to simply resetting the fields in vmcs02.
10193 ASSERT(vmx
->pml_pg
);
10194 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10195 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10198 if (nested_cpu_has_ept(vmcs12
)) {
10199 if (nested_ept_init_mmu_context(vcpu
)) {
10200 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10203 } else if (nested_cpu_has2(vmcs12
,
10204 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10205 vmx_flush_tlb_ept_only(vcpu
);
10209 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10210 * bits which we consider mandatory enabled.
10211 * The CR0_READ_SHADOW is what L2 should have expected to read given
10212 * the specifications by L1; It's not enough to take
10213 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10214 * have more bits than L1 expected.
10216 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10217 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10219 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10220 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10222 if (from_vmentry
&&
10223 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10224 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10225 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10226 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10228 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10229 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10230 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10232 /* Shadow page tables on either EPT or shadow page tables. */
10233 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10234 entry_failure_code
))
10238 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10241 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10244 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10245 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10246 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10247 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10250 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10251 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10255 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10257 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10259 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10260 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10261 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10263 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10264 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10266 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10267 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10269 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10270 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10272 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10273 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10275 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10276 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10277 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10278 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10279 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10280 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10281 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10282 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10283 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10284 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10285 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10286 vmx
->nested
.nested_vmx_exit_ctls_low
,
10287 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10288 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10289 vmx
->nested
.nested_vmx_entry_ctls_low
,
10290 vmx
->nested
.nested_vmx_entry_ctls_high
))
10291 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10293 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10294 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10296 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10297 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10298 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10299 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10304 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10309 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10311 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10312 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10315 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10316 vmcs12
->vmcs_link_pointer
!= -1ull) {
10317 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10322 * If the load IA32_EFER VM-entry control is 1, the following checks
10323 * are performed on the field for the IA32_EFER MSR:
10324 * - Bits reserved in the IA32_EFER MSR must be 0.
10325 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10326 * the IA-32e mode guest VM-exit control. It must also be identical
10327 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10330 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10331 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10332 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10333 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10334 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10335 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10336 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10341 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10342 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10343 * the values of the LMA and LME bits in the field must each be that of
10344 * the host address-space size VM-exit control.
10346 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10347 ia32e
= (vmcs12
->vm_exit_controls
&
10348 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10349 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10350 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10351 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10358 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10360 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10361 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10362 struct loaded_vmcs
*vmcs02
;
10366 vmcs02
= nested_get_current_vmcs02(vmx
);
10370 enter_guest_mode(vcpu
);
10372 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10373 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10375 vmx_switch_vmcs(vcpu
, vmcs02
);
10376 vmx_segment_cache_clear(vmx
);
10378 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10379 leave_guest_mode(vcpu
);
10380 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10381 nested_vmx_entry_failure(vcpu
, vmcs12
,
10382 EXIT_REASON_INVALID_STATE
, exit_qual
);
10386 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10388 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10389 vmcs12
->vm_entry_msr_load_addr
,
10390 vmcs12
->vm_entry_msr_load_count
);
10391 if (msr_entry_idx
) {
10392 leave_guest_mode(vcpu
);
10393 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10394 nested_vmx_entry_failure(vcpu
, vmcs12
,
10395 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10399 vmcs12
->launch_state
= 1;
10402 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10403 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10404 * returned as far as L1 is concerned. It will only return (and set
10405 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10411 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10412 * for running an L2 nested guest.
10414 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10416 struct vmcs12
*vmcs12
;
10417 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10421 if (!nested_vmx_check_permission(vcpu
))
10424 if (!nested_vmx_check_vmcs12(vcpu
))
10427 vmcs12
= get_vmcs12(vcpu
);
10429 if (enable_shadow_vmcs
)
10430 copy_shadow_to_vmcs12(vmx
);
10433 * The nested entry process starts with enforcing various prerequisites
10434 * on vmcs12 as required by the Intel SDM, and act appropriately when
10435 * they fail: As the SDM explains, some conditions should cause the
10436 * instruction to fail, while others will cause the instruction to seem
10437 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10438 * To speed up the normal (success) code path, we should avoid checking
10439 * for misconfigurations which will anyway be caught by the processor
10440 * when using the merged vmcs02.
10442 if (vmcs12
->launch_state
== launch
) {
10443 nested_vmx_failValid(vcpu
,
10444 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10445 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10449 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10451 nested_vmx_failValid(vcpu
, ret
);
10456 * After this point, the trap flag no longer triggers a singlestep trap
10457 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10458 * This is not 100% correct; for performance reasons, we delegate most
10459 * of the checks on host state to the processor. If those fail,
10460 * the singlestep trap is missed.
10462 skip_emulated_instruction(vcpu
);
10464 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10466 nested_vmx_entry_failure(vcpu
, vmcs12
,
10467 EXIT_REASON_INVALID_STATE
, exit_qual
);
10472 * We're finally done with prerequisite checking, and can start with
10473 * the nested entry.
10476 ret
= enter_vmx_non_root_mode(vcpu
, true);
10480 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10481 return kvm_vcpu_halt(vcpu
);
10483 vmx
->nested
.nested_run_pending
= 1;
10488 return kvm_skip_emulated_instruction(vcpu
);
10492 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10493 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10494 * This function returns the new value we should put in vmcs12.guest_cr0.
10495 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10496 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10497 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10498 * didn't trap the bit, because if L1 did, so would L0).
10499 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10500 * been modified by L2, and L1 knows it. So just leave the old value of
10501 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10502 * isn't relevant, because if L0 traps this bit it can set it to anything.
10503 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10504 * changed these bits, and therefore they need to be updated, but L0
10505 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10506 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10508 static inline unsigned long
10509 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10512 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10513 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10514 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10515 vcpu
->arch
.cr0_guest_owned_bits
));
10518 static inline unsigned long
10519 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10522 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10523 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10524 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10525 vcpu
->arch
.cr4_guest_owned_bits
));
10528 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10529 struct vmcs12
*vmcs12
)
10534 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10535 nr
= vcpu
->arch
.exception
.nr
;
10536 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10538 if (kvm_exception_is_soft(nr
)) {
10539 vmcs12
->vm_exit_instruction_len
=
10540 vcpu
->arch
.event_exit_inst_len
;
10541 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10543 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10545 if (vcpu
->arch
.exception
.has_error_code
) {
10546 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10547 vmcs12
->idt_vectoring_error_code
=
10548 vcpu
->arch
.exception
.error_code
;
10551 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10552 } else if (vcpu
->arch
.nmi_injected
) {
10553 vmcs12
->idt_vectoring_info_field
=
10554 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10555 } else if (vcpu
->arch
.interrupt
.pending
) {
10556 nr
= vcpu
->arch
.interrupt
.nr
;
10557 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10559 if (vcpu
->arch
.interrupt
.soft
) {
10560 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10561 vmcs12
->vm_entry_instruction_len
=
10562 vcpu
->arch
.event_exit_inst_len
;
10564 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10566 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10570 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10572 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10574 if (vcpu
->arch
.exception
.pending
||
10575 vcpu
->arch
.nmi_injected
||
10576 vcpu
->arch
.interrupt
.pending
)
10579 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10580 vmx
->nested
.preemption_timer_expired
) {
10581 if (vmx
->nested
.nested_run_pending
)
10583 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10587 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10588 if (vmx
->nested
.nested_run_pending
)
10590 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10591 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10592 INTR_INFO_VALID_MASK
, 0);
10594 * The NMI-triggered VM exit counts as injection:
10595 * clear this one and block further NMIs.
10597 vcpu
->arch
.nmi_pending
= 0;
10598 vmx_set_nmi_mask(vcpu
, true);
10602 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10603 nested_exit_on_intr(vcpu
)) {
10604 if (vmx
->nested
.nested_run_pending
)
10606 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10610 vmx_complete_nested_posted_interrupt(vcpu
);
10614 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10616 ktime_t remaining
=
10617 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10620 if (ktime_to_ns(remaining
) <= 0)
10623 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10624 do_div(value
, 1000000);
10625 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10629 * Update the guest state fields of vmcs12 to reflect changes that
10630 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10631 * VM-entry controls is also updated, since this is really a guest
10634 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10636 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10637 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10639 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10640 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10641 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10643 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10644 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10645 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10646 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10647 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10648 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10649 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10650 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10651 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10652 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10653 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10654 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10655 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10656 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10657 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10658 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10659 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10660 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10661 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10662 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10663 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10664 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10665 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10666 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10667 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10668 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10669 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10670 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10671 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10672 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10673 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10674 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10675 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10676 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10677 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10678 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10680 vmcs12
->guest_interruptibility_info
=
10681 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10682 vmcs12
->guest_pending_dbg_exceptions
=
10683 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10684 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10685 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10687 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10689 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10690 if (vmcs12
->vm_exit_controls
&
10691 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10692 vmcs12
->vmx_preemption_timer_value
=
10693 vmx_get_preemption_timer_value(vcpu
);
10694 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10698 * In some cases (usually, nested EPT), L2 is allowed to change its
10699 * own CR3 without exiting. If it has changed it, we must keep it.
10700 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10701 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10703 * Additionally, restore L2's PDPTR to vmcs12.
10706 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10707 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10708 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10709 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10710 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10713 if (nested_cpu_has_ept(vmcs12
))
10714 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
10716 if (nested_cpu_has_vid(vmcs12
))
10717 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10719 vmcs12
->vm_entry_controls
=
10720 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10721 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10723 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10724 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10725 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10728 /* TODO: These cannot have changed unless we have MSR bitmaps and
10729 * the relevant bit asks not to trap the change */
10730 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10731 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10732 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10733 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10734 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10735 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10736 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10737 if (kvm_mpx_supported())
10738 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10739 if (nested_cpu_has_xsaves(vmcs12
))
10740 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10744 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10745 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10746 * and this function updates it to reflect the changes to the guest state while
10747 * L2 was running (and perhaps made some exits which were handled directly by L0
10748 * without going back to L1), and to reflect the exit reason.
10749 * Note that we do not have to copy here all VMCS fields, just those that
10750 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10751 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10752 * which already writes to vmcs12 directly.
10754 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10755 u32 exit_reason
, u32 exit_intr_info
,
10756 unsigned long exit_qualification
)
10758 /* update guest state fields: */
10759 sync_vmcs12(vcpu
, vmcs12
);
10761 /* update exit information fields: */
10763 vmcs12
->vm_exit_reason
= exit_reason
;
10764 vmcs12
->exit_qualification
= exit_qualification
;
10766 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10767 if ((vmcs12
->vm_exit_intr_info
&
10768 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10769 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10770 vmcs12
->vm_exit_intr_error_code
=
10771 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10772 vmcs12
->idt_vectoring_info_field
= 0;
10773 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10774 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10776 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10777 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10778 * instead of reading the real value. */
10779 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10782 * Transfer the event that L0 or L1 may wanted to inject into
10783 * L2 to IDT_VECTORING_INFO_FIELD.
10785 vmcs12_save_pending_event(vcpu
, vmcs12
);
10789 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10790 * preserved above and would only end up incorrectly in L1.
10792 vcpu
->arch
.nmi_injected
= false;
10793 kvm_clear_exception_queue(vcpu
);
10794 kvm_clear_interrupt_queue(vcpu
);
10798 * A part of what we need to when the nested L2 guest exits and we want to
10799 * run its L1 parent, is to reset L1's guest state to the host state specified
10801 * This function is to be called not only on normal nested exit, but also on
10802 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10803 * Failures During or After Loading Guest State").
10804 * This function should be called when the active VMCS is L1's (vmcs01).
10806 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10807 struct vmcs12
*vmcs12
)
10809 struct kvm_segment seg
;
10810 u32 entry_failure_code
;
10812 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10813 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10814 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10815 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10817 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10818 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10820 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10821 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10822 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10824 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10825 * actually changed, because vmx_set_cr0 refers to efer set above.
10827 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10828 * (KVM doesn't change it);
10830 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
10831 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10833 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
10834 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10835 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10837 nested_ept_uninit_mmu_context(vcpu
);
10840 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10841 * couldn't have changed.
10843 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
10844 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
10847 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10851 * Trivially support vpid by letting L2s share their parent
10852 * L1's vpid. TODO: move to a more elaborate solution, giving
10853 * each L2 its own vpid and exposing the vpid feature to L1.
10855 vmx_flush_tlb(vcpu
);
10859 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10860 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10861 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10862 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10863 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10865 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10866 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10867 vmcs_write64(GUEST_BNDCFGS
, 0);
10869 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10870 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10871 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10873 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10874 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10875 vmcs12
->host_ia32_perf_global_ctrl
);
10877 /* Set L1 segment info according to Intel SDM
10878 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10879 seg
= (struct kvm_segment
) {
10881 .limit
= 0xFFFFFFFF,
10882 .selector
= vmcs12
->host_cs_selector
,
10888 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10892 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10893 seg
= (struct kvm_segment
) {
10895 .limit
= 0xFFFFFFFF,
10902 seg
.selector
= vmcs12
->host_ds_selector
;
10903 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10904 seg
.selector
= vmcs12
->host_es_selector
;
10905 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10906 seg
.selector
= vmcs12
->host_ss_selector
;
10907 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10908 seg
.selector
= vmcs12
->host_fs_selector
;
10909 seg
.base
= vmcs12
->host_fs_base
;
10910 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10911 seg
.selector
= vmcs12
->host_gs_selector
;
10912 seg
.base
= vmcs12
->host_gs_base
;
10913 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10914 seg
= (struct kvm_segment
) {
10915 .base
= vmcs12
->host_tr_base
,
10917 .selector
= vmcs12
->host_tr_selector
,
10921 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10923 kvm_set_dr(vcpu
, 7, 0x400);
10924 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10926 if (cpu_has_vmx_msr_bitmap())
10927 vmx_set_msr_bitmap(vcpu
);
10929 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10930 vmcs12
->vm_exit_msr_load_count
))
10931 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10935 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10936 * and modify vmcs12 to make it see what it would expect to see there if
10937 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10939 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10940 u32 exit_intr_info
,
10941 unsigned long exit_qualification
)
10943 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10944 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10945 u32 vm_inst_error
= 0;
10947 /* trying to cancel vmlaunch/vmresume is a bug */
10948 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10950 leave_guest_mode(vcpu
);
10951 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10952 exit_qualification
);
10954 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10955 vmcs12
->vm_exit_msr_store_count
))
10956 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10958 if (unlikely(vmx
->fail
))
10959 vm_inst_error
= vmcs_read32(VM_INSTRUCTION_ERROR
);
10961 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10963 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10964 && nested_exit_intr_ack_set(vcpu
)) {
10965 int irq
= kvm_cpu_get_interrupt(vcpu
);
10967 vmcs12
->vm_exit_intr_info
= irq
|
10968 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10971 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10972 vmcs12
->exit_qualification
,
10973 vmcs12
->idt_vectoring_info_field
,
10974 vmcs12
->vm_exit_intr_info
,
10975 vmcs12
->vm_exit_intr_error_code
,
10978 vm_entry_controls_reset_shadow(vmx
);
10979 vm_exit_controls_reset_shadow(vmx
);
10980 vmx_segment_cache_clear(vmx
);
10982 /* if no vmcs02 cache requested, remove the one we used */
10983 if (VMCS02_POOL_SIZE
== 0)
10984 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10986 load_vmcs12_host_state(vcpu
, vmcs12
);
10988 /* Update any VMCS fields that might have changed while L2 ran */
10989 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10990 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10991 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10992 if (vmx
->hv_deadline_tsc
== -1)
10993 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
10994 PIN_BASED_VMX_PREEMPTION_TIMER
);
10996 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
10997 PIN_BASED_VMX_PREEMPTION_TIMER
);
10998 if (kvm_has_tsc_control
)
10999 decache_tsc_multiplier(vmx
);
11001 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11002 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11003 vmx_set_virtual_x2apic_mode(vcpu
,
11004 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11005 } else if (!nested_cpu_has_ept(vmcs12
) &&
11006 nested_cpu_has2(vmcs12
,
11007 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11008 vmx_flush_tlb_ept_only(vcpu
);
11011 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11014 /* Unpin physical memory we referred to in vmcs02 */
11015 if (vmx
->nested
.apic_access_page
) {
11016 nested_release_page(vmx
->nested
.apic_access_page
);
11017 vmx
->nested
.apic_access_page
= NULL
;
11019 if (vmx
->nested
.virtual_apic_page
) {
11020 nested_release_page(vmx
->nested
.virtual_apic_page
);
11021 vmx
->nested
.virtual_apic_page
= NULL
;
11023 if (vmx
->nested
.pi_desc_page
) {
11024 kunmap(vmx
->nested
.pi_desc_page
);
11025 nested_release_page(vmx
->nested
.pi_desc_page
);
11026 vmx
->nested
.pi_desc_page
= NULL
;
11027 vmx
->nested
.pi_desc
= NULL
;
11031 * We are now running in L2, mmu_notifier will force to reload the
11032 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11034 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11037 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11038 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11039 * success or failure flag accordingly.
11041 if (unlikely(vmx
->fail
)) {
11043 nested_vmx_failValid(vcpu
, vm_inst_error
);
11045 nested_vmx_succeed(vcpu
);
11046 if (enable_shadow_vmcs
)
11047 vmx
->nested
.sync_shadow_vmcs
= true;
11049 /* in case we halted in L2 */
11050 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11054 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11056 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11058 if (is_guest_mode(vcpu
)) {
11059 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11060 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11062 free_nested(to_vmx(vcpu
));
11066 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11067 * 23.7 "VM-entry failures during or after loading guest state" (this also
11068 * lists the acceptable exit-reason and exit-qualification parameters).
11069 * It should only be called before L2 actually succeeded to run, and when
11070 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11072 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11073 struct vmcs12
*vmcs12
,
11074 u32 reason
, unsigned long qualification
)
11076 load_vmcs12_host_state(vcpu
, vmcs12
);
11077 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11078 vmcs12
->exit_qualification
= qualification
;
11079 nested_vmx_succeed(vcpu
);
11080 if (enable_shadow_vmcs
)
11081 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11084 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11085 struct x86_instruction_info
*info
,
11086 enum x86_intercept_stage stage
)
11088 return X86EMUL_CONTINUE
;
11091 #ifdef CONFIG_X86_64
11092 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11093 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11094 u64 divisor
, u64
*result
)
11096 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11098 /* To avoid the overflow on divq */
11099 if (high
>= divisor
)
11102 /* Low hold the result, high hold rem which is discarded */
11103 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11104 "rm" (divisor
), "0" (low
), "1" (high
));
11110 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11112 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11113 u64 tscl
= rdtsc();
11114 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11115 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11117 /* Convert to host delta tsc if tsc scaling is enabled */
11118 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11119 u64_shl_div_u64(delta_tsc
,
11120 kvm_tsc_scaling_ratio_frac_bits
,
11121 vcpu
->arch
.tsc_scaling_ratio
,
11126 * If the delta tsc can't fit in the 32 bit after the multi shift,
11127 * we can't use the preemption timer.
11128 * It's possible that it fits on later vmentries, but checking
11129 * on every vmentry is costly so we just use an hrtimer.
11131 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11134 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11135 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11136 PIN_BASED_VMX_PREEMPTION_TIMER
);
11140 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11142 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11143 vmx
->hv_deadline_tsc
= -1;
11144 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11145 PIN_BASED_VMX_PREEMPTION_TIMER
);
11149 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11152 shrink_ple_window(vcpu
);
11155 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11156 struct kvm_memory_slot
*slot
)
11158 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11159 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11162 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11163 struct kvm_memory_slot
*slot
)
11165 kvm_mmu_slot_set_dirty(kvm
, slot
);
11168 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11170 kvm_flush_pml_buffers(kvm
);
11173 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11175 struct vmcs12
*vmcs12
;
11176 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11178 struct page
*page
= NULL
;
11181 if (is_guest_mode(vcpu
)) {
11182 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11185 * Check if PML is enabled for the nested guest.
11186 * Whether eptp bit 6 is set is already checked
11187 * as part of A/D emulation.
11189 vmcs12
= get_vmcs12(vcpu
);
11190 if (!nested_cpu_has_pml(vmcs12
))
11193 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11194 vmx
->nested
.pml_full
= true;
11198 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11200 page
= nested_get_page(vcpu
, vmcs12
->pml_address
);
11204 pml_address
= kmap(page
);
11205 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11207 nested_release_page_clean(page
);
11213 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11214 struct kvm_memory_slot
*memslot
,
11215 gfn_t offset
, unsigned long mask
)
11217 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11221 * This routine does the following things for vCPU which is going
11222 * to be blocked if VT-d PI is enabled.
11223 * - Store the vCPU to the wakeup list, so when interrupts happen
11224 * we can find the right vCPU to wake up.
11225 * - Change the Posted-interrupt descriptor as below:
11226 * 'NDST' <-- vcpu->pre_pcpu
11227 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11228 * - If 'ON' is set during this process, which means at least one
11229 * interrupt is posted for this vCPU, we cannot block it, in
11230 * this case, return 1, otherwise, return 0.
11233 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11235 unsigned long flags
;
11237 struct pi_desc old
, new;
11238 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11240 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11241 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11242 !kvm_vcpu_apicv_active(vcpu
))
11245 vcpu
->pre_pcpu
= vcpu
->cpu
;
11246 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11247 vcpu
->pre_pcpu
), flags
);
11248 list_add_tail(&vcpu
->blocked_vcpu_list
,
11249 &per_cpu(blocked_vcpu_on_cpu
,
11251 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
11252 vcpu
->pre_pcpu
), flags
);
11255 old
.control
= new.control
= pi_desc
->control
;
11258 * We should not block the vCPU if
11259 * an interrupt is posted for it.
11261 if (pi_test_on(pi_desc
) == 1) {
11262 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11263 vcpu
->pre_pcpu
), flags
);
11264 list_del(&vcpu
->blocked_vcpu_list
);
11265 spin_unlock_irqrestore(
11266 &per_cpu(blocked_vcpu_on_cpu_lock
,
11267 vcpu
->pre_pcpu
), flags
);
11268 vcpu
->pre_pcpu
= -1;
11273 WARN((pi_desc
->sn
== 1),
11274 "Warning: SN field of posted-interrupts "
11275 "is set before blocking\n");
11278 * Since vCPU can be preempted during this process,
11279 * vcpu->cpu could be different with pre_pcpu, we
11280 * need to set pre_pcpu as the destination of wakeup
11281 * notification event, then we can find the right vCPU
11282 * to wakeup in wakeup handler if interrupts happen
11283 * when the vCPU is in blocked state.
11285 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11287 if (x2apic_enabled())
11290 new.ndst
= (dest
<< 8) & 0xFF00;
11292 /* set 'NV' to 'wakeup vector' */
11293 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11294 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11295 new.control
) != old
.control
);
11300 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11302 if (pi_pre_block(vcpu
))
11305 if (kvm_lapic_hv_timer_in_use(vcpu
))
11306 kvm_lapic_switch_to_sw_timer(vcpu
);
11311 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11313 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11314 struct pi_desc old
, new;
11316 unsigned long flags
;
11318 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11319 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11320 !kvm_vcpu_apicv_active(vcpu
))
11324 old
.control
= new.control
= pi_desc
->control
;
11326 dest
= cpu_physical_id(vcpu
->cpu
);
11328 if (x2apic_enabled())
11331 new.ndst
= (dest
<< 8) & 0xFF00;
11333 /* Allow posting non-urgent interrupts */
11336 /* set 'NV' to 'notification vector' */
11337 new.nv
= POSTED_INTR_VECTOR
;
11338 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11339 new.control
) != old
.control
);
11341 if(vcpu
->pre_pcpu
!= -1) {
11343 &per_cpu(blocked_vcpu_on_cpu_lock
,
11344 vcpu
->pre_pcpu
), flags
);
11345 list_del(&vcpu
->blocked_vcpu_list
);
11346 spin_unlock_irqrestore(
11347 &per_cpu(blocked_vcpu_on_cpu_lock
,
11348 vcpu
->pre_pcpu
), flags
);
11349 vcpu
->pre_pcpu
= -1;
11353 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11355 if (kvm_x86_ops
->set_hv_timer
)
11356 kvm_lapic_switch_to_hv_timer(vcpu
);
11358 pi_post_block(vcpu
);
11362 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11365 * @host_irq: host irq of the interrupt
11366 * @guest_irq: gsi of the interrupt
11367 * @set: set or unset PI
11368 * returns 0 on success, < 0 on failure
11370 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11371 uint32_t guest_irq
, bool set
)
11373 struct kvm_kernel_irq_routing_entry
*e
;
11374 struct kvm_irq_routing_table
*irq_rt
;
11375 struct kvm_lapic_irq irq
;
11376 struct kvm_vcpu
*vcpu
;
11377 struct vcpu_data vcpu_info
;
11378 int idx
, ret
= -EINVAL
;
11380 if (!kvm_arch_has_assigned_device(kvm
) ||
11381 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11382 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11385 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11386 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11387 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
11389 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11390 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11393 * VT-d PI cannot support posting multicast/broadcast
11394 * interrupts to a vCPU, we still use interrupt remapping
11395 * for these kind of interrupts.
11397 * For lowest-priority interrupts, we only support
11398 * those with single CPU as the destination, e.g. user
11399 * configures the interrupts via /proc/irq or uses
11400 * irqbalance to make the interrupts single-CPU.
11402 * We will support full lowest-priority interrupt later.
11405 kvm_set_msi_irq(kvm
, e
, &irq
);
11406 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11408 * Make sure the IRTE is in remapped mode if
11409 * we don't handle it in posted mode.
11411 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11414 "failed to back to remapped mode, irq: %u\n",
11422 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11423 vcpu_info
.vector
= irq
.vector
;
11425 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11426 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11429 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11431 /* suppress notification event before unposting */
11432 pi_set_sn(vcpu_to_pi_desc(vcpu
));
11433 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11434 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
11438 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11446 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11450 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11452 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11453 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11454 FEATURE_CONTROL_LMCE
;
11456 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11457 ~FEATURE_CONTROL_LMCE
;
11460 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11461 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11462 .disabled_by_bios
= vmx_disabled_by_bios
,
11463 .hardware_setup
= hardware_setup
,
11464 .hardware_unsetup
= hardware_unsetup
,
11465 .check_processor_compatibility
= vmx_check_processor_compat
,
11466 .hardware_enable
= hardware_enable
,
11467 .hardware_disable
= hardware_disable
,
11468 .cpu_has_accelerated_tpr
= report_flexpriority
,
11469 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11471 .vcpu_create
= vmx_create_vcpu
,
11472 .vcpu_free
= vmx_free_vcpu
,
11473 .vcpu_reset
= vmx_vcpu_reset
,
11475 .prepare_guest_switch
= vmx_save_host_state
,
11476 .vcpu_load
= vmx_vcpu_load
,
11477 .vcpu_put
= vmx_vcpu_put
,
11479 .update_bp_intercept
= update_exception_bitmap
,
11480 .get_msr
= vmx_get_msr
,
11481 .set_msr
= vmx_set_msr
,
11482 .get_segment_base
= vmx_get_segment_base
,
11483 .get_segment
= vmx_get_segment
,
11484 .set_segment
= vmx_set_segment
,
11485 .get_cpl
= vmx_get_cpl
,
11486 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11487 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11488 .decache_cr3
= vmx_decache_cr3
,
11489 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11490 .set_cr0
= vmx_set_cr0
,
11491 .set_cr3
= vmx_set_cr3
,
11492 .set_cr4
= vmx_set_cr4
,
11493 .set_efer
= vmx_set_efer
,
11494 .get_idt
= vmx_get_idt
,
11495 .set_idt
= vmx_set_idt
,
11496 .get_gdt
= vmx_get_gdt
,
11497 .set_gdt
= vmx_set_gdt
,
11498 .get_dr6
= vmx_get_dr6
,
11499 .set_dr6
= vmx_set_dr6
,
11500 .set_dr7
= vmx_set_dr7
,
11501 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11502 .cache_reg
= vmx_cache_reg
,
11503 .get_rflags
= vmx_get_rflags
,
11504 .set_rflags
= vmx_set_rflags
,
11506 .get_pkru
= vmx_get_pkru
,
11508 .tlb_flush
= vmx_flush_tlb
,
11510 .run
= vmx_vcpu_run
,
11511 .handle_exit
= vmx_handle_exit
,
11512 .skip_emulated_instruction
= skip_emulated_instruction
,
11513 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11514 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11515 .patch_hypercall
= vmx_patch_hypercall
,
11516 .set_irq
= vmx_inject_irq
,
11517 .set_nmi
= vmx_inject_nmi
,
11518 .queue_exception
= vmx_queue_exception
,
11519 .cancel_injection
= vmx_cancel_injection
,
11520 .interrupt_allowed
= vmx_interrupt_allowed
,
11521 .nmi_allowed
= vmx_nmi_allowed
,
11522 .get_nmi_mask
= vmx_get_nmi_mask
,
11523 .set_nmi_mask
= vmx_set_nmi_mask
,
11524 .enable_nmi_window
= enable_nmi_window
,
11525 .enable_irq_window
= enable_irq_window
,
11526 .update_cr8_intercept
= update_cr8_intercept
,
11527 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11528 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11529 .get_enable_apicv
= vmx_get_enable_apicv
,
11530 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11531 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11532 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
11533 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11534 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11535 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11536 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11538 .set_tss_addr
= vmx_set_tss_addr
,
11539 .get_tdp_level
= get_ept_level
,
11540 .get_mt_mask
= vmx_get_mt_mask
,
11542 .get_exit_info
= vmx_get_exit_info
,
11544 .get_lpage_level
= vmx_get_lpage_level
,
11546 .cpuid_update
= vmx_cpuid_update
,
11548 .rdtscp_supported
= vmx_rdtscp_supported
,
11549 .invpcid_supported
= vmx_invpcid_supported
,
11551 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11553 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11555 .write_tsc_offset
= vmx_write_tsc_offset
,
11557 .set_tdp_cr3
= vmx_set_cr3
,
11559 .check_intercept
= vmx_check_intercept
,
11560 .handle_external_intr
= vmx_handle_external_intr
,
11561 .mpx_supported
= vmx_mpx_supported
,
11562 .xsaves_supported
= vmx_xsaves_supported
,
11564 .check_nested_events
= vmx_check_nested_events
,
11566 .sched_in
= vmx_sched_in
,
11568 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11569 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11570 .flush_log_dirty
= vmx_flush_log_dirty
,
11571 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11572 .write_log_dirty
= vmx_write_pml_buffer
,
11574 .pre_block
= vmx_pre_block
,
11575 .post_block
= vmx_post_block
,
11577 .pmu_ops
= &intel_pmu_ops
,
11579 .update_pi_irte
= vmx_update_pi_irte
,
11581 #ifdef CONFIG_X86_64
11582 .set_hv_timer
= vmx_set_hv_timer
,
11583 .cancel_hv_timer
= vmx_cancel_hv_timer
,
11586 .setup_mce
= vmx_setup_mce
,
11589 static int __init
vmx_init(void)
11591 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11592 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11596 #ifdef CONFIG_KEXEC_CORE
11597 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11598 crash_vmclear_local_loaded_vmcss
);
11604 static void __exit
vmx_exit(void)
11606 #ifdef CONFIG_KEXEC_CORE
11607 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11614 module_init(vmx_init
)
11615 module_exit(vmx_exit
)