projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
KVM: VMX: fix handle_pause declaration
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include <linux/ftrace_event.h>
29 #include "kvm_cache_regs.h"
30 #include "x86.h"
31
32 #include <asm/io.h>
33 #include <asm/desc.h>
34 #include <asm/vmx.h>
35 #include <asm/virtext.h>
36 #include <asm/mce.h>
37
38 #include "trace.h"
39
40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
41
42 MODULE_AUTHOR("Qumranet");
43 MODULE_LICENSE("GPL");
44
45 static int __read_mostly bypass_guest_pf = 1;
46 module_param(bypass_guest_pf, bool, S_IRUGO);
47
48 static int __read_mostly enable_vpid = 1;
49 module_param_named(vpid, enable_vpid, bool, 0444);
50
51 static int __read_mostly flexpriority_enabled = 1;
52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
53
54 static int __read_mostly enable_ept = 1;
55 module_param_named(ept, enable_ept, bool, S_IRUGO);
56
57 static int __read_mostly enable_unrestricted_guest = 1;
58 module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
61 static int __read_mostly emulate_invalid_guest_state = 0;
62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
63
64 /*
65 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
66 * ple_gap: upper bound on the amount of time between two successive
67 * executions of PAUSE in a loop. Also indicate if ple enabled.
68 * According to test, this time is usually small than 41 cycles.
69 * ple_window: upper bound on the amount of time a guest is allowed to execute
70 * in a PAUSE loop. Tests indicate that most spinlocks are held for
71 * less than 2^12 cycles
72 * Time is measured based on a counter that runs at the same rate as the TSC,
73 * refer SDM volume 3b section 21.6.13 & 22.1.3.
74 */
75 #define KVM_VMX_DEFAULT_PLE_GAP 41
76 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
77 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
78 module_param(ple_gap, int, S_IRUGO);
79
80 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
81 module_param(ple_window, int, S_IRUGO);
82
83 struct vmcs {
84 u32 revision_id;
85 u32 abort;
86 char data[0];
87 };
88
89 struct vcpu_vmx {
90 struct kvm_vcpu vcpu;
91 struct list_head local_vcpus_link;
92 unsigned long host_rsp;
93 int launched;
94 u8 fail;
95 u32 idt_vectoring_info;
96 struct kvm_msr_entry *guest_msrs;
97 struct kvm_msr_entry *host_msrs;
98 int nmsrs;
99 int save_nmsrs;
100 int msr_offset_efer;
101 #ifdef CONFIG_X86_64
102 int msr_offset_kernel_gs_base;
103 #endif
104 struct vmcs *vmcs;
105 struct {
106 int loaded;
107 u16 fs_sel, gs_sel, ldt_sel;
108 int gs_ldt_reload_needed;
109 int fs_reload_needed;
110 int guest_efer_loaded;
111 } host_state;
112 struct {
113 int vm86_active;
114 u8 save_iopl;
115 struct kvm_save_segment {
116 u16 selector;
117 unsigned long base;
118 u32 limit;
119 u32 ar;
120 } tr, es, ds, fs, gs;
121 struct {
122 bool pending;
123 u8 vector;
124 unsigned rip;
125 } irq;
126 } rmode;
127 int vpid;
128 bool emulation_required;
129
130 /* Support for vnmi-less CPUs */
131 int soft_vnmi_blocked;
132 ktime_t entry_time;
133 s64 vnmi_blocked_time;
134 u32 exit_reason;
135 };
136
137 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
138 {
139 return container_of(vcpu, struct vcpu_vmx, vcpu);
140 }
141
142 static int init_rmode(struct kvm *kvm);
143 static u64 construct_eptp(unsigned long root_hpa);
144
145 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
146 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
147 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
148
149 static unsigned long *vmx_io_bitmap_a;
150 static unsigned long *vmx_io_bitmap_b;
151 static unsigned long *vmx_msr_bitmap_legacy;
152 static unsigned long *vmx_msr_bitmap_longmode;
153
154 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
155 static DEFINE_SPINLOCK(vmx_vpid_lock);
156
157 static struct vmcs_config {
158 int size;
159 int order;
160 u32 revision_id;
161 u32 pin_based_exec_ctrl;
162 u32 cpu_based_exec_ctrl;
163 u32 cpu_based_2nd_exec_ctrl;
164 u32 vmexit_ctrl;
165 u32 vmentry_ctrl;
166 } vmcs_config;
167
168 static struct vmx_capability {
169 u32 ept;
170 u32 vpid;
171 } vmx_capability;
172
173 #define VMX_SEGMENT_FIELD(seg) \
174 [VCPU_SREG_##seg] = { \
175 .selector = GUEST_##seg##_SELECTOR, \
176 .base = GUEST_##seg##_BASE, \
177 .limit = GUEST_##seg##_LIMIT, \
178 .ar_bytes = GUEST_##seg##_AR_BYTES, \
179 }
180
181 static struct kvm_vmx_segment_field {
182 unsigned selector;
183 unsigned base;
184 unsigned limit;
185 unsigned ar_bytes;
186 } kvm_vmx_segment_fields[] = {
187 VMX_SEGMENT_FIELD(CS),
188 VMX_SEGMENT_FIELD(DS),
189 VMX_SEGMENT_FIELD(ES),
190 VMX_SEGMENT_FIELD(FS),
191 VMX_SEGMENT_FIELD(GS),
192 VMX_SEGMENT_FIELD(SS),
193 VMX_SEGMENT_FIELD(TR),
194 VMX_SEGMENT_FIELD(LDTR),
195 };
196
197 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
198
199 /*
200 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
201 * away by decrementing the array size.
202 */
203 static const u32 vmx_msr_index[] = {
204 #ifdef CONFIG_X86_64
205 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
206 #endif
207 MSR_EFER, MSR_K6_STAR,
208 };
209 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
210
211 static void load_msrs(struct kvm_msr_entry *e, int n)
212 {
213 int i;
214
215 for (i = 0; i < n; ++i)
216 wrmsrl(e[i].index, e[i].data);
217 }
218
219 static void save_msrs(struct kvm_msr_entry *e, int n)
220 {
221 int i;
222
223 for (i = 0; i < n; ++i)
224 rdmsrl(e[i].index, e[i].data);
225 }
226
227 static inline int is_page_fault(u32 intr_info)
228 {
229 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
230 INTR_INFO_VALID_MASK)) ==
231 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
232 }
233
234 static inline int is_no_device(u32 intr_info)
235 {
236 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
237 INTR_INFO_VALID_MASK)) ==
238 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
239 }
240
241 static inline int is_invalid_opcode(u32 intr_info)
242 {
243 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
244 INTR_INFO_VALID_MASK)) ==
245 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
246 }
247
248 static inline int is_external_interrupt(u32 intr_info)
249 {
250 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
251 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
252 }
253
254 static inline int is_machine_check(u32 intr_info)
255 {
256 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
257 INTR_INFO_VALID_MASK)) ==
258 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
259 }
260
261 static inline int cpu_has_vmx_msr_bitmap(void)
262 {
263 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
264 }
265
266 static inline int cpu_has_vmx_tpr_shadow(void)
267 {
268 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
269 }
270
271 static inline int vm_need_tpr_shadow(struct kvm *kvm)
272 {
273 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
274 }
275
276 static inline int cpu_has_secondary_exec_ctrls(void)
277 {
278 return vmcs_config.cpu_based_exec_ctrl &
279 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
280 }
281
282 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
283 {
284 return vmcs_config.cpu_based_2nd_exec_ctrl &
285 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
286 }
287
288 static inline bool cpu_has_vmx_flexpriority(void)
289 {
290 return cpu_has_vmx_tpr_shadow() &&
291 cpu_has_vmx_virtualize_apic_accesses();
292 }
293
294 static inline bool cpu_has_vmx_ept_execute_only(void)
295 {
296 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
297 }
298
299 static inline bool cpu_has_vmx_eptp_uncacheable(void)
300 {
301 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
302 }
303
304 static inline bool cpu_has_vmx_eptp_writeback(void)
305 {
306 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
307 }
308
309 static inline bool cpu_has_vmx_ept_2m_page(void)
310 {
311 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
312 }
313
314 static inline int cpu_has_vmx_invept_individual_addr(void)
315 {
316 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
317 }
318
319 static inline int cpu_has_vmx_invept_context(void)
320 {
321 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
322 }
323
324 static inline int cpu_has_vmx_invept_global(void)
325 {
326 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
327 }
328
329 static inline int cpu_has_vmx_ept(void)
330 {
331 return vmcs_config.cpu_based_2nd_exec_ctrl &
332 SECONDARY_EXEC_ENABLE_EPT;
333 }
334
335 static inline int cpu_has_vmx_unrestricted_guest(void)
336 {
337 return vmcs_config.cpu_based_2nd_exec_ctrl &
338 SECONDARY_EXEC_UNRESTRICTED_GUEST;
339 }
340
341 static inline int cpu_has_vmx_ple(void)
342 {
343 return vmcs_config.cpu_based_2nd_exec_ctrl &
344 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
345 }
346
347 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
348 {
349 return flexpriority_enabled &&
350 (cpu_has_vmx_virtualize_apic_accesses()) &&
351 (irqchip_in_kernel(kvm));
352 }
353
354 static inline int cpu_has_vmx_vpid(void)
355 {
356 return vmcs_config.cpu_based_2nd_exec_ctrl &
357 SECONDARY_EXEC_ENABLE_VPID;
358 }
359
360 static inline int cpu_has_virtual_nmis(void)
361 {
362 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
363 }
364
365 static inline bool report_flexpriority(void)
366 {
367 return flexpriority_enabled;
368 }
369
370 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
371 {
372 int i;
373
374 for (i = 0; i < vmx->nmsrs; ++i)
375 if (vmx->guest_msrs[i].index == msr)
376 return i;
377 return -1;
378 }
379
380 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
381 {
382 struct {
383 u64 vpid : 16;
384 u64 rsvd : 48;
385 u64 gva;
386 } operand = { vpid, 0, gva };
387
388 asm volatile (__ex(ASM_VMX_INVVPID)
389 /* CF==1 or ZF==1 --> rc = -1 */
390 "; ja 1f ; ud2 ; 1:"
391 : : "a"(&operand), "c"(ext) : "cc", "memory");
392 }
393
394 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
395 {
396 struct {
397 u64 eptp, gpa;
398 } operand = {eptp, gpa};
399
400 asm volatile (__ex(ASM_VMX_INVEPT)
401 /* CF==1 or ZF==1 --> rc = -1 */
402 "; ja 1f ; ud2 ; 1:\n"
403 : : "a" (&operand), "c" (ext) : "cc", "memory");
404 }
405
406 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
407 {
408 int i;
409
410 i = __find_msr_index(vmx, msr);
411 if (i >= 0)
412 return &vmx->guest_msrs[i];
413 return NULL;
414 }
415
416 static void vmcs_clear(struct vmcs *vmcs)
417 {
418 u64 phys_addr = __pa(vmcs);
419 u8 error;
420
421 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
422 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
423 : "cc", "memory");
424 if (error)
425 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
426 vmcs, phys_addr);
427 }
428
429 static void __vcpu_clear(void *arg)
430 {
431 struct vcpu_vmx *vmx = arg;
432 int cpu = raw_smp_processor_id();
433
434 if (vmx->vcpu.cpu == cpu)
435 vmcs_clear(vmx->vmcs);
436 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
437 per_cpu(current_vmcs, cpu) = NULL;
438 rdtscll(vmx->vcpu.arch.host_tsc);
439 list_del(&vmx->local_vcpus_link);
440 vmx->vcpu.cpu = -1;
441 vmx->launched = 0;
442 }
443
444 static void vcpu_clear(struct vcpu_vmx *vmx)
445 {
446 if (vmx->vcpu.cpu == -1)
447 return;
448 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
449 }
450
451 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
452 {
453 if (vmx->vpid == 0)
454 return;
455
456 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
457 }
458
459 static inline void ept_sync_global(void)
460 {
461 if (cpu_has_vmx_invept_global())
462 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
463 }
464
465 static inline void ept_sync_context(u64 eptp)
466 {
467 if (enable_ept) {
468 if (cpu_has_vmx_invept_context())
469 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
470 else
471 ept_sync_global();
472 }
473 }
474
475 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
476 {
477 if (enable_ept) {
478 if (cpu_has_vmx_invept_individual_addr())
479 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
480 eptp, gpa);
481 else
482 ept_sync_context(eptp);
483 }
484 }
485
486 static unsigned long vmcs_readl(unsigned long field)
487 {
488 unsigned long value;
489
490 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
491 : "=a"(value) : "d"(field) : "cc");
492 return value;
493 }
494
495 static u16 vmcs_read16(unsigned long field)
496 {
497 return vmcs_readl(field);
498 }
499
500 static u32 vmcs_read32(unsigned long field)
501 {
502 return vmcs_readl(field);
503 }
504
505 static u64 vmcs_read64(unsigned long field)
506 {
507 #ifdef CONFIG_X86_64
508 return vmcs_readl(field);
509 #else
510 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
511 #endif
512 }
513
514 static noinline void vmwrite_error(unsigned long field, unsigned long value)
515 {
516 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
517 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
518 dump_stack();
519 }
520
521 static void vmcs_writel(unsigned long field, unsigned long value)
522 {
523 u8 error;
524
525 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
526 : "=q"(error) : "a"(value), "d"(field) : "cc");
527 if (unlikely(error))
528 vmwrite_error(field, value);
529 }
530
531 static void vmcs_write16(unsigned long field, u16 value)
532 {
533 vmcs_writel(field, value);
534 }
535
536 static void vmcs_write32(unsigned long field, u32 value)
537 {
538 vmcs_writel(field, value);
539 }
540
541 static void vmcs_write64(unsigned long field, u64 value)
542 {
543 vmcs_writel(field, value);
544 #ifndef CONFIG_X86_64
545 asm volatile ("");
546 vmcs_writel(field+1, value >> 32);
547 #endif
548 }
549
550 static void vmcs_clear_bits(unsigned long field, u32 mask)
551 {
552 vmcs_writel(field, vmcs_readl(field) & ~mask);
553 }
554
555 static void vmcs_set_bits(unsigned long field, u32 mask)
556 {
557 vmcs_writel(field, vmcs_readl(field) | mask);
558 }
559
560 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
561 {
562 u32 eb;
563
564 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
565 if (!vcpu->fpu_active)
566 eb |= 1u << NM_VECTOR;
567 /*
568 * Unconditionally intercept #DB so we can maintain dr6 without
569 * reading it every exit.
570 */
571 eb |= 1u << DB_VECTOR;
572 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
573 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
574 eb |= 1u << BP_VECTOR;
575 }
576 if (to_vmx(vcpu)->rmode.vm86_active)
577 eb = ~0;
578 if (enable_ept)
579 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
580 vmcs_write32(EXCEPTION_BITMAP, eb);
581 }
582
583 static void reload_tss(void)
584 {
585 /*
586 * VT restores TR but not its size. Useless.
587 */
588 struct descriptor_table gdt;
589 struct desc_struct *descs;
590
591 kvm_get_gdt(&gdt);
592 descs = (void *)gdt.base;
593 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
594 load_TR_desc();
595 }
596
597 static void load_transition_efer(struct vcpu_vmx *vmx)
598 {
599 int efer_offset = vmx->msr_offset_efer;
600 u64 host_efer;
601 u64 guest_efer;
602 u64 ignore_bits;
603
604 if (efer_offset < 0)
605 return;
606 host_efer = vmx->host_msrs[efer_offset].data;
607 guest_efer = vmx->guest_msrs[efer_offset].data;
608
609 /*
610 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
611 * outside long mode
612 */
613 ignore_bits = EFER_NX | EFER_SCE;
614 #ifdef CONFIG_X86_64
615 ignore_bits |= EFER_LMA | EFER_LME;
616 /* SCE is meaningful only in long mode on Intel */
617 if (guest_efer & EFER_LMA)
618 ignore_bits &= ~(u64)EFER_SCE;
619 #endif
620 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
621 return;
622
623 vmx->host_state.guest_efer_loaded = 1;
624 guest_efer &= ~ignore_bits;
625 guest_efer |= host_efer & ignore_bits;
626 wrmsrl(MSR_EFER, guest_efer);
627 vmx->vcpu.stat.efer_reload++;
628 }
629
630 static void reload_host_efer(struct vcpu_vmx *vmx)
631 {
632 if (vmx->host_state.guest_efer_loaded) {
633 vmx->host_state.guest_efer_loaded = 0;
634 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
635 }
636 }
637
638 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
639 {
640 struct vcpu_vmx *vmx = to_vmx(vcpu);
641
642 if (vmx->host_state.loaded)
643 return;
644
645 vmx->host_state.loaded = 1;
646 /*
647 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
648 * allow segment selectors with cpl > 0 or ti == 1.
649 */
650 vmx->host_state.ldt_sel = kvm_read_ldt();
651 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
652 vmx->host_state.fs_sel = kvm_read_fs();
653 if (!(vmx->host_state.fs_sel & 7)) {
654 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
655 vmx->host_state.fs_reload_needed = 0;
656 } else {
657 vmcs_write16(HOST_FS_SELECTOR, 0);
658 vmx->host_state.fs_reload_needed = 1;
659 }
660 vmx->host_state.gs_sel = kvm_read_gs();
661 if (!(vmx->host_state.gs_sel & 7))
662 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
663 else {
664 vmcs_write16(HOST_GS_SELECTOR, 0);
665 vmx->host_state.gs_ldt_reload_needed = 1;
666 }
667
668 #ifdef CONFIG_X86_64
669 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
670 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
671 #else
672 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
673 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
674 #endif
675
676 #ifdef CONFIG_X86_64
677 if (is_long_mode(&vmx->vcpu))
678 save_msrs(vmx->host_msrs +
679 vmx->msr_offset_kernel_gs_base, 1);
680
681 #endif
682 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
683 load_transition_efer(vmx);
684 }
685
686 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
687 {
688 unsigned long flags;
689
690 if (!vmx->host_state.loaded)
691 return;
692
693 ++vmx->vcpu.stat.host_state_reload;
694 vmx->host_state.loaded = 0;
695 if (vmx->host_state.fs_reload_needed)
696 kvm_load_fs(vmx->host_state.fs_sel);
697 if (vmx->host_state.gs_ldt_reload_needed) {
698 kvm_load_ldt(vmx->host_state.ldt_sel);
699 /*
700 * If we have to reload gs, we must take care to
701 * preserve our gs base.
702 */
703 local_irq_save(flags);
704 kvm_load_gs(vmx->host_state.gs_sel);
705 #ifdef CONFIG_X86_64
706 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
707 #endif
708 local_irq_restore(flags);
709 }
710 reload_tss();
711 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
712 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
713 reload_host_efer(vmx);
714 }
715
716 static void vmx_load_host_state(struct vcpu_vmx *vmx)
717 {
718 preempt_disable();
719 __vmx_load_host_state(vmx);
720 preempt_enable();
721 }
722
723 /*
724 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
725 * vcpu mutex is already taken.
726 */
727 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
728 {
729 struct vcpu_vmx *vmx = to_vmx(vcpu);
730 u64 phys_addr = __pa(vmx->vmcs);
731 u64 tsc_this, delta, new_offset;
732
733 if (vcpu->cpu != cpu) {
734 vcpu_clear(vmx);
735 kvm_migrate_timers(vcpu);
736 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
737 local_irq_disable();
738 list_add(&vmx->local_vcpus_link,
739 &per_cpu(vcpus_on_cpu, cpu));
740 local_irq_enable();
741 }
742
743 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
744 u8 error;
745
746 per_cpu(current_vmcs, cpu) = vmx->vmcs;
747 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
748 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
749 : "cc");
750 if (error)
751 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
752 vmx->vmcs, phys_addr);
753 }
754
755 if (vcpu->cpu != cpu) {
756 struct descriptor_table dt;
757 unsigned long sysenter_esp;
758
759 vcpu->cpu = cpu;
760 /*
761 * Linux uses per-cpu TSS and GDT, so set these when switching
762 * processors.
763 */
764 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
765 kvm_get_gdt(&dt);
766 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
767
768 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
769 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
770
771 /*
772 * Make sure the time stamp counter is monotonous.
773 */
774 rdtscll(tsc_this);
775 if (tsc_this < vcpu->arch.host_tsc) {
776 delta = vcpu->arch.host_tsc - tsc_this;
777 new_offset = vmcs_read64(TSC_OFFSET) + delta;
778 vmcs_write64(TSC_OFFSET, new_offset);
779 }
780 }
781 }
782
783 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
784 {
785 __vmx_load_host_state(to_vmx(vcpu));
786 }
787
788 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
789 {
790 if (vcpu->fpu_active)
791 return;
792 vcpu->fpu_active = 1;
793 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
794 if (vcpu->arch.cr0 & X86_CR0_TS)
795 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
796 update_exception_bitmap(vcpu);
797 }
798
799 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
800 {
801 if (!vcpu->fpu_active)
802 return;
803 vcpu->fpu_active = 0;
804 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
805 update_exception_bitmap(vcpu);
806 }
807
808 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
809 {
810 unsigned long rflags;
811
812 rflags = vmcs_readl(GUEST_RFLAGS);
813 if (to_vmx(vcpu)->rmode.vm86_active)
814 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
815 return rflags;
816 }
817
818 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
819 {
820 if (to_vmx(vcpu)->rmode.vm86_active)
821 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
822 vmcs_writel(GUEST_RFLAGS, rflags);
823 }
824
825 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
826 {
827 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
828 int ret = 0;
829
830 if (interruptibility & GUEST_INTR_STATE_STI)
831 ret |= X86_SHADOW_INT_STI;
832 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
833 ret |= X86_SHADOW_INT_MOV_SS;
834
835 return ret & mask;
836 }
837
838 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
839 {
840 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
841 u32 interruptibility = interruptibility_old;
842
843 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
844
845 if (mask & X86_SHADOW_INT_MOV_SS)
846 interruptibility |= GUEST_INTR_STATE_MOV_SS;
847 if (mask & X86_SHADOW_INT_STI)
848 interruptibility |= GUEST_INTR_STATE_STI;
849
850 if ((interruptibility != interruptibility_old))
851 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
852 }
853
854 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
855 {
856 unsigned long rip;
857
858 rip = kvm_rip_read(vcpu);
859 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
860 kvm_rip_write(vcpu, rip);
861
862 /* skipping an emulated instruction also counts */
863 vmx_set_interrupt_shadow(vcpu, 0);
864 }
865
866 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
867 bool has_error_code, u32 error_code)
868 {
869 struct vcpu_vmx *vmx = to_vmx(vcpu);
870 u32 intr_info = nr | INTR_INFO_VALID_MASK;
871
872 if (has_error_code) {
873 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
874 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
875 }
876
877 if (vmx->rmode.vm86_active) {
878 vmx->rmode.irq.pending = true;
879 vmx->rmode.irq.vector = nr;
880 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
881 if (kvm_exception_is_soft(nr))
882 vmx->rmode.irq.rip +=
883 vmx->vcpu.arch.event_exit_inst_len;
884 intr_info |= INTR_TYPE_SOFT_INTR;
885 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
886 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
887 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
888 return;
889 }
890
891 if (kvm_exception_is_soft(nr)) {
892 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
893 vmx->vcpu.arch.event_exit_inst_len);
894 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
895 } else
896 intr_info |= INTR_TYPE_HARD_EXCEPTION;
897
898 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
899 }
900
901 /*
902 * Swap MSR entry in host/guest MSR entry array.
903 */
904 #ifdef CONFIG_X86_64
905 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
906 {
907 struct kvm_msr_entry tmp;
908
909 tmp = vmx->guest_msrs[to];
910 vmx->guest_msrs[to] = vmx->guest_msrs[from];
911 vmx->guest_msrs[from] = tmp;
912 tmp = vmx->host_msrs[to];
913 vmx->host_msrs[to] = vmx->host_msrs[from];
914 vmx->host_msrs[from] = tmp;
915 }
916 #endif
917
918 /*
919 * Set up the vmcs to automatically save and restore system
920 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
921 * mode, as fiddling with msrs is very expensive.
922 */
923 static void setup_msrs(struct vcpu_vmx *vmx)
924 {
925 int save_nmsrs;
926 unsigned long *msr_bitmap;
927
928 vmx_load_host_state(vmx);
929 save_nmsrs = 0;
930 #ifdef CONFIG_X86_64
931 if (is_long_mode(&vmx->vcpu)) {
932 int index;
933
934 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
935 if (index >= 0)
936 move_msr_up(vmx, index, save_nmsrs++);
937 index = __find_msr_index(vmx, MSR_LSTAR);
938 if (index >= 0)
939 move_msr_up(vmx, index, save_nmsrs++);
940 index = __find_msr_index(vmx, MSR_CSTAR);
941 if (index >= 0)
942 move_msr_up(vmx, index, save_nmsrs++);
943 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
944 if (index >= 0)
945 move_msr_up(vmx, index, save_nmsrs++);
946 /*
947 * MSR_K6_STAR is only needed on long mode guests, and only
948 * if efer.sce is enabled.
949 */
950 index = __find_msr_index(vmx, MSR_K6_STAR);
951 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
952 move_msr_up(vmx, index, save_nmsrs++);
953 }
954 #endif
955 vmx->save_nmsrs = save_nmsrs;
956
957 #ifdef CONFIG_X86_64
958 vmx->msr_offset_kernel_gs_base =
959 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
960 #endif
961 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
962
963 if (cpu_has_vmx_msr_bitmap()) {
964 if (is_long_mode(&vmx->vcpu))
965 msr_bitmap = vmx_msr_bitmap_longmode;
966 else
967 msr_bitmap = vmx_msr_bitmap_legacy;
968
969 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
970 }
971 }
972
973 /*
974 * reads and returns guest's timestamp counter "register"
975 * guest_tsc = host_tsc + tsc_offset -- 21.3
976 */
977 static u64 guest_read_tsc(void)
978 {
979 u64 host_tsc, tsc_offset;
980
981 rdtscll(host_tsc);
982 tsc_offset = vmcs_read64(TSC_OFFSET);
983 return host_tsc + tsc_offset;
984 }
985
986 /*
987 * writes 'guest_tsc' into guest's timestamp counter "register"
988 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
989 */
990 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
991 {
992 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
993 }
994
995 /*
996 * Reads an msr value (of 'msr_index') into 'pdata'.
997 * Returns 0 on success, non-0 otherwise.
998 * Assumes vcpu_load() was already called.
999 */
1000 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1001 {
1002 u64 data;
1003 struct kvm_msr_entry *msr;
1004
1005 if (!pdata) {
1006 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1007 return -EINVAL;
1008 }
1009
1010 switch (msr_index) {
1011 #ifdef CONFIG_X86_64
1012 case MSR_FS_BASE:
1013 data = vmcs_readl(GUEST_FS_BASE);
1014 break;
1015 case MSR_GS_BASE:
1016 data = vmcs_readl(GUEST_GS_BASE);
1017 break;
1018 case MSR_EFER:
1019 return kvm_get_msr_common(vcpu, msr_index, pdata);
1020 #endif
1021 case MSR_IA32_TSC:
1022 data = guest_read_tsc();
1023 break;
1024 case MSR_IA32_SYSENTER_CS:
1025 data = vmcs_read32(GUEST_SYSENTER_CS);
1026 break;
1027 case MSR_IA32_SYSENTER_EIP:
1028 data = vmcs_readl(GUEST_SYSENTER_EIP);
1029 break;
1030 case MSR_IA32_SYSENTER_ESP:
1031 data = vmcs_readl(GUEST_SYSENTER_ESP);
1032 break;
1033 default:
1034 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1035 if (msr) {
1036 vmx_load_host_state(to_vmx(vcpu));
1037 data = msr->data;
1038 break;
1039 }
1040 return kvm_get_msr_common(vcpu, msr_index, pdata);
1041 }
1042
1043 *pdata = data;
1044 return 0;
1045 }
1046
1047 /*
1048 * Writes msr value into into the appropriate "register".
1049 * Returns 0 on success, non-0 otherwise.
1050 * Assumes vcpu_load() was already called.
1051 */
1052 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1053 {
1054 struct vcpu_vmx *vmx = to_vmx(vcpu);
1055 struct kvm_msr_entry *msr;
1056 u64 host_tsc;
1057 int ret = 0;
1058
1059 switch (msr_index) {
1060 case MSR_EFER:
1061 vmx_load_host_state(vmx);
1062 ret = kvm_set_msr_common(vcpu, msr_index, data);
1063 break;
1064 #ifdef CONFIG_X86_64
1065 case MSR_FS_BASE:
1066 vmcs_writel(GUEST_FS_BASE, data);
1067 break;
1068 case MSR_GS_BASE:
1069 vmcs_writel(GUEST_GS_BASE, data);
1070 break;
1071 #endif
1072 case MSR_IA32_SYSENTER_CS:
1073 vmcs_write32(GUEST_SYSENTER_CS, data);
1074 break;
1075 case MSR_IA32_SYSENTER_EIP:
1076 vmcs_writel(GUEST_SYSENTER_EIP, data);
1077 break;
1078 case MSR_IA32_SYSENTER_ESP:
1079 vmcs_writel(GUEST_SYSENTER_ESP, data);
1080 break;
1081 case MSR_IA32_TSC:
1082 rdtscll(host_tsc);
1083 guest_write_tsc(data, host_tsc);
1084 break;
1085 case MSR_IA32_CR_PAT:
1086 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1087 vmcs_write64(GUEST_IA32_PAT, data);
1088 vcpu->arch.pat = data;
1089 break;
1090 }
1091 /* Otherwise falls through to kvm_set_msr_common */
1092 default:
1093 msr = find_msr_entry(vmx, msr_index);
1094 if (msr) {
1095 vmx_load_host_state(vmx);
1096 msr->data = data;
1097 break;
1098 }
1099 ret = kvm_set_msr_common(vcpu, msr_index, data);
1100 }
1101
1102 return ret;
1103 }
1104
1105 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1106 {
1107 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1108 switch (reg) {
1109 case VCPU_REGS_RSP:
1110 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1111 break;
1112 case VCPU_REGS_RIP:
1113 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1114 break;
1115 case VCPU_EXREG_PDPTR:
1116 if (enable_ept)
1117 ept_save_pdptrs(vcpu);
1118 break;
1119 default:
1120 break;
1121 }
1122 }
1123
1124 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1125 {
1126 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1127 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1128 else
1129 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1130
1131 update_exception_bitmap(vcpu);
1132 }
1133
1134 static __init int cpu_has_kvm_support(void)
1135 {
1136 return cpu_has_vmx();
1137 }
1138
1139 static __init int vmx_disabled_by_bios(void)
1140 {
1141 u64 msr;
1142
1143 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1144 return (msr & (FEATURE_CONTROL_LOCKED |
1145 FEATURE_CONTROL_VMXON_ENABLED))
1146 == FEATURE_CONTROL_LOCKED;
1147 /* locked but not enabled */
1148 }
1149
1150 static int hardware_enable(void *garbage)
1151 {
1152 int cpu = raw_smp_processor_id();
1153 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1154 u64 old;
1155
1156 if (read_cr4() & X86_CR4_VMXE)
1157 return -EBUSY;
1158
1159 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1160 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1161 if ((old & (FEATURE_CONTROL_LOCKED |
1162 FEATURE_CONTROL_VMXON_ENABLED))
1163 != (FEATURE_CONTROL_LOCKED |
1164 FEATURE_CONTROL_VMXON_ENABLED))
1165 /* enable and lock */
1166 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1167 FEATURE_CONTROL_LOCKED |
1168 FEATURE_CONTROL_VMXON_ENABLED);
1169 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1170 asm volatile (ASM_VMX_VMXON_RAX
1171 : : "a"(&phys_addr), "m"(phys_addr)
1172 : "memory", "cc");
1173
1174 ept_sync_global();
1175
1176 return 0;
1177 }
1178
1179 static void vmclear_local_vcpus(void)
1180 {
1181 int cpu = raw_smp_processor_id();
1182 struct vcpu_vmx *vmx, *n;
1183
1184 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1185 local_vcpus_link)
1186 __vcpu_clear(vmx);
1187 }
1188
1189
1190 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1191 * tricks.
1192 */
1193 static void kvm_cpu_vmxoff(void)
1194 {
1195 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1196 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1197 }
1198
1199 static void hardware_disable(void *garbage)
1200 {
1201 vmclear_local_vcpus();
1202 kvm_cpu_vmxoff();
1203 }
1204
1205 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1206 u32 msr, u32 *result)
1207 {
1208 u32 vmx_msr_low, vmx_msr_high;
1209 u32 ctl = ctl_min | ctl_opt;
1210
1211 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1212
1213 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1214 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1215
1216 /* Ensure minimum (required) set of control bits are supported. */
1217 if (ctl_min & ~ctl)
1218 return -EIO;
1219
1220 *result = ctl;
1221 return 0;
1222 }
1223
1224 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1225 {
1226 u32 vmx_msr_low, vmx_msr_high;
1227 u32 min, opt, min2, opt2;
1228 u32 _pin_based_exec_control = 0;
1229 u32 _cpu_based_exec_control = 0;
1230 u32 _cpu_based_2nd_exec_control = 0;
1231 u32 _vmexit_control = 0;
1232 u32 _vmentry_control = 0;
1233
1234 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1235 opt = PIN_BASED_VIRTUAL_NMIS;
1236 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1237 &_pin_based_exec_control) < 0)
1238 return -EIO;
1239
1240 min = CPU_BASED_HLT_EXITING |
1241 #ifdef CONFIG_X86_64
1242 CPU_BASED_CR8_LOAD_EXITING |
1243 CPU_BASED_CR8_STORE_EXITING |
1244 #endif
1245 CPU_BASED_CR3_LOAD_EXITING |
1246 CPU_BASED_CR3_STORE_EXITING |
1247 CPU_BASED_USE_IO_BITMAPS |
1248 CPU_BASED_MOV_DR_EXITING |
1249 CPU_BASED_USE_TSC_OFFSETING |
1250 CPU_BASED_INVLPG_EXITING;
1251 opt = CPU_BASED_TPR_SHADOW |
1252 CPU_BASED_USE_MSR_BITMAPS |
1253 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1254 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1255 &_cpu_based_exec_control) < 0)
1256 return -EIO;
1257 #ifdef CONFIG_X86_64
1258 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1259 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1260 ~CPU_BASED_CR8_STORE_EXITING;
1261 #endif
1262 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1263 min2 = 0;
1264 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1265 SECONDARY_EXEC_WBINVD_EXITING |
1266 SECONDARY_EXEC_ENABLE_VPID |
1267 SECONDARY_EXEC_ENABLE_EPT |
1268 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1269 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1270 if (adjust_vmx_controls(min2, opt2,
1271 MSR_IA32_VMX_PROCBASED_CTLS2,
1272 &_cpu_based_2nd_exec_control) < 0)
1273 return -EIO;
1274 }
1275 #ifndef CONFIG_X86_64
1276 if (!(_cpu_based_2nd_exec_control &
1277 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1278 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1279 #endif
1280 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1281 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1282 enabled */
1283 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1284 CPU_BASED_CR3_STORE_EXITING |
1285 CPU_BASED_INVLPG_EXITING);
1286 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1287 vmx_capability.ept, vmx_capability.vpid);
1288 }
1289
1290 min = 0;
1291 #ifdef CONFIG_X86_64
1292 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1293 #endif
1294 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1295 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1296 &_vmexit_control) < 0)
1297 return -EIO;
1298
1299 min = 0;
1300 opt = VM_ENTRY_LOAD_IA32_PAT;
1301 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1302 &_vmentry_control) < 0)
1303 return -EIO;
1304
1305 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1306
1307 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1308 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1309 return -EIO;
1310
1311 #ifdef CONFIG_X86_64
1312 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1313 if (vmx_msr_high & (1u<<16))
1314 return -EIO;
1315 #endif
1316
1317 /* Require Write-Back (WB) memory type for VMCS accesses. */
1318 if (((vmx_msr_high >> 18) & 15) != 6)
1319 return -EIO;
1320
1321 vmcs_conf->size = vmx_msr_high & 0x1fff;
1322 vmcs_conf->order = get_order(vmcs_config.size);
1323 vmcs_conf->revision_id = vmx_msr_low;
1324
1325 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1326 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1327 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1328 vmcs_conf->vmexit_ctrl = _vmexit_control;
1329 vmcs_conf->vmentry_ctrl = _vmentry_control;
1330
1331 return 0;
1332 }
1333
1334 static struct vmcs *alloc_vmcs_cpu(int cpu)
1335 {
1336 int node = cpu_to_node(cpu);
1337 struct page *pages;
1338 struct vmcs *vmcs;
1339
1340 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1341 if (!pages)
1342 return NULL;
1343 vmcs = page_address(pages);
1344 memset(vmcs, 0, vmcs_config.size);
1345 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1346 return vmcs;
1347 }
1348
1349 static struct vmcs *alloc_vmcs(void)
1350 {
1351 return alloc_vmcs_cpu(raw_smp_processor_id());
1352 }
1353
1354 static void free_vmcs(struct vmcs *vmcs)
1355 {
1356 free_pages((unsigned long)vmcs, vmcs_config.order);
1357 }
1358
1359 static void free_kvm_area(void)
1360 {
1361 int cpu;
1362
1363 for_each_possible_cpu(cpu) {
1364 free_vmcs(per_cpu(vmxarea, cpu));
1365 per_cpu(vmxarea, cpu) = NULL;
1366 }
1367 }
1368
1369 static __init int alloc_kvm_area(void)
1370 {
1371 int cpu;
1372
1373 for_each_possible_cpu(cpu) {
1374 struct vmcs *vmcs;
1375
1376 vmcs = alloc_vmcs_cpu(cpu);
1377 if (!vmcs) {
1378 free_kvm_area();
1379 return -ENOMEM;
1380 }
1381
1382 per_cpu(vmxarea, cpu) = vmcs;
1383 }
1384 return 0;
1385 }
1386
1387 static __init int hardware_setup(void)
1388 {
1389 if (setup_vmcs_config(&vmcs_config) < 0)
1390 return -EIO;
1391
1392 if (boot_cpu_has(X86_FEATURE_NX))
1393 kvm_enable_efer_bits(EFER_NX);
1394
1395 if (!cpu_has_vmx_vpid())
1396 enable_vpid = 0;
1397
1398 if (!cpu_has_vmx_ept()) {
1399 enable_ept = 0;
1400 enable_unrestricted_guest = 0;
1401 }
1402
1403 if (!cpu_has_vmx_unrestricted_guest())
1404 enable_unrestricted_guest = 0;
1405
1406 if (!cpu_has_vmx_flexpriority())
1407 flexpriority_enabled = 0;
1408
1409 if (!cpu_has_vmx_tpr_shadow())
1410 kvm_x86_ops->update_cr8_intercept = NULL;
1411
1412 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1413 kvm_disable_largepages();
1414
1415 if (!cpu_has_vmx_ple())
1416 ple_gap = 0;
1417
1418 return alloc_kvm_area();
1419 }
1420
1421 static __exit void hardware_unsetup(void)
1422 {
1423 free_kvm_area();
1424 }
1425
1426 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1427 {
1428 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1429
1430 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1431 vmcs_write16(sf->selector, save->selector);
1432 vmcs_writel(sf->base, save->base);
1433 vmcs_write32(sf->limit, save->limit);
1434 vmcs_write32(sf->ar_bytes, save->ar);
1435 } else {
1436 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1437 << AR_DPL_SHIFT;
1438 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1439 }
1440 }
1441
1442 static void enter_pmode(struct kvm_vcpu *vcpu)
1443 {
1444 unsigned long flags;
1445 struct vcpu_vmx *vmx = to_vmx(vcpu);
1446
1447 vmx->emulation_required = 1;
1448 vmx->rmode.vm86_active = 0;
1449
1450 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1451 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1452 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1453
1454 flags = vmcs_readl(GUEST_RFLAGS);
1455 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1456 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1457 vmcs_writel(GUEST_RFLAGS, flags);
1458
1459 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1460 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1461
1462 update_exception_bitmap(vcpu);
1463
1464 if (emulate_invalid_guest_state)
1465 return;
1466
1467 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1468 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1469 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1470 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1471
1472 vmcs_write16(GUEST_SS_SELECTOR, 0);
1473 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1474
1475 vmcs_write16(GUEST_CS_SELECTOR,
1476 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1477 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1478 }
1479
1480 static gva_t rmode_tss_base(struct kvm *kvm)
1481 {
1482 if (!kvm->arch.tss_addr) {
1483 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1484 kvm->memslots[0].npages - 3;
1485 return base_gfn << PAGE_SHIFT;
1486 }
1487 return kvm->arch.tss_addr;
1488 }
1489
1490 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1491 {
1492 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1493
1494 save->selector = vmcs_read16(sf->selector);
1495 save->base = vmcs_readl(sf->base);
1496 save->limit = vmcs_read32(sf->limit);
1497 save->ar = vmcs_read32(sf->ar_bytes);
1498 vmcs_write16(sf->selector, save->base >> 4);
1499 vmcs_write32(sf->base, save->base & 0xfffff);
1500 vmcs_write32(sf->limit, 0xffff);
1501 vmcs_write32(sf->ar_bytes, 0xf3);
1502 }
1503
1504 static void enter_rmode(struct kvm_vcpu *vcpu)
1505 {
1506 unsigned long flags;
1507 struct vcpu_vmx *vmx = to_vmx(vcpu);
1508
1509 if (enable_unrestricted_guest)
1510 return;
1511
1512 vmx->emulation_required = 1;
1513 vmx->rmode.vm86_active = 1;
1514
1515 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1516 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1517
1518 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1519 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1520
1521 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1522 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1523
1524 flags = vmcs_readl(GUEST_RFLAGS);
1525 vmx->rmode.save_iopl
1526 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1527
1528 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1529
1530 vmcs_writel(GUEST_RFLAGS, flags);
1531 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1532 update_exception_bitmap(vcpu);
1533
1534 if (emulate_invalid_guest_state)
1535 goto continue_rmode;
1536
1537 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1538 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1539 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1540
1541 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1542 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1543 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1544 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1545 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1546
1547 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1548 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1549 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1550 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1551
1552 continue_rmode:
1553 kvm_mmu_reset_context(vcpu);
1554 init_rmode(vcpu->kvm);
1555 }
1556
1557 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1558 {
1559 struct vcpu_vmx *vmx = to_vmx(vcpu);
1560 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1561
1562 vcpu->arch.shadow_efer = efer;
1563 if (!msr)
1564 return;
1565 if (efer & EFER_LMA) {
1566 vmcs_write32(VM_ENTRY_CONTROLS,
1567 vmcs_read32(VM_ENTRY_CONTROLS) |
1568 VM_ENTRY_IA32E_MODE);
1569 msr->data = efer;
1570 } else {
1571 vmcs_write32(VM_ENTRY_CONTROLS,
1572 vmcs_read32(VM_ENTRY_CONTROLS) &
1573 ~VM_ENTRY_IA32E_MODE);
1574
1575 msr->data = efer & ~EFER_LME;
1576 }
1577 setup_msrs(vmx);
1578 }
1579
1580 #ifdef CONFIG_X86_64
1581
1582 static void enter_lmode(struct kvm_vcpu *vcpu)
1583 {
1584 u32 guest_tr_ar;
1585
1586 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1587 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1588 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1589 __func__);
1590 vmcs_write32(GUEST_TR_AR_BYTES,
1591 (guest_tr_ar & ~AR_TYPE_MASK)
1592 | AR_TYPE_BUSY_64_TSS);
1593 }
1594 vcpu->arch.shadow_efer |= EFER_LMA;
1595 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1596 }
1597
1598 static void exit_lmode(struct kvm_vcpu *vcpu)
1599 {
1600 vcpu->arch.shadow_efer &= ~EFER_LMA;
1601
1602 vmcs_write32(VM_ENTRY_CONTROLS,
1603 vmcs_read32(VM_ENTRY_CONTROLS)
1604 & ~VM_ENTRY_IA32E_MODE);
1605 }
1606
1607 #endif
1608
1609 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1610 {
1611 vpid_sync_vcpu_all(to_vmx(vcpu));
1612 if (enable_ept)
1613 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1614 }
1615
1616 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1617 {
1618 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1619 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1620 }
1621
1622 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1623 {
1624 if (!test_bit(VCPU_EXREG_PDPTR,
1625 (unsigned long *)&vcpu->arch.regs_dirty))
1626 return;
1627
1628 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1629 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1630 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1631 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1632 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1633 }
1634 }
1635
1636 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1637 {
1638 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1639 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1640 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1641 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1642 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1643 }
1644
1645 __set_bit(VCPU_EXREG_PDPTR,
1646 (unsigned long *)&vcpu->arch.regs_avail);
1647 __set_bit(VCPU_EXREG_PDPTR,
1648 (unsigned long *)&vcpu->arch.regs_dirty);
1649 }
1650
1651 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1652
1653 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1654 unsigned long cr0,
1655 struct kvm_vcpu *vcpu)
1656 {
1657 if (!(cr0 & X86_CR0_PG)) {
1658 /* From paging/starting to nonpaging */
1659 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1660 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1661 (CPU_BASED_CR3_LOAD_EXITING |
1662 CPU_BASED_CR3_STORE_EXITING));
1663 vcpu->arch.cr0 = cr0;
1664 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1665 } else if (!is_paging(vcpu)) {
1666 /* From nonpaging to paging */
1667 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1668 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1669 ~(CPU_BASED_CR3_LOAD_EXITING |
1670 CPU_BASED_CR3_STORE_EXITING));
1671 vcpu->arch.cr0 = cr0;
1672 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1673 }
1674
1675 if (!(cr0 & X86_CR0_WP))
1676 *hw_cr0 &= ~X86_CR0_WP;
1677 }
1678
1679 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1680 struct kvm_vcpu *vcpu)
1681 {
1682 if (!is_paging(vcpu)) {
1683 *hw_cr4 &= ~X86_CR4_PAE;
1684 *hw_cr4 |= X86_CR4_PSE;
1685 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1686 *hw_cr4 &= ~X86_CR4_PAE;
1687 }
1688
1689 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1690 {
1691 struct vcpu_vmx *vmx = to_vmx(vcpu);
1692 unsigned long hw_cr0;
1693
1694 if (enable_unrestricted_guest)
1695 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1696 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1697 else
1698 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1699
1700 vmx_fpu_deactivate(vcpu);
1701
1702 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1703 enter_pmode(vcpu);
1704
1705 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1706 enter_rmode(vcpu);
1707
1708 #ifdef CONFIG_X86_64
1709 if (vcpu->arch.shadow_efer & EFER_LME) {
1710 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1711 enter_lmode(vcpu);
1712 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1713 exit_lmode(vcpu);
1714 }
1715 #endif
1716
1717 if (enable_ept)
1718 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1719
1720 vmcs_writel(CR0_READ_SHADOW, cr0);
1721 vmcs_writel(GUEST_CR0, hw_cr0);
1722 vcpu->arch.cr0 = cr0;
1723
1724 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1725 vmx_fpu_activate(vcpu);
1726 }
1727
1728 static u64 construct_eptp(unsigned long root_hpa)
1729 {
1730 u64 eptp;
1731
1732 /* TODO write the value reading from MSR */
1733 eptp = VMX_EPT_DEFAULT_MT |
1734 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1735 eptp |= (root_hpa & PAGE_MASK);
1736
1737 return eptp;
1738 }
1739
1740 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1741 {
1742 unsigned long guest_cr3;
1743 u64 eptp;
1744
1745 guest_cr3 = cr3;
1746 if (enable_ept) {
1747 eptp = construct_eptp(cr3);
1748 vmcs_write64(EPT_POINTER, eptp);
1749 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1750 vcpu->kvm->arch.ept_identity_map_addr;
1751 }
1752
1753 vmx_flush_tlb(vcpu);
1754 vmcs_writel(GUEST_CR3, guest_cr3);
1755 if (vcpu->arch.cr0 & X86_CR0_PE)
1756 vmx_fpu_deactivate(vcpu);
1757 }
1758
1759 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1760 {
1761 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1762 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1763
1764 vcpu->arch.cr4 = cr4;
1765 if (enable_ept)
1766 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1767
1768 vmcs_writel(CR4_READ_SHADOW, cr4);
1769 vmcs_writel(GUEST_CR4, hw_cr4);
1770 }
1771
1772 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1773 {
1774 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1775
1776 return vmcs_readl(sf->base);
1777 }
1778
1779 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1780 struct kvm_segment *var, int seg)
1781 {
1782 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1783 u32 ar;
1784
1785 var->base = vmcs_readl(sf->base);
1786 var->limit = vmcs_read32(sf->limit);
1787 var->selector = vmcs_read16(sf->selector);
1788 ar = vmcs_read32(sf->ar_bytes);
1789 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1790 ar = 0;
1791 var->type = ar & 15;
1792 var->s = (ar >> 4) & 1;
1793 var->dpl = (ar >> 5) & 3;
1794 var->present = (ar >> 7) & 1;
1795 var->avl = (ar >> 12) & 1;
1796 var->l = (ar >> 13) & 1;
1797 var->db = (ar >> 14) & 1;
1798 var->g = (ar >> 15) & 1;
1799 var->unusable = (ar >> 16) & 1;
1800 }
1801
1802 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1803 {
1804 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1805 return 0;
1806
1807 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1808 return 3;
1809
1810 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1811 }
1812
1813 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1814 {
1815 u32 ar;
1816
1817 if (var->unusable)
1818 ar = 1 << 16;
1819 else {
1820 ar = var->type & 15;
1821 ar |= (var->s & 1) << 4;
1822 ar |= (var->dpl & 3) << 5;
1823 ar |= (var->present & 1) << 7;
1824 ar |= (var->avl & 1) << 12;
1825 ar |= (var->l & 1) << 13;
1826 ar |= (var->db & 1) << 14;
1827 ar |= (var->g & 1) << 15;
1828 }
1829 if (ar == 0) /* a 0 value means unusable */
1830 ar = AR_UNUSABLE_MASK;
1831
1832 return ar;
1833 }
1834
1835 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1836 struct kvm_segment *var, int seg)
1837 {
1838 struct vcpu_vmx *vmx = to_vmx(vcpu);
1839 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1840 u32 ar;
1841
1842 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1843 vmx->rmode.tr.selector = var->selector;
1844 vmx->rmode.tr.base = var->base;
1845 vmx->rmode.tr.limit = var->limit;
1846 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1847 return;
1848 }
1849 vmcs_writel(sf->base, var->base);
1850 vmcs_write32(sf->limit, var->limit);
1851 vmcs_write16(sf->selector, var->selector);
1852 if (vmx->rmode.vm86_active && var->s) {
1853 /*
1854 * Hack real-mode segments into vm86 compatibility.
1855 */
1856 if (var->base == 0xffff0000 && var->selector == 0xf000)
1857 vmcs_writel(sf->base, 0xf0000);
1858 ar = 0xf3;
1859 } else
1860 ar = vmx_segment_access_rights(var);
1861
1862 /*
1863 * Fix the "Accessed" bit in AR field of segment registers for older
1864 * qemu binaries.
1865 * IA32 arch specifies that at the time of processor reset the
1866 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1867 * is setting it to 0 in the usedland code. This causes invalid guest
1868 * state vmexit when "unrestricted guest" mode is turned on.
1869 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1870 * tree. Newer qemu binaries with that qemu fix would not need this
1871 * kvm hack.
1872 */
1873 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1874 ar |= 0x1; /* Accessed */
1875
1876 vmcs_write32(sf->ar_bytes, ar);
1877 }
1878
1879 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1880 {
1881 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1882
1883 *db = (ar >> 14) & 1;
1884 *l = (ar >> 13) & 1;
1885 }
1886
1887 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1888 {
1889 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1890 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1891 }
1892
1893 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1894 {
1895 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1896 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1897 }
1898
1899 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1900 {
1901 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1902 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1903 }
1904
1905 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1906 {
1907 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1908 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1909 }
1910
1911 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1912 {
1913 struct kvm_segment var;
1914 u32 ar;
1915
1916 vmx_get_segment(vcpu, &var, seg);
1917 ar = vmx_segment_access_rights(&var);
1918
1919 if (var.base != (var.selector << 4))
1920 return false;
1921 if (var.limit != 0xffff)
1922 return false;
1923 if (ar != 0xf3)
1924 return false;
1925
1926 return true;
1927 }
1928
1929 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1930 {
1931 struct kvm_segment cs;
1932 unsigned int cs_rpl;
1933
1934 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1935 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1936
1937 if (cs.unusable)
1938 return false;
1939 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1940 return false;
1941 if (!cs.s)
1942 return false;
1943 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1944 if (cs.dpl > cs_rpl)
1945 return false;
1946 } else {
1947 if (cs.dpl != cs_rpl)
1948 return false;
1949 }
1950 if (!cs.present)
1951 return false;
1952
1953 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1954 return true;
1955 }
1956
1957 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1958 {
1959 struct kvm_segment ss;
1960 unsigned int ss_rpl;
1961
1962 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1963 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1964
1965 if (ss.unusable)
1966 return true;
1967 if (ss.type != 3 && ss.type != 7)
1968 return false;
1969 if (!ss.s)
1970 return false;
1971 if (ss.dpl != ss_rpl) /* DPL != RPL */
1972 return false;
1973 if (!ss.present)
1974 return false;
1975
1976 return true;
1977 }
1978
1979 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1980 {
1981 struct kvm_segment var;
1982 unsigned int rpl;
1983
1984 vmx_get_segment(vcpu, &var, seg);
1985 rpl = var.selector & SELECTOR_RPL_MASK;
1986
1987 if (var.unusable)
1988 return true;
1989 if (!var.s)
1990 return false;
1991 if (!var.present)
1992 return false;
1993 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1994 if (var.dpl < rpl) /* DPL < RPL */
1995 return false;
1996 }
1997
1998 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1999 * rights flags
2000 */
2001 return true;
2002 }
2003
2004 static bool tr_valid(struct kvm_vcpu *vcpu)
2005 {
2006 struct kvm_segment tr;
2007
2008 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2009
2010 if (tr.unusable)
2011 return false;
2012 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2013 return false;
2014 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2015 return false;
2016 if (!tr.present)
2017 return false;
2018
2019 return true;
2020 }
2021
2022 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2023 {
2024 struct kvm_segment ldtr;
2025
2026 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2027
2028 if (ldtr.unusable)
2029 return true;
2030 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2031 return false;
2032 if (ldtr.type != 2)
2033 return false;
2034 if (!ldtr.present)
2035 return false;
2036
2037 return true;
2038 }
2039
2040 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2041 {
2042 struct kvm_segment cs, ss;
2043
2044 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2045 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2046
2047 return ((cs.selector & SELECTOR_RPL_MASK) ==
2048 (ss.selector & SELECTOR_RPL_MASK));
2049 }
2050
2051 /*
2052 * Check if guest state is valid. Returns true if valid, false if
2053 * not.
2054 * We assume that registers are always usable
2055 */
2056 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2057 {
2058 /* real mode guest state checks */
2059 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2060 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2061 return false;
2062 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2063 return false;
2064 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2065 return false;
2066 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2067 return false;
2068 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2069 return false;
2070 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2071 return false;
2072 } else {
2073 /* protected mode guest state checks */
2074 if (!cs_ss_rpl_check(vcpu))
2075 return false;
2076 if (!code_segment_valid(vcpu))
2077 return false;
2078 if (!stack_segment_valid(vcpu))
2079 return false;
2080 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2081 return false;
2082 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2083 return false;
2084 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2085 return false;
2086 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2087 return false;
2088 if (!tr_valid(vcpu))
2089 return false;
2090 if (!ldtr_valid(vcpu))
2091 return false;
2092 }
2093 /* TODO:
2094 * - Add checks on RIP
2095 * - Add checks on RFLAGS
2096 */
2097
2098 return true;
2099 }
2100
2101 static int init_rmode_tss(struct kvm *kvm)
2102 {
2103 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2104 u16 data = 0;
2105 int ret = 0;
2106 int r;
2107
2108 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2109 if (r < 0)
2110 goto out;
2111 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2112 r = kvm_write_guest_page(kvm, fn++, &data,
2113 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2114 if (r < 0)
2115 goto out;
2116 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2117 if (r < 0)
2118 goto out;
2119 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2120 if (r < 0)
2121 goto out;
2122 data = ~0;
2123 r = kvm_write_guest_page(kvm, fn, &data,
2124 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2125 sizeof(u8));
2126 if (r < 0)
2127 goto out;
2128
2129 ret = 1;
2130 out:
2131 return ret;
2132 }
2133
2134 static int init_rmode_identity_map(struct kvm *kvm)
2135 {
2136 int i, r, ret;
2137 pfn_t identity_map_pfn;
2138 u32 tmp;
2139
2140 if (!enable_ept)
2141 return 1;
2142 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2143 printk(KERN_ERR "EPT: identity-mapping pagetable "
2144 "haven't been allocated!\n");
2145 return 0;
2146 }
2147 if (likely(kvm->arch.ept_identity_pagetable_done))
2148 return 1;
2149 ret = 0;
2150 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2151 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2152 if (r < 0)
2153 goto out;
2154 /* Set up identity-mapping pagetable for EPT in real mode */
2155 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2156 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2157 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2158 r = kvm_write_guest_page(kvm, identity_map_pfn,
2159 &tmp, i * sizeof(tmp), sizeof(tmp));
2160 if (r < 0)
2161 goto out;
2162 }
2163 kvm->arch.ept_identity_pagetable_done = true;
2164 ret = 1;
2165 out:
2166 return ret;
2167 }
2168
2169 static void seg_setup(int seg)
2170 {
2171 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2172 unsigned int ar;
2173
2174 vmcs_write16(sf->selector, 0);
2175 vmcs_writel(sf->base, 0);
2176 vmcs_write32(sf->limit, 0xffff);
2177 if (enable_unrestricted_guest) {
2178 ar = 0x93;
2179 if (seg == VCPU_SREG_CS)
2180 ar |= 0x08; /* code segment */
2181 } else
2182 ar = 0xf3;
2183
2184 vmcs_write32(sf->ar_bytes, ar);
2185 }
2186
2187 static int alloc_apic_access_page(struct kvm *kvm)
2188 {
2189 struct kvm_userspace_memory_region kvm_userspace_mem;
2190 int r = 0;
2191
2192 down_write(&kvm->slots_lock);
2193 if (kvm->arch.apic_access_page)
2194 goto out;
2195 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2196 kvm_userspace_mem.flags = 0;
2197 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2198 kvm_userspace_mem.memory_size = PAGE_SIZE;
2199 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2200 if (r)
2201 goto out;
2202
2203 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2204 out:
2205 up_write(&kvm->slots_lock);
2206 return r;
2207 }
2208
2209 static int alloc_identity_pagetable(struct kvm *kvm)
2210 {
2211 struct kvm_userspace_memory_region kvm_userspace_mem;
2212 int r = 0;
2213
2214 down_write(&kvm->slots_lock);
2215 if (kvm->arch.ept_identity_pagetable)
2216 goto out;
2217 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2218 kvm_userspace_mem.flags = 0;
2219 kvm_userspace_mem.guest_phys_addr =
2220 kvm->arch.ept_identity_map_addr;
2221 kvm_userspace_mem.memory_size = PAGE_SIZE;
2222 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2223 if (r)
2224 goto out;
2225
2226 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2227 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2228 out:
2229 up_write(&kvm->slots_lock);
2230 return r;
2231 }
2232
2233 static void allocate_vpid(struct vcpu_vmx *vmx)
2234 {
2235 int vpid;
2236
2237 vmx->vpid = 0;
2238 if (!enable_vpid)
2239 return;
2240 spin_lock(&vmx_vpid_lock);
2241 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2242 if (vpid < VMX_NR_VPIDS) {
2243 vmx->vpid = vpid;
2244 __set_bit(vpid, vmx_vpid_bitmap);
2245 }
2246 spin_unlock(&vmx_vpid_lock);
2247 }
2248
2249 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2250 {
2251 int f = sizeof(unsigned long);
2252
2253 if (!cpu_has_vmx_msr_bitmap())
2254 return;
2255
2256 /*
2257 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2258 * have the write-low and read-high bitmap offsets the wrong way round.
2259 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2260 */
2261 if (msr <= 0x1fff) {
2262 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2263 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2264 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2265 msr &= 0x1fff;
2266 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2267 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2268 }
2269 }
2270
2271 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2272 {
2273 if (!longmode_only)
2274 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2275 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2276 }
2277
2278 /*
2279 * Sets up the vmcs for emulated real mode.
2280 */
2281 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2282 {
2283 u32 host_sysenter_cs, msr_low, msr_high;
2284 u32 junk;
2285 u64 host_pat, tsc_this, tsc_base;
2286 unsigned long a;
2287 struct descriptor_table dt;
2288 int i;
2289 unsigned long kvm_vmx_return;
2290 u32 exec_control;
2291
2292 /* I/O */
2293 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2294 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2295
2296 if (cpu_has_vmx_msr_bitmap())
2297 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2298
2299 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2300
2301 /* Control */
2302 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2303 vmcs_config.pin_based_exec_ctrl);
2304
2305 exec_control = vmcs_config.cpu_based_exec_ctrl;
2306 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2307 exec_control &= ~CPU_BASED_TPR_SHADOW;
2308 #ifdef CONFIG_X86_64
2309 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2310 CPU_BASED_CR8_LOAD_EXITING;
2311 #endif
2312 }
2313 if (!enable_ept)
2314 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2315 CPU_BASED_CR3_LOAD_EXITING |
2316 CPU_BASED_INVLPG_EXITING;
2317 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2318
2319 if (cpu_has_secondary_exec_ctrls()) {
2320 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2321 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2322 exec_control &=
2323 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2324 if (vmx->vpid == 0)
2325 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2326 if (!enable_ept)
2327 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2328 if (!enable_unrestricted_guest)
2329 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2330 if (!ple_gap)
2331 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2332 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2333 }
2334
2335 if (ple_gap) {
2336 vmcs_write32(PLE_GAP, ple_gap);
2337 vmcs_write32(PLE_WINDOW, ple_window);
2338 }
2339
2340 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2341 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2342 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2343
2344 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2345 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2346 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2347
2348 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2349 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2350 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2351 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2352 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2353 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2354 #ifdef CONFIG_X86_64
2355 rdmsrl(MSR_FS_BASE, a);
2356 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2357 rdmsrl(MSR_GS_BASE, a);
2358 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2359 #else
2360 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2361 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2362 #endif
2363
2364 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2365
2366 kvm_get_idt(&dt);
2367 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2368
2369 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2370 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2371 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2372 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2373 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2374
2375 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2376 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2377 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2378 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2379 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2380 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2381
2382 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2383 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2384 host_pat = msr_low | ((u64) msr_high << 32);
2385 vmcs_write64(HOST_IA32_PAT, host_pat);
2386 }
2387 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2388 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2389 host_pat = msr_low | ((u64) msr_high << 32);
2390 /* Write the default value follow host pat */
2391 vmcs_write64(GUEST_IA32_PAT, host_pat);
2392 /* Keep arch.pat sync with GUEST_IA32_PAT */
2393 vmx->vcpu.arch.pat = host_pat;
2394 }
2395
2396 for (i = 0; i < NR_VMX_MSR; ++i) {
2397 u32 index = vmx_msr_index[i];
2398 u32 data_low, data_high;
2399 u64 data;
2400 int j = vmx->nmsrs;
2401
2402 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2403 continue;
2404 if (wrmsr_safe(index, data_low, data_high) < 0)
2405 continue;
2406 data = data_low | ((u64)data_high << 32);
2407 vmx->host_msrs[j].index = index;
2408 vmx->host_msrs[j].reserved = 0;
2409 vmx->host_msrs[j].data = data;
2410 vmx->guest_msrs[j] = vmx->host_msrs[j];
2411 ++vmx->nmsrs;
2412 }
2413
2414 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2415
2416 /* 22.2.1, 20.8.1 */
2417 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2418
2419 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2420 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2421
2422 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2423 rdtscll(tsc_this);
2424 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2425 tsc_base = tsc_this;
2426
2427 guest_write_tsc(0, tsc_base);
2428
2429 return 0;
2430 }
2431
2432 static int init_rmode(struct kvm *kvm)
2433 {
2434 if (!init_rmode_tss(kvm))
2435 return 0;
2436 if (!init_rmode_identity_map(kvm))
2437 return 0;
2438 return 1;
2439 }
2440
2441 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2442 {
2443 struct vcpu_vmx *vmx = to_vmx(vcpu);
2444 u64 msr;
2445 int ret;
2446
2447 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2448 down_read(&vcpu->kvm->slots_lock);
2449 if (!init_rmode(vmx->vcpu.kvm)) {
2450 ret = -ENOMEM;
2451 goto out;
2452 }
2453
2454 vmx->rmode.vm86_active = 0;
2455
2456 vmx->soft_vnmi_blocked = 0;
2457
2458 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2459 kvm_set_cr8(&vmx->vcpu, 0);
2460 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2461 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2462 msr |= MSR_IA32_APICBASE_BSP;
2463 kvm_set_apic_base(&vmx->vcpu, msr);
2464
2465 fx_init(&vmx->vcpu);
2466
2467 seg_setup(VCPU_SREG_CS);
2468 /*
2469 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2470 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2471 */
2472 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2473 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2474 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2475 } else {
2476 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2477 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2478 }
2479
2480 seg_setup(VCPU_SREG_DS);
2481 seg_setup(VCPU_SREG_ES);
2482 seg_setup(VCPU_SREG_FS);
2483 seg_setup(VCPU_SREG_GS);
2484 seg_setup(VCPU_SREG_SS);
2485
2486 vmcs_write16(GUEST_TR_SELECTOR, 0);
2487 vmcs_writel(GUEST_TR_BASE, 0);
2488 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2489 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2490
2491 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2492 vmcs_writel(GUEST_LDTR_BASE, 0);
2493 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2494 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2495
2496 vmcs_write32(GUEST_SYSENTER_CS, 0);
2497 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2498 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2499
2500 vmcs_writel(GUEST_RFLAGS, 0x02);
2501 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2502 kvm_rip_write(vcpu, 0xfff0);
2503 else
2504 kvm_rip_write(vcpu, 0);
2505 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2506
2507 vmcs_writel(GUEST_DR7, 0x400);
2508
2509 vmcs_writel(GUEST_GDTR_BASE, 0);
2510 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2511
2512 vmcs_writel(GUEST_IDTR_BASE, 0);
2513 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2514
2515 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2516 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2517 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2518
2519 /* Special registers */
2520 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2521
2522 setup_msrs(vmx);
2523
2524 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2525
2526 if (cpu_has_vmx_tpr_shadow()) {
2527 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2528 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2529 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2530 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2531 vmcs_write32(TPR_THRESHOLD, 0);
2532 }
2533
2534 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2535 vmcs_write64(APIC_ACCESS_ADDR,
2536 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2537
2538 if (vmx->vpid != 0)
2539 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2540
2541 vmx->vcpu.arch.cr0 = 0x60000010;
2542 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2543 vmx_set_cr4(&vmx->vcpu, 0);
2544 vmx_set_efer(&vmx->vcpu, 0);
2545 vmx_fpu_activate(&vmx->vcpu);
2546 update_exception_bitmap(&vmx->vcpu);
2547
2548 vpid_sync_vcpu_all(vmx);
2549
2550 ret = 0;
2551
2552 /* HACK: Don't enable emulation on guest boot/reset */
2553 vmx->emulation_required = 0;
2554
2555 out:
2556 up_read(&vcpu->kvm->slots_lock);
2557 return ret;
2558 }
2559
2560 static void enable_irq_window(struct kvm_vcpu *vcpu)
2561 {
2562 u32 cpu_based_vm_exec_control;
2563
2564 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2565 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2566 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2567 }
2568
2569 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2570 {
2571 u32 cpu_based_vm_exec_control;
2572
2573 if (!cpu_has_virtual_nmis()) {
2574 enable_irq_window(vcpu);
2575 return;
2576 }
2577
2578 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2579 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2580 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2581 }
2582
2583 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2584 {
2585 struct vcpu_vmx *vmx = to_vmx(vcpu);
2586 uint32_t intr;
2587 int irq = vcpu->arch.interrupt.nr;
2588
2589 trace_kvm_inj_virq(irq);
2590
2591 ++vcpu->stat.irq_injections;
2592 if (vmx->rmode.vm86_active) {
2593 vmx->rmode.irq.pending = true;
2594 vmx->rmode.irq.vector = irq;
2595 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2596 if (vcpu->arch.interrupt.soft)
2597 vmx->rmode.irq.rip +=
2598 vmx->vcpu.arch.event_exit_inst_len;
2599 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2600 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2601 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2602 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2603 return;
2604 }
2605 intr = irq | INTR_INFO_VALID_MASK;
2606 if (vcpu->arch.interrupt.soft) {
2607 intr |= INTR_TYPE_SOFT_INTR;
2608 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2609 vmx->vcpu.arch.event_exit_inst_len);
2610 } else
2611 intr |= INTR_TYPE_EXT_INTR;
2612 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2613 }
2614
2615 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2616 {
2617 struct vcpu_vmx *vmx = to_vmx(vcpu);
2618
2619 if (!cpu_has_virtual_nmis()) {
2620 /*
2621 * Tracking the NMI-blocked state in software is built upon
2622 * finding the next open IRQ window. This, in turn, depends on
2623 * well-behaving guests: They have to keep IRQs disabled at
2624 * least as long as the NMI handler runs. Otherwise we may
2625 * cause NMI nesting, maybe breaking the guest. But as this is
2626 * highly unlikely, we can live with the residual risk.
2627 */
2628 vmx->soft_vnmi_blocked = 1;
2629 vmx->vnmi_blocked_time = 0;
2630 }
2631
2632 ++vcpu->stat.nmi_injections;
2633 if (vmx->rmode.vm86_active) {
2634 vmx->rmode.irq.pending = true;
2635 vmx->rmode.irq.vector = NMI_VECTOR;
2636 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2637 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2638 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2639 INTR_INFO_VALID_MASK);
2640 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2641 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2642 return;
2643 }
2644 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2645 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2646 }
2647
2648 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2649 {
2650 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2651 return 0;
2652
2653 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2654 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2655 GUEST_INTR_STATE_NMI));
2656 }
2657
2658 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2659 {
2660 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2661 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2662 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2663 }
2664
2665 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2666 {
2667 int ret;
2668 struct kvm_userspace_memory_region tss_mem = {
2669 .slot = TSS_PRIVATE_MEMSLOT,
2670 .guest_phys_addr = addr,
2671 .memory_size = PAGE_SIZE * 3,
2672 .flags = 0,
2673 };
2674
2675 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2676 if (ret)
2677 return ret;
2678 kvm->arch.tss_addr = addr;
2679 return 0;
2680 }
2681
2682 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2683 int vec, u32 err_code)
2684 {
2685 /*
2686 * Instruction with address size override prefix opcode 0x67
2687 * Cause the #SS fault with 0 error code in VM86 mode.
2688 */
2689 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2690 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2691 return 1;
2692 /*
2693 * Forward all other exceptions that are valid in real mode.
2694 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2695 * the required debugging infrastructure rework.
2696 */
2697 switch (vec) {
2698 case DB_VECTOR:
2699 if (vcpu->guest_debug &
2700 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2701 return 0;
2702 kvm_queue_exception(vcpu, vec);
2703 return 1;
2704 case BP_VECTOR:
2705 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2706 return 0;
2707 /* fall through */
2708 case DE_VECTOR:
2709 case OF_VECTOR:
2710 case BR_VECTOR:
2711 case UD_VECTOR:
2712 case DF_VECTOR:
2713 case SS_VECTOR:
2714 case GP_VECTOR:
2715 case MF_VECTOR:
2716 kvm_queue_exception(vcpu, vec);
2717 return 1;
2718 }
2719 return 0;
2720 }
2721
2722 /*
2723 * Trigger machine check on the host. We assume all the MSRs are already set up
2724 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2725 * We pass a fake environment to the machine check handler because we want
2726 * the guest to be always treated like user space, no matter what context
2727 * it used internally.
2728 */
2729 static void kvm_machine_check(void)
2730 {
2731 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2732 struct pt_regs regs = {
2733 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2734 .flags = X86_EFLAGS_IF,
2735 };
2736
2737 do_machine_check(&regs, 0);
2738 #endif
2739 }
2740
2741 static int handle_machine_check(struct kvm_vcpu *vcpu)
2742 {
2743 /* already handled by vcpu_run */
2744 return 1;
2745 }
2746
2747 static int handle_exception(struct kvm_vcpu *vcpu)
2748 {
2749 struct vcpu_vmx *vmx = to_vmx(vcpu);
2750 struct kvm_run *kvm_run = vcpu->run;
2751 u32 intr_info, ex_no, error_code;
2752 unsigned long cr2, rip, dr6;
2753 u32 vect_info;
2754 enum emulation_result er;
2755
2756 vect_info = vmx->idt_vectoring_info;
2757 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2758
2759 if (is_machine_check(intr_info))
2760 return handle_machine_check(vcpu);
2761
2762 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2763 !is_page_fault(intr_info))
2764 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2765 "intr info 0x%x\n", __func__, vect_info, intr_info);
2766
2767 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2768 return 1; /* already handled by vmx_vcpu_run() */
2769
2770 if (is_no_device(intr_info)) {
2771 vmx_fpu_activate(vcpu);
2772 return 1;
2773 }
2774
2775 if (is_invalid_opcode(intr_info)) {
2776 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2777 if (er != EMULATE_DONE)
2778 kvm_queue_exception(vcpu, UD_VECTOR);
2779 return 1;
2780 }
2781
2782 error_code = 0;
2783 rip = kvm_rip_read(vcpu);
2784 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2785 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2786 if (is_page_fault(intr_info)) {
2787 /* EPT won't cause page fault directly */
2788 if (enable_ept)
2789 BUG();
2790 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2791 trace_kvm_page_fault(cr2, error_code);
2792
2793 if (kvm_event_needs_reinjection(vcpu))
2794 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2795 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2796 }
2797
2798 if (vmx->rmode.vm86_active &&
2799 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2800 error_code)) {
2801 if (vcpu->arch.halt_request) {
2802 vcpu->arch.halt_request = 0;
2803 return kvm_emulate_halt(vcpu);
2804 }
2805 return 1;
2806 }
2807
2808 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2809 switch (ex_no) {
2810 case DB_VECTOR:
2811 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2812 if (!(vcpu->guest_debug &
2813 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2814 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2815 kvm_queue_exception(vcpu, DB_VECTOR);
2816 return 1;
2817 }
2818 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2819 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2820 /* fall through */
2821 case BP_VECTOR:
2822 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2823 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2824 kvm_run->debug.arch.exception = ex_no;
2825 break;
2826 default:
2827 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2828 kvm_run->ex.exception = ex_no;
2829 kvm_run->ex.error_code = error_code;
2830 break;
2831 }
2832 return 0;
2833 }
2834
2835 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2836 {
2837 ++vcpu->stat.irq_exits;
2838 return 1;
2839 }
2840
2841 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2842 {
2843 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2844 return 0;
2845 }
2846
2847 static int handle_io(struct kvm_vcpu *vcpu)
2848 {
2849 unsigned long exit_qualification;
2850 int size, in, string;
2851 unsigned port;
2852
2853 ++vcpu->stat.io_exits;
2854 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2855 string = (exit_qualification & 16) != 0;
2856
2857 if (string) {
2858 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2859 return 0;
2860 return 1;
2861 }
2862
2863 size = (exit_qualification & 7) + 1;
2864 in = (exit_qualification & 8) != 0;
2865 port = exit_qualification >> 16;
2866
2867 skip_emulated_instruction(vcpu);
2868 return kvm_emulate_pio(vcpu, in, size, port);
2869 }
2870
2871 static void
2872 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2873 {
2874 /*
2875 * Patch in the VMCALL instruction:
2876 */
2877 hypercall[0] = 0x0f;
2878 hypercall[1] = 0x01;
2879 hypercall[2] = 0xc1;
2880 }
2881
2882 static int handle_cr(struct kvm_vcpu *vcpu)
2883 {
2884 unsigned long exit_qualification, val;
2885 int cr;
2886 int reg;
2887
2888 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2889 cr = exit_qualification & 15;
2890 reg = (exit_qualification >> 8) & 15;
2891 switch ((exit_qualification >> 4) & 3) {
2892 case 0: /* mov to cr */
2893 val = kvm_register_read(vcpu, reg);
2894 trace_kvm_cr_write(cr, val);
2895 switch (cr) {
2896 case 0:
2897 kvm_set_cr0(vcpu, val);
2898 skip_emulated_instruction(vcpu);
2899 return 1;
2900 case 3:
2901 kvm_set_cr3(vcpu, val);
2902 skip_emulated_instruction(vcpu);
2903 return 1;
2904 case 4:
2905 kvm_set_cr4(vcpu, val);
2906 skip_emulated_instruction(vcpu);
2907 return 1;
2908 case 8: {
2909 u8 cr8_prev = kvm_get_cr8(vcpu);
2910 u8 cr8 = kvm_register_read(vcpu, reg);
2911 kvm_set_cr8(vcpu, cr8);
2912 skip_emulated_instruction(vcpu);
2913 if (irqchip_in_kernel(vcpu->kvm))
2914 return 1;
2915 if (cr8_prev <= cr8)
2916 return 1;
2917 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2918 return 0;
2919 }
2920 };
2921 break;
2922 case 2: /* clts */
2923 vmx_fpu_deactivate(vcpu);
2924 vcpu->arch.cr0 &= ~X86_CR0_TS;
2925 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2926 vmx_fpu_activate(vcpu);
2927 skip_emulated_instruction(vcpu);
2928 return 1;
2929 case 1: /*mov from cr*/
2930 switch (cr) {
2931 case 3:
2932 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2933 trace_kvm_cr_read(cr, vcpu->arch.cr3);
2934 skip_emulated_instruction(vcpu);
2935 return 1;
2936 case 8:
2937 val = kvm_get_cr8(vcpu);
2938 kvm_register_write(vcpu, reg, val);
2939 trace_kvm_cr_read(cr, val);
2940 skip_emulated_instruction(vcpu);
2941 return 1;
2942 }
2943 break;
2944 case 3: /* lmsw */
2945 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2946
2947 skip_emulated_instruction(vcpu);
2948 return 1;
2949 default:
2950 break;
2951 }
2952 vcpu->run->exit_reason = 0;
2953 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2954 (int)(exit_qualification >> 4) & 3, cr);
2955 return 0;
2956 }
2957
2958 static int handle_dr(struct kvm_vcpu *vcpu)
2959 {
2960 unsigned long exit_qualification;
2961 unsigned long val;
2962 int dr, reg;
2963
2964 if (!kvm_require_cpl(vcpu, 0))
2965 return 1;
2966 dr = vmcs_readl(GUEST_DR7);
2967 if (dr & DR7_GD) {
2968 /*
2969 * As the vm-exit takes precedence over the debug trap, we
2970 * need to emulate the latter, either for the host or the
2971 * guest debugging itself.
2972 */
2973 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2974 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
2975 vcpu->run->debug.arch.dr7 = dr;
2976 vcpu->run->debug.arch.pc =
2977 vmcs_readl(GUEST_CS_BASE) +
2978 vmcs_readl(GUEST_RIP);
2979 vcpu->run->debug.arch.exception = DB_VECTOR;
2980 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
2981 return 0;
2982 } else {
2983 vcpu->arch.dr7 &= ~DR7_GD;
2984 vcpu->arch.dr6 |= DR6_BD;
2985 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2986 kvm_queue_exception(vcpu, DB_VECTOR);
2987 return 1;
2988 }
2989 }
2990
2991 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2992 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2993 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2994 if (exit_qualification & TYPE_MOV_FROM_DR) {
2995 switch (dr) {
2996 case 0 ... 3:
2997 val = vcpu->arch.db[dr];
2998 break;
2999 case 6:
3000 val = vcpu->arch.dr6;
3001 break;
3002 case 7:
3003 val = vcpu->arch.dr7;
3004 break;
3005 default:
3006 val = 0;
3007 }
3008 kvm_register_write(vcpu, reg, val);
3009 } else {
3010 val = vcpu->arch.regs[reg];
3011 switch (dr) {
3012 case 0 ... 3:
3013 vcpu->arch.db[dr] = val;
3014 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3015 vcpu->arch.eff_db[dr] = val;
3016 break;
3017 case 4 ... 5:
3018 if (vcpu->arch.cr4 & X86_CR4_DE)
3019 kvm_queue_exception(vcpu, UD_VECTOR);
3020 break;
3021 case 6:
3022 if (val & 0xffffffff00000000ULL) {
3023 kvm_queue_exception(vcpu, GP_VECTOR);
3024 break;
3025 }
3026 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3027 break;
3028 case 7:
3029 if (val & 0xffffffff00000000ULL) {
3030 kvm_queue_exception(vcpu, GP_VECTOR);
3031 break;
3032 }
3033 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3034 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3035 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3036 vcpu->arch.switch_db_regs =
3037 (val & DR7_BP_EN_MASK);
3038 }
3039 break;
3040 }
3041 }
3042 skip_emulated_instruction(vcpu);
3043 return 1;
3044 }
3045
3046 static int handle_cpuid(struct kvm_vcpu *vcpu)
3047 {
3048 kvm_emulate_cpuid(vcpu);
3049 return 1;
3050 }
3051
3052 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3053 {
3054 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3055 u64 data;
3056
3057 if (vmx_get_msr(vcpu, ecx, &data)) {
3058 kvm_inject_gp(vcpu, 0);
3059 return 1;
3060 }
3061
3062 trace_kvm_msr_read(ecx, data);
3063
3064 /* FIXME: handling of bits 32:63 of rax, rdx */
3065 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3066 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3067 skip_emulated_instruction(vcpu);
3068 return 1;
3069 }
3070
3071 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3072 {
3073 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3074 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3075 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3076
3077 trace_kvm_msr_write(ecx, data);
3078
3079 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3080 kvm_inject_gp(vcpu, 0);
3081 return 1;
3082 }
3083
3084 skip_emulated_instruction(vcpu);
3085 return 1;
3086 }
3087
3088 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3089 {
3090 return 1;
3091 }
3092
3093 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3094 {
3095 u32 cpu_based_vm_exec_control;
3096
3097 /* clear pending irq */
3098 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3099 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3100 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3101
3102 ++vcpu->stat.irq_window_exits;
3103
3104 /*
3105 * If the user space waits to inject interrupts, exit as soon as
3106 * possible
3107 */
3108 if (!irqchip_in_kernel(vcpu->kvm) &&
3109 vcpu->run->request_interrupt_window &&
3110 !kvm_cpu_has_interrupt(vcpu)) {
3111 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3112 return 0;
3113 }
3114 return 1;
3115 }
3116
3117 static int handle_halt(struct kvm_vcpu *vcpu)
3118 {
3119 skip_emulated_instruction(vcpu);
3120 return kvm_emulate_halt(vcpu);
3121 }
3122
3123 static int handle_vmcall(struct kvm_vcpu *vcpu)
3124 {
3125 skip_emulated_instruction(vcpu);
3126 kvm_emulate_hypercall(vcpu);
3127 return 1;
3128 }
3129
3130 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3131 {
3132 kvm_queue_exception(vcpu, UD_VECTOR);
3133 return 1;
3134 }
3135
3136 static int handle_invlpg(struct kvm_vcpu *vcpu)
3137 {
3138 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3139
3140 kvm_mmu_invlpg(vcpu, exit_qualification);
3141 skip_emulated_instruction(vcpu);
3142 return 1;
3143 }
3144
3145 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3146 {
3147 skip_emulated_instruction(vcpu);
3148 /* TODO: Add support for VT-d/pass-through device */
3149 return 1;
3150 }
3151
3152 static int handle_apic_access(struct kvm_vcpu *vcpu)
3153 {
3154 unsigned long exit_qualification;
3155 enum emulation_result er;
3156 unsigned long offset;
3157
3158 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3159 offset = exit_qualification & 0xffful;
3160
3161 er = emulate_instruction(vcpu, 0, 0, 0);
3162
3163 if (er != EMULATE_DONE) {
3164 printk(KERN_ERR
3165 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3166 offset);
3167 return -ENOEXEC;
3168 }
3169 return 1;
3170 }
3171
3172 static int handle_task_switch(struct kvm_vcpu *vcpu)
3173 {
3174 struct vcpu_vmx *vmx = to_vmx(vcpu);
3175 unsigned long exit_qualification;
3176 u16 tss_selector;
3177 int reason, type, idt_v;
3178
3179 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3180 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3181
3182 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3183
3184 reason = (u32)exit_qualification >> 30;
3185 if (reason == TASK_SWITCH_GATE && idt_v) {
3186 switch (type) {
3187 case INTR_TYPE_NMI_INTR:
3188 vcpu->arch.nmi_injected = false;
3189 if (cpu_has_virtual_nmis())
3190 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3191 GUEST_INTR_STATE_NMI);
3192 break;
3193 case INTR_TYPE_EXT_INTR:
3194 case INTR_TYPE_SOFT_INTR:
3195 kvm_clear_interrupt_queue(vcpu);
3196 break;
3197 case INTR_TYPE_HARD_EXCEPTION:
3198 case INTR_TYPE_SOFT_EXCEPTION:
3199 kvm_clear_exception_queue(vcpu);
3200 break;
3201 default:
3202 break;
3203 }
3204 }
3205 tss_selector = exit_qualification;
3206
3207 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3208 type != INTR_TYPE_EXT_INTR &&
3209 type != INTR_TYPE_NMI_INTR))
3210 skip_emulated_instruction(vcpu);
3211
3212 if (!kvm_task_switch(vcpu, tss_selector, reason))
3213 return 0;
3214
3215 /* clear all local breakpoint enable flags */
3216 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3217
3218 /*
3219 * TODO: What about debug traps on tss switch?
3220 * Are we supposed to inject them and update dr6?
3221 */
3222
3223 return 1;
3224 }
3225
3226 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3227 {
3228 unsigned long exit_qualification;
3229 gpa_t gpa;
3230 int gla_validity;
3231
3232 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3233
3234 if (exit_qualification & (1 << 6)) {
3235 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3236 return -EINVAL;
3237 }
3238
3239 gla_validity = (exit_qualification >> 7) & 0x3;
3240 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3241 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3242 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3243 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3244 vmcs_readl(GUEST_LINEAR_ADDRESS));
3245 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3246 (long unsigned int)exit_qualification);
3247 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3248 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3249 return 0;
3250 }
3251
3252 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3253 trace_kvm_page_fault(gpa, exit_qualification);
3254 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3255 }
3256
3257 static u64 ept_rsvd_mask(u64 spte, int level)
3258 {
3259 int i;
3260 u64 mask = 0;
3261
3262 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3263 mask |= (1ULL << i);
3264
3265 if (level > 2)
3266 /* bits 7:3 reserved */
3267 mask |= 0xf8;
3268 else if (level == 2) {
3269 if (spte & (1ULL << 7))
3270 /* 2MB ref, bits 20:12 reserved */
3271 mask |= 0x1ff000;
3272 else
3273 /* bits 6:3 reserved */
3274 mask |= 0x78;
3275 }
3276
3277 return mask;
3278 }
3279
3280 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3281 int level)
3282 {
3283 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3284
3285 /* 010b (write-only) */
3286 WARN_ON((spte & 0x7) == 0x2);
3287
3288 /* 110b (write/execute) */
3289 WARN_ON((spte & 0x7) == 0x6);
3290
3291 /* 100b (execute-only) and value not supported by logical processor */
3292 if (!cpu_has_vmx_ept_execute_only())
3293 WARN_ON((spte & 0x7) == 0x4);
3294
3295 /* not 000b */
3296 if ((spte & 0x7)) {
3297 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3298
3299 if (rsvd_bits != 0) {
3300 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3301 __func__, rsvd_bits);
3302 WARN_ON(1);
3303 }
3304
3305 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3306 u64 ept_mem_type = (spte & 0x38) >> 3;
3307
3308 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3309 ept_mem_type == 7) {
3310 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3311 __func__, ept_mem_type);
3312 WARN_ON(1);
3313 }
3314 }
3315 }
3316 }
3317
3318 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3319 {
3320 u64 sptes[4];
3321 int nr_sptes, i;
3322 gpa_t gpa;
3323
3324 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3325
3326 printk(KERN_ERR "EPT: Misconfiguration.\n");
3327 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3328
3329 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3330
3331 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3332 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3333
3334 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3335 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3336
3337 return 0;
3338 }
3339
3340 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3341 {
3342 u32 cpu_based_vm_exec_control;
3343
3344 /* clear pending NMI */
3345 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3346 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3347 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3348 ++vcpu->stat.nmi_window_exits;
3349
3350 return 1;
3351 }
3352
3353 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3354 {
3355 struct vcpu_vmx *vmx = to_vmx(vcpu);
3356 enum emulation_result err = EMULATE_DONE;
3357 int ret = 1;
3358
3359 while (!guest_state_valid(vcpu)) {
3360 err = emulate_instruction(vcpu, 0, 0, 0);
3361
3362 if (err == EMULATE_DO_MMIO) {
3363 ret = 0;
3364 goto out;
3365 }
3366
3367 if (err != EMULATE_DONE) {
3368 kvm_report_emulation_failure(vcpu, "emulation failure");
3369 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3370 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3371 ret = 0;
3372 goto out;
3373 }
3374
3375 if (signal_pending(current))
3376 goto out;
3377 if (need_resched())
3378 schedule();
3379 }
3380
3381 vmx->emulation_required = 0;
3382 out:
3383 return ret;
3384 }
3385
3386 /*
3387 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3388 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3389 */
3390 static int handle_pause(struct kvm_vcpu *vcpu)
3391 {
3392 skip_emulated_instruction(vcpu);
3393 kvm_vcpu_on_spin(vcpu);
3394
3395 return 1;
3396 }
3397
3398 /*
3399 * The exit handlers return 1 if the exit was handled fully and guest execution
3400 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3401 * to be done to userspace and return 0.
3402 */
3403 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3404 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3405 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3406 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3407 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3408 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3409 [EXIT_REASON_CR_ACCESS] = handle_cr,
3410 [EXIT_REASON_DR_ACCESS] = handle_dr,
3411 [EXIT_REASON_CPUID] = handle_cpuid,
3412 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3413 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3414 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3415 [EXIT_REASON_HLT] = handle_halt,
3416 [EXIT_REASON_INVLPG] = handle_invlpg,
3417 [EXIT_REASON_VMCALL] = handle_vmcall,
3418 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3419 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3420 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3421 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3422 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3423 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3424 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3425 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3426 [EXIT_REASON_VMON] = handle_vmx_insn,
3427 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3428 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3429 [EXIT_REASON_WBINVD] = handle_wbinvd,
3430 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3431 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3432 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3433 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3434 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3435 };
3436
3437 static const int kvm_vmx_max_exit_handlers =
3438 ARRAY_SIZE(kvm_vmx_exit_handlers);
3439
3440 /*
3441 * The guest has exited. See if we can fix it or if we need userspace
3442 * assistance.
3443 */
3444 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3445 {
3446 struct vcpu_vmx *vmx = to_vmx(vcpu);
3447 u32 exit_reason = vmx->exit_reason;
3448 u32 vectoring_info = vmx->idt_vectoring_info;
3449
3450 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3451
3452 /* If guest state is invalid, start emulating */
3453 if (vmx->emulation_required && emulate_invalid_guest_state)
3454 return handle_invalid_guest_state(vcpu);
3455
3456 /* Access CR3 don't cause VMExit in paging mode, so we need
3457 * to sync with guest real CR3. */
3458 if (enable_ept && is_paging(vcpu))
3459 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3460
3461 if (unlikely(vmx->fail)) {
3462 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3463 vcpu->run->fail_entry.hardware_entry_failure_reason
3464 = vmcs_read32(VM_INSTRUCTION_ERROR);
3465 return 0;
3466 }
3467
3468 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3469 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3470 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3471 exit_reason != EXIT_REASON_TASK_SWITCH))
3472 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3473 "(0x%x) and exit reason is 0x%x\n",
3474 __func__, vectoring_info, exit_reason);
3475
3476 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3477 if (vmx_interrupt_allowed(vcpu)) {
3478 vmx->soft_vnmi_blocked = 0;
3479 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3480 vcpu->arch.nmi_pending) {
3481 /*
3482 * This CPU don't support us in finding the end of an
3483 * NMI-blocked window if the guest runs with IRQs
3484 * disabled. So we pull the trigger after 1 s of
3485 * futile waiting, but inform the user about this.
3486 */
3487 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3488 "state on VCPU %d after 1 s timeout\n",
3489 __func__, vcpu->vcpu_id);
3490 vmx->soft_vnmi_blocked = 0;
3491 }
3492 }
3493
3494 if (exit_reason < kvm_vmx_max_exit_handlers
3495 && kvm_vmx_exit_handlers[exit_reason])
3496 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3497 else {
3498 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3499 vcpu->run->hw.hardware_exit_reason = exit_reason;
3500 }
3501 return 0;
3502 }
3503
3504 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3505 {
3506 if (irr == -1 || tpr < irr) {
3507 vmcs_write32(TPR_THRESHOLD, 0);
3508 return;
3509 }
3510
3511 vmcs_write32(TPR_THRESHOLD, irr);
3512 }
3513
3514 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3515 {
3516 u32 exit_intr_info;
3517 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3518 bool unblock_nmi;
3519 u8 vector;
3520 int type;
3521 bool idtv_info_valid;
3522
3523 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3524
3525 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3526
3527 /* Handle machine checks before interrupts are enabled */
3528 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3529 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3530 && is_machine_check(exit_intr_info)))
3531 kvm_machine_check();
3532
3533 /* We need to handle NMIs before interrupts are enabled */
3534 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3535 (exit_intr_info & INTR_INFO_VALID_MASK))
3536 asm("int $2");
3537
3538 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3539
3540 if (cpu_has_virtual_nmis()) {
3541 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3542 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3543 /*
3544 * SDM 3: 27.7.1.2 (September 2008)
3545 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3546 * a guest IRET fault.
3547 * SDM 3: 23.2.2 (September 2008)
3548 * Bit 12 is undefined in any of the following cases:
3549 * If the VM exit sets the valid bit in the IDT-vectoring
3550 * information field.
3551 * If the VM exit is due to a double fault.
3552 */
3553 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3554 vector != DF_VECTOR && !idtv_info_valid)
3555 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3556 GUEST_INTR_STATE_NMI);
3557 } else if (unlikely(vmx->soft_vnmi_blocked))
3558 vmx->vnmi_blocked_time +=
3559 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3560
3561 vmx->vcpu.arch.nmi_injected = false;
3562 kvm_clear_exception_queue(&vmx->vcpu);
3563 kvm_clear_interrupt_queue(&vmx->vcpu);
3564
3565 if (!idtv_info_valid)
3566 return;
3567
3568 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3569 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3570
3571 switch (type) {
3572 case INTR_TYPE_NMI_INTR:
3573 vmx->vcpu.arch.nmi_injected = true;
3574 /*
3575 * SDM 3: 27.7.1.2 (September 2008)
3576 * Clear bit "block by NMI" before VM entry if a NMI
3577 * delivery faulted.
3578 */
3579 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3580 GUEST_INTR_STATE_NMI);
3581 break;
3582 case INTR_TYPE_SOFT_EXCEPTION:
3583 vmx->vcpu.arch.event_exit_inst_len =
3584 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3585 /* fall through */
3586 case INTR_TYPE_HARD_EXCEPTION:
3587 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3588 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3589 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3590 } else
3591 kvm_queue_exception(&vmx->vcpu, vector);
3592 break;
3593 case INTR_TYPE_SOFT_INTR:
3594 vmx->vcpu.arch.event_exit_inst_len =
3595 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3596 /* fall through */
3597 case INTR_TYPE_EXT_INTR:
3598 kvm_queue_interrupt(&vmx->vcpu, vector,
3599 type == INTR_TYPE_SOFT_INTR);
3600 break;
3601 default:
3602 break;
3603 }
3604 }
3605
3606 /*
3607 * Failure to inject an interrupt should give us the information
3608 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3609 * when fetching the interrupt redirection bitmap in the real-mode
3610 * tss, this doesn't happen. So we do it ourselves.
3611 */
3612 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3613 {
3614 vmx->rmode.irq.pending = 0;
3615 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3616 return;
3617 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3618 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3619 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3620 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3621 return;
3622 }
3623 vmx->idt_vectoring_info =
3624 VECTORING_INFO_VALID_MASK
3625 | INTR_TYPE_EXT_INTR
3626 | vmx->rmode.irq.vector;
3627 }
3628
3629 #ifdef CONFIG_X86_64
3630 #define R "r"
3631 #define Q "q"
3632 #else
3633 #define R "e"
3634 #define Q "l"
3635 #endif
3636
3637 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3638 {
3639 struct vcpu_vmx *vmx = to_vmx(vcpu);
3640
3641 if (enable_ept && is_paging(vcpu)) {
3642 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3643 ept_load_pdptrs(vcpu);
3644 }
3645 /* Record the guest's net vcpu time for enforced NMI injections. */
3646 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3647 vmx->entry_time = ktime_get();
3648
3649 /* Don't enter VMX if guest state is invalid, let the exit handler
3650 start emulation until we arrive back to a valid state */
3651 if (vmx->emulation_required && emulate_invalid_guest_state)
3652 return;
3653
3654 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3655 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3656 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3657 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3658
3659 /* When single-stepping over STI and MOV SS, we must clear the
3660 * corresponding interruptibility bits in the guest state. Otherwise
3661 * vmentry fails as it then expects bit 14 (BS) in pending debug
3662 * exceptions being set, but that's not correct for the guest debugging
3663 * case. */
3664 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3665 vmx_set_interrupt_shadow(vcpu, 0);
3666
3667 /*
3668 * Loading guest fpu may have cleared host cr0.ts
3669 */
3670 vmcs_writel(HOST_CR0, read_cr0());
3671
3672 if (vcpu->arch.switch_db_regs)
3673 set_debugreg(vcpu->arch.dr6, 6);
3674
3675 asm(
3676 /* Store host registers */
3677 "push %%"R"dx; push %%"R"bp;"
3678 "push %%"R"cx \n\t"
3679 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3680 "je 1f \n\t"
3681 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3682 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3683 "1: \n\t"
3684 /* Reload cr2 if changed */
3685 "mov %c[cr2](%0), %%"R"ax \n\t"
3686 "mov %%cr2, %%"R"dx \n\t"
3687 "cmp %%"R"ax, %%"R"dx \n\t"
3688 "je 2f \n\t"
3689 "mov %%"R"ax, %%cr2 \n\t"
3690 "2: \n\t"
3691 /* Check if vmlaunch of vmresume is needed */
3692 "cmpl $0, %c[launched](%0) \n\t"
3693 /* Load guest registers. Don't clobber flags. */
3694 "mov %c[rax](%0), %%"R"ax \n\t"
3695 "mov %c[rbx](%0), %%"R"bx \n\t"
3696 "mov %c[rdx](%0), %%"R"dx \n\t"
3697 "mov %c[rsi](%0), %%"R"si \n\t"
3698 "mov %c[rdi](%0), %%"R"di \n\t"
3699 "mov %c[rbp](%0), %%"R"bp \n\t"
3700 #ifdef CONFIG_X86_64
3701 "mov %c[r8](%0), %%r8 \n\t"
3702 "mov %c[r9](%0), %%r9 \n\t"
3703 "mov %c[r10](%0), %%r10 \n\t"
3704 "mov %c[r11](%0), %%r11 \n\t"
3705 "mov %c[r12](%0), %%r12 \n\t"
3706 "mov %c[r13](%0), %%r13 \n\t"
3707 "mov %c[r14](%0), %%r14 \n\t"
3708 "mov %c[r15](%0), %%r15 \n\t"
3709 #endif
3710 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3711
3712 /* Enter guest mode */
3713 "jne .Llaunched \n\t"
3714 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3715 "jmp .Lkvm_vmx_return \n\t"
3716 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3717 ".Lkvm_vmx_return: "
3718 /* Save guest registers, load host registers, keep flags */
3719 "xchg %0, (%%"R"sp) \n\t"
3720 "mov %%"R"ax, %c[rax](%0) \n\t"
3721 "mov %%"R"bx, %c[rbx](%0) \n\t"
3722 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3723 "mov %%"R"dx, %c[rdx](%0) \n\t"
3724 "mov %%"R"si, %c[rsi](%0) \n\t"
3725 "mov %%"R"di, %c[rdi](%0) \n\t"
3726 "mov %%"R"bp, %c[rbp](%0) \n\t"
3727 #ifdef CONFIG_X86_64
3728 "mov %%r8, %c[r8](%0) \n\t"
3729 "mov %%r9, %c[r9](%0) \n\t"
3730 "mov %%r10, %c[r10](%0) \n\t"
3731 "mov %%r11, %c[r11](%0) \n\t"
3732 "mov %%r12, %c[r12](%0) \n\t"
3733 "mov %%r13, %c[r13](%0) \n\t"
3734 "mov %%r14, %c[r14](%0) \n\t"
3735 "mov %%r15, %c[r15](%0) \n\t"
3736 #endif
3737 "mov %%cr2, %%"R"ax \n\t"
3738 "mov %%"R"ax, %c[cr2](%0) \n\t"
3739
3740 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3741 "setbe %c[fail](%0) \n\t"
3742 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3743 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3744 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3745 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3746 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3747 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3748 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3749 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3750 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3751 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3752 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3753 #ifdef CONFIG_X86_64
3754 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3755 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3756 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3757 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3758 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3759 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3760 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3761 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3762 #endif
3763 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3764 : "cc", "memory"
3765 , R"bx", R"di", R"si"
3766 #ifdef CONFIG_X86_64
3767 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3768 #endif
3769 );
3770
3771 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3772 | (1 << VCPU_EXREG_PDPTR));
3773 vcpu->arch.regs_dirty = 0;
3774
3775 if (vcpu->arch.switch_db_regs)
3776 get_debugreg(vcpu->arch.dr6, 6);
3777
3778 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3779 if (vmx->rmode.irq.pending)
3780 fixup_rmode_irq(vmx);
3781
3782 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3783 vmx->launched = 1;
3784
3785 vmx_complete_interrupts(vmx);
3786 }
3787
3788 #undef R
3789 #undef Q
3790
3791 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3792 {
3793 struct vcpu_vmx *vmx = to_vmx(vcpu);
3794
3795 if (vmx->vmcs) {
3796 vcpu_clear(vmx);
3797 free_vmcs(vmx->vmcs);
3798 vmx->vmcs = NULL;
3799 }
3800 }
3801
3802 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3803 {
3804 struct vcpu_vmx *vmx = to_vmx(vcpu);
3805
3806 spin_lock(&vmx_vpid_lock);
3807 if (vmx->vpid != 0)
3808 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3809 spin_unlock(&vmx_vpid_lock);
3810 vmx_free_vmcs(vcpu);
3811 kfree(vmx->host_msrs);
3812 kfree(vmx->guest_msrs);
3813 kvm_vcpu_uninit(vcpu);
3814 kmem_cache_free(kvm_vcpu_cache, vmx);
3815 }
3816
3817 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3818 {
3819 int err;
3820 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3821 int cpu;
3822
3823 if (!vmx)
3824 return ERR_PTR(-ENOMEM);
3825
3826 allocate_vpid(vmx);
3827
3828 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3829 if (err)
3830 goto free_vcpu;
3831
3832 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3833 if (!vmx->guest_msrs) {
3834 err = -ENOMEM;
3835 goto uninit_vcpu;
3836 }
3837
3838 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3839 if (!vmx->host_msrs)
3840 goto free_guest_msrs;
3841
3842 vmx->vmcs = alloc_vmcs();
3843 if (!vmx->vmcs)
3844 goto free_msrs;
3845
3846 vmcs_clear(vmx->vmcs);
3847
3848 cpu = get_cpu();
3849 vmx_vcpu_load(&vmx->vcpu, cpu);
3850 err = vmx_vcpu_setup(vmx);
3851 vmx_vcpu_put(&vmx->vcpu);
3852 put_cpu();
3853 if (err)
3854 goto free_vmcs;
3855 if (vm_need_virtualize_apic_accesses(kvm))
3856 if (alloc_apic_access_page(kvm) != 0)
3857 goto free_vmcs;
3858
3859 if (enable_ept) {
3860 if (!kvm->arch.ept_identity_map_addr)
3861 kvm->arch.ept_identity_map_addr =
3862 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3863 if (alloc_identity_pagetable(kvm) != 0)
3864 goto free_vmcs;
3865 }
3866
3867 return &vmx->vcpu;
3868
3869 free_vmcs:
3870 free_vmcs(vmx->vmcs);
3871 free_msrs:
3872 kfree(vmx->host_msrs);
3873 free_guest_msrs:
3874 kfree(vmx->guest_msrs);
3875 uninit_vcpu:
3876 kvm_vcpu_uninit(&vmx->vcpu);
3877 free_vcpu:
3878 kmem_cache_free(kvm_vcpu_cache, vmx);
3879 return ERR_PTR(err);
3880 }
3881
3882 static void __init vmx_check_processor_compat(void *rtn)
3883 {
3884 struct vmcs_config vmcs_conf;
3885
3886 *(int *)rtn = 0;
3887 if (setup_vmcs_config(&vmcs_conf) < 0)
3888 *(int *)rtn = -EIO;
3889 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3890 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3891 smp_processor_id());
3892 *(int *)rtn = -EIO;
3893 }
3894 }
3895
3896 static int get_ept_level(void)
3897 {
3898 return VMX_EPT_DEFAULT_GAW + 1;
3899 }
3900
3901 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3902 {
3903 u64 ret;
3904
3905 /* For VT-d and EPT combination
3906 * 1. MMIO: always map as UC
3907 * 2. EPT with VT-d:
3908 * a. VT-d without snooping control feature: can't guarantee the
3909 * result, try to trust guest.
3910 * b. VT-d with snooping control feature: snooping control feature of
3911 * VT-d engine can guarantee the cache correctness. Just set it
3912 * to WB to keep consistent with host. So the same as item 3.
3913 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3914 * consistent with host MTRR
3915 */
3916 if (is_mmio)
3917 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3918 else if (vcpu->kvm->arch.iommu_domain &&
3919 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3920 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3921 VMX_EPT_MT_EPTE_SHIFT;
3922 else
3923 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3924 | VMX_EPT_IGMT_BIT;
3925
3926 return ret;
3927 }
3928
3929 static const struct trace_print_flags vmx_exit_reasons_str[] = {
3930 { EXIT_REASON_EXCEPTION_NMI, "exception" },
3931 { EXIT_REASON_EXTERNAL_INTERRUPT, "ext_irq" },
3932 { EXIT_REASON_TRIPLE_FAULT, "triple_fault" },
3933 { EXIT_REASON_NMI_WINDOW, "nmi_window" },
3934 { EXIT_REASON_IO_INSTRUCTION, "io_instruction" },
3935 { EXIT_REASON_CR_ACCESS, "cr_access" },
3936 { EXIT_REASON_DR_ACCESS, "dr_access" },
3937 { EXIT_REASON_CPUID, "cpuid" },
3938 { EXIT_REASON_MSR_READ, "rdmsr" },
3939 { EXIT_REASON_MSR_WRITE, "wrmsr" },
3940 { EXIT_REASON_PENDING_INTERRUPT, "interrupt_window" },
3941 { EXIT_REASON_HLT, "halt" },
3942 { EXIT_REASON_INVLPG, "invlpg" },
3943 { EXIT_REASON_VMCALL, "hypercall" },
3944 { EXIT_REASON_TPR_BELOW_THRESHOLD, "tpr_below_thres" },
3945 { EXIT_REASON_APIC_ACCESS, "apic_access" },
3946 { EXIT_REASON_WBINVD, "wbinvd" },
3947 { EXIT_REASON_TASK_SWITCH, "task_switch" },
3948 { EXIT_REASON_EPT_VIOLATION, "ept_violation" },
3949 { -1, NULL }
3950 };
3951
3952 static bool vmx_gb_page_enable(void)
3953 {
3954 return false;
3955 }
3956
3957 static struct kvm_x86_ops vmx_x86_ops = {
3958 .cpu_has_kvm_support = cpu_has_kvm_support,
3959 .disabled_by_bios = vmx_disabled_by_bios,
3960 .hardware_setup = hardware_setup,
3961 .hardware_unsetup = hardware_unsetup,
3962 .check_processor_compatibility = vmx_check_processor_compat,
3963 .hardware_enable = hardware_enable,
3964 .hardware_disable = hardware_disable,
3965 .cpu_has_accelerated_tpr = report_flexpriority,
3966
3967 .vcpu_create = vmx_create_vcpu,
3968 .vcpu_free = vmx_free_vcpu,
3969 .vcpu_reset = vmx_vcpu_reset,
3970
3971 .prepare_guest_switch = vmx_save_host_state,
3972 .vcpu_load = vmx_vcpu_load,
3973 .vcpu_put = vmx_vcpu_put,
3974
3975 .set_guest_debug = set_guest_debug,
3976 .get_msr = vmx_get_msr,
3977 .set_msr = vmx_set_msr,
3978 .get_segment_base = vmx_get_segment_base,
3979 .get_segment = vmx_get_segment,
3980 .set_segment = vmx_set_segment,
3981 .get_cpl = vmx_get_cpl,
3982 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3983 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3984 .set_cr0 = vmx_set_cr0,
3985 .set_cr3 = vmx_set_cr3,
3986 .set_cr4 = vmx_set_cr4,
3987 .set_efer = vmx_set_efer,
3988 .get_idt = vmx_get_idt,
3989 .set_idt = vmx_set_idt,
3990 .get_gdt = vmx_get_gdt,
3991 .set_gdt = vmx_set_gdt,
3992 .cache_reg = vmx_cache_reg,
3993 .get_rflags = vmx_get_rflags,
3994 .set_rflags = vmx_set_rflags,
3995
3996 .tlb_flush = vmx_flush_tlb,
3997
3998 .run = vmx_vcpu_run,
3999 .handle_exit = vmx_handle_exit,
4000 .skip_emulated_instruction = skip_emulated_instruction,
4001 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4002 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4003 .patch_hypercall = vmx_patch_hypercall,
4004 .set_irq = vmx_inject_irq,
4005 .set_nmi = vmx_inject_nmi,
4006 .queue_exception = vmx_queue_exception,
4007 .interrupt_allowed = vmx_interrupt_allowed,
4008 .nmi_allowed = vmx_nmi_allowed,
4009 .enable_nmi_window = enable_nmi_window,
4010 .enable_irq_window = enable_irq_window,
4011 .update_cr8_intercept = update_cr8_intercept,
4012
4013 .set_tss_addr = vmx_set_tss_addr,
4014 .get_tdp_level = get_ept_level,
4015 .get_mt_mask = vmx_get_mt_mask,
4016
4017 .exit_reasons_str = vmx_exit_reasons_str,
4018 .gb_page_enable = vmx_gb_page_enable,
4019 };
4020
4021 static int __init vmx_init(void)
4022 {
4023 int r;
4024
4025 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4026 if (!vmx_io_bitmap_a)
4027 return -ENOMEM;
4028
4029 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4030 if (!vmx_io_bitmap_b) {
4031 r = -ENOMEM;
4032 goto out;
4033 }
4034
4035 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4036 if (!vmx_msr_bitmap_legacy) {
4037 r = -ENOMEM;
4038 goto out1;
4039 }
4040
4041 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4042 if (!vmx_msr_bitmap_longmode) {
4043 r = -ENOMEM;
4044 goto out2;
4045 }
4046
4047 /*
4048 * Allow direct access to the PC debug port (it is often used for I/O
4049 * delays, but the vmexits simply slow things down).
4050 */
4051 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4052 clear_bit(0x80, vmx_io_bitmap_a);
4053
4054 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4055
4056 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4057 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4058
4059 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4060
4061 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4062 if (r)
4063 goto out3;
4064
4065 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4066 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4067 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4068 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4069 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4070 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4071
4072 if (enable_ept) {
4073 bypass_guest_pf = 0;
4074 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4075 VMX_EPT_WRITABLE_MASK);
4076 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4077 VMX_EPT_EXECUTABLE_MASK);
4078 kvm_enable_tdp();
4079 } else
4080 kvm_disable_tdp();
4081
4082 if (bypass_guest_pf)
4083 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4084
4085 return 0;
4086
4087 out3:
4088 free_page((unsigned long)vmx_msr_bitmap_longmode);
4089 out2:
4090 free_page((unsigned long)vmx_msr_bitmap_legacy);
4091 out1:
4092 free_page((unsigned long)vmx_io_bitmap_b);
4093 out:
4094 free_page((unsigned long)vmx_io_bitmap_a);
4095 return r;
4096 }
4097
4098 static void __exit vmx_exit(void)
4099 {
4100 free_page((unsigned long)vmx_msr_bitmap_legacy);
4101 free_page((unsigned long)vmx_msr_bitmap_longmode);
4102 free_page((unsigned long)vmx_io_bitmap_b);
4103 free_page((unsigned long)vmx_io_bitmap_a);
4104
4105 kvm_exit();
4106 }
4107
4108 module_init(vmx_init)
4109 module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)