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Merge branch 'for-linus' of git://oss.sgi.com/xfs/xfs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42
43 #include "trace.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
49
50 static int __read_mostly bypass_guest_pf = 1;
51 module_param(bypass_guest_pf, bool, S_IRUGO);
52
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
55
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
58
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
61
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
68
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
71
72 static int __read_mostly yield_on_hlt = 1;
73 module_param(yield_on_hlt, bool, S_IRUGO);
74
75 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
76 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
77 #define KVM_GUEST_CR0_MASK \
78 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
79 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
80 (X86_CR0_WP | X86_CR0_NE)
81 #define KVM_VM_CR0_ALWAYS_ON \
82 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
83 #define KVM_CR4_GUEST_OWNED_BITS \
84 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
85 | X86_CR4_OSXMMEXCPT)
86
87 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
88 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
89
90 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
91
92 /*
93 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
94 * ple_gap: upper bound on the amount of time between two successive
95 * executions of PAUSE in a loop. Also indicate if ple enabled.
96 * According to test, this time is usually smaller than 128 cycles.
97 * ple_window: upper bound on the amount of time a guest is allowed to execute
98 * in a PAUSE loop. Tests indicate that most spinlocks are held for
99 * less than 2^12 cycles
100 * Time is measured based on a counter that runs at the same rate as the TSC,
101 * refer SDM volume 3b section 21.6.13 & 22.1.3.
102 */
103 #define KVM_VMX_DEFAULT_PLE_GAP 128
104 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
105 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
106 module_param(ple_gap, int, S_IRUGO);
107
108 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
109 module_param(ple_window, int, S_IRUGO);
110
111 #define NR_AUTOLOAD_MSRS 1
112
113 struct vmcs {
114 u32 revision_id;
115 u32 abort;
116 char data[0];
117 };
118
119 struct shared_msr_entry {
120 unsigned index;
121 u64 data;
122 u64 mask;
123 };
124
125 struct vcpu_vmx {
126 struct kvm_vcpu vcpu;
127 struct list_head local_vcpus_link;
128 unsigned long host_rsp;
129 int launched;
130 u8 fail;
131 u32 exit_intr_info;
132 u32 idt_vectoring_info;
133 struct shared_msr_entry *guest_msrs;
134 int nmsrs;
135 int save_nmsrs;
136 #ifdef CONFIG_X86_64
137 u64 msr_host_kernel_gs_base;
138 u64 msr_guest_kernel_gs_base;
139 #endif
140 struct vmcs *vmcs;
141 struct msr_autoload {
142 unsigned nr;
143 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
144 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
145 } msr_autoload;
146 struct {
147 int loaded;
148 u16 fs_sel, gs_sel, ldt_sel;
149 int gs_ldt_reload_needed;
150 int fs_reload_needed;
151 } host_state;
152 struct {
153 int vm86_active;
154 ulong save_rflags;
155 struct kvm_save_segment {
156 u16 selector;
157 unsigned long base;
158 u32 limit;
159 u32 ar;
160 } tr, es, ds, fs, gs;
161 } rmode;
162 int vpid;
163 bool emulation_required;
164
165 /* Support for vnmi-less CPUs */
166 int soft_vnmi_blocked;
167 ktime_t entry_time;
168 s64 vnmi_blocked_time;
169 u32 exit_reason;
170
171 bool rdtscp_enabled;
172 };
173
174 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
175 {
176 return container_of(vcpu, struct vcpu_vmx, vcpu);
177 }
178
179 static u64 construct_eptp(unsigned long root_hpa);
180 static void kvm_cpu_vmxon(u64 addr);
181 static void kvm_cpu_vmxoff(void);
182 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
183 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
184
185 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
186 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
187 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
188 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
189
190 static unsigned long *vmx_io_bitmap_a;
191 static unsigned long *vmx_io_bitmap_b;
192 static unsigned long *vmx_msr_bitmap_legacy;
193 static unsigned long *vmx_msr_bitmap_longmode;
194
195 static bool cpu_has_load_ia32_efer;
196
197 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
198 static DEFINE_SPINLOCK(vmx_vpid_lock);
199
200 static struct vmcs_config {
201 int size;
202 int order;
203 u32 revision_id;
204 u32 pin_based_exec_ctrl;
205 u32 cpu_based_exec_ctrl;
206 u32 cpu_based_2nd_exec_ctrl;
207 u32 vmexit_ctrl;
208 u32 vmentry_ctrl;
209 } vmcs_config;
210
211 static struct vmx_capability {
212 u32 ept;
213 u32 vpid;
214 } vmx_capability;
215
216 #define VMX_SEGMENT_FIELD(seg) \
217 [VCPU_SREG_##seg] = { \
218 .selector = GUEST_##seg##_SELECTOR, \
219 .base = GUEST_##seg##_BASE, \
220 .limit = GUEST_##seg##_LIMIT, \
221 .ar_bytes = GUEST_##seg##_AR_BYTES, \
222 }
223
224 static struct kvm_vmx_segment_field {
225 unsigned selector;
226 unsigned base;
227 unsigned limit;
228 unsigned ar_bytes;
229 } kvm_vmx_segment_fields[] = {
230 VMX_SEGMENT_FIELD(CS),
231 VMX_SEGMENT_FIELD(DS),
232 VMX_SEGMENT_FIELD(ES),
233 VMX_SEGMENT_FIELD(FS),
234 VMX_SEGMENT_FIELD(GS),
235 VMX_SEGMENT_FIELD(SS),
236 VMX_SEGMENT_FIELD(TR),
237 VMX_SEGMENT_FIELD(LDTR),
238 };
239
240 static u64 host_efer;
241
242 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
243
244 /*
245 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
246 * away by decrementing the array size.
247 */
248 static const u32 vmx_msr_index[] = {
249 #ifdef CONFIG_X86_64
250 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
251 #endif
252 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
253 };
254 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
255
256 static inline bool is_page_fault(u32 intr_info)
257 {
258 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
259 INTR_INFO_VALID_MASK)) ==
260 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
261 }
262
263 static inline bool is_no_device(u32 intr_info)
264 {
265 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
266 INTR_INFO_VALID_MASK)) ==
267 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
268 }
269
270 static inline bool is_invalid_opcode(u32 intr_info)
271 {
272 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
273 INTR_INFO_VALID_MASK)) ==
274 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
275 }
276
277 static inline bool is_external_interrupt(u32 intr_info)
278 {
279 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
280 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
281 }
282
283 static inline bool is_machine_check(u32 intr_info)
284 {
285 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
286 INTR_INFO_VALID_MASK)) ==
287 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
288 }
289
290 static inline bool cpu_has_vmx_msr_bitmap(void)
291 {
292 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
293 }
294
295 static inline bool cpu_has_vmx_tpr_shadow(void)
296 {
297 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
298 }
299
300 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
301 {
302 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
303 }
304
305 static inline bool cpu_has_secondary_exec_ctrls(void)
306 {
307 return vmcs_config.cpu_based_exec_ctrl &
308 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
309 }
310
311 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
312 {
313 return vmcs_config.cpu_based_2nd_exec_ctrl &
314 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
315 }
316
317 static inline bool cpu_has_vmx_flexpriority(void)
318 {
319 return cpu_has_vmx_tpr_shadow() &&
320 cpu_has_vmx_virtualize_apic_accesses();
321 }
322
323 static inline bool cpu_has_vmx_ept_execute_only(void)
324 {
325 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
326 }
327
328 static inline bool cpu_has_vmx_eptp_uncacheable(void)
329 {
330 return vmx_capability.ept & VMX_EPTP_UC_BIT;
331 }
332
333 static inline bool cpu_has_vmx_eptp_writeback(void)
334 {
335 return vmx_capability.ept & VMX_EPTP_WB_BIT;
336 }
337
338 static inline bool cpu_has_vmx_ept_2m_page(void)
339 {
340 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
341 }
342
343 static inline bool cpu_has_vmx_ept_1g_page(void)
344 {
345 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
346 }
347
348 static inline bool cpu_has_vmx_ept_4levels(void)
349 {
350 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
351 }
352
353 static inline bool cpu_has_vmx_invept_individual_addr(void)
354 {
355 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
356 }
357
358 static inline bool cpu_has_vmx_invept_context(void)
359 {
360 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
361 }
362
363 static inline bool cpu_has_vmx_invept_global(void)
364 {
365 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
366 }
367
368 static inline bool cpu_has_vmx_invvpid_single(void)
369 {
370 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
371 }
372
373 static inline bool cpu_has_vmx_invvpid_global(void)
374 {
375 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
376 }
377
378 static inline bool cpu_has_vmx_ept(void)
379 {
380 return vmcs_config.cpu_based_2nd_exec_ctrl &
381 SECONDARY_EXEC_ENABLE_EPT;
382 }
383
384 static inline bool cpu_has_vmx_unrestricted_guest(void)
385 {
386 return vmcs_config.cpu_based_2nd_exec_ctrl &
387 SECONDARY_EXEC_UNRESTRICTED_GUEST;
388 }
389
390 static inline bool cpu_has_vmx_ple(void)
391 {
392 return vmcs_config.cpu_based_2nd_exec_ctrl &
393 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
394 }
395
396 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
397 {
398 return flexpriority_enabled && irqchip_in_kernel(kvm);
399 }
400
401 static inline bool cpu_has_vmx_vpid(void)
402 {
403 return vmcs_config.cpu_based_2nd_exec_ctrl &
404 SECONDARY_EXEC_ENABLE_VPID;
405 }
406
407 static inline bool cpu_has_vmx_rdtscp(void)
408 {
409 return vmcs_config.cpu_based_2nd_exec_ctrl &
410 SECONDARY_EXEC_RDTSCP;
411 }
412
413 static inline bool cpu_has_virtual_nmis(void)
414 {
415 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
416 }
417
418 static inline bool cpu_has_vmx_wbinvd_exit(void)
419 {
420 return vmcs_config.cpu_based_2nd_exec_ctrl &
421 SECONDARY_EXEC_WBINVD_EXITING;
422 }
423
424 static inline bool report_flexpriority(void)
425 {
426 return flexpriority_enabled;
427 }
428
429 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
430 {
431 int i;
432
433 for (i = 0; i < vmx->nmsrs; ++i)
434 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
435 return i;
436 return -1;
437 }
438
439 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
440 {
441 struct {
442 u64 vpid : 16;
443 u64 rsvd : 48;
444 u64 gva;
445 } operand = { vpid, 0, gva };
446
447 asm volatile (__ex(ASM_VMX_INVVPID)
448 /* CF==1 or ZF==1 --> rc = -1 */
449 "; ja 1f ; ud2 ; 1:"
450 : : "a"(&operand), "c"(ext) : "cc", "memory");
451 }
452
453 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
454 {
455 struct {
456 u64 eptp, gpa;
457 } operand = {eptp, gpa};
458
459 asm volatile (__ex(ASM_VMX_INVEPT)
460 /* CF==1 or ZF==1 --> rc = -1 */
461 "; ja 1f ; ud2 ; 1:\n"
462 : : "a" (&operand), "c" (ext) : "cc", "memory");
463 }
464
465 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
466 {
467 int i;
468
469 i = __find_msr_index(vmx, msr);
470 if (i >= 0)
471 return &vmx->guest_msrs[i];
472 return NULL;
473 }
474
475 static void vmcs_clear(struct vmcs *vmcs)
476 {
477 u64 phys_addr = __pa(vmcs);
478 u8 error;
479
480 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
481 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
482 : "cc", "memory");
483 if (error)
484 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
485 vmcs, phys_addr);
486 }
487
488 static void vmcs_load(struct vmcs *vmcs)
489 {
490 u64 phys_addr = __pa(vmcs);
491 u8 error;
492
493 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
494 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
495 : "cc", "memory");
496 if (error)
497 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
498 vmcs, phys_addr);
499 }
500
501 static void __vcpu_clear(void *arg)
502 {
503 struct vcpu_vmx *vmx = arg;
504 int cpu = raw_smp_processor_id();
505
506 if (vmx->vcpu.cpu == cpu)
507 vmcs_clear(vmx->vmcs);
508 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
509 per_cpu(current_vmcs, cpu) = NULL;
510 list_del(&vmx->local_vcpus_link);
511 vmx->vcpu.cpu = -1;
512 vmx->launched = 0;
513 }
514
515 static void vcpu_clear(struct vcpu_vmx *vmx)
516 {
517 if (vmx->vcpu.cpu == -1)
518 return;
519 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
520 }
521
522 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
523 {
524 if (vmx->vpid == 0)
525 return;
526
527 if (cpu_has_vmx_invvpid_single())
528 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
529 }
530
531 static inline void vpid_sync_vcpu_global(void)
532 {
533 if (cpu_has_vmx_invvpid_global())
534 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
535 }
536
537 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
538 {
539 if (cpu_has_vmx_invvpid_single())
540 vpid_sync_vcpu_single(vmx);
541 else
542 vpid_sync_vcpu_global();
543 }
544
545 static inline void ept_sync_global(void)
546 {
547 if (cpu_has_vmx_invept_global())
548 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
549 }
550
551 static inline void ept_sync_context(u64 eptp)
552 {
553 if (enable_ept) {
554 if (cpu_has_vmx_invept_context())
555 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
556 else
557 ept_sync_global();
558 }
559 }
560
561 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
562 {
563 if (enable_ept) {
564 if (cpu_has_vmx_invept_individual_addr())
565 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
566 eptp, gpa);
567 else
568 ept_sync_context(eptp);
569 }
570 }
571
572 static unsigned long vmcs_readl(unsigned long field)
573 {
574 unsigned long value = 0;
575
576 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
577 : "+a"(value) : "d"(field) : "cc");
578 return value;
579 }
580
581 static u16 vmcs_read16(unsigned long field)
582 {
583 return vmcs_readl(field);
584 }
585
586 static u32 vmcs_read32(unsigned long field)
587 {
588 return vmcs_readl(field);
589 }
590
591 static u64 vmcs_read64(unsigned long field)
592 {
593 #ifdef CONFIG_X86_64
594 return vmcs_readl(field);
595 #else
596 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
597 #endif
598 }
599
600 static noinline void vmwrite_error(unsigned long field, unsigned long value)
601 {
602 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
603 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
604 dump_stack();
605 }
606
607 static void vmcs_writel(unsigned long field, unsigned long value)
608 {
609 u8 error;
610
611 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
612 : "=q"(error) : "a"(value), "d"(field) : "cc");
613 if (unlikely(error))
614 vmwrite_error(field, value);
615 }
616
617 static void vmcs_write16(unsigned long field, u16 value)
618 {
619 vmcs_writel(field, value);
620 }
621
622 static void vmcs_write32(unsigned long field, u32 value)
623 {
624 vmcs_writel(field, value);
625 }
626
627 static void vmcs_write64(unsigned long field, u64 value)
628 {
629 vmcs_writel(field, value);
630 #ifndef CONFIG_X86_64
631 asm volatile ("");
632 vmcs_writel(field+1, value >> 32);
633 #endif
634 }
635
636 static void vmcs_clear_bits(unsigned long field, u32 mask)
637 {
638 vmcs_writel(field, vmcs_readl(field) & ~mask);
639 }
640
641 static void vmcs_set_bits(unsigned long field, u32 mask)
642 {
643 vmcs_writel(field, vmcs_readl(field) | mask);
644 }
645
646 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
647 {
648 u32 eb;
649
650 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
651 (1u << NM_VECTOR) | (1u << DB_VECTOR);
652 if ((vcpu->guest_debug &
653 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
654 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
655 eb |= 1u << BP_VECTOR;
656 if (to_vmx(vcpu)->rmode.vm86_active)
657 eb = ~0;
658 if (enable_ept)
659 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
660 if (vcpu->fpu_active)
661 eb &= ~(1u << NM_VECTOR);
662 vmcs_write32(EXCEPTION_BITMAP, eb);
663 }
664
665 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
666 {
667 unsigned i;
668 struct msr_autoload *m = &vmx->msr_autoload;
669
670 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
671 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
672 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
673 return;
674 }
675
676 for (i = 0; i < m->nr; ++i)
677 if (m->guest[i].index == msr)
678 break;
679
680 if (i == m->nr)
681 return;
682 --m->nr;
683 m->guest[i] = m->guest[m->nr];
684 m->host[i] = m->host[m->nr];
685 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
686 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
687 }
688
689 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
690 u64 guest_val, u64 host_val)
691 {
692 unsigned i;
693 struct msr_autoload *m = &vmx->msr_autoload;
694
695 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
696 vmcs_write64(GUEST_IA32_EFER, guest_val);
697 vmcs_write64(HOST_IA32_EFER, host_val);
698 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
699 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
700 return;
701 }
702
703 for (i = 0; i < m->nr; ++i)
704 if (m->guest[i].index == msr)
705 break;
706
707 if (i == m->nr) {
708 ++m->nr;
709 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
710 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
711 }
712
713 m->guest[i].index = msr;
714 m->guest[i].value = guest_val;
715 m->host[i].index = msr;
716 m->host[i].value = host_val;
717 }
718
719 static void reload_tss(void)
720 {
721 /*
722 * VT restores TR but not its size. Useless.
723 */
724 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
725 struct desc_struct *descs;
726
727 descs = (void *)gdt->address;
728 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
729 load_TR_desc();
730 }
731
732 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
733 {
734 u64 guest_efer;
735 u64 ignore_bits;
736
737 guest_efer = vmx->vcpu.arch.efer;
738
739 /*
740 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
741 * outside long mode
742 */
743 ignore_bits = EFER_NX | EFER_SCE;
744 #ifdef CONFIG_X86_64
745 ignore_bits |= EFER_LMA | EFER_LME;
746 /* SCE is meaningful only in long mode on Intel */
747 if (guest_efer & EFER_LMA)
748 ignore_bits &= ~(u64)EFER_SCE;
749 #endif
750 guest_efer &= ~ignore_bits;
751 guest_efer |= host_efer & ignore_bits;
752 vmx->guest_msrs[efer_offset].data = guest_efer;
753 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
754
755 clear_atomic_switch_msr(vmx, MSR_EFER);
756 /* On ept, can't emulate nx, and must switch nx atomically */
757 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
758 guest_efer = vmx->vcpu.arch.efer;
759 if (!(guest_efer & EFER_LMA))
760 guest_efer &= ~EFER_LME;
761 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
762 return false;
763 }
764
765 return true;
766 }
767
768 static unsigned long segment_base(u16 selector)
769 {
770 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
771 struct desc_struct *d;
772 unsigned long table_base;
773 unsigned long v;
774
775 if (!(selector & ~3))
776 return 0;
777
778 table_base = gdt->address;
779
780 if (selector & 4) { /* from ldt */
781 u16 ldt_selector = kvm_read_ldt();
782
783 if (!(ldt_selector & ~3))
784 return 0;
785
786 table_base = segment_base(ldt_selector);
787 }
788 d = (struct desc_struct *)(table_base + (selector & ~7));
789 v = get_desc_base(d);
790 #ifdef CONFIG_X86_64
791 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
792 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
793 #endif
794 return v;
795 }
796
797 static inline unsigned long kvm_read_tr_base(void)
798 {
799 u16 tr;
800 asm("str %0" : "=g"(tr));
801 return segment_base(tr);
802 }
803
804 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
805 {
806 struct vcpu_vmx *vmx = to_vmx(vcpu);
807 int i;
808
809 if (vmx->host_state.loaded)
810 return;
811
812 vmx->host_state.loaded = 1;
813 /*
814 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
815 * allow segment selectors with cpl > 0 or ti == 1.
816 */
817 vmx->host_state.ldt_sel = kvm_read_ldt();
818 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
819 savesegment(fs, vmx->host_state.fs_sel);
820 if (!(vmx->host_state.fs_sel & 7)) {
821 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
822 vmx->host_state.fs_reload_needed = 0;
823 } else {
824 vmcs_write16(HOST_FS_SELECTOR, 0);
825 vmx->host_state.fs_reload_needed = 1;
826 }
827 savesegment(gs, vmx->host_state.gs_sel);
828 if (!(vmx->host_state.gs_sel & 7))
829 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
830 else {
831 vmcs_write16(HOST_GS_SELECTOR, 0);
832 vmx->host_state.gs_ldt_reload_needed = 1;
833 }
834
835 #ifdef CONFIG_X86_64
836 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
837 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
838 #else
839 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
840 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
841 #endif
842
843 #ifdef CONFIG_X86_64
844 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
845 if (is_long_mode(&vmx->vcpu))
846 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
847 #endif
848 for (i = 0; i < vmx->save_nmsrs; ++i)
849 kvm_set_shared_msr(vmx->guest_msrs[i].index,
850 vmx->guest_msrs[i].data,
851 vmx->guest_msrs[i].mask);
852 }
853
854 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
855 {
856 if (!vmx->host_state.loaded)
857 return;
858
859 ++vmx->vcpu.stat.host_state_reload;
860 vmx->host_state.loaded = 0;
861 #ifdef CONFIG_X86_64
862 if (is_long_mode(&vmx->vcpu))
863 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
864 #endif
865 if (vmx->host_state.gs_ldt_reload_needed) {
866 kvm_load_ldt(vmx->host_state.ldt_sel);
867 #ifdef CONFIG_X86_64
868 load_gs_index(vmx->host_state.gs_sel);
869 #else
870 loadsegment(gs, vmx->host_state.gs_sel);
871 #endif
872 }
873 if (vmx->host_state.fs_reload_needed)
874 loadsegment(fs, vmx->host_state.fs_sel);
875 reload_tss();
876 #ifdef CONFIG_X86_64
877 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
878 #endif
879 if (current_thread_info()->status & TS_USEDFPU)
880 clts();
881 load_gdt(&__get_cpu_var(host_gdt));
882 }
883
884 static void vmx_load_host_state(struct vcpu_vmx *vmx)
885 {
886 preempt_disable();
887 __vmx_load_host_state(vmx);
888 preempt_enable();
889 }
890
891 /*
892 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
893 * vcpu mutex is already taken.
894 */
895 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
896 {
897 struct vcpu_vmx *vmx = to_vmx(vcpu);
898 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
899
900 if (!vmm_exclusive)
901 kvm_cpu_vmxon(phys_addr);
902 else if (vcpu->cpu != cpu)
903 vcpu_clear(vmx);
904
905 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
906 per_cpu(current_vmcs, cpu) = vmx->vmcs;
907 vmcs_load(vmx->vmcs);
908 }
909
910 if (vcpu->cpu != cpu) {
911 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
912 unsigned long sysenter_esp;
913
914 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
915 local_irq_disable();
916 list_add(&vmx->local_vcpus_link,
917 &per_cpu(vcpus_on_cpu, cpu));
918 local_irq_enable();
919
920 /*
921 * Linux uses per-cpu TSS and GDT, so set these when switching
922 * processors.
923 */
924 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
925 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
926
927 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
928 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
929 }
930 }
931
932 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
933 {
934 __vmx_load_host_state(to_vmx(vcpu));
935 if (!vmm_exclusive) {
936 __vcpu_clear(to_vmx(vcpu));
937 kvm_cpu_vmxoff();
938 }
939 }
940
941 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
942 {
943 ulong cr0;
944
945 if (vcpu->fpu_active)
946 return;
947 vcpu->fpu_active = 1;
948 cr0 = vmcs_readl(GUEST_CR0);
949 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
950 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
951 vmcs_writel(GUEST_CR0, cr0);
952 update_exception_bitmap(vcpu);
953 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
954 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
955 }
956
957 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
958
959 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
960 {
961 vmx_decache_cr0_guest_bits(vcpu);
962 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
963 update_exception_bitmap(vcpu);
964 vcpu->arch.cr0_guest_owned_bits = 0;
965 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
966 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
967 }
968
969 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
970 {
971 unsigned long rflags, save_rflags;
972
973 rflags = vmcs_readl(GUEST_RFLAGS);
974 if (to_vmx(vcpu)->rmode.vm86_active) {
975 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
976 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
977 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
978 }
979 return rflags;
980 }
981
982 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
983 {
984 if (to_vmx(vcpu)->rmode.vm86_active) {
985 to_vmx(vcpu)->rmode.save_rflags = rflags;
986 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
987 }
988 vmcs_writel(GUEST_RFLAGS, rflags);
989 }
990
991 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
992 {
993 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
994 int ret = 0;
995
996 if (interruptibility & GUEST_INTR_STATE_STI)
997 ret |= KVM_X86_SHADOW_INT_STI;
998 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
999 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1000
1001 return ret & mask;
1002 }
1003
1004 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1005 {
1006 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1007 u32 interruptibility = interruptibility_old;
1008
1009 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1010
1011 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1012 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1013 else if (mask & KVM_X86_SHADOW_INT_STI)
1014 interruptibility |= GUEST_INTR_STATE_STI;
1015
1016 if ((interruptibility != interruptibility_old))
1017 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1018 }
1019
1020 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1021 {
1022 unsigned long rip;
1023
1024 rip = kvm_rip_read(vcpu);
1025 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1026 kvm_rip_write(vcpu, rip);
1027
1028 /* skipping an emulated instruction also counts */
1029 vmx_set_interrupt_shadow(vcpu, 0);
1030 }
1031
1032 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1033 {
1034 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1035 * explicitly skip the instruction because if the HLT state is set, then
1036 * the instruction is already executing and RIP has already been
1037 * advanced. */
1038 if (!yield_on_hlt &&
1039 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1040 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1041 }
1042
1043 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1044 bool has_error_code, u32 error_code,
1045 bool reinject)
1046 {
1047 struct vcpu_vmx *vmx = to_vmx(vcpu);
1048 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1049
1050 if (has_error_code) {
1051 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1052 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1053 }
1054
1055 if (vmx->rmode.vm86_active) {
1056 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1057 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1058 return;
1059 }
1060
1061 if (kvm_exception_is_soft(nr)) {
1062 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1063 vmx->vcpu.arch.event_exit_inst_len);
1064 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1065 } else
1066 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1067
1068 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1069 vmx_clear_hlt(vcpu);
1070 }
1071
1072 static bool vmx_rdtscp_supported(void)
1073 {
1074 return cpu_has_vmx_rdtscp();
1075 }
1076
1077 /*
1078 * Swap MSR entry in host/guest MSR entry array.
1079 */
1080 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1081 {
1082 struct shared_msr_entry tmp;
1083
1084 tmp = vmx->guest_msrs[to];
1085 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1086 vmx->guest_msrs[from] = tmp;
1087 }
1088
1089 /*
1090 * Set up the vmcs to automatically save and restore system
1091 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1092 * mode, as fiddling with msrs is very expensive.
1093 */
1094 static void setup_msrs(struct vcpu_vmx *vmx)
1095 {
1096 int save_nmsrs, index;
1097 unsigned long *msr_bitmap;
1098
1099 vmx_load_host_state(vmx);
1100 save_nmsrs = 0;
1101 #ifdef CONFIG_X86_64
1102 if (is_long_mode(&vmx->vcpu)) {
1103 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1104 if (index >= 0)
1105 move_msr_up(vmx, index, save_nmsrs++);
1106 index = __find_msr_index(vmx, MSR_LSTAR);
1107 if (index >= 0)
1108 move_msr_up(vmx, index, save_nmsrs++);
1109 index = __find_msr_index(vmx, MSR_CSTAR);
1110 if (index >= 0)
1111 move_msr_up(vmx, index, save_nmsrs++);
1112 index = __find_msr_index(vmx, MSR_TSC_AUX);
1113 if (index >= 0 && vmx->rdtscp_enabled)
1114 move_msr_up(vmx, index, save_nmsrs++);
1115 /*
1116 * MSR_STAR is only needed on long mode guests, and only
1117 * if efer.sce is enabled.
1118 */
1119 index = __find_msr_index(vmx, MSR_STAR);
1120 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1121 move_msr_up(vmx, index, save_nmsrs++);
1122 }
1123 #endif
1124 index = __find_msr_index(vmx, MSR_EFER);
1125 if (index >= 0 && update_transition_efer(vmx, index))
1126 move_msr_up(vmx, index, save_nmsrs++);
1127
1128 vmx->save_nmsrs = save_nmsrs;
1129
1130 if (cpu_has_vmx_msr_bitmap()) {
1131 if (is_long_mode(&vmx->vcpu))
1132 msr_bitmap = vmx_msr_bitmap_longmode;
1133 else
1134 msr_bitmap = vmx_msr_bitmap_legacy;
1135
1136 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1137 }
1138 }
1139
1140 /*
1141 * reads and returns guest's timestamp counter "register"
1142 * guest_tsc = host_tsc + tsc_offset -- 21.3
1143 */
1144 static u64 guest_read_tsc(void)
1145 {
1146 u64 host_tsc, tsc_offset;
1147
1148 rdtscll(host_tsc);
1149 tsc_offset = vmcs_read64(TSC_OFFSET);
1150 return host_tsc + tsc_offset;
1151 }
1152
1153 /*
1154 * writes 'offset' into guest's timestamp counter offset register
1155 */
1156 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1157 {
1158 vmcs_write64(TSC_OFFSET, offset);
1159 }
1160
1161 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1162 {
1163 u64 offset = vmcs_read64(TSC_OFFSET);
1164 vmcs_write64(TSC_OFFSET, offset + adjustment);
1165 }
1166
1167 /*
1168 * Reads an msr value (of 'msr_index') into 'pdata'.
1169 * Returns 0 on success, non-0 otherwise.
1170 * Assumes vcpu_load() was already called.
1171 */
1172 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1173 {
1174 u64 data;
1175 struct shared_msr_entry *msr;
1176
1177 if (!pdata) {
1178 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1179 return -EINVAL;
1180 }
1181
1182 switch (msr_index) {
1183 #ifdef CONFIG_X86_64
1184 case MSR_FS_BASE:
1185 data = vmcs_readl(GUEST_FS_BASE);
1186 break;
1187 case MSR_GS_BASE:
1188 data = vmcs_readl(GUEST_GS_BASE);
1189 break;
1190 case MSR_KERNEL_GS_BASE:
1191 vmx_load_host_state(to_vmx(vcpu));
1192 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1193 break;
1194 #endif
1195 case MSR_EFER:
1196 return kvm_get_msr_common(vcpu, msr_index, pdata);
1197 case MSR_IA32_TSC:
1198 data = guest_read_tsc();
1199 break;
1200 case MSR_IA32_SYSENTER_CS:
1201 data = vmcs_read32(GUEST_SYSENTER_CS);
1202 break;
1203 case MSR_IA32_SYSENTER_EIP:
1204 data = vmcs_readl(GUEST_SYSENTER_EIP);
1205 break;
1206 case MSR_IA32_SYSENTER_ESP:
1207 data = vmcs_readl(GUEST_SYSENTER_ESP);
1208 break;
1209 case MSR_TSC_AUX:
1210 if (!to_vmx(vcpu)->rdtscp_enabled)
1211 return 1;
1212 /* Otherwise falls through */
1213 default:
1214 vmx_load_host_state(to_vmx(vcpu));
1215 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1216 if (msr) {
1217 vmx_load_host_state(to_vmx(vcpu));
1218 data = msr->data;
1219 break;
1220 }
1221 return kvm_get_msr_common(vcpu, msr_index, pdata);
1222 }
1223
1224 *pdata = data;
1225 return 0;
1226 }
1227
1228 /*
1229 * Writes msr value into into the appropriate "register".
1230 * Returns 0 on success, non-0 otherwise.
1231 * Assumes vcpu_load() was already called.
1232 */
1233 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1234 {
1235 struct vcpu_vmx *vmx = to_vmx(vcpu);
1236 struct shared_msr_entry *msr;
1237 int ret = 0;
1238
1239 switch (msr_index) {
1240 case MSR_EFER:
1241 vmx_load_host_state(vmx);
1242 ret = kvm_set_msr_common(vcpu, msr_index, data);
1243 break;
1244 #ifdef CONFIG_X86_64
1245 case MSR_FS_BASE:
1246 vmcs_writel(GUEST_FS_BASE, data);
1247 break;
1248 case MSR_GS_BASE:
1249 vmcs_writel(GUEST_GS_BASE, data);
1250 break;
1251 case MSR_KERNEL_GS_BASE:
1252 vmx_load_host_state(vmx);
1253 vmx->msr_guest_kernel_gs_base = data;
1254 break;
1255 #endif
1256 case MSR_IA32_SYSENTER_CS:
1257 vmcs_write32(GUEST_SYSENTER_CS, data);
1258 break;
1259 case MSR_IA32_SYSENTER_EIP:
1260 vmcs_writel(GUEST_SYSENTER_EIP, data);
1261 break;
1262 case MSR_IA32_SYSENTER_ESP:
1263 vmcs_writel(GUEST_SYSENTER_ESP, data);
1264 break;
1265 case MSR_IA32_TSC:
1266 kvm_write_tsc(vcpu, data);
1267 break;
1268 case MSR_IA32_CR_PAT:
1269 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1270 vmcs_write64(GUEST_IA32_PAT, data);
1271 vcpu->arch.pat = data;
1272 break;
1273 }
1274 ret = kvm_set_msr_common(vcpu, msr_index, data);
1275 break;
1276 case MSR_TSC_AUX:
1277 if (!vmx->rdtscp_enabled)
1278 return 1;
1279 /* Check reserved bit, higher 32 bits should be zero */
1280 if ((data >> 32) != 0)
1281 return 1;
1282 /* Otherwise falls through */
1283 default:
1284 msr = find_msr_entry(vmx, msr_index);
1285 if (msr) {
1286 vmx_load_host_state(vmx);
1287 msr->data = data;
1288 break;
1289 }
1290 ret = kvm_set_msr_common(vcpu, msr_index, data);
1291 }
1292
1293 return ret;
1294 }
1295
1296 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1297 {
1298 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1299 switch (reg) {
1300 case VCPU_REGS_RSP:
1301 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1302 break;
1303 case VCPU_REGS_RIP:
1304 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1305 break;
1306 case VCPU_EXREG_PDPTR:
1307 if (enable_ept)
1308 ept_save_pdptrs(vcpu);
1309 break;
1310 default:
1311 break;
1312 }
1313 }
1314
1315 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1316 {
1317 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1318 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1319 else
1320 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1321
1322 update_exception_bitmap(vcpu);
1323 }
1324
1325 static __init int cpu_has_kvm_support(void)
1326 {
1327 return cpu_has_vmx();
1328 }
1329
1330 static __init int vmx_disabled_by_bios(void)
1331 {
1332 u64 msr;
1333
1334 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1335 if (msr & FEATURE_CONTROL_LOCKED) {
1336 /* launched w/ TXT and VMX disabled */
1337 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1338 && tboot_enabled())
1339 return 1;
1340 /* launched w/o TXT and VMX only enabled w/ TXT */
1341 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1342 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1343 && !tboot_enabled()) {
1344 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1345 "activate TXT before enabling KVM\n");
1346 return 1;
1347 }
1348 /* launched w/o TXT and VMX disabled */
1349 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1350 && !tboot_enabled())
1351 return 1;
1352 }
1353
1354 return 0;
1355 }
1356
1357 static void kvm_cpu_vmxon(u64 addr)
1358 {
1359 asm volatile (ASM_VMX_VMXON_RAX
1360 : : "a"(&addr), "m"(addr)
1361 : "memory", "cc");
1362 }
1363
1364 static int hardware_enable(void *garbage)
1365 {
1366 int cpu = raw_smp_processor_id();
1367 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1368 u64 old, test_bits;
1369
1370 if (read_cr4() & X86_CR4_VMXE)
1371 return -EBUSY;
1372
1373 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1374 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1375
1376 test_bits = FEATURE_CONTROL_LOCKED;
1377 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1378 if (tboot_enabled())
1379 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1380
1381 if ((old & test_bits) != test_bits) {
1382 /* enable and lock */
1383 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1384 }
1385 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1386
1387 if (vmm_exclusive) {
1388 kvm_cpu_vmxon(phys_addr);
1389 ept_sync_global();
1390 }
1391
1392 store_gdt(&__get_cpu_var(host_gdt));
1393
1394 return 0;
1395 }
1396
1397 static void vmclear_local_vcpus(void)
1398 {
1399 int cpu = raw_smp_processor_id();
1400 struct vcpu_vmx *vmx, *n;
1401
1402 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1403 local_vcpus_link)
1404 __vcpu_clear(vmx);
1405 }
1406
1407
1408 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1409 * tricks.
1410 */
1411 static void kvm_cpu_vmxoff(void)
1412 {
1413 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1414 }
1415
1416 static void hardware_disable(void *garbage)
1417 {
1418 if (vmm_exclusive) {
1419 vmclear_local_vcpus();
1420 kvm_cpu_vmxoff();
1421 }
1422 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1423 }
1424
1425 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1426 u32 msr, u32 *result)
1427 {
1428 u32 vmx_msr_low, vmx_msr_high;
1429 u32 ctl = ctl_min | ctl_opt;
1430
1431 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1432
1433 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1434 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1435
1436 /* Ensure minimum (required) set of control bits are supported. */
1437 if (ctl_min & ~ctl)
1438 return -EIO;
1439
1440 *result = ctl;
1441 return 0;
1442 }
1443
1444 static __init bool allow_1_setting(u32 msr, u32 ctl)
1445 {
1446 u32 vmx_msr_low, vmx_msr_high;
1447
1448 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1449 return vmx_msr_high & ctl;
1450 }
1451
1452 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1453 {
1454 u32 vmx_msr_low, vmx_msr_high;
1455 u32 min, opt, min2, opt2;
1456 u32 _pin_based_exec_control = 0;
1457 u32 _cpu_based_exec_control = 0;
1458 u32 _cpu_based_2nd_exec_control = 0;
1459 u32 _vmexit_control = 0;
1460 u32 _vmentry_control = 0;
1461
1462 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1463 opt = PIN_BASED_VIRTUAL_NMIS;
1464 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1465 &_pin_based_exec_control) < 0)
1466 return -EIO;
1467
1468 min =
1469 #ifdef CONFIG_X86_64
1470 CPU_BASED_CR8_LOAD_EXITING |
1471 CPU_BASED_CR8_STORE_EXITING |
1472 #endif
1473 CPU_BASED_CR3_LOAD_EXITING |
1474 CPU_BASED_CR3_STORE_EXITING |
1475 CPU_BASED_USE_IO_BITMAPS |
1476 CPU_BASED_MOV_DR_EXITING |
1477 CPU_BASED_USE_TSC_OFFSETING |
1478 CPU_BASED_MWAIT_EXITING |
1479 CPU_BASED_MONITOR_EXITING |
1480 CPU_BASED_INVLPG_EXITING;
1481
1482 if (yield_on_hlt)
1483 min |= CPU_BASED_HLT_EXITING;
1484
1485 opt = CPU_BASED_TPR_SHADOW |
1486 CPU_BASED_USE_MSR_BITMAPS |
1487 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1488 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1489 &_cpu_based_exec_control) < 0)
1490 return -EIO;
1491 #ifdef CONFIG_X86_64
1492 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1493 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1494 ~CPU_BASED_CR8_STORE_EXITING;
1495 #endif
1496 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1497 min2 = 0;
1498 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1499 SECONDARY_EXEC_WBINVD_EXITING |
1500 SECONDARY_EXEC_ENABLE_VPID |
1501 SECONDARY_EXEC_ENABLE_EPT |
1502 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1503 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1504 SECONDARY_EXEC_RDTSCP;
1505 if (adjust_vmx_controls(min2, opt2,
1506 MSR_IA32_VMX_PROCBASED_CTLS2,
1507 &_cpu_based_2nd_exec_control) < 0)
1508 return -EIO;
1509 }
1510 #ifndef CONFIG_X86_64
1511 if (!(_cpu_based_2nd_exec_control &
1512 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1513 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1514 #endif
1515 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1516 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1517 enabled */
1518 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1519 CPU_BASED_CR3_STORE_EXITING |
1520 CPU_BASED_INVLPG_EXITING);
1521 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1522 vmx_capability.ept, vmx_capability.vpid);
1523 }
1524
1525 min = 0;
1526 #ifdef CONFIG_X86_64
1527 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1528 #endif
1529 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1530 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1531 &_vmexit_control) < 0)
1532 return -EIO;
1533
1534 min = 0;
1535 opt = VM_ENTRY_LOAD_IA32_PAT;
1536 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1537 &_vmentry_control) < 0)
1538 return -EIO;
1539
1540 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1541
1542 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1543 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1544 return -EIO;
1545
1546 #ifdef CONFIG_X86_64
1547 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1548 if (vmx_msr_high & (1u<<16))
1549 return -EIO;
1550 #endif
1551
1552 /* Require Write-Back (WB) memory type for VMCS accesses. */
1553 if (((vmx_msr_high >> 18) & 15) != 6)
1554 return -EIO;
1555
1556 vmcs_conf->size = vmx_msr_high & 0x1fff;
1557 vmcs_conf->order = get_order(vmcs_config.size);
1558 vmcs_conf->revision_id = vmx_msr_low;
1559
1560 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1561 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1562 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1563 vmcs_conf->vmexit_ctrl = _vmexit_control;
1564 vmcs_conf->vmentry_ctrl = _vmentry_control;
1565
1566 cpu_has_load_ia32_efer =
1567 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1568 VM_ENTRY_LOAD_IA32_EFER)
1569 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1570 VM_EXIT_LOAD_IA32_EFER);
1571
1572 return 0;
1573 }
1574
1575 static struct vmcs *alloc_vmcs_cpu(int cpu)
1576 {
1577 int node = cpu_to_node(cpu);
1578 struct page *pages;
1579 struct vmcs *vmcs;
1580
1581 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1582 if (!pages)
1583 return NULL;
1584 vmcs = page_address(pages);
1585 memset(vmcs, 0, vmcs_config.size);
1586 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1587 return vmcs;
1588 }
1589
1590 static struct vmcs *alloc_vmcs(void)
1591 {
1592 return alloc_vmcs_cpu(raw_smp_processor_id());
1593 }
1594
1595 static void free_vmcs(struct vmcs *vmcs)
1596 {
1597 free_pages((unsigned long)vmcs, vmcs_config.order);
1598 }
1599
1600 static void free_kvm_area(void)
1601 {
1602 int cpu;
1603
1604 for_each_possible_cpu(cpu) {
1605 free_vmcs(per_cpu(vmxarea, cpu));
1606 per_cpu(vmxarea, cpu) = NULL;
1607 }
1608 }
1609
1610 static __init int alloc_kvm_area(void)
1611 {
1612 int cpu;
1613
1614 for_each_possible_cpu(cpu) {
1615 struct vmcs *vmcs;
1616
1617 vmcs = alloc_vmcs_cpu(cpu);
1618 if (!vmcs) {
1619 free_kvm_area();
1620 return -ENOMEM;
1621 }
1622
1623 per_cpu(vmxarea, cpu) = vmcs;
1624 }
1625 return 0;
1626 }
1627
1628 static __init int hardware_setup(void)
1629 {
1630 if (setup_vmcs_config(&vmcs_config) < 0)
1631 return -EIO;
1632
1633 if (boot_cpu_has(X86_FEATURE_NX))
1634 kvm_enable_efer_bits(EFER_NX);
1635
1636 if (!cpu_has_vmx_vpid())
1637 enable_vpid = 0;
1638
1639 if (!cpu_has_vmx_ept() ||
1640 !cpu_has_vmx_ept_4levels()) {
1641 enable_ept = 0;
1642 enable_unrestricted_guest = 0;
1643 }
1644
1645 if (!cpu_has_vmx_unrestricted_guest())
1646 enable_unrestricted_guest = 0;
1647
1648 if (!cpu_has_vmx_flexpriority())
1649 flexpriority_enabled = 0;
1650
1651 if (!cpu_has_vmx_tpr_shadow())
1652 kvm_x86_ops->update_cr8_intercept = NULL;
1653
1654 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1655 kvm_disable_largepages();
1656
1657 if (!cpu_has_vmx_ple())
1658 ple_gap = 0;
1659
1660 return alloc_kvm_area();
1661 }
1662
1663 static __exit void hardware_unsetup(void)
1664 {
1665 free_kvm_area();
1666 }
1667
1668 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1669 {
1670 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1671
1672 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1673 vmcs_write16(sf->selector, save->selector);
1674 vmcs_writel(sf->base, save->base);
1675 vmcs_write32(sf->limit, save->limit);
1676 vmcs_write32(sf->ar_bytes, save->ar);
1677 } else {
1678 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1679 << AR_DPL_SHIFT;
1680 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1681 }
1682 }
1683
1684 static void enter_pmode(struct kvm_vcpu *vcpu)
1685 {
1686 unsigned long flags;
1687 struct vcpu_vmx *vmx = to_vmx(vcpu);
1688
1689 vmx->emulation_required = 1;
1690 vmx->rmode.vm86_active = 0;
1691
1692 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
1693 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1694 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1695 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1696
1697 flags = vmcs_readl(GUEST_RFLAGS);
1698 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1699 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1700 vmcs_writel(GUEST_RFLAGS, flags);
1701
1702 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1703 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1704
1705 update_exception_bitmap(vcpu);
1706
1707 if (emulate_invalid_guest_state)
1708 return;
1709
1710 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1711 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1712 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1713 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1714
1715 vmcs_write16(GUEST_SS_SELECTOR, 0);
1716 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1717
1718 vmcs_write16(GUEST_CS_SELECTOR,
1719 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1720 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1721 }
1722
1723 static gva_t rmode_tss_base(struct kvm *kvm)
1724 {
1725 if (!kvm->arch.tss_addr) {
1726 struct kvm_memslots *slots;
1727 gfn_t base_gfn;
1728
1729 slots = kvm_memslots(kvm);
1730 base_gfn = slots->memslots[0].base_gfn +
1731 kvm->memslots->memslots[0].npages - 3;
1732 return base_gfn << PAGE_SHIFT;
1733 }
1734 return kvm->arch.tss_addr;
1735 }
1736
1737 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1738 {
1739 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1740
1741 save->selector = vmcs_read16(sf->selector);
1742 save->base = vmcs_readl(sf->base);
1743 save->limit = vmcs_read32(sf->limit);
1744 save->ar = vmcs_read32(sf->ar_bytes);
1745 vmcs_write16(sf->selector, save->base >> 4);
1746 vmcs_write32(sf->base, save->base & 0xffff0);
1747 vmcs_write32(sf->limit, 0xffff);
1748 vmcs_write32(sf->ar_bytes, 0xf3);
1749 if (save->base & 0xf)
1750 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1751 " aligned when entering protected mode (seg=%d)",
1752 seg);
1753 }
1754
1755 static void enter_rmode(struct kvm_vcpu *vcpu)
1756 {
1757 unsigned long flags;
1758 struct vcpu_vmx *vmx = to_vmx(vcpu);
1759
1760 if (enable_unrestricted_guest)
1761 return;
1762
1763 vmx->emulation_required = 1;
1764 vmx->rmode.vm86_active = 1;
1765
1766 /*
1767 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
1768 * vcpu. Call it here with phys address pointing 16M below 4G.
1769 */
1770 if (!vcpu->kvm->arch.tss_addr) {
1771 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
1772 "called before entering vcpu\n");
1773 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
1774 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
1775 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
1776 }
1777
1778 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
1779 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1780 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1781
1782 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1783 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1784
1785 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1786 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1787
1788 flags = vmcs_readl(GUEST_RFLAGS);
1789 vmx->rmode.save_rflags = flags;
1790
1791 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1792
1793 vmcs_writel(GUEST_RFLAGS, flags);
1794 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1795 update_exception_bitmap(vcpu);
1796
1797 if (emulate_invalid_guest_state)
1798 goto continue_rmode;
1799
1800 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1801 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1802 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1803
1804 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1805 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1806 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1807 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1808 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1809
1810 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1811 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1812 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1813 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1814
1815 continue_rmode:
1816 kvm_mmu_reset_context(vcpu);
1817 }
1818
1819 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1820 {
1821 struct vcpu_vmx *vmx = to_vmx(vcpu);
1822 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1823
1824 if (!msr)
1825 return;
1826
1827 /*
1828 * Force kernel_gs_base reloading before EFER changes, as control
1829 * of this msr depends on is_long_mode().
1830 */
1831 vmx_load_host_state(to_vmx(vcpu));
1832 vcpu->arch.efer = efer;
1833 if (efer & EFER_LMA) {
1834 vmcs_write32(VM_ENTRY_CONTROLS,
1835 vmcs_read32(VM_ENTRY_CONTROLS) |
1836 VM_ENTRY_IA32E_MODE);
1837 msr->data = efer;
1838 } else {
1839 vmcs_write32(VM_ENTRY_CONTROLS,
1840 vmcs_read32(VM_ENTRY_CONTROLS) &
1841 ~VM_ENTRY_IA32E_MODE);
1842
1843 msr->data = efer & ~EFER_LME;
1844 }
1845 setup_msrs(vmx);
1846 }
1847
1848 #ifdef CONFIG_X86_64
1849
1850 static void enter_lmode(struct kvm_vcpu *vcpu)
1851 {
1852 u32 guest_tr_ar;
1853
1854 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1855 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1856 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1857 __func__);
1858 vmcs_write32(GUEST_TR_AR_BYTES,
1859 (guest_tr_ar & ~AR_TYPE_MASK)
1860 | AR_TYPE_BUSY_64_TSS);
1861 }
1862 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1863 }
1864
1865 static void exit_lmode(struct kvm_vcpu *vcpu)
1866 {
1867 vmcs_write32(VM_ENTRY_CONTROLS,
1868 vmcs_read32(VM_ENTRY_CONTROLS)
1869 & ~VM_ENTRY_IA32E_MODE);
1870 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1871 }
1872
1873 #endif
1874
1875 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1876 {
1877 vpid_sync_context(to_vmx(vcpu));
1878 if (enable_ept) {
1879 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1880 return;
1881 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1882 }
1883 }
1884
1885 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1886 {
1887 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1888
1889 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1890 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1891 }
1892
1893 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
1894 {
1895 if (enable_ept && is_paging(vcpu))
1896 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1897 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
1898 }
1899
1900 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1901 {
1902 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1903
1904 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1905 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1906 }
1907
1908 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1909 {
1910 if (!test_bit(VCPU_EXREG_PDPTR,
1911 (unsigned long *)&vcpu->arch.regs_dirty))
1912 return;
1913
1914 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1915 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1916 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1917 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1918 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1919 }
1920 }
1921
1922 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1923 {
1924 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1925 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1926 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1927 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1928 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1929 }
1930
1931 __set_bit(VCPU_EXREG_PDPTR,
1932 (unsigned long *)&vcpu->arch.regs_avail);
1933 __set_bit(VCPU_EXREG_PDPTR,
1934 (unsigned long *)&vcpu->arch.regs_dirty);
1935 }
1936
1937 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1938
1939 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1940 unsigned long cr0,
1941 struct kvm_vcpu *vcpu)
1942 {
1943 vmx_decache_cr3(vcpu);
1944 if (!(cr0 & X86_CR0_PG)) {
1945 /* From paging/starting to nonpaging */
1946 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1947 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1948 (CPU_BASED_CR3_LOAD_EXITING |
1949 CPU_BASED_CR3_STORE_EXITING));
1950 vcpu->arch.cr0 = cr0;
1951 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1952 } else if (!is_paging(vcpu)) {
1953 /* From nonpaging to paging */
1954 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1955 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1956 ~(CPU_BASED_CR3_LOAD_EXITING |
1957 CPU_BASED_CR3_STORE_EXITING));
1958 vcpu->arch.cr0 = cr0;
1959 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1960 }
1961
1962 if (!(cr0 & X86_CR0_WP))
1963 *hw_cr0 &= ~X86_CR0_WP;
1964 }
1965
1966 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1967 {
1968 struct vcpu_vmx *vmx = to_vmx(vcpu);
1969 unsigned long hw_cr0;
1970
1971 if (enable_unrestricted_guest)
1972 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1973 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1974 else
1975 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1976
1977 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1978 enter_pmode(vcpu);
1979
1980 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1981 enter_rmode(vcpu);
1982
1983 #ifdef CONFIG_X86_64
1984 if (vcpu->arch.efer & EFER_LME) {
1985 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1986 enter_lmode(vcpu);
1987 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1988 exit_lmode(vcpu);
1989 }
1990 #endif
1991
1992 if (enable_ept)
1993 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1994
1995 if (!vcpu->fpu_active)
1996 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1997
1998 vmcs_writel(CR0_READ_SHADOW, cr0);
1999 vmcs_writel(GUEST_CR0, hw_cr0);
2000 vcpu->arch.cr0 = cr0;
2001 }
2002
2003 static u64 construct_eptp(unsigned long root_hpa)
2004 {
2005 u64 eptp;
2006
2007 /* TODO write the value reading from MSR */
2008 eptp = VMX_EPT_DEFAULT_MT |
2009 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2010 eptp |= (root_hpa & PAGE_MASK);
2011
2012 return eptp;
2013 }
2014
2015 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2016 {
2017 unsigned long guest_cr3;
2018 u64 eptp;
2019
2020 guest_cr3 = cr3;
2021 if (enable_ept) {
2022 eptp = construct_eptp(cr3);
2023 vmcs_write64(EPT_POINTER, eptp);
2024 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2025 vcpu->kvm->arch.ept_identity_map_addr;
2026 ept_load_pdptrs(vcpu);
2027 }
2028
2029 vmx_flush_tlb(vcpu);
2030 vmcs_writel(GUEST_CR3, guest_cr3);
2031 }
2032
2033 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2034 {
2035 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2036 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2037
2038 vcpu->arch.cr4 = cr4;
2039 if (enable_ept) {
2040 if (!is_paging(vcpu)) {
2041 hw_cr4 &= ~X86_CR4_PAE;
2042 hw_cr4 |= X86_CR4_PSE;
2043 } else if (!(cr4 & X86_CR4_PAE)) {
2044 hw_cr4 &= ~X86_CR4_PAE;
2045 }
2046 }
2047
2048 vmcs_writel(CR4_READ_SHADOW, cr4);
2049 vmcs_writel(GUEST_CR4, hw_cr4);
2050 }
2051
2052 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2053 struct kvm_segment *var, int seg)
2054 {
2055 struct vcpu_vmx *vmx = to_vmx(vcpu);
2056 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2057 struct kvm_save_segment *save;
2058 u32 ar;
2059
2060 if (vmx->rmode.vm86_active
2061 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2062 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2063 || seg == VCPU_SREG_GS)
2064 && !emulate_invalid_guest_state) {
2065 switch (seg) {
2066 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2067 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2068 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2069 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2070 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2071 default: BUG();
2072 }
2073 var->selector = save->selector;
2074 var->base = save->base;
2075 var->limit = save->limit;
2076 ar = save->ar;
2077 if (seg == VCPU_SREG_TR
2078 || var->selector == vmcs_read16(sf->selector))
2079 goto use_saved_rmode_seg;
2080 }
2081 var->base = vmcs_readl(sf->base);
2082 var->limit = vmcs_read32(sf->limit);
2083 var->selector = vmcs_read16(sf->selector);
2084 ar = vmcs_read32(sf->ar_bytes);
2085 use_saved_rmode_seg:
2086 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2087 ar = 0;
2088 var->type = ar & 15;
2089 var->s = (ar >> 4) & 1;
2090 var->dpl = (ar >> 5) & 3;
2091 var->present = (ar >> 7) & 1;
2092 var->avl = (ar >> 12) & 1;
2093 var->l = (ar >> 13) & 1;
2094 var->db = (ar >> 14) & 1;
2095 var->g = (ar >> 15) & 1;
2096 var->unusable = (ar >> 16) & 1;
2097 }
2098
2099 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2100 {
2101 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2102 struct kvm_segment s;
2103
2104 if (to_vmx(vcpu)->rmode.vm86_active) {
2105 vmx_get_segment(vcpu, &s, seg);
2106 return s.base;
2107 }
2108 return vmcs_readl(sf->base);
2109 }
2110
2111 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2112 {
2113 if (!is_protmode(vcpu))
2114 return 0;
2115
2116 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2117 return 3;
2118
2119 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2120 }
2121
2122 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2123 {
2124 u32 ar;
2125
2126 if (var->unusable)
2127 ar = 1 << 16;
2128 else {
2129 ar = var->type & 15;
2130 ar |= (var->s & 1) << 4;
2131 ar |= (var->dpl & 3) << 5;
2132 ar |= (var->present & 1) << 7;
2133 ar |= (var->avl & 1) << 12;
2134 ar |= (var->l & 1) << 13;
2135 ar |= (var->db & 1) << 14;
2136 ar |= (var->g & 1) << 15;
2137 }
2138 if (ar == 0) /* a 0 value means unusable */
2139 ar = AR_UNUSABLE_MASK;
2140
2141 return ar;
2142 }
2143
2144 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2145 struct kvm_segment *var, int seg)
2146 {
2147 struct vcpu_vmx *vmx = to_vmx(vcpu);
2148 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2149 u32 ar;
2150
2151 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2152 vmcs_write16(sf->selector, var->selector);
2153 vmx->rmode.tr.selector = var->selector;
2154 vmx->rmode.tr.base = var->base;
2155 vmx->rmode.tr.limit = var->limit;
2156 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2157 return;
2158 }
2159 vmcs_writel(sf->base, var->base);
2160 vmcs_write32(sf->limit, var->limit);
2161 vmcs_write16(sf->selector, var->selector);
2162 if (vmx->rmode.vm86_active && var->s) {
2163 /*
2164 * Hack real-mode segments into vm86 compatibility.
2165 */
2166 if (var->base == 0xffff0000 && var->selector == 0xf000)
2167 vmcs_writel(sf->base, 0xf0000);
2168 ar = 0xf3;
2169 } else
2170 ar = vmx_segment_access_rights(var);
2171
2172 /*
2173 * Fix the "Accessed" bit in AR field of segment registers for older
2174 * qemu binaries.
2175 * IA32 arch specifies that at the time of processor reset the
2176 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2177 * is setting it to 0 in the usedland code. This causes invalid guest
2178 * state vmexit when "unrestricted guest" mode is turned on.
2179 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2180 * tree. Newer qemu binaries with that qemu fix would not need this
2181 * kvm hack.
2182 */
2183 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2184 ar |= 0x1; /* Accessed */
2185
2186 vmcs_write32(sf->ar_bytes, ar);
2187 }
2188
2189 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2190 {
2191 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2192
2193 *db = (ar >> 14) & 1;
2194 *l = (ar >> 13) & 1;
2195 }
2196
2197 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2198 {
2199 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2200 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2201 }
2202
2203 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2204 {
2205 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2206 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2207 }
2208
2209 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2210 {
2211 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2212 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2213 }
2214
2215 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2216 {
2217 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2218 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2219 }
2220
2221 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2222 {
2223 struct kvm_segment var;
2224 u32 ar;
2225
2226 vmx_get_segment(vcpu, &var, seg);
2227 ar = vmx_segment_access_rights(&var);
2228
2229 if (var.base != (var.selector << 4))
2230 return false;
2231 if (var.limit != 0xffff)
2232 return false;
2233 if (ar != 0xf3)
2234 return false;
2235
2236 return true;
2237 }
2238
2239 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2240 {
2241 struct kvm_segment cs;
2242 unsigned int cs_rpl;
2243
2244 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2245 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2246
2247 if (cs.unusable)
2248 return false;
2249 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2250 return false;
2251 if (!cs.s)
2252 return false;
2253 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2254 if (cs.dpl > cs_rpl)
2255 return false;
2256 } else {
2257 if (cs.dpl != cs_rpl)
2258 return false;
2259 }
2260 if (!cs.present)
2261 return false;
2262
2263 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2264 return true;
2265 }
2266
2267 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2268 {
2269 struct kvm_segment ss;
2270 unsigned int ss_rpl;
2271
2272 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2273 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2274
2275 if (ss.unusable)
2276 return true;
2277 if (ss.type != 3 && ss.type != 7)
2278 return false;
2279 if (!ss.s)
2280 return false;
2281 if (ss.dpl != ss_rpl) /* DPL != RPL */
2282 return false;
2283 if (!ss.present)
2284 return false;
2285
2286 return true;
2287 }
2288
2289 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2290 {
2291 struct kvm_segment var;
2292 unsigned int rpl;
2293
2294 vmx_get_segment(vcpu, &var, seg);
2295 rpl = var.selector & SELECTOR_RPL_MASK;
2296
2297 if (var.unusable)
2298 return true;
2299 if (!var.s)
2300 return false;
2301 if (!var.present)
2302 return false;
2303 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2304 if (var.dpl < rpl) /* DPL < RPL */
2305 return false;
2306 }
2307
2308 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2309 * rights flags
2310 */
2311 return true;
2312 }
2313
2314 static bool tr_valid(struct kvm_vcpu *vcpu)
2315 {
2316 struct kvm_segment tr;
2317
2318 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2319
2320 if (tr.unusable)
2321 return false;
2322 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2323 return false;
2324 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2325 return false;
2326 if (!tr.present)
2327 return false;
2328
2329 return true;
2330 }
2331
2332 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2333 {
2334 struct kvm_segment ldtr;
2335
2336 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2337
2338 if (ldtr.unusable)
2339 return true;
2340 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2341 return false;
2342 if (ldtr.type != 2)
2343 return false;
2344 if (!ldtr.present)
2345 return false;
2346
2347 return true;
2348 }
2349
2350 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2351 {
2352 struct kvm_segment cs, ss;
2353
2354 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2355 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2356
2357 return ((cs.selector & SELECTOR_RPL_MASK) ==
2358 (ss.selector & SELECTOR_RPL_MASK));
2359 }
2360
2361 /*
2362 * Check if guest state is valid. Returns true if valid, false if
2363 * not.
2364 * We assume that registers are always usable
2365 */
2366 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2367 {
2368 /* real mode guest state checks */
2369 if (!is_protmode(vcpu)) {
2370 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2371 return false;
2372 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2373 return false;
2374 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2375 return false;
2376 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2377 return false;
2378 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2379 return false;
2380 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2381 return false;
2382 } else {
2383 /* protected mode guest state checks */
2384 if (!cs_ss_rpl_check(vcpu))
2385 return false;
2386 if (!code_segment_valid(vcpu))
2387 return false;
2388 if (!stack_segment_valid(vcpu))
2389 return false;
2390 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2391 return false;
2392 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2393 return false;
2394 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2395 return false;
2396 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2397 return false;
2398 if (!tr_valid(vcpu))
2399 return false;
2400 if (!ldtr_valid(vcpu))
2401 return false;
2402 }
2403 /* TODO:
2404 * - Add checks on RIP
2405 * - Add checks on RFLAGS
2406 */
2407
2408 return true;
2409 }
2410
2411 static int init_rmode_tss(struct kvm *kvm)
2412 {
2413 gfn_t fn;
2414 u16 data = 0;
2415 int r, idx, ret = 0;
2416
2417 idx = srcu_read_lock(&kvm->srcu);
2418 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2419 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2420 if (r < 0)
2421 goto out;
2422 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2423 r = kvm_write_guest_page(kvm, fn++, &data,
2424 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2425 if (r < 0)
2426 goto out;
2427 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2428 if (r < 0)
2429 goto out;
2430 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2431 if (r < 0)
2432 goto out;
2433 data = ~0;
2434 r = kvm_write_guest_page(kvm, fn, &data,
2435 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2436 sizeof(u8));
2437 if (r < 0)
2438 goto out;
2439
2440 ret = 1;
2441 out:
2442 srcu_read_unlock(&kvm->srcu, idx);
2443 return ret;
2444 }
2445
2446 static int init_rmode_identity_map(struct kvm *kvm)
2447 {
2448 int i, idx, r, ret;
2449 pfn_t identity_map_pfn;
2450 u32 tmp;
2451
2452 if (!enable_ept)
2453 return 1;
2454 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2455 printk(KERN_ERR "EPT: identity-mapping pagetable "
2456 "haven't been allocated!\n");
2457 return 0;
2458 }
2459 if (likely(kvm->arch.ept_identity_pagetable_done))
2460 return 1;
2461 ret = 0;
2462 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2463 idx = srcu_read_lock(&kvm->srcu);
2464 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2465 if (r < 0)
2466 goto out;
2467 /* Set up identity-mapping pagetable for EPT in real mode */
2468 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2469 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2470 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2471 r = kvm_write_guest_page(kvm, identity_map_pfn,
2472 &tmp, i * sizeof(tmp), sizeof(tmp));
2473 if (r < 0)
2474 goto out;
2475 }
2476 kvm->arch.ept_identity_pagetable_done = true;
2477 ret = 1;
2478 out:
2479 srcu_read_unlock(&kvm->srcu, idx);
2480 return ret;
2481 }
2482
2483 static void seg_setup(int seg)
2484 {
2485 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2486 unsigned int ar;
2487
2488 vmcs_write16(sf->selector, 0);
2489 vmcs_writel(sf->base, 0);
2490 vmcs_write32(sf->limit, 0xffff);
2491 if (enable_unrestricted_guest) {
2492 ar = 0x93;
2493 if (seg == VCPU_SREG_CS)
2494 ar |= 0x08; /* code segment */
2495 } else
2496 ar = 0xf3;
2497
2498 vmcs_write32(sf->ar_bytes, ar);
2499 }
2500
2501 static int alloc_apic_access_page(struct kvm *kvm)
2502 {
2503 struct kvm_userspace_memory_region kvm_userspace_mem;
2504 int r = 0;
2505
2506 mutex_lock(&kvm->slots_lock);
2507 if (kvm->arch.apic_access_page)
2508 goto out;
2509 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2510 kvm_userspace_mem.flags = 0;
2511 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2512 kvm_userspace_mem.memory_size = PAGE_SIZE;
2513 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2514 if (r)
2515 goto out;
2516
2517 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2518 out:
2519 mutex_unlock(&kvm->slots_lock);
2520 return r;
2521 }
2522
2523 static int alloc_identity_pagetable(struct kvm *kvm)
2524 {
2525 struct kvm_userspace_memory_region kvm_userspace_mem;
2526 int r = 0;
2527
2528 mutex_lock(&kvm->slots_lock);
2529 if (kvm->arch.ept_identity_pagetable)
2530 goto out;
2531 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2532 kvm_userspace_mem.flags = 0;
2533 kvm_userspace_mem.guest_phys_addr =
2534 kvm->arch.ept_identity_map_addr;
2535 kvm_userspace_mem.memory_size = PAGE_SIZE;
2536 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2537 if (r)
2538 goto out;
2539
2540 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2541 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2542 out:
2543 mutex_unlock(&kvm->slots_lock);
2544 return r;
2545 }
2546
2547 static void allocate_vpid(struct vcpu_vmx *vmx)
2548 {
2549 int vpid;
2550
2551 vmx->vpid = 0;
2552 if (!enable_vpid)
2553 return;
2554 spin_lock(&vmx_vpid_lock);
2555 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2556 if (vpid < VMX_NR_VPIDS) {
2557 vmx->vpid = vpid;
2558 __set_bit(vpid, vmx_vpid_bitmap);
2559 }
2560 spin_unlock(&vmx_vpid_lock);
2561 }
2562
2563 static void free_vpid(struct vcpu_vmx *vmx)
2564 {
2565 if (!enable_vpid)
2566 return;
2567 spin_lock(&vmx_vpid_lock);
2568 if (vmx->vpid != 0)
2569 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2570 spin_unlock(&vmx_vpid_lock);
2571 }
2572
2573 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2574 {
2575 int f = sizeof(unsigned long);
2576
2577 if (!cpu_has_vmx_msr_bitmap())
2578 return;
2579
2580 /*
2581 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2582 * have the write-low and read-high bitmap offsets the wrong way round.
2583 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2584 */
2585 if (msr <= 0x1fff) {
2586 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2587 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2588 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2589 msr &= 0x1fff;
2590 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2591 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2592 }
2593 }
2594
2595 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2596 {
2597 if (!longmode_only)
2598 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2599 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2600 }
2601
2602 /*
2603 * Sets up the vmcs for emulated real mode.
2604 */
2605 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2606 {
2607 u32 host_sysenter_cs, msr_low, msr_high;
2608 u32 junk;
2609 u64 host_pat;
2610 unsigned long a;
2611 struct desc_ptr dt;
2612 int i;
2613 unsigned long kvm_vmx_return;
2614 u32 exec_control;
2615
2616 /* I/O */
2617 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2618 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2619
2620 if (cpu_has_vmx_msr_bitmap())
2621 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2622
2623 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2624
2625 /* Control */
2626 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2627 vmcs_config.pin_based_exec_ctrl);
2628
2629 exec_control = vmcs_config.cpu_based_exec_ctrl;
2630 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2631 exec_control &= ~CPU_BASED_TPR_SHADOW;
2632 #ifdef CONFIG_X86_64
2633 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2634 CPU_BASED_CR8_LOAD_EXITING;
2635 #endif
2636 }
2637 if (!enable_ept)
2638 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2639 CPU_BASED_CR3_LOAD_EXITING |
2640 CPU_BASED_INVLPG_EXITING;
2641 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2642
2643 if (cpu_has_secondary_exec_ctrls()) {
2644 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2645 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2646 exec_control &=
2647 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2648 if (vmx->vpid == 0)
2649 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2650 if (!enable_ept) {
2651 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2652 enable_unrestricted_guest = 0;
2653 }
2654 if (!enable_unrestricted_guest)
2655 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2656 if (!ple_gap)
2657 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2658 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2659 }
2660
2661 if (ple_gap) {
2662 vmcs_write32(PLE_GAP, ple_gap);
2663 vmcs_write32(PLE_WINDOW, ple_window);
2664 }
2665
2666 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2667 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2668 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2669
2670 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2671 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2672 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2673
2674 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2675 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2676 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2677 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2678 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
2679 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2680 #ifdef CONFIG_X86_64
2681 rdmsrl(MSR_FS_BASE, a);
2682 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2683 rdmsrl(MSR_GS_BASE, a);
2684 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2685 #else
2686 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2687 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2688 #endif
2689
2690 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2691
2692 native_store_idt(&dt);
2693 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2694
2695 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2696 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2697 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2698 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2699 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2700 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2701 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2702
2703 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2704 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2705 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2706 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2707 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2708 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2709
2710 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2711 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2712 host_pat = msr_low | ((u64) msr_high << 32);
2713 vmcs_write64(HOST_IA32_PAT, host_pat);
2714 }
2715 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2716 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2717 host_pat = msr_low | ((u64) msr_high << 32);
2718 /* Write the default value follow host pat */
2719 vmcs_write64(GUEST_IA32_PAT, host_pat);
2720 /* Keep arch.pat sync with GUEST_IA32_PAT */
2721 vmx->vcpu.arch.pat = host_pat;
2722 }
2723
2724 for (i = 0; i < NR_VMX_MSR; ++i) {
2725 u32 index = vmx_msr_index[i];
2726 u32 data_low, data_high;
2727 int j = vmx->nmsrs;
2728
2729 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2730 continue;
2731 if (wrmsr_safe(index, data_low, data_high) < 0)
2732 continue;
2733 vmx->guest_msrs[j].index = i;
2734 vmx->guest_msrs[j].data = 0;
2735 vmx->guest_msrs[j].mask = -1ull;
2736 ++vmx->nmsrs;
2737 }
2738
2739 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2740
2741 /* 22.2.1, 20.8.1 */
2742 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2743
2744 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2745 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2746 if (enable_ept)
2747 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2748 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2749
2750 kvm_write_tsc(&vmx->vcpu, 0);
2751
2752 return 0;
2753 }
2754
2755 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2756 {
2757 struct vcpu_vmx *vmx = to_vmx(vcpu);
2758 u64 msr;
2759 int ret;
2760
2761 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2762
2763 vmx->rmode.vm86_active = 0;
2764
2765 vmx->soft_vnmi_blocked = 0;
2766
2767 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2768 kvm_set_cr8(&vmx->vcpu, 0);
2769 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2770 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2771 msr |= MSR_IA32_APICBASE_BSP;
2772 kvm_set_apic_base(&vmx->vcpu, msr);
2773
2774 ret = fx_init(&vmx->vcpu);
2775 if (ret != 0)
2776 goto out;
2777
2778 seg_setup(VCPU_SREG_CS);
2779 /*
2780 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2781 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2782 */
2783 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2784 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2785 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2786 } else {
2787 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2788 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2789 }
2790
2791 seg_setup(VCPU_SREG_DS);
2792 seg_setup(VCPU_SREG_ES);
2793 seg_setup(VCPU_SREG_FS);
2794 seg_setup(VCPU_SREG_GS);
2795 seg_setup(VCPU_SREG_SS);
2796
2797 vmcs_write16(GUEST_TR_SELECTOR, 0);
2798 vmcs_writel(GUEST_TR_BASE, 0);
2799 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2800 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2801
2802 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2803 vmcs_writel(GUEST_LDTR_BASE, 0);
2804 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2805 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2806
2807 vmcs_write32(GUEST_SYSENTER_CS, 0);
2808 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2809 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2810
2811 vmcs_writel(GUEST_RFLAGS, 0x02);
2812 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2813 kvm_rip_write(vcpu, 0xfff0);
2814 else
2815 kvm_rip_write(vcpu, 0);
2816 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2817
2818 vmcs_writel(GUEST_DR7, 0x400);
2819
2820 vmcs_writel(GUEST_GDTR_BASE, 0);
2821 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2822
2823 vmcs_writel(GUEST_IDTR_BASE, 0);
2824 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2825
2826 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2827 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2828 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2829
2830 /* Special registers */
2831 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2832
2833 setup_msrs(vmx);
2834
2835 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2836
2837 if (cpu_has_vmx_tpr_shadow()) {
2838 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2839 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2840 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2841 __pa(vmx->vcpu.arch.apic->regs));
2842 vmcs_write32(TPR_THRESHOLD, 0);
2843 }
2844
2845 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2846 vmcs_write64(APIC_ACCESS_ADDR,
2847 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2848
2849 if (vmx->vpid != 0)
2850 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2851
2852 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2853 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2854 vmx_set_cr4(&vmx->vcpu, 0);
2855 vmx_set_efer(&vmx->vcpu, 0);
2856 vmx_fpu_activate(&vmx->vcpu);
2857 update_exception_bitmap(&vmx->vcpu);
2858
2859 vpid_sync_context(vmx);
2860
2861 ret = 0;
2862
2863 /* HACK: Don't enable emulation on guest boot/reset */
2864 vmx->emulation_required = 0;
2865
2866 out:
2867 return ret;
2868 }
2869
2870 static void enable_irq_window(struct kvm_vcpu *vcpu)
2871 {
2872 u32 cpu_based_vm_exec_control;
2873
2874 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2875 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2876 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2877 }
2878
2879 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2880 {
2881 u32 cpu_based_vm_exec_control;
2882
2883 if (!cpu_has_virtual_nmis()) {
2884 enable_irq_window(vcpu);
2885 return;
2886 }
2887
2888 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2889 enable_irq_window(vcpu);
2890 return;
2891 }
2892 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2893 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2894 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2895 }
2896
2897 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2898 {
2899 struct vcpu_vmx *vmx = to_vmx(vcpu);
2900 uint32_t intr;
2901 int irq = vcpu->arch.interrupt.nr;
2902
2903 trace_kvm_inj_virq(irq);
2904
2905 ++vcpu->stat.irq_injections;
2906 if (vmx->rmode.vm86_active) {
2907 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2908 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2909 return;
2910 }
2911 intr = irq | INTR_INFO_VALID_MASK;
2912 if (vcpu->arch.interrupt.soft) {
2913 intr |= INTR_TYPE_SOFT_INTR;
2914 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2915 vmx->vcpu.arch.event_exit_inst_len);
2916 } else
2917 intr |= INTR_TYPE_EXT_INTR;
2918 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2919 vmx_clear_hlt(vcpu);
2920 }
2921
2922 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2923 {
2924 struct vcpu_vmx *vmx = to_vmx(vcpu);
2925
2926 if (!cpu_has_virtual_nmis()) {
2927 /*
2928 * Tracking the NMI-blocked state in software is built upon
2929 * finding the next open IRQ window. This, in turn, depends on
2930 * well-behaving guests: They have to keep IRQs disabled at
2931 * least as long as the NMI handler runs. Otherwise we may
2932 * cause NMI nesting, maybe breaking the guest. But as this is
2933 * highly unlikely, we can live with the residual risk.
2934 */
2935 vmx->soft_vnmi_blocked = 1;
2936 vmx->vnmi_blocked_time = 0;
2937 }
2938
2939 ++vcpu->stat.nmi_injections;
2940 if (vmx->rmode.vm86_active) {
2941 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2942 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2943 return;
2944 }
2945 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2946 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2947 vmx_clear_hlt(vcpu);
2948 }
2949
2950 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2951 {
2952 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2953 return 0;
2954
2955 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2956 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2957 | GUEST_INTR_STATE_NMI));
2958 }
2959
2960 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2961 {
2962 if (!cpu_has_virtual_nmis())
2963 return to_vmx(vcpu)->soft_vnmi_blocked;
2964 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2965 }
2966
2967 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2968 {
2969 struct vcpu_vmx *vmx = to_vmx(vcpu);
2970
2971 if (!cpu_has_virtual_nmis()) {
2972 if (vmx->soft_vnmi_blocked != masked) {
2973 vmx->soft_vnmi_blocked = masked;
2974 vmx->vnmi_blocked_time = 0;
2975 }
2976 } else {
2977 if (masked)
2978 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2979 GUEST_INTR_STATE_NMI);
2980 else
2981 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2982 GUEST_INTR_STATE_NMI);
2983 }
2984 }
2985
2986 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2987 {
2988 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2989 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2990 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2991 }
2992
2993 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2994 {
2995 int ret;
2996 struct kvm_userspace_memory_region tss_mem = {
2997 .slot = TSS_PRIVATE_MEMSLOT,
2998 .guest_phys_addr = addr,
2999 .memory_size = PAGE_SIZE * 3,
3000 .flags = 0,
3001 };
3002
3003 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3004 if (ret)
3005 return ret;
3006 kvm->arch.tss_addr = addr;
3007 if (!init_rmode_tss(kvm))
3008 return -ENOMEM;
3009
3010 return 0;
3011 }
3012
3013 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3014 int vec, u32 err_code)
3015 {
3016 /*
3017 * Instruction with address size override prefix opcode 0x67
3018 * Cause the #SS fault with 0 error code in VM86 mode.
3019 */
3020 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3021 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3022 return 1;
3023 /*
3024 * Forward all other exceptions that are valid in real mode.
3025 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3026 * the required debugging infrastructure rework.
3027 */
3028 switch (vec) {
3029 case DB_VECTOR:
3030 if (vcpu->guest_debug &
3031 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3032 return 0;
3033 kvm_queue_exception(vcpu, vec);
3034 return 1;
3035 case BP_VECTOR:
3036 /*
3037 * Update instruction length as we may reinject the exception
3038 * from user space while in guest debugging mode.
3039 */
3040 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3041 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3042 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3043 return 0;
3044 /* fall through */
3045 case DE_VECTOR:
3046 case OF_VECTOR:
3047 case BR_VECTOR:
3048 case UD_VECTOR:
3049 case DF_VECTOR:
3050 case SS_VECTOR:
3051 case GP_VECTOR:
3052 case MF_VECTOR:
3053 kvm_queue_exception(vcpu, vec);
3054 return 1;
3055 }
3056 return 0;
3057 }
3058
3059 /*
3060 * Trigger machine check on the host. We assume all the MSRs are already set up
3061 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3062 * We pass a fake environment to the machine check handler because we want
3063 * the guest to be always treated like user space, no matter what context
3064 * it used internally.
3065 */
3066 static void kvm_machine_check(void)
3067 {
3068 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3069 struct pt_regs regs = {
3070 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3071 .flags = X86_EFLAGS_IF,
3072 };
3073
3074 do_machine_check(&regs, 0);
3075 #endif
3076 }
3077
3078 static int handle_machine_check(struct kvm_vcpu *vcpu)
3079 {
3080 /* already handled by vcpu_run */
3081 return 1;
3082 }
3083
3084 static int handle_exception(struct kvm_vcpu *vcpu)
3085 {
3086 struct vcpu_vmx *vmx = to_vmx(vcpu);
3087 struct kvm_run *kvm_run = vcpu->run;
3088 u32 intr_info, ex_no, error_code;
3089 unsigned long cr2, rip, dr6;
3090 u32 vect_info;
3091 enum emulation_result er;
3092
3093 vect_info = vmx->idt_vectoring_info;
3094 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3095
3096 if (is_machine_check(intr_info))
3097 return handle_machine_check(vcpu);
3098
3099 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3100 !is_page_fault(intr_info)) {
3101 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3102 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3103 vcpu->run->internal.ndata = 2;
3104 vcpu->run->internal.data[0] = vect_info;
3105 vcpu->run->internal.data[1] = intr_info;
3106 return 0;
3107 }
3108
3109 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3110 return 1; /* already handled by vmx_vcpu_run() */
3111
3112 if (is_no_device(intr_info)) {
3113 vmx_fpu_activate(vcpu);
3114 return 1;
3115 }
3116
3117 if (is_invalid_opcode(intr_info)) {
3118 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3119 if (er != EMULATE_DONE)
3120 kvm_queue_exception(vcpu, UD_VECTOR);
3121 return 1;
3122 }
3123
3124 error_code = 0;
3125 rip = kvm_rip_read(vcpu);
3126 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3127 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3128 if (is_page_fault(intr_info)) {
3129 /* EPT won't cause page fault directly */
3130 if (enable_ept)
3131 BUG();
3132 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3133 trace_kvm_page_fault(cr2, error_code);
3134
3135 if (kvm_event_needs_reinjection(vcpu))
3136 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3137 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3138 }
3139
3140 if (vmx->rmode.vm86_active &&
3141 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3142 error_code)) {
3143 if (vcpu->arch.halt_request) {
3144 vcpu->arch.halt_request = 0;
3145 return kvm_emulate_halt(vcpu);
3146 }
3147 return 1;
3148 }
3149
3150 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3151 switch (ex_no) {
3152 case DB_VECTOR:
3153 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3154 if (!(vcpu->guest_debug &
3155 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3156 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3157 kvm_queue_exception(vcpu, DB_VECTOR);
3158 return 1;
3159 }
3160 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3161 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3162 /* fall through */
3163 case BP_VECTOR:
3164 /*
3165 * Update instruction length as we may reinject #BP from
3166 * user space while in guest debugging mode. Reading it for
3167 * #DB as well causes no harm, it is not used in that case.
3168 */
3169 vmx->vcpu.arch.event_exit_inst_len =
3170 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3171 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3172 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3173 kvm_run->debug.arch.exception = ex_no;
3174 break;
3175 default:
3176 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3177 kvm_run->ex.exception = ex_no;
3178 kvm_run->ex.error_code = error_code;
3179 break;
3180 }
3181 return 0;
3182 }
3183
3184 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3185 {
3186 ++vcpu->stat.irq_exits;
3187 return 1;
3188 }
3189
3190 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3191 {
3192 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3193 return 0;
3194 }
3195
3196 static int handle_io(struct kvm_vcpu *vcpu)
3197 {
3198 unsigned long exit_qualification;
3199 int size, in, string;
3200 unsigned port;
3201
3202 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3203 string = (exit_qualification & 16) != 0;
3204 in = (exit_qualification & 8) != 0;
3205
3206 ++vcpu->stat.io_exits;
3207
3208 if (string || in)
3209 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3210
3211 port = exit_qualification >> 16;
3212 size = (exit_qualification & 7) + 1;
3213 skip_emulated_instruction(vcpu);
3214
3215 return kvm_fast_pio_out(vcpu, size, port);
3216 }
3217
3218 static void
3219 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3220 {
3221 /*
3222 * Patch in the VMCALL instruction:
3223 */
3224 hypercall[0] = 0x0f;
3225 hypercall[1] = 0x01;
3226 hypercall[2] = 0xc1;
3227 }
3228
3229 static int handle_cr(struct kvm_vcpu *vcpu)
3230 {
3231 unsigned long exit_qualification, val;
3232 int cr;
3233 int reg;
3234 int err;
3235
3236 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3237 cr = exit_qualification & 15;
3238 reg = (exit_qualification >> 8) & 15;
3239 switch ((exit_qualification >> 4) & 3) {
3240 case 0: /* mov to cr */
3241 val = kvm_register_read(vcpu, reg);
3242 trace_kvm_cr_write(cr, val);
3243 switch (cr) {
3244 case 0:
3245 err = kvm_set_cr0(vcpu, val);
3246 kvm_complete_insn_gp(vcpu, err);
3247 return 1;
3248 case 3:
3249 err = kvm_set_cr3(vcpu, val);
3250 kvm_complete_insn_gp(vcpu, err);
3251 return 1;
3252 case 4:
3253 err = kvm_set_cr4(vcpu, val);
3254 kvm_complete_insn_gp(vcpu, err);
3255 return 1;
3256 case 8: {
3257 u8 cr8_prev = kvm_get_cr8(vcpu);
3258 u8 cr8 = kvm_register_read(vcpu, reg);
3259 err = kvm_set_cr8(vcpu, cr8);
3260 kvm_complete_insn_gp(vcpu, err);
3261 if (irqchip_in_kernel(vcpu->kvm))
3262 return 1;
3263 if (cr8_prev <= cr8)
3264 return 1;
3265 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3266 return 0;
3267 }
3268 };
3269 break;
3270 case 2: /* clts */
3271 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3272 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3273 skip_emulated_instruction(vcpu);
3274 vmx_fpu_activate(vcpu);
3275 return 1;
3276 case 1: /*mov from cr*/
3277 switch (cr) {
3278 case 3:
3279 val = kvm_read_cr3(vcpu);
3280 kvm_register_write(vcpu, reg, val);
3281 trace_kvm_cr_read(cr, val);
3282 skip_emulated_instruction(vcpu);
3283 return 1;
3284 case 8:
3285 val = kvm_get_cr8(vcpu);
3286 kvm_register_write(vcpu, reg, val);
3287 trace_kvm_cr_read(cr, val);
3288 skip_emulated_instruction(vcpu);
3289 return 1;
3290 }
3291 break;
3292 case 3: /* lmsw */
3293 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3294 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3295 kvm_lmsw(vcpu, val);
3296
3297 skip_emulated_instruction(vcpu);
3298 return 1;
3299 default:
3300 break;
3301 }
3302 vcpu->run->exit_reason = 0;
3303 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3304 (int)(exit_qualification >> 4) & 3, cr);
3305 return 0;
3306 }
3307
3308 static int handle_dr(struct kvm_vcpu *vcpu)
3309 {
3310 unsigned long exit_qualification;
3311 int dr, reg;
3312
3313 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3314 if (!kvm_require_cpl(vcpu, 0))
3315 return 1;
3316 dr = vmcs_readl(GUEST_DR7);
3317 if (dr & DR7_GD) {
3318 /*
3319 * As the vm-exit takes precedence over the debug trap, we
3320 * need to emulate the latter, either for the host or the
3321 * guest debugging itself.
3322 */
3323 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3324 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3325 vcpu->run->debug.arch.dr7 = dr;
3326 vcpu->run->debug.arch.pc =
3327 vmcs_readl(GUEST_CS_BASE) +
3328 vmcs_readl(GUEST_RIP);
3329 vcpu->run->debug.arch.exception = DB_VECTOR;
3330 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3331 return 0;
3332 } else {
3333 vcpu->arch.dr7 &= ~DR7_GD;
3334 vcpu->arch.dr6 |= DR6_BD;
3335 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3336 kvm_queue_exception(vcpu, DB_VECTOR);
3337 return 1;
3338 }
3339 }
3340
3341 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3342 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3343 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3344 if (exit_qualification & TYPE_MOV_FROM_DR) {
3345 unsigned long val;
3346 if (!kvm_get_dr(vcpu, dr, &val))
3347 kvm_register_write(vcpu, reg, val);
3348 } else
3349 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3350 skip_emulated_instruction(vcpu);
3351 return 1;
3352 }
3353
3354 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3355 {
3356 vmcs_writel(GUEST_DR7, val);
3357 }
3358
3359 static int handle_cpuid(struct kvm_vcpu *vcpu)
3360 {
3361 kvm_emulate_cpuid(vcpu);
3362 return 1;
3363 }
3364
3365 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3366 {
3367 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3368 u64 data;
3369
3370 if (vmx_get_msr(vcpu, ecx, &data)) {
3371 trace_kvm_msr_read_ex(ecx);
3372 kvm_inject_gp(vcpu, 0);
3373 return 1;
3374 }
3375
3376 trace_kvm_msr_read(ecx, data);
3377
3378 /* FIXME: handling of bits 32:63 of rax, rdx */
3379 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3380 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3381 skip_emulated_instruction(vcpu);
3382 return 1;
3383 }
3384
3385 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3386 {
3387 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3388 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3389 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3390
3391 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3392 trace_kvm_msr_write_ex(ecx, data);
3393 kvm_inject_gp(vcpu, 0);
3394 return 1;
3395 }
3396
3397 trace_kvm_msr_write(ecx, data);
3398 skip_emulated_instruction(vcpu);
3399 return 1;
3400 }
3401
3402 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3403 {
3404 kvm_make_request(KVM_REQ_EVENT, vcpu);
3405 return 1;
3406 }
3407
3408 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3409 {
3410 u32 cpu_based_vm_exec_control;
3411
3412 /* clear pending irq */
3413 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3414 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3415 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3416
3417 kvm_make_request(KVM_REQ_EVENT, vcpu);
3418
3419 ++vcpu->stat.irq_window_exits;
3420
3421 /*
3422 * If the user space waits to inject interrupts, exit as soon as
3423 * possible
3424 */
3425 if (!irqchip_in_kernel(vcpu->kvm) &&
3426 vcpu->run->request_interrupt_window &&
3427 !kvm_cpu_has_interrupt(vcpu)) {
3428 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3429 return 0;
3430 }
3431 return 1;
3432 }
3433
3434 static int handle_halt(struct kvm_vcpu *vcpu)
3435 {
3436 skip_emulated_instruction(vcpu);
3437 return kvm_emulate_halt(vcpu);
3438 }
3439
3440 static int handle_vmcall(struct kvm_vcpu *vcpu)
3441 {
3442 skip_emulated_instruction(vcpu);
3443 kvm_emulate_hypercall(vcpu);
3444 return 1;
3445 }
3446
3447 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3448 {
3449 kvm_queue_exception(vcpu, UD_VECTOR);
3450 return 1;
3451 }
3452
3453 static int handle_invd(struct kvm_vcpu *vcpu)
3454 {
3455 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3456 }
3457
3458 static int handle_invlpg(struct kvm_vcpu *vcpu)
3459 {
3460 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3461
3462 kvm_mmu_invlpg(vcpu, exit_qualification);
3463 skip_emulated_instruction(vcpu);
3464 return 1;
3465 }
3466
3467 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3468 {
3469 skip_emulated_instruction(vcpu);
3470 kvm_emulate_wbinvd(vcpu);
3471 return 1;
3472 }
3473
3474 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3475 {
3476 u64 new_bv = kvm_read_edx_eax(vcpu);
3477 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3478
3479 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3480 skip_emulated_instruction(vcpu);
3481 return 1;
3482 }
3483
3484 static int handle_apic_access(struct kvm_vcpu *vcpu)
3485 {
3486 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3487 }
3488
3489 static int handle_task_switch(struct kvm_vcpu *vcpu)
3490 {
3491 struct vcpu_vmx *vmx = to_vmx(vcpu);
3492 unsigned long exit_qualification;
3493 bool has_error_code = false;
3494 u32 error_code = 0;
3495 u16 tss_selector;
3496 int reason, type, idt_v;
3497
3498 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3499 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3500
3501 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3502
3503 reason = (u32)exit_qualification >> 30;
3504 if (reason == TASK_SWITCH_GATE && idt_v) {
3505 switch (type) {
3506 case INTR_TYPE_NMI_INTR:
3507 vcpu->arch.nmi_injected = false;
3508 if (cpu_has_virtual_nmis())
3509 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3510 GUEST_INTR_STATE_NMI);
3511 break;
3512 case INTR_TYPE_EXT_INTR:
3513 case INTR_TYPE_SOFT_INTR:
3514 kvm_clear_interrupt_queue(vcpu);
3515 break;
3516 case INTR_TYPE_HARD_EXCEPTION:
3517 if (vmx->idt_vectoring_info &
3518 VECTORING_INFO_DELIVER_CODE_MASK) {
3519 has_error_code = true;
3520 error_code =
3521 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3522 }
3523 /* fall through */
3524 case INTR_TYPE_SOFT_EXCEPTION:
3525 kvm_clear_exception_queue(vcpu);
3526 break;
3527 default:
3528 break;
3529 }
3530 }
3531 tss_selector = exit_qualification;
3532
3533 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3534 type != INTR_TYPE_EXT_INTR &&
3535 type != INTR_TYPE_NMI_INTR))
3536 skip_emulated_instruction(vcpu);
3537
3538 if (kvm_task_switch(vcpu, tss_selector, reason,
3539 has_error_code, error_code) == EMULATE_FAIL) {
3540 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3541 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3542 vcpu->run->internal.ndata = 0;
3543 return 0;
3544 }
3545
3546 /* clear all local breakpoint enable flags */
3547 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3548
3549 /*
3550 * TODO: What about debug traps on tss switch?
3551 * Are we supposed to inject them and update dr6?
3552 */
3553
3554 return 1;
3555 }
3556
3557 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3558 {
3559 unsigned long exit_qualification;
3560 gpa_t gpa;
3561 int gla_validity;
3562
3563 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3564
3565 if (exit_qualification & (1 << 6)) {
3566 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3567 return -EINVAL;
3568 }
3569
3570 gla_validity = (exit_qualification >> 7) & 0x3;
3571 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3572 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3573 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3574 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3575 vmcs_readl(GUEST_LINEAR_ADDRESS));
3576 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3577 (long unsigned int)exit_qualification);
3578 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3579 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3580 return 0;
3581 }
3582
3583 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3584 trace_kvm_page_fault(gpa, exit_qualification);
3585 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
3586 }
3587
3588 static u64 ept_rsvd_mask(u64 spte, int level)
3589 {
3590 int i;
3591 u64 mask = 0;
3592
3593 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3594 mask |= (1ULL << i);
3595
3596 if (level > 2)
3597 /* bits 7:3 reserved */
3598 mask |= 0xf8;
3599 else if (level == 2) {
3600 if (spte & (1ULL << 7))
3601 /* 2MB ref, bits 20:12 reserved */
3602 mask |= 0x1ff000;
3603 else
3604 /* bits 6:3 reserved */
3605 mask |= 0x78;
3606 }
3607
3608 return mask;
3609 }
3610
3611 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3612 int level)
3613 {
3614 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3615
3616 /* 010b (write-only) */
3617 WARN_ON((spte & 0x7) == 0x2);
3618
3619 /* 110b (write/execute) */
3620 WARN_ON((spte & 0x7) == 0x6);
3621
3622 /* 100b (execute-only) and value not supported by logical processor */
3623 if (!cpu_has_vmx_ept_execute_only())
3624 WARN_ON((spte & 0x7) == 0x4);
3625
3626 /* not 000b */
3627 if ((spte & 0x7)) {
3628 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3629
3630 if (rsvd_bits != 0) {
3631 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3632 __func__, rsvd_bits);
3633 WARN_ON(1);
3634 }
3635
3636 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3637 u64 ept_mem_type = (spte & 0x38) >> 3;
3638
3639 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3640 ept_mem_type == 7) {
3641 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3642 __func__, ept_mem_type);
3643 WARN_ON(1);
3644 }
3645 }
3646 }
3647 }
3648
3649 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3650 {
3651 u64 sptes[4];
3652 int nr_sptes, i;
3653 gpa_t gpa;
3654
3655 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3656
3657 printk(KERN_ERR "EPT: Misconfiguration.\n");
3658 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3659
3660 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3661
3662 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3663 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3664
3665 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3666 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3667
3668 return 0;
3669 }
3670
3671 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3672 {
3673 u32 cpu_based_vm_exec_control;
3674
3675 /* clear pending NMI */
3676 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3677 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3678 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3679 ++vcpu->stat.nmi_window_exits;
3680 kvm_make_request(KVM_REQ_EVENT, vcpu);
3681
3682 return 1;
3683 }
3684
3685 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3686 {
3687 struct vcpu_vmx *vmx = to_vmx(vcpu);
3688 enum emulation_result err = EMULATE_DONE;
3689 int ret = 1;
3690 u32 cpu_exec_ctrl;
3691 bool intr_window_requested;
3692
3693 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3694 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3695
3696 while (!guest_state_valid(vcpu)) {
3697 if (intr_window_requested
3698 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3699 return handle_interrupt_window(&vmx->vcpu);
3700
3701 err = emulate_instruction(vcpu, 0);
3702
3703 if (err == EMULATE_DO_MMIO) {
3704 ret = 0;
3705 goto out;
3706 }
3707
3708 if (err != EMULATE_DONE)
3709 return 0;
3710
3711 if (signal_pending(current))
3712 goto out;
3713 if (need_resched())
3714 schedule();
3715 }
3716
3717 vmx->emulation_required = 0;
3718 out:
3719 return ret;
3720 }
3721
3722 /*
3723 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3724 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3725 */
3726 static int handle_pause(struct kvm_vcpu *vcpu)
3727 {
3728 skip_emulated_instruction(vcpu);
3729 kvm_vcpu_on_spin(vcpu);
3730
3731 return 1;
3732 }
3733
3734 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3735 {
3736 kvm_queue_exception(vcpu, UD_VECTOR);
3737 return 1;
3738 }
3739
3740 /*
3741 * The exit handlers return 1 if the exit was handled fully and guest execution
3742 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3743 * to be done to userspace and return 0.
3744 */
3745 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3746 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3747 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3748 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3749 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3750 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3751 [EXIT_REASON_CR_ACCESS] = handle_cr,
3752 [EXIT_REASON_DR_ACCESS] = handle_dr,
3753 [EXIT_REASON_CPUID] = handle_cpuid,
3754 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3755 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3756 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3757 [EXIT_REASON_HLT] = handle_halt,
3758 [EXIT_REASON_INVD] = handle_invd,
3759 [EXIT_REASON_INVLPG] = handle_invlpg,
3760 [EXIT_REASON_VMCALL] = handle_vmcall,
3761 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3762 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3763 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3764 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3765 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3766 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3767 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3768 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3769 [EXIT_REASON_VMON] = handle_vmx_insn,
3770 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3771 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3772 [EXIT_REASON_WBINVD] = handle_wbinvd,
3773 [EXIT_REASON_XSETBV] = handle_xsetbv,
3774 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3775 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3776 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3777 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3778 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3779 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3780 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3781 };
3782
3783 static const int kvm_vmx_max_exit_handlers =
3784 ARRAY_SIZE(kvm_vmx_exit_handlers);
3785
3786 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3787 {
3788 *info1 = vmcs_readl(EXIT_QUALIFICATION);
3789 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3790 }
3791
3792 /*
3793 * The guest has exited. See if we can fix it or if we need userspace
3794 * assistance.
3795 */
3796 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3797 {
3798 struct vcpu_vmx *vmx = to_vmx(vcpu);
3799 u32 exit_reason = vmx->exit_reason;
3800 u32 vectoring_info = vmx->idt_vectoring_info;
3801
3802 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
3803
3804 /* If guest state is invalid, start emulating */
3805 if (vmx->emulation_required && emulate_invalid_guest_state)
3806 return handle_invalid_guest_state(vcpu);
3807
3808 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3809 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3810 vcpu->run->fail_entry.hardware_entry_failure_reason
3811 = exit_reason;
3812 return 0;
3813 }
3814
3815 if (unlikely(vmx->fail)) {
3816 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3817 vcpu->run->fail_entry.hardware_entry_failure_reason
3818 = vmcs_read32(VM_INSTRUCTION_ERROR);
3819 return 0;
3820 }
3821
3822 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3823 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3824 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3825 exit_reason != EXIT_REASON_TASK_SWITCH))
3826 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3827 "(0x%x) and exit reason is 0x%x\n",
3828 __func__, vectoring_info, exit_reason);
3829
3830 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3831 if (vmx_interrupt_allowed(vcpu)) {
3832 vmx->soft_vnmi_blocked = 0;
3833 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3834 vcpu->arch.nmi_pending) {
3835 /*
3836 * This CPU don't support us in finding the end of an
3837 * NMI-blocked window if the guest runs with IRQs
3838 * disabled. So we pull the trigger after 1 s of
3839 * futile waiting, but inform the user about this.
3840 */
3841 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3842 "state on VCPU %d after 1 s timeout\n",
3843 __func__, vcpu->vcpu_id);
3844 vmx->soft_vnmi_blocked = 0;
3845 }
3846 }
3847
3848 if (exit_reason < kvm_vmx_max_exit_handlers
3849 && kvm_vmx_exit_handlers[exit_reason])
3850 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3851 else {
3852 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3853 vcpu->run->hw.hardware_exit_reason = exit_reason;
3854 }
3855 return 0;
3856 }
3857
3858 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3859 {
3860 if (irr == -1 || tpr < irr) {
3861 vmcs_write32(TPR_THRESHOLD, 0);
3862 return;
3863 }
3864
3865 vmcs_write32(TPR_THRESHOLD, irr);
3866 }
3867
3868 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
3869 {
3870 u32 exit_intr_info = vmx->exit_intr_info;
3871
3872 /* Handle machine checks before interrupts are enabled */
3873 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3874 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3875 && is_machine_check(exit_intr_info)))
3876 kvm_machine_check();
3877
3878 /* We need to handle NMIs before interrupts are enabled */
3879 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3880 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3881 kvm_before_handle_nmi(&vmx->vcpu);
3882 asm("int $2");
3883 kvm_after_handle_nmi(&vmx->vcpu);
3884 }
3885 }
3886
3887 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3888 {
3889 u32 exit_intr_info = vmx->exit_intr_info;
3890 bool unblock_nmi;
3891 u8 vector;
3892 bool idtv_info_valid;
3893
3894 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3895
3896 if (cpu_has_virtual_nmis()) {
3897 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3898 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3899 /*
3900 * SDM 3: 27.7.1.2 (September 2008)
3901 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3902 * a guest IRET fault.
3903 * SDM 3: 23.2.2 (September 2008)
3904 * Bit 12 is undefined in any of the following cases:
3905 * If the VM exit sets the valid bit in the IDT-vectoring
3906 * information field.
3907 * If the VM exit is due to a double fault.
3908 */
3909 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3910 vector != DF_VECTOR && !idtv_info_valid)
3911 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3912 GUEST_INTR_STATE_NMI);
3913 } else if (unlikely(vmx->soft_vnmi_blocked))
3914 vmx->vnmi_blocked_time +=
3915 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3916 }
3917
3918 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3919 u32 idt_vectoring_info,
3920 int instr_len_field,
3921 int error_code_field)
3922 {
3923 u8 vector;
3924 int type;
3925 bool idtv_info_valid;
3926
3927 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3928
3929 vmx->vcpu.arch.nmi_injected = false;
3930 kvm_clear_exception_queue(&vmx->vcpu);
3931 kvm_clear_interrupt_queue(&vmx->vcpu);
3932
3933 if (!idtv_info_valid)
3934 return;
3935
3936 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3937
3938 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3939 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3940
3941 switch (type) {
3942 case INTR_TYPE_NMI_INTR:
3943 vmx->vcpu.arch.nmi_injected = true;
3944 /*
3945 * SDM 3: 27.7.1.2 (September 2008)
3946 * Clear bit "block by NMI" before VM entry if a NMI
3947 * delivery faulted.
3948 */
3949 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3950 GUEST_INTR_STATE_NMI);
3951 break;
3952 case INTR_TYPE_SOFT_EXCEPTION:
3953 vmx->vcpu.arch.event_exit_inst_len =
3954 vmcs_read32(instr_len_field);
3955 /* fall through */
3956 case INTR_TYPE_HARD_EXCEPTION:
3957 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3958 u32 err = vmcs_read32(error_code_field);
3959 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3960 } else
3961 kvm_queue_exception(&vmx->vcpu, vector);
3962 break;
3963 case INTR_TYPE_SOFT_INTR:
3964 vmx->vcpu.arch.event_exit_inst_len =
3965 vmcs_read32(instr_len_field);
3966 /* fall through */
3967 case INTR_TYPE_EXT_INTR:
3968 kvm_queue_interrupt(&vmx->vcpu, vector,
3969 type == INTR_TYPE_SOFT_INTR);
3970 break;
3971 default:
3972 break;
3973 }
3974 }
3975
3976 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3977 {
3978 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3979 VM_EXIT_INSTRUCTION_LEN,
3980 IDT_VECTORING_ERROR_CODE);
3981 }
3982
3983 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3984 {
3985 __vmx_complete_interrupts(to_vmx(vcpu),
3986 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3987 VM_ENTRY_INSTRUCTION_LEN,
3988 VM_ENTRY_EXCEPTION_ERROR_CODE);
3989
3990 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3991 }
3992
3993 #ifdef CONFIG_X86_64
3994 #define R "r"
3995 #define Q "q"
3996 #else
3997 #define R "e"
3998 #define Q "l"
3999 #endif
4000
4001 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
4002 {
4003 struct vcpu_vmx *vmx = to_vmx(vcpu);
4004
4005 /* Record the guest's net vcpu time for enforced NMI injections. */
4006 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
4007 vmx->entry_time = ktime_get();
4008
4009 /* Don't enter VMX if guest state is invalid, let the exit handler
4010 start emulation until we arrive back to a valid state */
4011 if (vmx->emulation_required && emulate_invalid_guest_state)
4012 return;
4013
4014 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4015 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4016 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4017 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4018
4019 /* When single-stepping over STI and MOV SS, we must clear the
4020 * corresponding interruptibility bits in the guest state. Otherwise
4021 * vmentry fails as it then expects bit 14 (BS) in pending debug
4022 * exceptions being set, but that's not correct for the guest debugging
4023 * case. */
4024 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4025 vmx_set_interrupt_shadow(vcpu, 0);
4026
4027 asm(
4028 /* Store host registers */
4029 "push %%"R"dx; push %%"R"bp;"
4030 "push %%"R"cx \n\t" /* placeholder for guest rcx */
4031 "push %%"R"cx \n\t"
4032 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4033 "je 1f \n\t"
4034 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4035 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
4036 "1: \n\t"
4037 /* Reload cr2 if changed */
4038 "mov %c[cr2](%0), %%"R"ax \n\t"
4039 "mov %%cr2, %%"R"dx \n\t"
4040 "cmp %%"R"ax, %%"R"dx \n\t"
4041 "je 2f \n\t"
4042 "mov %%"R"ax, %%cr2 \n\t"
4043 "2: \n\t"
4044 /* Check if vmlaunch of vmresume is needed */
4045 "cmpl $0, %c[launched](%0) \n\t"
4046 /* Load guest registers. Don't clobber flags. */
4047 "mov %c[rax](%0), %%"R"ax \n\t"
4048 "mov %c[rbx](%0), %%"R"bx \n\t"
4049 "mov %c[rdx](%0), %%"R"dx \n\t"
4050 "mov %c[rsi](%0), %%"R"si \n\t"
4051 "mov %c[rdi](%0), %%"R"di \n\t"
4052 "mov %c[rbp](%0), %%"R"bp \n\t"
4053 #ifdef CONFIG_X86_64
4054 "mov %c[r8](%0), %%r8 \n\t"
4055 "mov %c[r9](%0), %%r9 \n\t"
4056 "mov %c[r10](%0), %%r10 \n\t"
4057 "mov %c[r11](%0), %%r11 \n\t"
4058 "mov %c[r12](%0), %%r12 \n\t"
4059 "mov %c[r13](%0), %%r13 \n\t"
4060 "mov %c[r14](%0), %%r14 \n\t"
4061 "mov %c[r15](%0), %%r15 \n\t"
4062 #endif
4063 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4064
4065 /* Enter guest mode */
4066 "jne .Llaunched \n\t"
4067 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4068 "jmp .Lkvm_vmx_return \n\t"
4069 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4070 ".Lkvm_vmx_return: "
4071 /* Save guest registers, load host registers, keep flags */
4072 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4073 "pop %0 \n\t"
4074 "mov %%"R"ax, %c[rax](%0) \n\t"
4075 "mov %%"R"bx, %c[rbx](%0) \n\t"
4076 "pop"Q" %c[rcx](%0) \n\t"
4077 "mov %%"R"dx, %c[rdx](%0) \n\t"
4078 "mov %%"R"si, %c[rsi](%0) \n\t"
4079 "mov %%"R"di, %c[rdi](%0) \n\t"
4080 "mov %%"R"bp, %c[rbp](%0) \n\t"
4081 #ifdef CONFIG_X86_64
4082 "mov %%r8, %c[r8](%0) \n\t"
4083 "mov %%r9, %c[r9](%0) \n\t"
4084 "mov %%r10, %c[r10](%0) \n\t"
4085 "mov %%r11, %c[r11](%0) \n\t"
4086 "mov %%r12, %c[r12](%0) \n\t"
4087 "mov %%r13, %c[r13](%0) \n\t"
4088 "mov %%r14, %c[r14](%0) \n\t"
4089 "mov %%r15, %c[r15](%0) \n\t"
4090 #endif
4091 "mov %%cr2, %%"R"ax \n\t"
4092 "mov %%"R"ax, %c[cr2](%0) \n\t"
4093
4094 "pop %%"R"bp; pop %%"R"dx \n\t"
4095 "setbe %c[fail](%0) \n\t"
4096 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4097 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4098 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4099 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4100 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4101 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4102 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4103 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4104 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4105 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4106 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4107 #ifdef CONFIG_X86_64
4108 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4109 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4110 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4111 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4112 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4113 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4114 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4115 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4116 #endif
4117 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4118 [wordsize]"i"(sizeof(ulong))
4119 : "cc", "memory"
4120 , R"ax", R"bx", R"di", R"si"
4121 #ifdef CONFIG_X86_64
4122 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4123 #endif
4124 );
4125
4126 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4127 | (1 << VCPU_EXREG_PDPTR)
4128 | (1 << VCPU_EXREG_CR3));
4129 vcpu->arch.regs_dirty = 0;
4130
4131 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4132
4133 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4134 vmx->launched = 1;
4135
4136 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4137 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4138
4139 vmx_complete_atomic_exit(vmx);
4140 vmx_recover_nmi_blocking(vmx);
4141 vmx_complete_interrupts(vmx);
4142 }
4143
4144 #undef R
4145 #undef Q
4146
4147 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4148 {
4149 struct vcpu_vmx *vmx = to_vmx(vcpu);
4150
4151 if (vmx->vmcs) {
4152 vcpu_clear(vmx);
4153 free_vmcs(vmx->vmcs);
4154 vmx->vmcs = NULL;
4155 }
4156 }
4157
4158 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4159 {
4160 struct vcpu_vmx *vmx = to_vmx(vcpu);
4161
4162 free_vpid(vmx);
4163 vmx_free_vmcs(vcpu);
4164 kfree(vmx->guest_msrs);
4165 kvm_vcpu_uninit(vcpu);
4166 kmem_cache_free(kvm_vcpu_cache, vmx);
4167 }
4168
4169 static inline void vmcs_init(struct vmcs *vmcs)
4170 {
4171 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4172
4173 if (!vmm_exclusive)
4174 kvm_cpu_vmxon(phys_addr);
4175
4176 vmcs_clear(vmcs);
4177
4178 if (!vmm_exclusive)
4179 kvm_cpu_vmxoff();
4180 }
4181
4182 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4183 {
4184 int err;
4185 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4186 int cpu;
4187
4188 if (!vmx)
4189 return ERR_PTR(-ENOMEM);
4190
4191 allocate_vpid(vmx);
4192
4193 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4194 if (err)
4195 goto free_vcpu;
4196
4197 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4198 if (!vmx->guest_msrs) {
4199 err = -ENOMEM;
4200 goto uninit_vcpu;
4201 }
4202
4203 vmx->vmcs = alloc_vmcs();
4204 if (!vmx->vmcs)
4205 goto free_msrs;
4206
4207 vmcs_init(vmx->vmcs);
4208
4209 cpu = get_cpu();
4210 vmx_vcpu_load(&vmx->vcpu, cpu);
4211 vmx->vcpu.cpu = cpu;
4212 err = vmx_vcpu_setup(vmx);
4213 vmx_vcpu_put(&vmx->vcpu);
4214 put_cpu();
4215 if (err)
4216 goto free_vmcs;
4217 if (vm_need_virtualize_apic_accesses(kvm))
4218 if (alloc_apic_access_page(kvm) != 0)
4219 goto free_vmcs;
4220
4221 if (enable_ept) {
4222 if (!kvm->arch.ept_identity_map_addr)
4223 kvm->arch.ept_identity_map_addr =
4224 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4225 err = -ENOMEM;
4226 if (alloc_identity_pagetable(kvm) != 0)
4227 goto free_vmcs;
4228 if (!init_rmode_identity_map(kvm))
4229 goto free_vmcs;
4230 }
4231
4232 return &vmx->vcpu;
4233
4234 free_vmcs:
4235 free_vmcs(vmx->vmcs);
4236 free_msrs:
4237 kfree(vmx->guest_msrs);
4238 uninit_vcpu:
4239 kvm_vcpu_uninit(&vmx->vcpu);
4240 free_vcpu:
4241 free_vpid(vmx);
4242 kmem_cache_free(kvm_vcpu_cache, vmx);
4243 return ERR_PTR(err);
4244 }
4245
4246 static void __init vmx_check_processor_compat(void *rtn)
4247 {
4248 struct vmcs_config vmcs_conf;
4249
4250 *(int *)rtn = 0;
4251 if (setup_vmcs_config(&vmcs_conf) < 0)
4252 *(int *)rtn = -EIO;
4253 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4254 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4255 smp_processor_id());
4256 *(int *)rtn = -EIO;
4257 }
4258 }
4259
4260 static int get_ept_level(void)
4261 {
4262 return VMX_EPT_DEFAULT_GAW + 1;
4263 }
4264
4265 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4266 {
4267 u64 ret;
4268
4269 /* For VT-d and EPT combination
4270 * 1. MMIO: always map as UC
4271 * 2. EPT with VT-d:
4272 * a. VT-d without snooping control feature: can't guarantee the
4273 * result, try to trust guest.
4274 * b. VT-d with snooping control feature: snooping control feature of
4275 * VT-d engine can guarantee the cache correctness. Just set it
4276 * to WB to keep consistent with host. So the same as item 3.
4277 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4278 * consistent with host MTRR
4279 */
4280 if (is_mmio)
4281 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4282 else if (vcpu->kvm->arch.iommu_domain &&
4283 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4284 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4285 VMX_EPT_MT_EPTE_SHIFT;
4286 else
4287 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4288 | VMX_EPT_IPAT_BIT;
4289
4290 return ret;
4291 }
4292
4293 #define _ER(x) { EXIT_REASON_##x, #x }
4294
4295 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4296 _ER(EXCEPTION_NMI),
4297 _ER(EXTERNAL_INTERRUPT),
4298 _ER(TRIPLE_FAULT),
4299 _ER(PENDING_INTERRUPT),
4300 _ER(NMI_WINDOW),
4301 _ER(TASK_SWITCH),
4302 _ER(CPUID),
4303 _ER(HLT),
4304 _ER(INVLPG),
4305 _ER(RDPMC),
4306 _ER(RDTSC),
4307 _ER(VMCALL),
4308 _ER(VMCLEAR),
4309 _ER(VMLAUNCH),
4310 _ER(VMPTRLD),
4311 _ER(VMPTRST),
4312 _ER(VMREAD),
4313 _ER(VMRESUME),
4314 _ER(VMWRITE),
4315 _ER(VMOFF),
4316 _ER(VMON),
4317 _ER(CR_ACCESS),
4318 _ER(DR_ACCESS),
4319 _ER(IO_INSTRUCTION),
4320 _ER(MSR_READ),
4321 _ER(MSR_WRITE),
4322 _ER(MWAIT_INSTRUCTION),
4323 _ER(MONITOR_INSTRUCTION),
4324 _ER(PAUSE_INSTRUCTION),
4325 _ER(MCE_DURING_VMENTRY),
4326 _ER(TPR_BELOW_THRESHOLD),
4327 _ER(APIC_ACCESS),
4328 _ER(EPT_VIOLATION),
4329 _ER(EPT_MISCONFIG),
4330 _ER(WBINVD),
4331 { -1, NULL }
4332 };
4333
4334 #undef _ER
4335
4336 static int vmx_get_lpage_level(void)
4337 {
4338 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4339 return PT_DIRECTORY_LEVEL;
4340 else
4341 /* For shadow and EPT supported 1GB page */
4342 return PT_PDPE_LEVEL;
4343 }
4344
4345 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4346 {
4347 struct kvm_cpuid_entry2 *best;
4348 struct vcpu_vmx *vmx = to_vmx(vcpu);
4349 u32 exec_control;
4350
4351 vmx->rdtscp_enabled = false;
4352 if (vmx_rdtscp_supported()) {
4353 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4354 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4355 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4356 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4357 vmx->rdtscp_enabled = true;
4358 else {
4359 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4360 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4361 exec_control);
4362 }
4363 }
4364 }
4365 }
4366
4367 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4368 {
4369 }
4370
4371 static struct kvm_x86_ops vmx_x86_ops = {
4372 .cpu_has_kvm_support = cpu_has_kvm_support,
4373 .disabled_by_bios = vmx_disabled_by_bios,
4374 .hardware_setup = hardware_setup,
4375 .hardware_unsetup = hardware_unsetup,
4376 .check_processor_compatibility = vmx_check_processor_compat,
4377 .hardware_enable = hardware_enable,
4378 .hardware_disable = hardware_disable,
4379 .cpu_has_accelerated_tpr = report_flexpriority,
4380
4381 .vcpu_create = vmx_create_vcpu,
4382 .vcpu_free = vmx_free_vcpu,
4383 .vcpu_reset = vmx_vcpu_reset,
4384
4385 .prepare_guest_switch = vmx_save_host_state,
4386 .vcpu_load = vmx_vcpu_load,
4387 .vcpu_put = vmx_vcpu_put,
4388
4389 .set_guest_debug = set_guest_debug,
4390 .get_msr = vmx_get_msr,
4391 .set_msr = vmx_set_msr,
4392 .get_segment_base = vmx_get_segment_base,
4393 .get_segment = vmx_get_segment,
4394 .set_segment = vmx_set_segment,
4395 .get_cpl = vmx_get_cpl,
4396 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4397 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4398 .decache_cr3 = vmx_decache_cr3,
4399 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4400 .set_cr0 = vmx_set_cr0,
4401 .set_cr3 = vmx_set_cr3,
4402 .set_cr4 = vmx_set_cr4,
4403 .set_efer = vmx_set_efer,
4404 .get_idt = vmx_get_idt,
4405 .set_idt = vmx_set_idt,
4406 .get_gdt = vmx_get_gdt,
4407 .set_gdt = vmx_set_gdt,
4408 .set_dr7 = vmx_set_dr7,
4409 .cache_reg = vmx_cache_reg,
4410 .get_rflags = vmx_get_rflags,
4411 .set_rflags = vmx_set_rflags,
4412 .fpu_activate = vmx_fpu_activate,
4413 .fpu_deactivate = vmx_fpu_deactivate,
4414
4415 .tlb_flush = vmx_flush_tlb,
4416
4417 .run = vmx_vcpu_run,
4418 .handle_exit = vmx_handle_exit,
4419 .skip_emulated_instruction = skip_emulated_instruction,
4420 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4421 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4422 .patch_hypercall = vmx_patch_hypercall,
4423 .set_irq = vmx_inject_irq,
4424 .set_nmi = vmx_inject_nmi,
4425 .queue_exception = vmx_queue_exception,
4426 .cancel_injection = vmx_cancel_injection,
4427 .interrupt_allowed = vmx_interrupt_allowed,
4428 .nmi_allowed = vmx_nmi_allowed,
4429 .get_nmi_mask = vmx_get_nmi_mask,
4430 .set_nmi_mask = vmx_set_nmi_mask,
4431 .enable_nmi_window = enable_nmi_window,
4432 .enable_irq_window = enable_irq_window,
4433 .update_cr8_intercept = update_cr8_intercept,
4434
4435 .set_tss_addr = vmx_set_tss_addr,
4436 .get_tdp_level = get_ept_level,
4437 .get_mt_mask = vmx_get_mt_mask,
4438
4439 .get_exit_info = vmx_get_exit_info,
4440 .exit_reasons_str = vmx_exit_reasons_str,
4441
4442 .get_lpage_level = vmx_get_lpage_level,
4443
4444 .cpuid_update = vmx_cpuid_update,
4445
4446 .rdtscp_supported = vmx_rdtscp_supported,
4447
4448 .set_supported_cpuid = vmx_set_supported_cpuid,
4449
4450 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4451
4452 .write_tsc_offset = vmx_write_tsc_offset,
4453 .adjust_tsc_offset = vmx_adjust_tsc_offset,
4454
4455 .set_tdp_cr3 = vmx_set_cr3,
4456 };
4457
4458 static int __init vmx_init(void)
4459 {
4460 int r, i;
4461
4462 rdmsrl_safe(MSR_EFER, &host_efer);
4463
4464 for (i = 0; i < NR_VMX_MSR; ++i)
4465 kvm_define_shared_msr(i, vmx_msr_index[i]);
4466
4467 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4468 if (!vmx_io_bitmap_a)
4469 return -ENOMEM;
4470
4471 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4472 if (!vmx_io_bitmap_b) {
4473 r = -ENOMEM;
4474 goto out;
4475 }
4476
4477 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4478 if (!vmx_msr_bitmap_legacy) {
4479 r = -ENOMEM;
4480 goto out1;
4481 }
4482
4483 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4484 if (!vmx_msr_bitmap_longmode) {
4485 r = -ENOMEM;
4486 goto out2;
4487 }
4488
4489 /*
4490 * Allow direct access to the PC debug port (it is often used for I/O
4491 * delays, but the vmexits simply slow things down).
4492 */
4493 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4494 clear_bit(0x80, vmx_io_bitmap_a);
4495
4496 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4497
4498 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4499 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4500
4501 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4502
4503 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4504 __alignof__(struct vcpu_vmx), THIS_MODULE);
4505 if (r)
4506 goto out3;
4507
4508 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4509 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4510 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4511 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4512 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4513 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4514
4515 if (enable_ept) {
4516 bypass_guest_pf = 0;
4517 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4518 VMX_EPT_EXECUTABLE_MASK);
4519 kvm_enable_tdp();
4520 } else
4521 kvm_disable_tdp();
4522
4523 if (bypass_guest_pf)
4524 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4525
4526 return 0;
4527
4528 out3:
4529 free_page((unsigned long)vmx_msr_bitmap_longmode);
4530 out2:
4531 free_page((unsigned long)vmx_msr_bitmap_legacy);
4532 out1:
4533 free_page((unsigned long)vmx_io_bitmap_b);
4534 out:
4535 free_page((unsigned long)vmx_io_bitmap_a);
4536 return r;
4537 }
4538
4539 static void __exit vmx_exit(void)
4540 {
4541 free_page((unsigned long)vmx_msr_bitmap_legacy);
4542 free_page((unsigned long)vmx_msr_bitmap_longmode);
4543 free_page((unsigned long)vmx_io_bitmap_b);
4544 free_page((unsigned long)vmx_io_bitmap_a);
4545
4546 kvm_exit();
4547 }
4548
4549 module_init(vmx_init)
4550 module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)