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KVM: VMX: Ensure that vmx_create_vcpu always returns proper error
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42
43 #include "trace.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
49
50 static int __read_mostly bypass_guest_pf = 1;
51 module_param(bypass_guest_pf, bool, S_IRUGO);
52
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
55
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
58
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
61
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
68
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
71
72 static int __read_mostly yield_on_hlt = 1;
73 module_param(yield_on_hlt, bool, S_IRUGO);
74
75 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
76 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
77 #define KVM_GUEST_CR0_MASK \
78 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
79 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
80 (X86_CR0_WP | X86_CR0_NE)
81 #define KVM_VM_CR0_ALWAYS_ON \
82 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
83 #define KVM_CR4_GUEST_OWNED_BITS \
84 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
85 | X86_CR4_OSXMMEXCPT)
86
87 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
88 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
89
90 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
91
92 /*
93 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
94 * ple_gap: upper bound on the amount of time between two successive
95 * executions of PAUSE in a loop. Also indicate if ple enabled.
96 * According to test, this time is usually smaller than 128 cycles.
97 * ple_window: upper bound on the amount of time a guest is allowed to execute
98 * in a PAUSE loop. Tests indicate that most spinlocks are held for
99 * less than 2^12 cycles
100 * Time is measured based on a counter that runs at the same rate as the TSC,
101 * refer SDM volume 3b section 21.6.13 & 22.1.3.
102 */
103 #define KVM_VMX_DEFAULT_PLE_GAP 128
104 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
105 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
106 module_param(ple_gap, int, S_IRUGO);
107
108 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
109 module_param(ple_window, int, S_IRUGO);
110
111 #define NR_AUTOLOAD_MSRS 1
112
113 struct vmcs {
114 u32 revision_id;
115 u32 abort;
116 char data[0];
117 };
118
119 struct shared_msr_entry {
120 unsigned index;
121 u64 data;
122 u64 mask;
123 };
124
125 struct vcpu_vmx {
126 struct kvm_vcpu vcpu;
127 struct list_head local_vcpus_link;
128 unsigned long host_rsp;
129 int launched;
130 u8 fail;
131 u8 cpl;
132 bool nmi_known_unmasked;
133 u32 exit_intr_info;
134 u32 idt_vectoring_info;
135 ulong rflags;
136 struct shared_msr_entry *guest_msrs;
137 int nmsrs;
138 int save_nmsrs;
139 #ifdef CONFIG_X86_64
140 u64 msr_host_kernel_gs_base;
141 u64 msr_guest_kernel_gs_base;
142 #endif
143 struct vmcs *vmcs;
144 struct msr_autoload {
145 unsigned nr;
146 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
147 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
148 } msr_autoload;
149 struct {
150 int loaded;
151 u16 fs_sel, gs_sel, ldt_sel;
152 int gs_ldt_reload_needed;
153 int fs_reload_needed;
154 } host_state;
155 struct {
156 int vm86_active;
157 ulong save_rflags;
158 struct kvm_save_segment {
159 u16 selector;
160 unsigned long base;
161 u32 limit;
162 u32 ar;
163 } tr, es, ds, fs, gs;
164 } rmode;
165 int vpid;
166 bool emulation_required;
167
168 /* Support for vnmi-less CPUs */
169 int soft_vnmi_blocked;
170 ktime_t entry_time;
171 s64 vnmi_blocked_time;
172 u32 exit_reason;
173
174 bool rdtscp_enabled;
175 };
176
177 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
178 {
179 return container_of(vcpu, struct vcpu_vmx, vcpu);
180 }
181
182 static u64 construct_eptp(unsigned long root_hpa);
183 static void kvm_cpu_vmxon(u64 addr);
184 static void kvm_cpu_vmxoff(void);
185 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
186 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
187
188 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
189 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
190 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
191 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
192
193 static unsigned long *vmx_io_bitmap_a;
194 static unsigned long *vmx_io_bitmap_b;
195 static unsigned long *vmx_msr_bitmap_legacy;
196 static unsigned long *vmx_msr_bitmap_longmode;
197
198 static bool cpu_has_load_ia32_efer;
199
200 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
201 static DEFINE_SPINLOCK(vmx_vpid_lock);
202
203 static struct vmcs_config {
204 int size;
205 int order;
206 u32 revision_id;
207 u32 pin_based_exec_ctrl;
208 u32 cpu_based_exec_ctrl;
209 u32 cpu_based_2nd_exec_ctrl;
210 u32 vmexit_ctrl;
211 u32 vmentry_ctrl;
212 } vmcs_config;
213
214 static struct vmx_capability {
215 u32 ept;
216 u32 vpid;
217 } vmx_capability;
218
219 #define VMX_SEGMENT_FIELD(seg) \
220 [VCPU_SREG_##seg] = { \
221 .selector = GUEST_##seg##_SELECTOR, \
222 .base = GUEST_##seg##_BASE, \
223 .limit = GUEST_##seg##_LIMIT, \
224 .ar_bytes = GUEST_##seg##_AR_BYTES, \
225 }
226
227 static struct kvm_vmx_segment_field {
228 unsigned selector;
229 unsigned base;
230 unsigned limit;
231 unsigned ar_bytes;
232 } kvm_vmx_segment_fields[] = {
233 VMX_SEGMENT_FIELD(CS),
234 VMX_SEGMENT_FIELD(DS),
235 VMX_SEGMENT_FIELD(ES),
236 VMX_SEGMENT_FIELD(FS),
237 VMX_SEGMENT_FIELD(GS),
238 VMX_SEGMENT_FIELD(SS),
239 VMX_SEGMENT_FIELD(TR),
240 VMX_SEGMENT_FIELD(LDTR),
241 };
242
243 static u64 host_efer;
244
245 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
246
247 /*
248 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
249 * away by decrementing the array size.
250 */
251 static const u32 vmx_msr_index[] = {
252 #ifdef CONFIG_X86_64
253 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
254 #endif
255 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
256 };
257 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
258
259 static inline bool is_page_fault(u32 intr_info)
260 {
261 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
262 INTR_INFO_VALID_MASK)) ==
263 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
264 }
265
266 static inline bool is_no_device(u32 intr_info)
267 {
268 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
269 INTR_INFO_VALID_MASK)) ==
270 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
271 }
272
273 static inline bool is_invalid_opcode(u32 intr_info)
274 {
275 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
276 INTR_INFO_VALID_MASK)) ==
277 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
278 }
279
280 static inline bool is_external_interrupt(u32 intr_info)
281 {
282 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
283 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
284 }
285
286 static inline bool is_machine_check(u32 intr_info)
287 {
288 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
289 INTR_INFO_VALID_MASK)) ==
290 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
291 }
292
293 static inline bool cpu_has_vmx_msr_bitmap(void)
294 {
295 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
296 }
297
298 static inline bool cpu_has_vmx_tpr_shadow(void)
299 {
300 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
301 }
302
303 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
304 {
305 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
306 }
307
308 static inline bool cpu_has_secondary_exec_ctrls(void)
309 {
310 return vmcs_config.cpu_based_exec_ctrl &
311 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
312 }
313
314 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
315 {
316 return vmcs_config.cpu_based_2nd_exec_ctrl &
317 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
318 }
319
320 static inline bool cpu_has_vmx_flexpriority(void)
321 {
322 return cpu_has_vmx_tpr_shadow() &&
323 cpu_has_vmx_virtualize_apic_accesses();
324 }
325
326 static inline bool cpu_has_vmx_ept_execute_only(void)
327 {
328 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
329 }
330
331 static inline bool cpu_has_vmx_eptp_uncacheable(void)
332 {
333 return vmx_capability.ept & VMX_EPTP_UC_BIT;
334 }
335
336 static inline bool cpu_has_vmx_eptp_writeback(void)
337 {
338 return vmx_capability.ept & VMX_EPTP_WB_BIT;
339 }
340
341 static inline bool cpu_has_vmx_ept_2m_page(void)
342 {
343 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
344 }
345
346 static inline bool cpu_has_vmx_ept_1g_page(void)
347 {
348 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
349 }
350
351 static inline bool cpu_has_vmx_ept_4levels(void)
352 {
353 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
354 }
355
356 static inline bool cpu_has_vmx_invept_individual_addr(void)
357 {
358 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
359 }
360
361 static inline bool cpu_has_vmx_invept_context(void)
362 {
363 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
364 }
365
366 static inline bool cpu_has_vmx_invept_global(void)
367 {
368 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
369 }
370
371 static inline bool cpu_has_vmx_invvpid_single(void)
372 {
373 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
374 }
375
376 static inline bool cpu_has_vmx_invvpid_global(void)
377 {
378 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
379 }
380
381 static inline bool cpu_has_vmx_ept(void)
382 {
383 return vmcs_config.cpu_based_2nd_exec_ctrl &
384 SECONDARY_EXEC_ENABLE_EPT;
385 }
386
387 static inline bool cpu_has_vmx_unrestricted_guest(void)
388 {
389 return vmcs_config.cpu_based_2nd_exec_ctrl &
390 SECONDARY_EXEC_UNRESTRICTED_GUEST;
391 }
392
393 static inline bool cpu_has_vmx_ple(void)
394 {
395 return vmcs_config.cpu_based_2nd_exec_ctrl &
396 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
397 }
398
399 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
400 {
401 return flexpriority_enabled && irqchip_in_kernel(kvm);
402 }
403
404 static inline bool cpu_has_vmx_vpid(void)
405 {
406 return vmcs_config.cpu_based_2nd_exec_ctrl &
407 SECONDARY_EXEC_ENABLE_VPID;
408 }
409
410 static inline bool cpu_has_vmx_rdtscp(void)
411 {
412 return vmcs_config.cpu_based_2nd_exec_ctrl &
413 SECONDARY_EXEC_RDTSCP;
414 }
415
416 static inline bool cpu_has_virtual_nmis(void)
417 {
418 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
419 }
420
421 static inline bool cpu_has_vmx_wbinvd_exit(void)
422 {
423 return vmcs_config.cpu_based_2nd_exec_ctrl &
424 SECONDARY_EXEC_WBINVD_EXITING;
425 }
426
427 static inline bool report_flexpriority(void)
428 {
429 return flexpriority_enabled;
430 }
431
432 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
433 {
434 int i;
435
436 for (i = 0; i < vmx->nmsrs; ++i)
437 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
438 return i;
439 return -1;
440 }
441
442 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
443 {
444 struct {
445 u64 vpid : 16;
446 u64 rsvd : 48;
447 u64 gva;
448 } operand = { vpid, 0, gva };
449
450 asm volatile (__ex(ASM_VMX_INVVPID)
451 /* CF==1 or ZF==1 --> rc = -1 */
452 "; ja 1f ; ud2 ; 1:"
453 : : "a"(&operand), "c"(ext) : "cc", "memory");
454 }
455
456 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
457 {
458 struct {
459 u64 eptp, gpa;
460 } operand = {eptp, gpa};
461
462 asm volatile (__ex(ASM_VMX_INVEPT)
463 /* CF==1 or ZF==1 --> rc = -1 */
464 "; ja 1f ; ud2 ; 1:\n"
465 : : "a" (&operand), "c" (ext) : "cc", "memory");
466 }
467
468 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
469 {
470 int i;
471
472 i = __find_msr_index(vmx, msr);
473 if (i >= 0)
474 return &vmx->guest_msrs[i];
475 return NULL;
476 }
477
478 static void vmcs_clear(struct vmcs *vmcs)
479 {
480 u64 phys_addr = __pa(vmcs);
481 u8 error;
482
483 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
484 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
485 : "cc", "memory");
486 if (error)
487 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
488 vmcs, phys_addr);
489 }
490
491 static void vmcs_load(struct vmcs *vmcs)
492 {
493 u64 phys_addr = __pa(vmcs);
494 u8 error;
495
496 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
497 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
498 : "cc", "memory");
499 if (error)
500 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
501 vmcs, phys_addr);
502 }
503
504 static void __vcpu_clear(void *arg)
505 {
506 struct vcpu_vmx *vmx = arg;
507 int cpu = raw_smp_processor_id();
508
509 if (vmx->vcpu.cpu == cpu)
510 vmcs_clear(vmx->vmcs);
511 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
512 per_cpu(current_vmcs, cpu) = NULL;
513 list_del(&vmx->local_vcpus_link);
514 vmx->vcpu.cpu = -1;
515 vmx->launched = 0;
516 }
517
518 static void vcpu_clear(struct vcpu_vmx *vmx)
519 {
520 if (vmx->vcpu.cpu == -1)
521 return;
522 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
523 }
524
525 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
526 {
527 if (vmx->vpid == 0)
528 return;
529
530 if (cpu_has_vmx_invvpid_single())
531 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
532 }
533
534 static inline void vpid_sync_vcpu_global(void)
535 {
536 if (cpu_has_vmx_invvpid_global())
537 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
538 }
539
540 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
541 {
542 if (cpu_has_vmx_invvpid_single())
543 vpid_sync_vcpu_single(vmx);
544 else
545 vpid_sync_vcpu_global();
546 }
547
548 static inline void ept_sync_global(void)
549 {
550 if (cpu_has_vmx_invept_global())
551 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
552 }
553
554 static inline void ept_sync_context(u64 eptp)
555 {
556 if (enable_ept) {
557 if (cpu_has_vmx_invept_context())
558 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
559 else
560 ept_sync_global();
561 }
562 }
563
564 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
565 {
566 if (enable_ept) {
567 if (cpu_has_vmx_invept_individual_addr())
568 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
569 eptp, gpa);
570 else
571 ept_sync_context(eptp);
572 }
573 }
574
575 static unsigned long vmcs_readl(unsigned long field)
576 {
577 unsigned long value = 0;
578
579 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
580 : "+a"(value) : "d"(field) : "cc");
581 return value;
582 }
583
584 static u16 vmcs_read16(unsigned long field)
585 {
586 return vmcs_readl(field);
587 }
588
589 static u32 vmcs_read32(unsigned long field)
590 {
591 return vmcs_readl(field);
592 }
593
594 static u64 vmcs_read64(unsigned long field)
595 {
596 #ifdef CONFIG_X86_64
597 return vmcs_readl(field);
598 #else
599 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
600 #endif
601 }
602
603 static noinline void vmwrite_error(unsigned long field, unsigned long value)
604 {
605 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
606 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
607 dump_stack();
608 }
609
610 static void vmcs_writel(unsigned long field, unsigned long value)
611 {
612 u8 error;
613
614 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
615 : "=q"(error) : "a"(value), "d"(field) : "cc");
616 if (unlikely(error))
617 vmwrite_error(field, value);
618 }
619
620 static void vmcs_write16(unsigned long field, u16 value)
621 {
622 vmcs_writel(field, value);
623 }
624
625 static void vmcs_write32(unsigned long field, u32 value)
626 {
627 vmcs_writel(field, value);
628 }
629
630 static void vmcs_write64(unsigned long field, u64 value)
631 {
632 vmcs_writel(field, value);
633 #ifndef CONFIG_X86_64
634 asm volatile ("");
635 vmcs_writel(field+1, value >> 32);
636 #endif
637 }
638
639 static void vmcs_clear_bits(unsigned long field, u32 mask)
640 {
641 vmcs_writel(field, vmcs_readl(field) & ~mask);
642 }
643
644 static void vmcs_set_bits(unsigned long field, u32 mask)
645 {
646 vmcs_writel(field, vmcs_readl(field) | mask);
647 }
648
649 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
650 {
651 u32 eb;
652
653 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
654 (1u << NM_VECTOR) | (1u << DB_VECTOR);
655 if ((vcpu->guest_debug &
656 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
657 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
658 eb |= 1u << BP_VECTOR;
659 if (to_vmx(vcpu)->rmode.vm86_active)
660 eb = ~0;
661 if (enable_ept)
662 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
663 if (vcpu->fpu_active)
664 eb &= ~(1u << NM_VECTOR);
665 vmcs_write32(EXCEPTION_BITMAP, eb);
666 }
667
668 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
669 {
670 unsigned i;
671 struct msr_autoload *m = &vmx->msr_autoload;
672
673 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
674 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
675 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
676 return;
677 }
678
679 for (i = 0; i < m->nr; ++i)
680 if (m->guest[i].index == msr)
681 break;
682
683 if (i == m->nr)
684 return;
685 --m->nr;
686 m->guest[i] = m->guest[m->nr];
687 m->host[i] = m->host[m->nr];
688 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
689 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
690 }
691
692 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
693 u64 guest_val, u64 host_val)
694 {
695 unsigned i;
696 struct msr_autoload *m = &vmx->msr_autoload;
697
698 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
699 vmcs_write64(GUEST_IA32_EFER, guest_val);
700 vmcs_write64(HOST_IA32_EFER, host_val);
701 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
702 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
703 return;
704 }
705
706 for (i = 0; i < m->nr; ++i)
707 if (m->guest[i].index == msr)
708 break;
709
710 if (i == m->nr) {
711 ++m->nr;
712 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
713 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
714 }
715
716 m->guest[i].index = msr;
717 m->guest[i].value = guest_val;
718 m->host[i].index = msr;
719 m->host[i].value = host_val;
720 }
721
722 static void reload_tss(void)
723 {
724 /*
725 * VT restores TR but not its size. Useless.
726 */
727 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
728 struct desc_struct *descs;
729
730 descs = (void *)gdt->address;
731 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
732 load_TR_desc();
733 }
734
735 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
736 {
737 u64 guest_efer;
738 u64 ignore_bits;
739
740 guest_efer = vmx->vcpu.arch.efer;
741
742 /*
743 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
744 * outside long mode
745 */
746 ignore_bits = EFER_NX | EFER_SCE;
747 #ifdef CONFIG_X86_64
748 ignore_bits |= EFER_LMA | EFER_LME;
749 /* SCE is meaningful only in long mode on Intel */
750 if (guest_efer & EFER_LMA)
751 ignore_bits &= ~(u64)EFER_SCE;
752 #endif
753 guest_efer &= ~ignore_bits;
754 guest_efer |= host_efer & ignore_bits;
755 vmx->guest_msrs[efer_offset].data = guest_efer;
756 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
757
758 clear_atomic_switch_msr(vmx, MSR_EFER);
759 /* On ept, can't emulate nx, and must switch nx atomically */
760 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
761 guest_efer = vmx->vcpu.arch.efer;
762 if (!(guest_efer & EFER_LMA))
763 guest_efer &= ~EFER_LME;
764 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
765 return false;
766 }
767
768 return true;
769 }
770
771 static unsigned long segment_base(u16 selector)
772 {
773 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
774 struct desc_struct *d;
775 unsigned long table_base;
776 unsigned long v;
777
778 if (!(selector & ~3))
779 return 0;
780
781 table_base = gdt->address;
782
783 if (selector & 4) { /* from ldt */
784 u16 ldt_selector = kvm_read_ldt();
785
786 if (!(ldt_selector & ~3))
787 return 0;
788
789 table_base = segment_base(ldt_selector);
790 }
791 d = (struct desc_struct *)(table_base + (selector & ~7));
792 v = get_desc_base(d);
793 #ifdef CONFIG_X86_64
794 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
795 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
796 #endif
797 return v;
798 }
799
800 static inline unsigned long kvm_read_tr_base(void)
801 {
802 u16 tr;
803 asm("str %0" : "=g"(tr));
804 return segment_base(tr);
805 }
806
807 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
808 {
809 struct vcpu_vmx *vmx = to_vmx(vcpu);
810 int i;
811
812 if (vmx->host_state.loaded)
813 return;
814
815 vmx->host_state.loaded = 1;
816 /*
817 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
818 * allow segment selectors with cpl > 0 or ti == 1.
819 */
820 vmx->host_state.ldt_sel = kvm_read_ldt();
821 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
822 savesegment(fs, vmx->host_state.fs_sel);
823 if (!(vmx->host_state.fs_sel & 7)) {
824 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
825 vmx->host_state.fs_reload_needed = 0;
826 } else {
827 vmcs_write16(HOST_FS_SELECTOR, 0);
828 vmx->host_state.fs_reload_needed = 1;
829 }
830 savesegment(gs, vmx->host_state.gs_sel);
831 if (!(vmx->host_state.gs_sel & 7))
832 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
833 else {
834 vmcs_write16(HOST_GS_SELECTOR, 0);
835 vmx->host_state.gs_ldt_reload_needed = 1;
836 }
837
838 #ifdef CONFIG_X86_64
839 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
840 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
841 #else
842 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
843 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
844 #endif
845
846 #ifdef CONFIG_X86_64
847 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
848 if (is_long_mode(&vmx->vcpu))
849 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
850 #endif
851 for (i = 0; i < vmx->save_nmsrs; ++i)
852 kvm_set_shared_msr(vmx->guest_msrs[i].index,
853 vmx->guest_msrs[i].data,
854 vmx->guest_msrs[i].mask);
855 }
856
857 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
858 {
859 if (!vmx->host_state.loaded)
860 return;
861
862 ++vmx->vcpu.stat.host_state_reload;
863 vmx->host_state.loaded = 0;
864 #ifdef CONFIG_X86_64
865 if (is_long_mode(&vmx->vcpu))
866 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
867 #endif
868 if (vmx->host_state.gs_ldt_reload_needed) {
869 kvm_load_ldt(vmx->host_state.ldt_sel);
870 #ifdef CONFIG_X86_64
871 load_gs_index(vmx->host_state.gs_sel);
872 #else
873 loadsegment(gs, vmx->host_state.gs_sel);
874 #endif
875 }
876 if (vmx->host_state.fs_reload_needed)
877 loadsegment(fs, vmx->host_state.fs_sel);
878 reload_tss();
879 #ifdef CONFIG_X86_64
880 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
881 #endif
882 if (current_thread_info()->status & TS_USEDFPU)
883 clts();
884 load_gdt(&__get_cpu_var(host_gdt));
885 }
886
887 static void vmx_load_host_state(struct vcpu_vmx *vmx)
888 {
889 preempt_disable();
890 __vmx_load_host_state(vmx);
891 preempt_enable();
892 }
893
894 /*
895 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
896 * vcpu mutex is already taken.
897 */
898 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
899 {
900 struct vcpu_vmx *vmx = to_vmx(vcpu);
901 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
902
903 if (!vmm_exclusive)
904 kvm_cpu_vmxon(phys_addr);
905 else if (vcpu->cpu != cpu)
906 vcpu_clear(vmx);
907
908 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
909 per_cpu(current_vmcs, cpu) = vmx->vmcs;
910 vmcs_load(vmx->vmcs);
911 }
912
913 if (vcpu->cpu != cpu) {
914 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
915 unsigned long sysenter_esp;
916
917 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
918 local_irq_disable();
919 list_add(&vmx->local_vcpus_link,
920 &per_cpu(vcpus_on_cpu, cpu));
921 local_irq_enable();
922
923 /*
924 * Linux uses per-cpu TSS and GDT, so set these when switching
925 * processors.
926 */
927 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
928 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
929
930 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
931 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
932 }
933 }
934
935 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
936 {
937 __vmx_load_host_state(to_vmx(vcpu));
938 if (!vmm_exclusive) {
939 __vcpu_clear(to_vmx(vcpu));
940 kvm_cpu_vmxoff();
941 }
942 }
943
944 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
945 {
946 ulong cr0;
947
948 if (vcpu->fpu_active)
949 return;
950 vcpu->fpu_active = 1;
951 cr0 = vmcs_readl(GUEST_CR0);
952 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
953 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
954 vmcs_writel(GUEST_CR0, cr0);
955 update_exception_bitmap(vcpu);
956 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
957 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
958 }
959
960 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
961
962 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
963 {
964 vmx_decache_cr0_guest_bits(vcpu);
965 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
966 update_exception_bitmap(vcpu);
967 vcpu->arch.cr0_guest_owned_bits = 0;
968 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
969 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
970 }
971
972 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
973 {
974 unsigned long rflags, save_rflags;
975
976 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
977 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
978 rflags = vmcs_readl(GUEST_RFLAGS);
979 if (to_vmx(vcpu)->rmode.vm86_active) {
980 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
981 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
982 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
983 }
984 to_vmx(vcpu)->rflags = rflags;
985 }
986 return to_vmx(vcpu)->rflags;
987 }
988
989 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
990 {
991 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
992 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
993 to_vmx(vcpu)->rflags = rflags;
994 if (to_vmx(vcpu)->rmode.vm86_active) {
995 to_vmx(vcpu)->rmode.save_rflags = rflags;
996 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
997 }
998 vmcs_writel(GUEST_RFLAGS, rflags);
999 }
1000
1001 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1002 {
1003 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1004 int ret = 0;
1005
1006 if (interruptibility & GUEST_INTR_STATE_STI)
1007 ret |= KVM_X86_SHADOW_INT_STI;
1008 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1009 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1010
1011 return ret & mask;
1012 }
1013
1014 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1015 {
1016 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1017 u32 interruptibility = interruptibility_old;
1018
1019 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1020
1021 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1022 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1023 else if (mask & KVM_X86_SHADOW_INT_STI)
1024 interruptibility |= GUEST_INTR_STATE_STI;
1025
1026 if ((interruptibility != interruptibility_old))
1027 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1028 }
1029
1030 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1031 {
1032 unsigned long rip;
1033
1034 rip = kvm_rip_read(vcpu);
1035 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1036 kvm_rip_write(vcpu, rip);
1037
1038 /* skipping an emulated instruction also counts */
1039 vmx_set_interrupt_shadow(vcpu, 0);
1040 }
1041
1042 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1043 {
1044 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1045 * explicitly skip the instruction because if the HLT state is set, then
1046 * the instruction is already executing and RIP has already been
1047 * advanced. */
1048 if (!yield_on_hlt &&
1049 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1050 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1051 }
1052
1053 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1054 bool has_error_code, u32 error_code,
1055 bool reinject)
1056 {
1057 struct vcpu_vmx *vmx = to_vmx(vcpu);
1058 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1059
1060 if (has_error_code) {
1061 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1062 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1063 }
1064
1065 if (vmx->rmode.vm86_active) {
1066 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1067 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1068 return;
1069 }
1070
1071 if (kvm_exception_is_soft(nr)) {
1072 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1073 vmx->vcpu.arch.event_exit_inst_len);
1074 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1075 } else
1076 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1077
1078 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1079 vmx_clear_hlt(vcpu);
1080 }
1081
1082 static bool vmx_rdtscp_supported(void)
1083 {
1084 return cpu_has_vmx_rdtscp();
1085 }
1086
1087 /*
1088 * Swap MSR entry in host/guest MSR entry array.
1089 */
1090 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1091 {
1092 struct shared_msr_entry tmp;
1093
1094 tmp = vmx->guest_msrs[to];
1095 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1096 vmx->guest_msrs[from] = tmp;
1097 }
1098
1099 /*
1100 * Set up the vmcs to automatically save and restore system
1101 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1102 * mode, as fiddling with msrs is very expensive.
1103 */
1104 static void setup_msrs(struct vcpu_vmx *vmx)
1105 {
1106 int save_nmsrs, index;
1107 unsigned long *msr_bitmap;
1108
1109 vmx_load_host_state(vmx);
1110 save_nmsrs = 0;
1111 #ifdef CONFIG_X86_64
1112 if (is_long_mode(&vmx->vcpu)) {
1113 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1114 if (index >= 0)
1115 move_msr_up(vmx, index, save_nmsrs++);
1116 index = __find_msr_index(vmx, MSR_LSTAR);
1117 if (index >= 0)
1118 move_msr_up(vmx, index, save_nmsrs++);
1119 index = __find_msr_index(vmx, MSR_CSTAR);
1120 if (index >= 0)
1121 move_msr_up(vmx, index, save_nmsrs++);
1122 index = __find_msr_index(vmx, MSR_TSC_AUX);
1123 if (index >= 0 && vmx->rdtscp_enabled)
1124 move_msr_up(vmx, index, save_nmsrs++);
1125 /*
1126 * MSR_STAR is only needed on long mode guests, and only
1127 * if efer.sce is enabled.
1128 */
1129 index = __find_msr_index(vmx, MSR_STAR);
1130 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1131 move_msr_up(vmx, index, save_nmsrs++);
1132 }
1133 #endif
1134 index = __find_msr_index(vmx, MSR_EFER);
1135 if (index >= 0 && update_transition_efer(vmx, index))
1136 move_msr_up(vmx, index, save_nmsrs++);
1137
1138 vmx->save_nmsrs = save_nmsrs;
1139
1140 if (cpu_has_vmx_msr_bitmap()) {
1141 if (is_long_mode(&vmx->vcpu))
1142 msr_bitmap = vmx_msr_bitmap_longmode;
1143 else
1144 msr_bitmap = vmx_msr_bitmap_legacy;
1145
1146 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1147 }
1148 }
1149
1150 /*
1151 * reads and returns guest's timestamp counter "register"
1152 * guest_tsc = host_tsc + tsc_offset -- 21.3
1153 */
1154 static u64 guest_read_tsc(void)
1155 {
1156 u64 host_tsc, tsc_offset;
1157
1158 rdtscll(host_tsc);
1159 tsc_offset = vmcs_read64(TSC_OFFSET);
1160 return host_tsc + tsc_offset;
1161 }
1162
1163 /*
1164 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1165 * ioctl. In this case the call-back should update internal vmx state to make
1166 * the changes effective.
1167 */
1168 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1169 {
1170 /* Nothing to do here */
1171 }
1172
1173 /*
1174 * writes 'offset' into guest's timestamp counter offset register
1175 */
1176 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1177 {
1178 vmcs_write64(TSC_OFFSET, offset);
1179 }
1180
1181 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1182 {
1183 u64 offset = vmcs_read64(TSC_OFFSET);
1184 vmcs_write64(TSC_OFFSET, offset + adjustment);
1185 }
1186
1187 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1188 {
1189 return target_tsc - native_read_tsc();
1190 }
1191
1192 /*
1193 * Reads an msr value (of 'msr_index') into 'pdata'.
1194 * Returns 0 on success, non-0 otherwise.
1195 * Assumes vcpu_load() was already called.
1196 */
1197 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1198 {
1199 u64 data;
1200 struct shared_msr_entry *msr;
1201
1202 if (!pdata) {
1203 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1204 return -EINVAL;
1205 }
1206
1207 switch (msr_index) {
1208 #ifdef CONFIG_X86_64
1209 case MSR_FS_BASE:
1210 data = vmcs_readl(GUEST_FS_BASE);
1211 break;
1212 case MSR_GS_BASE:
1213 data = vmcs_readl(GUEST_GS_BASE);
1214 break;
1215 case MSR_KERNEL_GS_BASE:
1216 vmx_load_host_state(to_vmx(vcpu));
1217 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1218 break;
1219 #endif
1220 case MSR_EFER:
1221 return kvm_get_msr_common(vcpu, msr_index, pdata);
1222 case MSR_IA32_TSC:
1223 data = guest_read_tsc();
1224 break;
1225 case MSR_IA32_SYSENTER_CS:
1226 data = vmcs_read32(GUEST_SYSENTER_CS);
1227 break;
1228 case MSR_IA32_SYSENTER_EIP:
1229 data = vmcs_readl(GUEST_SYSENTER_EIP);
1230 break;
1231 case MSR_IA32_SYSENTER_ESP:
1232 data = vmcs_readl(GUEST_SYSENTER_ESP);
1233 break;
1234 case MSR_TSC_AUX:
1235 if (!to_vmx(vcpu)->rdtscp_enabled)
1236 return 1;
1237 /* Otherwise falls through */
1238 default:
1239 vmx_load_host_state(to_vmx(vcpu));
1240 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1241 if (msr) {
1242 vmx_load_host_state(to_vmx(vcpu));
1243 data = msr->data;
1244 break;
1245 }
1246 return kvm_get_msr_common(vcpu, msr_index, pdata);
1247 }
1248
1249 *pdata = data;
1250 return 0;
1251 }
1252
1253 /*
1254 * Writes msr value into into the appropriate "register".
1255 * Returns 0 on success, non-0 otherwise.
1256 * Assumes vcpu_load() was already called.
1257 */
1258 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1259 {
1260 struct vcpu_vmx *vmx = to_vmx(vcpu);
1261 struct shared_msr_entry *msr;
1262 int ret = 0;
1263
1264 switch (msr_index) {
1265 case MSR_EFER:
1266 vmx_load_host_state(vmx);
1267 ret = kvm_set_msr_common(vcpu, msr_index, data);
1268 break;
1269 #ifdef CONFIG_X86_64
1270 case MSR_FS_BASE:
1271 vmcs_writel(GUEST_FS_BASE, data);
1272 break;
1273 case MSR_GS_BASE:
1274 vmcs_writel(GUEST_GS_BASE, data);
1275 break;
1276 case MSR_KERNEL_GS_BASE:
1277 vmx_load_host_state(vmx);
1278 vmx->msr_guest_kernel_gs_base = data;
1279 break;
1280 #endif
1281 case MSR_IA32_SYSENTER_CS:
1282 vmcs_write32(GUEST_SYSENTER_CS, data);
1283 break;
1284 case MSR_IA32_SYSENTER_EIP:
1285 vmcs_writel(GUEST_SYSENTER_EIP, data);
1286 break;
1287 case MSR_IA32_SYSENTER_ESP:
1288 vmcs_writel(GUEST_SYSENTER_ESP, data);
1289 break;
1290 case MSR_IA32_TSC:
1291 kvm_write_tsc(vcpu, data);
1292 break;
1293 case MSR_IA32_CR_PAT:
1294 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1295 vmcs_write64(GUEST_IA32_PAT, data);
1296 vcpu->arch.pat = data;
1297 break;
1298 }
1299 ret = kvm_set_msr_common(vcpu, msr_index, data);
1300 break;
1301 case MSR_TSC_AUX:
1302 if (!vmx->rdtscp_enabled)
1303 return 1;
1304 /* Check reserved bit, higher 32 bits should be zero */
1305 if ((data >> 32) != 0)
1306 return 1;
1307 /* Otherwise falls through */
1308 default:
1309 msr = find_msr_entry(vmx, msr_index);
1310 if (msr) {
1311 vmx_load_host_state(vmx);
1312 msr->data = data;
1313 break;
1314 }
1315 ret = kvm_set_msr_common(vcpu, msr_index, data);
1316 }
1317
1318 return ret;
1319 }
1320
1321 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1322 {
1323 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1324 switch (reg) {
1325 case VCPU_REGS_RSP:
1326 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1327 break;
1328 case VCPU_REGS_RIP:
1329 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1330 break;
1331 case VCPU_EXREG_PDPTR:
1332 if (enable_ept)
1333 ept_save_pdptrs(vcpu);
1334 break;
1335 default:
1336 break;
1337 }
1338 }
1339
1340 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1341 {
1342 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1343 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1344 else
1345 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1346
1347 update_exception_bitmap(vcpu);
1348 }
1349
1350 static __init int cpu_has_kvm_support(void)
1351 {
1352 return cpu_has_vmx();
1353 }
1354
1355 static __init int vmx_disabled_by_bios(void)
1356 {
1357 u64 msr;
1358
1359 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1360 if (msr & FEATURE_CONTROL_LOCKED) {
1361 /* launched w/ TXT and VMX disabled */
1362 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1363 && tboot_enabled())
1364 return 1;
1365 /* launched w/o TXT and VMX only enabled w/ TXT */
1366 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1367 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1368 && !tboot_enabled()) {
1369 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1370 "activate TXT before enabling KVM\n");
1371 return 1;
1372 }
1373 /* launched w/o TXT and VMX disabled */
1374 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1375 && !tboot_enabled())
1376 return 1;
1377 }
1378
1379 return 0;
1380 }
1381
1382 static void kvm_cpu_vmxon(u64 addr)
1383 {
1384 asm volatile (ASM_VMX_VMXON_RAX
1385 : : "a"(&addr), "m"(addr)
1386 : "memory", "cc");
1387 }
1388
1389 static int hardware_enable(void *garbage)
1390 {
1391 int cpu = raw_smp_processor_id();
1392 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1393 u64 old, test_bits;
1394
1395 if (read_cr4() & X86_CR4_VMXE)
1396 return -EBUSY;
1397
1398 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1399 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1400
1401 test_bits = FEATURE_CONTROL_LOCKED;
1402 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1403 if (tboot_enabled())
1404 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1405
1406 if ((old & test_bits) != test_bits) {
1407 /* enable and lock */
1408 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1409 }
1410 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1411
1412 if (vmm_exclusive) {
1413 kvm_cpu_vmxon(phys_addr);
1414 ept_sync_global();
1415 }
1416
1417 store_gdt(&__get_cpu_var(host_gdt));
1418
1419 return 0;
1420 }
1421
1422 static void vmclear_local_vcpus(void)
1423 {
1424 int cpu = raw_smp_processor_id();
1425 struct vcpu_vmx *vmx, *n;
1426
1427 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1428 local_vcpus_link)
1429 __vcpu_clear(vmx);
1430 }
1431
1432
1433 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1434 * tricks.
1435 */
1436 static void kvm_cpu_vmxoff(void)
1437 {
1438 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1439 }
1440
1441 static void hardware_disable(void *garbage)
1442 {
1443 if (vmm_exclusive) {
1444 vmclear_local_vcpus();
1445 kvm_cpu_vmxoff();
1446 }
1447 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1448 }
1449
1450 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1451 u32 msr, u32 *result)
1452 {
1453 u32 vmx_msr_low, vmx_msr_high;
1454 u32 ctl = ctl_min | ctl_opt;
1455
1456 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1457
1458 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1459 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1460
1461 /* Ensure minimum (required) set of control bits are supported. */
1462 if (ctl_min & ~ctl)
1463 return -EIO;
1464
1465 *result = ctl;
1466 return 0;
1467 }
1468
1469 static __init bool allow_1_setting(u32 msr, u32 ctl)
1470 {
1471 u32 vmx_msr_low, vmx_msr_high;
1472
1473 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1474 return vmx_msr_high & ctl;
1475 }
1476
1477 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1478 {
1479 u32 vmx_msr_low, vmx_msr_high;
1480 u32 min, opt, min2, opt2;
1481 u32 _pin_based_exec_control = 0;
1482 u32 _cpu_based_exec_control = 0;
1483 u32 _cpu_based_2nd_exec_control = 0;
1484 u32 _vmexit_control = 0;
1485 u32 _vmentry_control = 0;
1486
1487 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1488 opt = PIN_BASED_VIRTUAL_NMIS;
1489 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1490 &_pin_based_exec_control) < 0)
1491 return -EIO;
1492
1493 min =
1494 #ifdef CONFIG_X86_64
1495 CPU_BASED_CR8_LOAD_EXITING |
1496 CPU_BASED_CR8_STORE_EXITING |
1497 #endif
1498 CPU_BASED_CR3_LOAD_EXITING |
1499 CPU_BASED_CR3_STORE_EXITING |
1500 CPU_BASED_USE_IO_BITMAPS |
1501 CPU_BASED_MOV_DR_EXITING |
1502 CPU_BASED_USE_TSC_OFFSETING |
1503 CPU_BASED_MWAIT_EXITING |
1504 CPU_BASED_MONITOR_EXITING |
1505 CPU_BASED_INVLPG_EXITING;
1506
1507 if (yield_on_hlt)
1508 min |= CPU_BASED_HLT_EXITING;
1509
1510 opt = CPU_BASED_TPR_SHADOW |
1511 CPU_BASED_USE_MSR_BITMAPS |
1512 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1513 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1514 &_cpu_based_exec_control) < 0)
1515 return -EIO;
1516 #ifdef CONFIG_X86_64
1517 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1518 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1519 ~CPU_BASED_CR8_STORE_EXITING;
1520 #endif
1521 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1522 min2 = 0;
1523 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1524 SECONDARY_EXEC_WBINVD_EXITING |
1525 SECONDARY_EXEC_ENABLE_VPID |
1526 SECONDARY_EXEC_ENABLE_EPT |
1527 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1528 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1529 SECONDARY_EXEC_RDTSCP;
1530 if (adjust_vmx_controls(min2, opt2,
1531 MSR_IA32_VMX_PROCBASED_CTLS2,
1532 &_cpu_based_2nd_exec_control) < 0)
1533 return -EIO;
1534 }
1535 #ifndef CONFIG_X86_64
1536 if (!(_cpu_based_2nd_exec_control &
1537 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1538 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1539 #endif
1540 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1541 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1542 enabled */
1543 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1544 CPU_BASED_CR3_STORE_EXITING |
1545 CPU_BASED_INVLPG_EXITING);
1546 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1547 vmx_capability.ept, vmx_capability.vpid);
1548 }
1549
1550 min = 0;
1551 #ifdef CONFIG_X86_64
1552 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1553 #endif
1554 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1555 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1556 &_vmexit_control) < 0)
1557 return -EIO;
1558
1559 min = 0;
1560 opt = VM_ENTRY_LOAD_IA32_PAT;
1561 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1562 &_vmentry_control) < 0)
1563 return -EIO;
1564
1565 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1566
1567 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1568 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1569 return -EIO;
1570
1571 #ifdef CONFIG_X86_64
1572 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1573 if (vmx_msr_high & (1u<<16))
1574 return -EIO;
1575 #endif
1576
1577 /* Require Write-Back (WB) memory type for VMCS accesses. */
1578 if (((vmx_msr_high >> 18) & 15) != 6)
1579 return -EIO;
1580
1581 vmcs_conf->size = vmx_msr_high & 0x1fff;
1582 vmcs_conf->order = get_order(vmcs_config.size);
1583 vmcs_conf->revision_id = vmx_msr_low;
1584
1585 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1586 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1587 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1588 vmcs_conf->vmexit_ctrl = _vmexit_control;
1589 vmcs_conf->vmentry_ctrl = _vmentry_control;
1590
1591 cpu_has_load_ia32_efer =
1592 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1593 VM_ENTRY_LOAD_IA32_EFER)
1594 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1595 VM_EXIT_LOAD_IA32_EFER);
1596
1597 return 0;
1598 }
1599
1600 static struct vmcs *alloc_vmcs_cpu(int cpu)
1601 {
1602 int node = cpu_to_node(cpu);
1603 struct page *pages;
1604 struct vmcs *vmcs;
1605
1606 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1607 if (!pages)
1608 return NULL;
1609 vmcs = page_address(pages);
1610 memset(vmcs, 0, vmcs_config.size);
1611 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1612 return vmcs;
1613 }
1614
1615 static struct vmcs *alloc_vmcs(void)
1616 {
1617 return alloc_vmcs_cpu(raw_smp_processor_id());
1618 }
1619
1620 static void free_vmcs(struct vmcs *vmcs)
1621 {
1622 free_pages((unsigned long)vmcs, vmcs_config.order);
1623 }
1624
1625 static void free_kvm_area(void)
1626 {
1627 int cpu;
1628
1629 for_each_possible_cpu(cpu) {
1630 free_vmcs(per_cpu(vmxarea, cpu));
1631 per_cpu(vmxarea, cpu) = NULL;
1632 }
1633 }
1634
1635 static __init int alloc_kvm_area(void)
1636 {
1637 int cpu;
1638
1639 for_each_possible_cpu(cpu) {
1640 struct vmcs *vmcs;
1641
1642 vmcs = alloc_vmcs_cpu(cpu);
1643 if (!vmcs) {
1644 free_kvm_area();
1645 return -ENOMEM;
1646 }
1647
1648 per_cpu(vmxarea, cpu) = vmcs;
1649 }
1650 return 0;
1651 }
1652
1653 static __init int hardware_setup(void)
1654 {
1655 if (setup_vmcs_config(&vmcs_config) < 0)
1656 return -EIO;
1657
1658 if (boot_cpu_has(X86_FEATURE_NX))
1659 kvm_enable_efer_bits(EFER_NX);
1660
1661 if (!cpu_has_vmx_vpid())
1662 enable_vpid = 0;
1663
1664 if (!cpu_has_vmx_ept() ||
1665 !cpu_has_vmx_ept_4levels()) {
1666 enable_ept = 0;
1667 enable_unrestricted_guest = 0;
1668 }
1669
1670 if (!cpu_has_vmx_unrestricted_guest())
1671 enable_unrestricted_guest = 0;
1672
1673 if (!cpu_has_vmx_flexpriority())
1674 flexpriority_enabled = 0;
1675
1676 if (!cpu_has_vmx_tpr_shadow())
1677 kvm_x86_ops->update_cr8_intercept = NULL;
1678
1679 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1680 kvm_disable_largepages();
1681
1682 if (!cpu_has_vmx_ple())
1683 ple_gap = 0;
1684
1685 return alloc_kvm_area();
1686 }
1687
1688 static __exit void hardware_unsetup(void)
1689 {
1690 free_kvm_area();
1691 }
1692
1693 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1694 {
1695 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1696
1697 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1698 vmcs_write16(sf->selector, save->selector);
1699 vmcs_writel(sf->base, save->base);
1700 vmcs_write32(sf->limit, save->limit);
1701 vmcs_write32(sf->ar_bytes, save->ar);
1702 } else {
1703 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1704 << AR_DPL_SHIFT;
1705 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1706 }
1707 }
1708
1709 static void enter_pmode(struct kvm_vcpu *vcpu)
1710 {
1711 unsigned long flags;
1712 struct vcpu_vmx *vmx = to_vmx(vcpu);
1713
1714 vmx->emulation_required = 1;
1715 vmx->rmode.vm86_active = 0;
1716
1717 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
1718 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1719 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1720 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1721
1722 flags = vmcs_readl(GUEST_RFLAGS);
1723 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1724 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1725 vmcs_writel(GUEST_RFLAGS, flags);
1726
1727 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1728 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1729
1730 update_exception_bitmap(vcpu);
1731
1732 if (emulate_invalid_guest_state)
1733 return;
1734
1735 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1736 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1737 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1738 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1739
1740 vmcs_write16(GUEST_SS_SELECTOR, 0);
1741 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1742
1743 vmcs_write16(GUEST_CS_SELECTOR,
1744 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1745 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1746 }
1747
1748 static gva_t rmode_tss_base(struct kvm *kvm)
1749 {
1750 if (!kvm->arch.tss_addr) {
1751 struct kvm_memslots *slots;
1752 gfn_t base_gfn;
1753
1754 slots = kvm_memslots(kvm);
1755 base_gfn = slots->memslots[0].base_gfn +
1756 kvm->memslots->memslots[0].npages - 3;
1757 return base_gfn << PAGE_SHIFT;
1758 }
1759 return kvm->arch.tss_addr;
1760 }
1761
1762 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1763 {
1764 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1765
1766 save->selector = vmcs_read16(sf->selector);
1767 save->base = vmcs_readl(sf->base);
1768 save->limit = vmcs_read32(sf->limit);
1769 save->ar = vmcs_read32(sf->ar_bytes);
1770 vmcs_write16(sf->selector, save->base >> 4);
1771 vmcs_write32(sf->base, save->base & 0xffff0);
1772 vmcs_write32(sf->limit, 0xffff);
1773 vmcs_write32(sf->ar_bytes, 0xf3);
1774 if (save->base & 0xf)
1775 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1776 " aligned when entering protected mode (seg=%d)",
1777 seg);
1778 }
1779
1780 static void enter_rmode(struct kvm_vcpu *vcpu)
1781 {
1782 unsigned long flags;
1783 struct vcpu_vmx *vmx = to_vmx(vcpu);
1784
1785 if (enable_unrestricted_guest)
1786 return;
1787
1788 vmx->emulation_required = 1;
1789 vmx->rmode.vm86_active = 1;
1790
1791 /*
1792 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
1793 * vcpu. Call it here with phys address pointing 16M below 4G.
1794 */
1795 if (!vcpu->kvm->arch.tss_addr) {
1796 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
1797 "called before entering vcpu\n");
1798 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
1799 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
1800 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
1801 }
1802
1803 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
1804 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1805 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1806
1807 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1808 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1809
1810 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1811 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1812
1813 flags = vmcs_readl(GUEST_RFLAGS);
1814 vmx->rmode.save_rflags = flags;
1815
1816 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1817
1818 vmcs_writel(GUEST_RFLAGS, flags);
1819 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1820 update_exception_bitmap(vcpu);
1821
1822 if (emulate_invalid_guest_state)
1823 goto continue_rmode;
1824
1825 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1826 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1827 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1828
1829 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1830 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1831 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1832 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1833 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1834
1835 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1836 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1837 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1838 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1839
1840 continue_rmode:
1841 kvm_mmu_reset_context(vcpu);
1842 }
1843
1844 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1845 {
1846 struct vcpu_vmx *vmx = to_vmx(vcpu);
1847 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1848
1849 if (!msr)
1850 return;
1851
1852 /*
1853 * Force kernel_gs_base reloading before EFER changes, as control
1854 * of this msr depends on is_long_mode().
1855 */
1856 vmx_load_host_state(to_vmx(vcpu));
1857 vcpu->arch.efer = efer;
1858 if (efer & EFER_LMA) {
1859 vmcs_write32(VM_ENTRY_CONTROLS,
1860 vmcs_read32(VM_ENTRY_CONTROLS) |
1861 VM_ENTRY_IA32E_MODE);
1862 msr->data = efer;
1863 } else {
1864 vmcs_write32(VM_ENTRY_CONTROLS,
1865 vmcs_read32(VM_ENTRY_CONTROLS) &
1866 ~VM_ENTRY_IA32E_MODE);
1867
1868 msr->data = efer & ~EFER_LME;
1869 }
1870 setup_msrs(vmx);
1871 }
1872
1873 #ifdef CONFIG_X86_64
1874
1875 static void enter_lmode(struct kvm_vcpu *vcpu)
1876 {
1877 u32 guest_tr_ar;
1878
1879 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1880 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1881 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1882 __func__);
1883 vmcs_write32(GUEST_TR_AR_BYTES,
1884 (guest_tr_ar & ~AR_TYPE_MASK)
1885 | AR_TYPE_BUSY_64_TSS);
1886 }
1887 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1888 }
1889
1890 static void exit_lmode(struct kvm_vcpu *vcpu)
1891 {
1892 vmcs_write32(VM_ENTRY_CONTROLS,
1893 vmcs_read32(VM_ENTRY_CONTROLS)
1894 & ~VM_ENTRY_IA32E_MODE);
1895 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1896 }
1897
1898 #endif
1899
1900 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1901 {
1902 vpid_sync_context(to_vmx(vcpu));
1903 if (enable_ept) {
1904 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1905 return;
1906 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1907 }
1908 }
1909
1910 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1911 {
1912 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1913
1914 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1915 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1916 }
1917
1918 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
1919 {
1920 if (enable_ept && is_paging(vcpu))
1921 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1922 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
1923 }
1924
1925 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1926 {
1927 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1928
1929 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1930 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1931 }
1932
1933 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1934 {
1935 if (!test_bit(VCPU_EXREG_PDPTR,
1936 (unsigned long *)&vcpu->arch.regs_dirty))
1937 return;
1938
1939 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1940 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1941 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1942 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1943 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1944 }
1945 }
1946
1947 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1948 {
1949 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1950 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1951 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1952 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1953 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1954 }
1955
1956 __set_bit(VCPU_EXREG_PDPTR,
1957 (unsigned long *)&vcpu->arch.regs_avail);
1958 __set_bit(VCPU_EXREG_PDPTR,
1959 (unsigned long *)&vcpu->arch.regs_dirty);
1960 }
1961
1962 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1963
1964 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1965 unsigned long cr0,
1966 struct kvm_vcpu *vcpu)
1967 {
1968 vmx_decache_cr3(vcpu);
1969 if (!(cr0 & X86_CR0_PG)) {
1970 /* From paging/starting to nonpaging */
1971 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1972 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1973 (CPU_BASED_CR3_LOAD_EXITING |
1974 CPU_BASED_CR3_STORE_EXITING));
1975 vcpu->arch.cr0 = cr0;
1976 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1977 } else if (!is_paging(vcpu)) {
1978 /* From nonpaging to paging */
1979 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1980 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1981 ~(CPU_BASED_CR3_LOAD_EXITING |
1982 CPU_BASED_CR3_STORE_EXITING));
1983 vcpu->arch.cr0 = cr0;
1984 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1985 }
1986
1987 if (!(cr0 & X86_CR0_WP))
1988 *hw_cr0 &= ~X86_CR0_WP;
1989 }
1990
1991 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1992 {
1993 struct vcpu_vmx *vmx = to_vmx(vcpu);
1994 unsigned long hw_cr0;
1995
1996 if (enable_unrestricted_guest)
1997 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1998 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1999 else
2000 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2001
2002 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2003 enter_pmode(vcpu);
2004
2005 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2006 enter_rmode(vcpu);
2007
2008 #ifdef CONFIG_X86_64
2009 if (vcpu->arch.efer & EFER_LME) {
2010 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2011 enter_lmode(vcpu);
2012 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2013 exit_lmode(vcpu);
2014 }
2015 #endif
2016
2017 if (enable_ept)
2018 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2019
2020 if (!vcpu->fpu_active)
2021 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2022
2023 vmcs_writel(CR0_READ_SHADOW, cr0);
2024 vmcs_writel(GUEST_CR0, hw_cr0);
2025 vcpu->arch.cr0 = cr0;
2026 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2027 }
2028
2029 static u64 construct_eptp(unsigned long root_hpa)
2030 {
2031 u64 eptp;
2032
2033 /* TODO write the value reading from MSR */
2034 eptp = VMX_EPT_DEFAULT_MT |
2035 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2036 eptp |= (root_hpa & PAGE_MASK);
2037
2038 return eptp;
2039 }
2040
2041 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2042 {
2043 unsigned long guest_cr3;
2044 u64 eptp;
2045
2046 guest_cr3 = cr3;
2047 if (enable_ept) {
2048 eptp = construct_eptp(cr3);
2049 vmcs_write64(EPT_POINTER, eptp);
2050 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2051 vcpu->kvm->arch.ept_identity_map_addr;
2052 ept_load_pdptrs(vcpu);
2053 }
2054
2055 vmx_flush_tlb(vcpu);
2056 vmcs_writel(GUEST_CR3, guest_cr3);
2057 }
2058
2059 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2060 {
2061 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2062 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2063
2064 vcpu->arch.cr4 = cr4;
2065 if (enable_ept) {
2066 if (!is_paging(vcpu)) {
2067 hw_cr4 &= ~X86_CR4_PAE;
2068 hw_cr4 |= X86_CR4_PSE;
2069 } else if (!(cr4 & X86_CR4_PAE)) {
2070 hw_cr4 &= ~X86_CR4_PAE;
2071 }
2072 }
2073
2074 vmcs_writel(CR4_READ_SHADOW, cr4);
2075 vmcs_writel(GUEST_CR4, hw_cr4);
2076 }
2077
2078 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2079 struct kvm_segment *var, int seg)
2080 {
2081 struct vcpu_vmx *vmx = to_vmx(vcpu);
2082 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2083 struct kvm_save_segment *save;
2084 u32 ar;
2085
2086 if (vmx->rmode.vm86_active
2087 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2088 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2089 || seg == VCPU_SREG_GS)
2090 && !emulate_invalid_guest_state) {
2091 switch (seg) {
2092 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2093 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2094 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2095 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2096 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2097 default: BUG();
2098 }
2099 var->selector = save->selector;
2100 var->base = save->base;
2101 var->limit = save->limit;
2102 ar = save->ar;
2103 if (seg == VCPU_SREG_TR
2104 || var->selector == vmcs_read16(sf->selector))
2105 goto use_saved_rmode_seg;
2106 }
2107 var->base = vmcs_readl(sf->base);
2108 var->limit = vmcs_read32(sf->limit);
2109 var->selector = vmcs_read16(sf->selector);
2110 ar = vmcs_read32(sf->ar_bytes);
2111 use_saved_rmode_seg:
2112 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2113 ar = 0;
2114 var->type = ar & 15;
2115 var->s = (ar >> 4) & 1;
2116 var->dpl = (ar >> 5) & 3;
2117 var->present = (ar >> 7) & 1;
2118 var->avl = (ar >> 12) & 1;
2119 var->l = (ar >> 13) & 1;
2120 var->db = (ar >> 14) & 1;
2121 var->g = (ar >> 15) & 1;
2122 var->unusable = (ar >> 16) & 1;
2123 }
2124
2125 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2126 {
2127 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2128 struct kvm_segment s;
2129
2130 if (to_vmx(vcpu)->rmode.vm86_active) {
2131 vmx_get_segment(vcpu, &s, seg);
2132 return s.base;
2133 }
2134 return vmcs_readl(sf->base);
2135 }
2136
2137 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2138 {
2139 if (!is_protmode(vcpu))
2140 return 0;
2141
2142 if (!is_long_mode(vcpu)
2143 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2144 return 3;
2145
2146 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2147 }
2148
2149 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2150 {
2151 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2152 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2153 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2154 }
2155 return to_vmx(vcpu)->cpl;
2156 }
2157
2158
2159 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2160 {
2161 u32 ar;
2162
2163 if (var->unusable)
2164 ar = 1 << 16;
2165 else {
2166 ar = var->type & 15;
2167 ar |= (var->s & 1) << 4;
2168 ar |= (var->dpl & 3) << 5;
2169 ar |= (var->present & 1) << 7;
2170 ar |= (var->avl & 1) << 12;
2171 ar |= (var->l & 1) << 13;
2172 ar |= (var->db & 1) << 14;
2173 ar |= (var->g & 1) << 15;
2174 }
2175 if (ar == 0) /* a 0 value means unusable */
2176 ar = AR_UNUSABLE_MASK;
2177
2178 return ar;
2179 }
2180
2181 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2182 struct kvm_segment *var, int seg)
2183 {
2184 struct vcpu_vmx *vmx = to_vmx(vcpu);
2185 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2186 u32 ar;
2187
2188 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2189 vmcs_write16(sf->selector, var->selector);
2190 vmx->rmode.tr.selector = var->selector;
2191 vmx->rmode.tr.base = var->base;
2192 vmx->rmode.tr.limit = var->limit;
2193 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2194 return;
2195 }
2196 vmcs_writel(sf->base, var->base);
2197 vmcs_write32(sf->limit, var->limit);
2198 vmcs_write16(sf->selector, var->selector);
2199 if (vmx->rmode.vm86_active && var->s) {
2200 /*
2201 * Hack real-mode segments into vm86 compatibility.
2202 */
2203 if (var->base == 0xffff0000 && var->selector == 0xf000)
2204 vmcs_writel(sf->base, 0xf0000);
2205 ar = 0xf3;
2206 } else
2207 ar = vmx_segment_access_rights(var);
2208
2209 /*
2210 * Fix the "Accessed" bit in AR field of segment registers for older
2211 * qemu binaries.
2212 * IA32 arch specifies that at the time of processor reset the
2213 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2214 * is setting it to 0 in the usedland code. This causes invalid guest
2215 * state vmexit when "unrestricted guest" mode is turned on.
2216 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2217 * tree. Newer qemu binaries with that qemu fix would not need this
2218 * kvm hack.
2219 */
2220 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2221 ar |= 0x1; /* Accessed */
2222
2223 vmcs_write32(sf->ar_bytes, ar);
2224 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2225 }
2226
2227 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2228 {
2229 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2230
2231 *db = (ar >> 14) & 1;
2232 *l = (ar >> 13) & 1;
2233 }
2234
2235 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2236 {
2237 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2238 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2239 }
2240
2241 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2242 {
2243 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2244 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2245 }
2246
2247 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2248 {
2249 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2250 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2251 }
2252
2253 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2254 {
2255 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2256 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2257 }
2258
2259 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2260 {
2261 struct kvm_segment var;
2262 u32 ar;
2263
2264 vmx_get_segment(vcpu, &var, seg);
2265 ar = vmx_segment_access_rights(&var);
2266
2267 if (var.base != (var.selector << 4))
2268 return false;
2269 if (var.limit != 0xffff)
2270 return false;
2271 if (ar != 0xf3)
2272 return false;
2273
2274 return true;
2275 }
2276
2277 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2278 {
2279 struct kvm_segment cs;
2280 unsigned int cs_rpl;
2281
2282 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2283 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2284
2285 if (cs.unusable)
2286 return false;
2287 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2288 return false;
2289 if (!cs.s)
2290 return false;
2291 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2292 if (cs.dpl > cs_rpl)
2293 return false;
2294 } else {
2295 if (cs.dpl != cs_rpl)
2296 return false;
2297 }
2298 if (!cs.present)
2299 return false;
2300
2301 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2302 return true;
2303 }
2304
2305 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2306 {
2307 struct kvm_segment ss;
2308 unsigned int ss_rpl;
2309
2310 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2311 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2312
2313 if (ss.unusable)
2314 return true;
2315 if (ss.type != 3 && ss.type != 7)
2316 return false;
2317 if (!ss.s)
2318 return false;
2319 if (ss.dpl != ss_rpl) /* DPL != RPL */
2320 return false;
2321 if (!ss.present)
2322 return false;
2323
2324 return true;
2325 }
2326
2327 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2328 {
2329 struct kvm_segment var;
2330 unsigned int rpl;
2331
2332 vmx_get_segment(vcpu, &var, seg);
2333 rpl = var.selector & SELECTOR_RPL_MASK;
2334
2335 if (var.unusable)
2336 return true;
2337 if (!var.s)
2338 return false;
2339 if (!var.present)
2340 return false;
2341 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2342 if (var.dpl < rpl) /* DPL < RPL */
2343 return false;
2344 }
2345
2346 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2347 * rights flags
2348 */
2349 return true;
2350 }
2351
2352 static bool tr_valid(struct kvm_vcpu *vcpu)
2353 {
2354 struct kvm_segment tr;
2355
2356 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2357
2358 if (tr.unusable)
2359 return false;
2360 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2361 return false;
2362 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2363 return false;
2364 if (!tr.present)
2365 return false;
2366
2367 return true;
2368 }
2369
2370 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2371 {
2372 struct kvm_segment ldtr;
2373
2374 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2375
2376 if (ldtr.unusable)
2377 return true;
2378 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2379 return false;
2380 if (ldtr.type != 2)
2381 return false;
2382 if (!ldtr.present)
2383 return false;
2384
2385 return true;
2386 }
2387
2388 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2389 {
2390 struct kvm_segment cs, ss;
2391
2392 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2393 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2394
2395 return ((cs.selector & SELECTOR_RPL_MASK) ==
2396 (ss.selector & SELECTOR_RPL_MASK));
2397 }
2398
2399 /*
2400 * Check if guest state is valid. Returns true if valid, false if
2401 * not.
2402 * We assume that registers are always usable
2403 */
2404 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2405 {
2406 /* real mode guest state checks */
2407 if (!is_protmode(vcpu)) {
2408 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2409 return false;
2410 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2411 return false;
2412 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2413 return false;
2414 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2415 return false;
2416 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2417 return false;
2418 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2419 return false;
2420 } else {
2421 /* protected mode guest state checks */
2422 if (!cs_ss_rpl_check(vcpu))
2423 return false;
2424 if (!code_segment_valid(vcpu))
2425 return false;
2426 if (!stack_segment_valid(vcpu))
2427 return false;
2428 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2429 return false;
2430 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2431 return false;
2432 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2433 return false;
2434 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2435 return false;
2436 if (!tr_valid(vcpu))
2437 return false;
2438 if (!ldtr_valid(vcpu))
2439 return false;
2440 }
2441 /* TODO:
2442 * - Add checks on RIP
2443 * - Add checks on RFLAGS
2444 */
2445
2446 return true;
2447 }
2448
2449 static int init_rmode_tss(struct kvm *kvm)
2450 {
2451 gfn_t fn;
2452 u16 data = 0;
2453 int r, idx, ret = 0;
2454
2455 idx = srcu_read_lock(&kvm->srcu);
2456 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2457 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2458 if (r < 0)
2459 goto out;
2460 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2461 r = kvm_write_guest_page(kvm, fn++, &data,
2462 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2463 if (r < 0)
2464 goto out;
2465 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2466 if (r < 0)
2467 goto out;
2468 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2469 if (r < 0)
2470 goto out;
2471 data = ~0;
2472 r = kvm_write_guest_page(kvm, fn, &data,
2473 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2474 sizeof(u8));
2475 if (r < 0)
2476 goto out;
2477
2478 ret = 1;
2479 out:
2480 srcu_read_unlock(&kvm->srcu, idx);
2481 return ret;
2482 }
2483
2484 static int init_rmode_identity_map(struct kvm *kvm)
2485 {
2486 int i, idx, r, ret;
2487 pfn_t identity_map_pfn;
2488 u32 tmp;
2489
2490 if (!enable_ept)
2491 return 1;
2492 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2493 printk(KERN_ERR "EPT: identity-mapping pagetable "
2494 "haven't been allocated!\n");
2495 return 0;
2496 }
2497 if (likely(kvm->arch.ept_identity_pagetable_done))
2498 return 1;
2499 ret = 0;
2500 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2501 idx = srcu_read_lock(&kvm->srcu);
2502 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2503 if (r < 0)
2504 goto out;
2505 /* Set up identity-mapping pagetable for EPT in real mode */
2506 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2507 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2508 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2509 r = kvm_write_guest_page(kvm, identity_map_pfn,
2510 &tmp, i * sizeof(tmp), sizeof(tmp));
2511 if (r < 0)
2512 goto out;
2513 }
2514 kvm->arch.ept_identity_pagetable_done = true;
2515 ret = 1;
2516 out:
2517 srcu_read_unlock(&kvm->srcu, idx);
2518 return ret;
2519 }
2520
2521 static void seg_setup(int seg)
2522 {
2523 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2524 unsigned int ar;
2525
2526 vmcs_write16(sf->selector, 0);
2527 vmcs_writel(sf->base, 0);
2528 vmcs_write32(sf->limit, 0xffff);
2529 if (enable_unrestricted_guest) {
2530 ar = 0x93;
2531 if (seg == VCPU_SREG_CS)
2532 ar |= 0x08; /* code segment */
2533 } else
2534 ar = 0xf3;
2535
2536 vmcs_write32(sf->ar_bytes, ar);
2537 }
2538
2539 static int alloc_apic_access_page(struct kvm *kvm)
2540 {
2541 struct kvm_userspace_memory_region kvm_userspace_mem;
2542 int r = 0;
2543
2544 mutex_lock(&kvm->slots_lock);
2545 if (kvm->arch.apic_access_page)
2546 goto out;
2547 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2548 kvm_userspace_mem.flags = 0;
2549 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2550 kvm_userspace_mem.memory_size = PAGE_SIZE;
2551 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2552 if (r)
2553 goto out;
2554
2555 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2556 out:
2557 mutex_unlock(&kvm->slots_lock);
2558 return r;
2559 }
2560
2561 static int alloc_identity_pagetable(struct kvm *kvm)
2562 {
2563 struct kvm_userspace_memory_region kvm_userspace_mem;
2564 int r = 0;
2565
2566 mutex_lock(&kvm->slots_lock);
2567 if (kvm->arch.ept_identity_pagetable)
2568 goto out;
2569 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2570 kvm_userspace_mem.flags = 0;
2571 kvm_userspace_mem.guest_phys_addr =
2572 kvm->arch.ept_identity_map_addr;
2573 kvm_userspace_mem.memory_size = PAGE_SIZE;
2574 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2575 if (r)
2576 goto out;
2577
2578 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2579 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2580 out:
2581 mutex_unlock(&kvm->slots_lock);
2582 return r;
2583 }
2584
2585 static void allocate_vpid(struct vcpu_vmx *vmx)
2586 {
2587 int vpid;
2588
2589 vmx->vpid = 0;
2590 if (!enable_vpid)
2591 return;
2592 spin_lock(&vmx_vpid_lock);
2593 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2594 if (vpid < VMX_NR_VPIDS) {
2595 vmx->vpid = vpid;
2596 __set_bit(vpid, vmx_vpid_bitmap);
2597 }
2598 spin_unlock(&vmx_vpid_lock);
2599 }
2600
2601 static void free_vpid(struct vcpu_vmx *vmx)
2602 {
2603 if (!enable_vpid)
2604 return;
2605 spin_lock(&vmx_vpid_lock);
2606 if (vmx->vpid != 0)
2607 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2608 spin_unlock(&vmx_vpid_lock);
2609 }
2610
2611 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2612 {
2613 int f = sizeof(unsigned long);
2614
2615 if (!cpu_has_vmx_msr_bitmap())
2616 return;
2617
2618 /*
2619 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2620 * have the write-low and read-high bitmap offsets the wrong way round.
2621 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2622 */
2623 if (msr <= 0x1fff) {
2624 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2625 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2626 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2627 msr &= 0x1fff;
2628 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2629 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2630 }
2631 }
2632
2633 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2634 {
2635 if (!longmode_only)
2636 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2637 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2638 }
2639
2640 /*
2641 * Sets up the vmcs for emulated real mode.
2642 */
2643 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2644 {
2645 u32 host_sysenter_cs, msr_low, msr_high;
2646 u32 junk;
2647 u64 host_pat;
2648 unsigned long a;
2649 struct desc_ptr dt;
2650 int i;
2651 unsigned long kvm_vmx_return;
2652 u32 exec_control;
2653
2654 /* I/O */
2655 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2656 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2657
2658 if (cpu_has_vmx_msr_bitmap())
2659 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2660
2661 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2662
2663 /* Control */
2664 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2665 vmcs_config.pin_based_exec_ctrl);
2666
2667 exec_control = vmcs_config.cpu_based_exec_ctrl;
2668 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2669 exec_control &= ~CPU_BASED_TPR_SHADOW;
2670 #ifdef CONFIG_X86_64
2671 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2672 CPU_BASED_CR8_LOAD_EXITING;
2673 #endif
2674 }
2675 if (!enable_ept)
2676 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2677 CPU_BASED_CR3_LOAD_EXITING |
2678 CPU_BASED_INVLPG_EXITING;
2679 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2680
2681 if (cpu_has_secondary_exec_ctrls()) {
2682 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2683 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2684 exec_control &=
2685 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2686 if (vmx->vpid == 0)
2687 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2688 if (!enable_ept) {
2689 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2690 enable_unrestricted_guest = 0;
2691 }
2692 if (!enable_unrestricted_guest)
2693 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2694 if (!ple_gap)
2695 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2696 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2697 }
2698
2699 if (ple_gap) {
2700 vmcs_write32(PLE_GAP, ple_gap);
2701 vmcs_write32(PLE_WINDOW, ple_window);
2702 }
2703
2704 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2705 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2706 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2707
2708 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2709 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2710 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2711
2712 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2713 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2714 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2715 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2716 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
2717 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2718 #ifdef CONFIG_X86_64
2719 rdmsrl(MSR_FS_BASE, a);
2720 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2721 rdmsrl(MSR_GS_BASE, a);
2722 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2723 #else
2724 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2725 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2726 #endif
2727
2728 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2729
2730 native_store_idt(&dt);
2731 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2732
2733 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2734 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2735 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2736 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2737 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2738 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2739 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2740
2741 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2742 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2743 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2744 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2745 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2746 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2747
2748 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2749 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2750 host_pat = msr_low | ((u64) msr_high << 32);
2751 vmcs_write64(HOST_IA32_PAT, host_pat);
2752 }
2753 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2754 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2755 host_pat = msr_low | ((u64) msr_high << 32);
2756 /* Write the default value follow host pat */
2757 vmcs_write64(GUEST_IA32_PAT, host_pat);
2758 /* Keep arch.pat sync with GUEST_IA32_PAT */
2759 vmx->vcpu.arch.pat = host_pat;
2760 }
2761
2762 for (i = 0; i < NR_VMX_MSR; ++i) {
2763 u32 index = vmx_msr_index[i];
2764 u32 data_low, data_high;
2765 int j = vmx->nmsrs;
2766
2767 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2768 continue;
2769 if (wrmsr_safe(index, data_low, data_high) < 0)
2770 continue;
2771 vmx->guest_msrs[j].index = i;
2772 vmx->guest_msrs[j].data = 0;
2773 vmx->guest_msrs[j].mask = -1ull;
2774 ++vmx->nmsrs;
2775 }
2776
2777 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2778
2779 /* 22.2.1, 20.8.1 */
2780 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2781
2782 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2783 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2784 if (enable_ept)
2785 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2786 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2787
2788 kvm_write_tsc(&vmx->vcpu, 0);
2789
2790 return 0;
2791 }
2792
2793 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2794 {
2795 struct vcpu_vmx *vmx = to_vmx(vcpu);
2796 u64 msr;
2797 int ret;
2798
2799 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2800
2801 vmx->rmode.vm86_active = 0;
2802
2803 vmx->soft_vnmi_blocked = 0;
2804
2805 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2806 kvm_set_cr8(&vmx->vcpu, 0);
2807 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2808 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2809 msr |= MSR_IA32_APICBASE_BSP;
2810 kvm_set_apic_base(&vmx->vcpu, msr);
2811
2812 ret = fx_init(&vmx->vcpu);
2813 if (ret != 0)
2814 goto out;
2815
2816 seg_setup(VCPU_SREG_CS);
2817 /*
2818 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2819 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2820 */
2821 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2822 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2823 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2824 } else {
2825 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2826 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2827 }
2828
2829 seg_setup(VCPU_SREG_DS);
2830 seg_setup(VCPU_SREG_ES);
2831 seg_setup(VCPU_SREG_FS);
2832 seg_setup(VCPU_SREG_GS);
2833 seg_setup(VCPU_SREG_SS);
2834
2835 vmcs_write16(GUEST_TR_SELECTOR, 0);
2836 vmcs_writel(GUEST_TR_BASE, 0);
2837 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2838 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2839
2840 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2841 vmcs_writel(GUEST_LDTR_BASE, 0);
2842 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2843 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2844
2845 vmcs_write32(GUEST_SYSENTER_CS, 0);
2846 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2847 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2848
2849 vmcs_writel(GUEST_RFLAGS, 0x02);
2850 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2851 kvm_rip_write(vcpu, 0xfff0);
2852 else
2853 kvm_rip_write(vcpu, 0);
2854 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2855
2856 vmcs_writel(GUEST_DR7, 0x400);
2857
2858 vmcs_writel(GUEST_GDTR_BASE, 0);
2859 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2860
2861 vmcs_writel(GUEST_IDTR_BASE, 0);
2862 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2863
2864 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2865 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2866 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2867
2868 /* Special registers */
2869 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2870
2871 setup_msrs(vmx);
2872
2873 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2874
2875 if (cpu_has_vmx_tpr_shadow()) {
2876 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2877 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2878 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2879 __pa(vmx->vcpu.arch.apic->regs));
2880 vmcs_write32(TPR_THRESHOLD, 0);
2881 }
2882
2883 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2884 vmcs_write64(APIC_ACCESS_ADDR,
2885 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2886
2887 if (vmx->vpid != 0)
2888 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2889
2890 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2891 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2892 vmx_set_cr4(&vmx->vcpu, 0);
2893 vmx_set_efer(&vmx->vcpu, 0);
2894 vmx_fpu_activate(&vmx->vcpu);
2895 update_exception_bitmap(&vmx->vcpu);
2896
2897 vpid_sync_context(vmx);
2898
2899 ret = 0;
2900
2901 /* HACK: Don't enable emulation on guest boot/reset */
2902 vmx->emulation_required = 0;
2903
2904 out:
2905 return ret;
2906 }
2907
2908 static void enable_irq_window(struct kvm_vcpu *vcpu)
2909 {
2910 u32 cpu_based_vm_exec_control;
2911
2912 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2913 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2914 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2915 }
2916
2917 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2918 {
2919 u32 cpu_based_vm_exec_control;
2920
2921 if (!cpu_has_virtual_nmis()) {
2922 enable_irq_window(vcpu);
2923 return;
2924 }
2925
2926 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2927 enable_irq_window(vcpu);
2928 return;
2929 }
2930 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2931 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2932 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2933 }
2934
2935 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2936 {
2937 struct vcpu_vmx *vmx = to_vmx(vcpu);
2938 uint32_t intr;
2939 int irq = vcpu->arch.interrupt.nr;
2940
2941 trace_kvm_inj_virq(irq);
2942
2943 ++vcpu->stat.irq_injections;
2944 if (vmx->rmode.vm86_active) {
2945 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2946 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2947 return;
2948 }
2949 intr = irq | INTR_INFO_VALID_MASK;
2950 if (vcpu->arch.interrupt.soft) {
2951 intr |= INTR_TYPE_SOFT_INTR;
2952 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2953 vmx->vcpu.arch.event_exit_inst_len);
2954 } else
2955 intr |= INTR_TYPE_EXT_INTR;
2956 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2957 vmx_clear_hlt(vcpu);
2958 }
2959
2960 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2961 {
2962 struct vcpu_vmx *vmx = to_vmx(vcpu);
2963
2964 if (!cpu_has_virtual_nmis()) {
2965 /*
2966 * Tracking the NMI-blocked state in software is built upon
2967 * finding the next open IRQ window. This, in turn, depends on
2968 * well-behaving guests: They have to keep IRQs disabled at
2969 * least as long as the NMI handler runs. Otherwise we may
2970 * cause NMI nesting, maybe breaking the guest. But as this is
2971 * highly unlikely, we can live with the residual risk.
2972 */
2973 vmx->soft_vnmi_blocked = 1;
2974 vmx->vnmi_blocked_time = 0;
2975 }
2976
2977 ++vcpu->stat.nmi_injections;
2978 vmx->nmi_known_unmasked = false;
2979 if (vmx->rmode.vm86_active) {
2980 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2981 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2982 return;
2983 }
2984 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2985 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2986 vmx_clear_hlt(vcpu);
2987 }
2988
2989 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2990 {
2991 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2992 return 0;
2993
2994 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2995 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2996 | GUEST_INTR_STATE_NMI));
2997 }
2998
2999 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3000 {
3001 if (!cpu_has_virtual_nmis())
3002 return to_vmx(vcpu)->soft_vnmi_blocked;
3003 if (to_vmx(vcpu)->nmi_known_unmasked)
3004 return false;
3005 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3006 }
3007
3008 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3009 {
3010 struct vcpu_vmx *vmx = to_vmx(vcpu);
3011
3012 if (!cpu_has_virtual_nmis()) {
3013 if (vmx->soft_vnmi_blocked != masked) {
3014 vmx->soft_vnmi_blocked = masked;
3015 vmx->vnmi_blocked_time = 0;
3016 }
3017 } else {
3018 vmx->nmi_known_unmasked = !masked;
3019 if (masked)
3020 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3021 GUEST_INTR_STATE_NMI);
3022 else
3023 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3024 GUEST_INTR_STATE_NMI);
3025 }
3026 }
3027
3028 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3029 {
3030 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3031 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3032 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3033 }
3034
3035 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3036 {
3037 int ret;
3038 struct kvm_userspace_memory_region tss_mem = {
3039 .slot = TSS_PRIVATE_MEMSLOT,
3040 .guest_phys_addr = addr,
3041 .memory_size = PAGE_SIZE * 3,
3042 .flags = 0,
3043 };
3044
3045 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3046 if (ret)
3047 return ret;
3048 kvm->arch.tss_addr = addr;
3049 if (!init_rmode_tss(kvm))
3050 return -ENOMEM;
3051
3052 return 0;
3053 }
3054
3055 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3056 int vec, u32 err_code)
3057 {
3058 /*
3059 * Instruction with address size override prefix opcode 0x67
3060 * Cause the #SS fault with 0 error code in VM86 mode.
3061 */
3062 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3063 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3064 return 1;
3065 /*
3066 * Forward all other exceptions that are valid in real mode.
3067 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3068 * the required debugging infrastructure rework.
3069 */
3070 switch (vec) {
3071 case DB_VECTOR:
3072 if (vcpu->guest_debug &
3073 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3074 return 0;
3075 kvm_queue_exception(vcpu, vec);
3076 return 1;
3077 case BP_VECTOR:
3078 /*
3079 * Update instruction length as we may reinject the exception
3080 * from user space while in guest debugging mode.
3081 */
3082 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3083 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3084 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3085 return 0;
3086 /* fall through */
3087 case DE_VECTOR:
3088 case OF_VECTOR:
3089 case BR_VECTOR:
3090 case UD_VECTOR:
3091 case DF_VECTOR:
3092 case SS_VECTOR:
3093 case GP_VECTOR:
3094 case MF_VECTOR:
3095 kvm_queue_exception(vcpu, vec);
3096 return 1;
3097 }
3098 return 0;
3099 }
3100
3101 /*
3102 * Trigger machine check on the host. We assume all the MSRs are already set up
3103 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3104 * We pass a fake environment to the machine check handler because we want
3105 * the guest to be always treated like user space, no matter what context
3106 * it used internally.
3107 */
3108 static void kvm_machine_check(void)
3109 {
3110 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3111 struct pt_regs regs = {
3112 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3113 .flags = X86_EFLAGS_IF,
3114 };
3115
3116 do_machine_check(&regs, 0);
3117 #endif
3118 }
3119
3120 static int handle_machine_check(struct kvm_vcpu *vcpu)
3121 {
3122 /* already handled by vcpu_run */
3123 return 1;
3124 }
3125
3126 static int handle_exception(struct kvm_vcpu *vcpu)
3127 {
3128 struct vcpu_vmx *vmx = to_vmx(vcpu);
3129 struct kvm_run *kvm_run = vcpu->run;
3130 u32 intr_info, ex_no, error_code;
3131 unsigned long cr2, rip, dr6;
3132 u32 vect_info;
3133 enum emulation_result er;
3134
3135 vect_info = vmx->idt_vectoring_info;
3136 intr_info = vmx->exit_intr_info;
3137
3138 if (is_machine_check(intr_info))
3139 return handle_machine_check(vcpu);
3140
3141 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3142 !is_page_fault(intr_info)) {
3143 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3144 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3145 vcpu->run->internal.ndata = 2;
3146 vcpu->run->internal.data[0] = vect_info;
3147 vcpu->run->internal.data[1] = intr_info;
3148 return 0;
3149 }
3150
3151 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3152 return 1; /* already handled by vmx_vcpu_run() */
3153
3154 if (is_no_device(intr_info)) {
3155 vmx_fpu_activate(vcpu);
3156 return 1;
3157 }
3158
3159 if (is_invalid_opcode(intr_info)) {
3160 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3161 if (er != EMULATE_DONE)
3162 kvm_queue_exception(vcpu, UD_VECTOR);
3163 return 1;
3164 }
3165
3166 error_code = 0;
3167 rip = kvm_rip_read(vcpu);
3168 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3169 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3170 if (is_page_fault(intr_info)) {
3171 /* EPT won't cause page fault directly */
3172 if (enable_ept)
3173 BUG();
3174 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3175 trace_kvm_page_fault(cr2, error_code);
3176
3177 if (kvm_event_needs_reinjection(vcpu))
3178 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3179 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3180 }
3181
3182 if (vmx->rmode.vm86_active &&
3183 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3184 error_code)) {
3185 if (vcpu->arch.halt_request) {
3186 vcpu->arch.halt_request = 0;
3187 return kvm_emulate_halt(vcpu);
3188 }
3189 return 1;
3190 }
3191
3192 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3193 switch (ex_no) {
3194 case DB_VECTOR:
3195 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3196 if (!(vcpu->guest_debug &
3197 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3198 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3199 kvm_queue_exception(vcpu, DB_VECTOR);
3200 return 1;
3201 }
3202 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3203 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3204 /* fall through */
3205 case BP_VECTOR:
3206 /*
3207 * Update instruction length as we may reinject #BP from
3208 * user space while in guest debugging mode. Reading it for
3209 * #DB as well causes no harm, it is not used in that case.
3210 */
3211 vmx->vcpu.arch.event_exit_inst_len =
3212 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3213 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3214 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3215 kvm_run->debug.arch.exception = ex_no;
3216 break;
3217 default:
3218 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3219 kvm_run->ex.exception = ex_no;
3220 kvm_run->ex.error_code = error_code;
3221 break;
3222 }
3223 return 0;
3224 }
3225
3226 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3227 {
3228 ++vcpu->stat.irq_exits;
3229 return 1;
3230 }
3231
3232 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3233 {
3234 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3235 return 0;
3236 }
3237
3238 static int handle_io(struct kvm_vcpu *vcpu)
3239 {
3240 unsigned long exit_qualification;
3241 int size, in, string;
3242 unsigned port;
3243
3244 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3245 string = (exit_qualification & 16) != 0;
3246 in = (exit_qualification & 8) != 0;
3247
3248 ++vcpu->stat.io_exits;
3249
3250 if (string || in)
3251 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3252
3253 port = exit_qualification >> 16;
3254 size = (exit_qualification & 7) + 1;
3255 skip_emulated_instruction(vcpu);
3256
3257 return kvm_fast_pio_out(vcpu, size, port);
3258 }
3259
3260 static void
3261 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3262 {
3263 /*
3264 * Patch in the VMCALL instruction:
3265 */
3266 hypercall[0] = 0x0f;
3267 hypercall[1] = 0x01;
3268 hypercall[2] = 0xc1;
3269 }
3270
3271 static int handle_cr(struct kvm_vcpu *vcpu)
3272 {
3273 unsigned long exit_qualification, val;
3274 int cr;
3275 int reg;
3276 int err;
3277
3278 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3279 cr = exit_qualification & 15;
3280 reg = (exit_qualification >> 8) & 15;
3281 switch ((exit_qualification >> 4) & 3) {
3282 case 0: /* mov to cr */
3283 val = kvm_register_read(vcpu, reg);
3284 trace_kvm_cr_write(cr, val);
3285 switch (cr) {
3286 case 0:
3287 err = kvm_set_cr0(vcpu, val);
3288 kvm_complete_insn_gp(vcpu, err);
3289 return 1;
3290 case 3:
3291 err = kvm_set_cr3(vcpu, val);
3292 kvm_complete_insn_gp(vcpu, err);
3293 return 1;
3294 case 4:
3295 err = kvm_set_cr4(vcpu, val);
3296 kvm_complete_insn_gp(vcpu, err);
3297 return 1;
3298 case 8: {
3299 u8 cr8_prev = kvm_get_cr8(vcpu);
3300 u8 cr8 = kvm_register_read(vcpu, reg);
3301 err = kvm_set_cr8(vcpu, cr8);
3302 kvm_complete_insn_gp(vcpu, err);
3303 if (irqchip_in_kernel(vcpu->kvm))
3304 return 1;
3305 if (cr8_prev <= cr8)
3306 return 1;
3307 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3308 return 0;
3309 }
3310 };
3311 break;
3312 case 2: /* clts */
3313 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3314 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3315 skip_emulated_instruction(vcpu);
3316 vmx_fpu_activate(vcpu);
3317 return 1;
3318 case 1: /*mov from cr*/
3319 switch (cr) {
3320 case 3:
3321 val = kvm_read_cr3(vcpu);
3322 kvm_register_write(vcpu, reg, val);
3323 trace_kvm_cr_read(cr, val);
3324 skip_emulated_instruction(vcpu);
3325 return 1;
3326 case 8:
3327 val = kvm_get_cr8(vcpu);
3328 kvm_register_write(vcpu, reg, val);
3329 trace_kvm_cr_read(cr, val);
3330 skip_emulated_instruction(vcpu);
3331 return 1;
3332 }
3333 break;
3334 case 3: /* lmsw */
3335 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3336 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3337 kvm_lmsw(vcpu, val);
3338
3339 skip_emulated_instruction(vcpu);
3340 return 1;
3341 default:
3342 break;
3343 }
3344 vcpu->run->exit_reason = 0;
3345 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3346 (int)(exit_qualification >> 4) & 3, cr);
3347 return 0;
3348 }
3349
3350 static int handle_dr(struct kvm_vcpu *vcpu)
3351 {
3352 unsigned long exit_qualification;
3353 int dr, reg;
3354
3355 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3356 if (!kvm_require_cpl(vcpu, 0))
3357 return 1;
3358 dr = vmcs_readl(GUEST_DR7);
3359 if (dr & DR7_GD) {
3360 /*
3361 * As the vm-exit takes precedence over the debug trap, we
3362 * need to emulate the latter, either for the host or the
3363 * guest debugging itself.
3364 */
3365 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3366 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3367 vcpu->run->debug.arch.dr7 = dr;
3368 vcpu->run->debug.arch.pc =
3369 vmcs_readl(GUEST_CS_BASE) +
3370 vmcs_readl(GUEST_RIP);
3371 vcpu->run->debug.arch.exception = DB_VECTOR;
3372 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3373 return 0;
3374 } else {
3375 vcpu->arch.dr7 &= ~DR7_GD;
3376 vcpu->arch.dr6 |= DR6_BD;
3377 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3378 kvm_queue_exception(vcpu, DB_VECTOR);
3379 return 1;
3380 }
3381 }
3382
3383 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3384 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3385 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3386 if (exit_qualification & TYPE_MOV_FROM_DR) {
3387 unsigned long val;
3388 if (!kvm_get_dr(vcpu, dr, &val))
3389 kvm_register_write(vcpu, reg, val);
3390 } else
3391 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3392 skip_emulated_instruction(vcpu);
3393 return 1;
3394 }
3395
3396 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3397 {
3398 vmcs_writel(GUEST_DR7, val);
3399 }
3400
3401 static int handle_cpuid(struct kvm_vcpu *vcpu)
3402 {
3403 kvm_emulate_cpuid(vcpu);
3404 return 1;
3405 }
3406
3407 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3408 {
3409 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3410 u64 data;
3411
3412 if (vmx_get_msr(vcpu, ecx, &data)) {
3413 trace_kvm_msr_read_ex(ecx);
3414 kvm_inject_gp(vcpu, 0);
3415 return 1;
3416 }
3417
3418 trace_kvm_msr_read(ecx, data);
3419
3420 /* FIXME: handling of bits 32:63 of rax, rdx */
3421 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3422 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3423 skip_emulated_instruction(vcpu);
3424 return 1;
3425 }
3426
3427 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3428 {
3429 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3430 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3431 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3432
3433 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3434 trace_kvm_msr_write_ex(ecx, data);
3435 kvm_inject_gp(vcpu, 0);
3436 return 1;
3437 }
3438
3439 trace_kvm_msr_write(ecx, data);
3440 skip_emulated_instruction(vcpu);
3441 return 1;
3442 }
3443
3444 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3445 {
3446 kvm_make_request(KVM_REQ_EVENT, vcpu);
3447 return 1;
3448 }
3449
3450 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3451 {
3452 u32 cpu_based_vm_exec_control;
3453
3454 /* clear pending irq */
3455 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3456 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3457 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3458
3459 kvm_make_request(KVM_REQ_EVENT, vcpu);
3460
3461 ++vcpu->stat.irq_window_exits;
3462
3463 /*
3464 * If the user space waits to inject interrupts, exit as soon as
3465 * possible
3466 */
3467 if (!irqchip_in_kernel(vcpu->kvm) &&
3468 vcpu->run->request_interrupt_window &&
3469 !kvm_cpu_has_interrupt(vcpu)) {
3470 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3471 return 0;
3472 }
3473 return 1;
3474 }
3475
3476 static int handle_halt(struct kvm_vcpu *vcpu)
3477 {
3478 skip_emulated_instruction(vcpu);
3479 return kvm_emulate_halt(vcpu);
3480 }
3481
3482 static int handle_vmcall(struct kvm_vcpu *vcpu)
3483 {
3484 skip_emulated_instruction(vcpu);
3485 kvm_emulate_hypercall(vcpu);
3486 return 1;
3487 }
3488
3489 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3490 {
3491 kvm_queue_exception(vcpu, UD_VECTOR);
3492 return 1;
3493 }
3494
3495 static int handle_invd(struct kvm_vcpu *vcpu)
3496 {
3497 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3498 }
3499
3500 static int handle_invlpg(struct kvm_vcpu *vcpu)
3501 {
3502 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3503
3504 kvm_mmu_invlpg(vcpu, exit_qualification);
3505 skip_emulated_instruction(vcpu);
3506 return 1;
3507 }
3508
3509 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3510 {
3511 skip_emulated_instruction(vcpu);
3512 kvm_emulate_wbinvd(vcpu);
3513 return 1;
3514 }
3515
3516 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3517 {
3518 u64 new_bv = kvm_read_edx_eax(vcpu);
3519 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3520
3521 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3522 skip_emulated_instruction(vcpu);
3523 return 1;
3524 }
3525
3526 static int handle_apic_access(struct kvm_vcpu *vcpu)
3527 {
3528 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3529 }
3530
3531 static int handle_task_switch(struct kvm_vcpu *vcpu)
3532 {
3533 struct vcpu_vmx *vmx = to_vmx(vcpu);
3534 unsigned long exit_qualification;
3535 bool has_error_code = false;
3536 u32 error_code = 0;
3537 u16 tss_selector;
3538 int reason, type, idt_v;
3539
3540 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3541 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3542
3543 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3544
3545 reason = (u32)exit_qualification >> 30;
3546 if (reason == TASK_SWITCH_GATE && idt_v) {
3547 switch (type) {
3548 case INTR_TYPE_NMI_INTR:
3549 vcpu->arch.nmi_injected = false;
3550 vmx_set_nmi_mask(vcpu, true);
3551 break;
3552 case INTR_TYPE_EXT_INTR:
3553 case INTR_TYPE_SOFT_INTR:
3554 kvm_clear_interrupt_queue(vcpu);
3555 break;
3556 case INTR_TYPE_HARD_EXCEPTION:
3557 if (vmx->idt_vectoring_info &
3558 VECTORING_INFO_DELIVER_CODE_MASK) {
3559 has_error_code = true;
3560 error_code =
3561 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3562 }
3563 /* fall through */
3564 case INTR_TYPE_SOFT_EXCEPTION:
3565 kvm_clear_exception_queue(vcpu);
3566 break;
3567 default:
3568 break;
3569 }
3570 }
3571 tss_selector = exit_qualification;
3572
3573 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3574 type != INTR_TYPE_EXT_INTR &&
3575 type != INTR_TYPE_NMI_INTR))
3576 skip_emulated_instruction(vcpu);
3577
3578 if (kvm_task_switch(vcpu, tss_selector, reason,
3579 has_error_code, error_code) == EMULATE_FAIL) {
3580 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3581 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3582 vcpu->run->internal.ndata = 0;
3583 return 0;
3584 }
3585
3586 /* clear all local breakpoint enable flags */
3587 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3588
3589 /*
3590 * TODO: What about debug traps on tss switch?
3591 * Are we supposed to inject them and update dr6?
3592 */
3593
3594 return 1;
3595 }
3596
3597 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3598 {
3599 unsigned long exit_qualification;
3600 gpa_t gpa;
3601 int gla_validity;
3602
3603 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3604
3605 if (exit_qualification & (1 << 6)) {
3606 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3607 return -EINVAL;
3608 }
3609
3610 gla_validity = (exit_qualification >> 7) & 0x3;
3611 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3612 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3613 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3614 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3615 vmcs_readl(GUEST_LINEAR_ADDRESS));
3616 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3617 (long unsigned int)exit_qualification);
3618 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3619 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3620 return 0;
3621 }
3622
3623 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3624 trace_kvm_page_fault(gpa, exit_qualification);
3625 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
3626 }
3627
3628 static u64 ept_rsvd_mask(u64 spte, int level)
3629 {
3630 int i;
3631 u64 mask = 0;
3632
3633 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3634 mask |= (1ULL << i);
3635
3636 if (level > 2)
3637 /* bits 7:3 reserved */
3638 mask |= 0xf8;
3639 else if (level == 2) {
3640 if (spte & (1ULL << 7))
3641 /* 2MB ref, bits 20:12 reserved */
3642 mask |= 0x1ff000;
3643 else
3644 /* bits 6:3 reserved */
3645 mask |= 0x78;
3646 }
3647
3648 return mask;
3649 }
3650
3651 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3652 int level)
3653 {
3654 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3655
3656 /* 010b (write-only) */
3657 WARN_ON((spte & 0x7) == 0x2);
3658
3659 /* 110b (write/execute) */
3660 WARN_ON((spte & 0x7) == 0x6);
3661
3662 /* 100b (execute-only) and value not supported by logical processor */
3663 if (!cpu_has_vmx_ept_execute_only())
3664 WARN_ON((spte & 0x7) == 0x4);
3665
3666 /* not 000b */
3667 if ((spte & 0x7)) {
3668 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3669
3670 if (rsvd_bits != 0) {
3671 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3672 __func__, rsvd_bits);
3673 WARN_ON(1);
3674 }
3675
3676 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3677 u64 ept_mem_type = (spte & 0x38) >> 3;
3678
3679 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3680 ept_mem_type == 7) {
3681 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3682 __func__, ept_mem_type);
3683 WARN_ON(1);
3684 }
3685 }
3686 }
3687 }
3688
3689 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3690 {
3691 u64 sptes[4];
3692 int nr_sptes, i;
3693 gpa_t gpa;
3694
3695 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3696
3697 printk(KERN_ERR "EPT: Misconfiguration.\n");
3698 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3699
3700 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3701
3702 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3703 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3704
3705 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3706 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3707
3708 return 0;
3709 }
3710
3711 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3712 {
3713 u32 cpu_based_vm_exec_control;
3714
3715 /* clear pending NMI */
3716 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3717 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3718 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3719 ++vcpu->stat.nmi_window_exits;
3720 kvm_make_request(KVM_REQ_EVENT, vcpu);
3721
3722 return 1;
3723 }
3724
3725 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3726 {
3727 struct vcpu_vmx *vmx = to_vmx(vcpu);
3728 enum emulation_result err = EMULATE_DONE;
3729 int ret = 1;
3730 u32 cpu_exec_ctrl;
3731 bool intr_window_requested;
3732
3733 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3734 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3735
3736 while (!guest_state_valid(vcpu)) {
3737 if (intr_window_requested
3738 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3739 return handle_interrupt_window(&vmx->vcpu);
3740
3741 err = emulate_instruction(vcpu, 0);
3742
3743 if (err == EMULATE_DO_MMIO) {
3744 ret = 0;
3745 goto out;
3746 }
3747
3748 if (err != EMULATE_DONE)
3749 return 0;
3750
3751 if (signal_pending(current))
3752 goto out;
3753 if (need_resched())
3754 schedule();
3755 }
3756
3757 vmx->emulation_required = 0;
3758 out:
3759 return ret;
3760 }
3761
3762 /*
3763 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3764 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3765 */
3766 static int handle_pause(struct kvm_vcpu *vcpu)
3767 {
3768 skip_emulated_instruction(vcpu);
3769 kvm_vcpu_on_spin(vcpu);
3770
3771 return 1;
3772 }
3773
3774 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3775 {
3776 kvm_queue_exception(vcpu, UD_VECTOR);
3777 return 1;
3778 }
3779
3780 /*
3781 * The exit handlers return 1 if the exit was handled fully and guest execution
3782 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3783 * to be done to userspace and return 0.
3784 */
3785 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3786 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3787 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3788 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3789 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3790 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3791 [EXIT_REASON_CR_ACCESS] = handle_cr,
3792 [EXIT_REASON_DR_ACCESS] = handle_dr,
3793 [EXIT_REASON_CPUID] = handle_cpuid,
3794 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3795 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3796 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3797 [EXIT_REASON_HLT] = handle_halt,
3798 [EXIT_REASON_INVD] = handle_invd,
3799 [EXIT_REASON_INVLPG] = handle_invlpg,
3800 [EXIT_REASON_VMCALL] = handle_vmcall,
3801 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3802 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3803 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3804 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3805 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3806 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3807 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3808 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3809 [EXIT_REASON_VMON] = handle_vmx_insn,
3810 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3811 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3812 [EXIT_REASON_WBINVD] = handle_wbinvd,
3813 [EXIT_REASON_XSETBV] = handle_xsetbv,
3814 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3815 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3816 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3817 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3818 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3819 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3820 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3821 };
3822
3823 static const int kvm_vmx_max_exit_handlers =
3824 ARRAY_SIZE(kvm_vmx_exit_handlers);
3825
3826 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3827 {
3828 *info1 = vmcs_readl(EXIT_QUALIFICATION);
3829 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3830 }
3831
3832 /*
3833 * The guest has exited. See if we can fix it or if we need userspace
3834 * assistance.
3835 */
3836 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3837 {
3838 struct vcpu_vmx *vmx = to_vmx(vcpu);
3839 u32 exit_reason = vmx->exit_reason;
3840 u32 vectoring_info = vmx->idt_vectoring_info;
3841
3842 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
3843
3844 /* If guest state is invalid, start emulating */
3845 if (vmx->emulation_required && emulate_invalid_guest_state)
3846 return handle_invalid_guest_state(vcpu);
3847
3848 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3849 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3850 vcpu->run->fail_entry.hardware_entry_failure_reason
3851 = exit_reason;
3852 return 0;
3853 }
3854
3855 if (unlikely(vmx->fail)) {
3856 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3857 vcpu->run->fail_entry.hardware_entry_failure_reason
3858 = vmcs_read32(VM_INSTRUCTION_ERROR);
3859 return 0;
3860 }
3861
3862 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3863 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3864 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3865 exit_reason != EXIT_REASON_TASK_SWITCH))
3866 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3867 "(0x%x) and exit reason is 0x%x\n",
3868 __func__, vectoring_info, exit_reason);
3869
3870 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3871 if (vmx_interrupt_allowed(vcpu)) {
3872 vmx->soft_vnmi_blocked = 0;
3873 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3874 vcpu->arch.nmi_pending) {
3875 /*
3876 * This CPU don't support us in finding the end of an
3877 * NMI-blocked window if the guest runs with IRQs
3878 * disabled. So we pull the trigger after 1 s of
3879 * futile waiting, but inform the user about this.
3880 */
3881 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3882 "state on VCPU %d after 1 s timeout\n",
3883 __func__, vcpu->vcpu_id);
3884 vmx->soft_vnmi_blocked = 0;
3885 }
3886 }
3887
3888 if (exit_reason < kvm_vmx_max_exit_handlers
3889 && kvm_vmx_exit_handlers[exit_reason])
3890 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3891 else {
3892 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3893 vcpu->run->hw.hardware_exit_reason = exit_reason;
3894 }
3895 return 0;
3896 }
3897
3898 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3899 {
3900 if (irr == -1 || tpr < irr) {
3901 vmcs_write32(TPR_THRESHOLD, 0);
3902 return;
3903 }
3904
3905 vmcs_write32(TPR_THRESHOLD, irr);
3906 }
3907
3908 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
3909 {
3910 u32 exit_intr_info;
3911
3912 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
3913 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
3914 return;
3915
3916 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3917 exit_intr_info = vmx->exit_intr_info;
3918
3919 /* Handle machine checks before interrupts are enabled */
3920 if (is_machine_check(exit_intr_info))
3921 kvm_machine_check();
3922
3923 /* We need to handle NMIs before interrupts are enabled */
3924 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3925 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3926 kvm_before_handle_nmi(&vmx->vcpu);
3927 asm("int $2");
3928 kvm_after_handle_nmi(&vmx->vcpu);
3929 }
3930 }
3931
3932 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3933 {
3934 u32 exit_intr_info;
3935 bool unblock_nmi;
3936 u8 vector;
3937 bool idtv_info_valid;
3938
3939 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3940
3941 if (cpu_has_virtual_nmis()) {
3942 if (vmx->nmi_known_unmasked)
3943 return;
3944 /*
3945 * Can't use vmx->exit_intr_info since we're not sure what
3946 * the exit reason is.
3947 */
3948 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3949 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3950 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3951 /*
3952 * SDM 3: 27.7.1.2 (September 2008)
3953 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3954 * a guest IRET fault.
3955 * SDM 3: 23.2.2 (September 2008)
3956 * Bit 12 is undefined in any of the following cases:
3957 * If the VM exit sets the valid bit in the IDT-vectoring
3958 * information field.
3959 * If the VM exit is due to a double fault.
3960 */
3961 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3962 vector != DF_VECTOR && !idtv_info_valid)
3963 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3964 GUEST_INTR_STATE_NMI);
3965 else
3966 vmx->nmi_known_unmasked =
3967 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
3968 & GUEST_INTR_STATE_NMI);
3969 } else if (unlikely(vmx->soft_vnmi_blocked))
3970 vmx->vnmi_blocked_time +=
3971 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3972 }
3973
3974 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3975 u32 idt_vectoring_info,
3976 int instr_len_field,
3977 int error_code_field)
3978 {
3979 u8 vector;
3980 int type;
3981 bool idtv_info_valid;
3982
3983 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3984
3985 vmx->vcpu.arch.nmi_injected = false;
3986 kvm_clear_exception_queue(&vmx->vcpu);
3987 kvm_clear_interrupt_queue(&vmx->vcpu);
3988
3989 if (!idtv_info_valid)
3990 return;
3991
3992 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3993
3994 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3995 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3996
3997 switch (type) {
3998 case INTR_TYPE_NMI_INTR:
3999 vmx->vcpu.arch.nmi_injected = true;
4000 /*
4001 * SDM 3: 27.7.1.2 (September 2008)
4002 * Clear bit "block by NMI" before VM entry if a NMI
4003 * delivery faulted.
4004 */
4005 vmx_set_nmi_mask(&vmx->vcpu, false);
4006 break;
4007 case INTR_TYPE_SOFT_EXCEPTION:
4008 vmx->vcpu.arch.event_exit_inst_len =
4009 vmcs_read32(instr_len_field);
4010 /* fall through */
4011 case INTR_TYPE_HARD_EXCEPTION:
4012 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
4013 u32 err = vmcs_read32(error_code_field);
4014 kvm_queue_exception_e(&vmx->vcpu, vector, err);
4015 } else
4016 kvm_queue_exception(&vmx->vcpu, vector);
4017 break;
4018 case INTR_TYPE_SOFT_INTR:
4019 vmx->vcpu.arch.event_exit_inst_len =
4020 vmcs_read32(instr_len_field);
4021 /* fall through */
4022 case INTR_TYPE_EXT_INTR:
4023 kvm_queue_interrupt(&vmx->vcpu, vector,
4024 type == INTR_TYPE_SOFT_INTR);
4025 break;
4026 default:
4027 break;
4028 }
4029 }
4030
4031 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
4032 {
4033 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
4034 VM_EXIT_INSTRUCTION_LEN,
4035 IDT_VECTORING_ERROR_CODE);
4036 }
4037
4038 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
4039 {
4040 __vmx_complete_interrupts(to_vmx(vcpu),
4041 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
4042 VM_ENTRY_INSTRUCTION_LEN,
4043 VM_ENTRY_EXCEPTION_ERROR_CODE);
4044
4045 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
4046 }
4047
4048 #ifdef CONFIG_X86_64
4049 #define R "r"
4050 #define Q "q"
4051 #else
4052 #define R "e"
4053 #define Q "l"
4054 #endif
4055
4056 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
4057 {
4058 struct vcpu_vmx *vmx = to_vmx(vcpu);
4059
4060 /* Record the guest's net vcpu time for enforced NMI injections. */
4061 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
4062 vmx->entry_time = ktime_get();
4063
4064 /* Don't enter VMX if guest state is invalid, let the exit handler
4065 start emulation until we arrive back to a valid state */
4066 if (vmx->emulation_required && emulate_invalid_guest_state)
4067 return;
4068
4069 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4070 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4071 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4072 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4073
4074 /* When single-stepping over STI and MOV SS, we must clear the
4075 * corresponding interruptibility bits in the guest state. Otherwise
4076 * vmentry fails as it then expects bit 14 (BS) in pending debug
4077 * exceptions being set, but that's not correct for the guest debugging
4078 * case. */
4079 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4080 vmx_set_interrupt_shadow(vcpu, 0);
4081
4082 asm(
4083 /* Store host registers */
4084 "push %%"R"dx; push %%"R"bp;"
4085 "push %%"R"cx \n\t" /* placeholder for guest rcx */
4086 "push %%"R"cx \n\t"
4087 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4088 "je 1f \n\t"
4089 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4090 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
4091 "1: \n\t"
4092 /* Reload cr2 if changed */
4093 "mov %c[cr2](%0), %%"R"ax \n\t"
4094 "mov %%cr2, %%"R"dx \n\t"
4095 "cmp %%"R"ax, %%"R"dx \n\t"
4096 "je 2f \n\t"
4097 "mov %%"R"ax, %%cr2 \n\t"
4098 "2: \n\t"
4099 /* Check if vmlaunch of vmresume is needed */
4100 "cmpl $0, %c[launched](%0) \n\t"
4101 /* Load guest registers. Don't clobber flags. */
4102 "mov %c[rax](%0), %%"R"ax \n\t"
4103 "mov %c[rbx](%0), %%"R"bx \n\t"
4104 "mov %c[rdx](%0), %%"R"dx \n\t"
4105 "mov %c[rsi](%0), %%"R"si \n\t"
4106 "mov %c[rdi](%0), %%"R"di \n\t"
4107 "mov %c[rbp](%0), %%"R"bp \n\t"
4108 #ifdef CONFIG_X86_64
4109 "mov %c[r8](%0), %%r8 \n\t"
4110 "mov %c[r9](%0), %%r9 \n\t"
4111 "mov %c[r10](%0), %%r10 \n\t"
4112 "mov %c[r11](%0), %%r11 \n\t"
4113 "mov %c[r12](%0), %%r12 \n\t"
4114 "mov %c[r13](%0), %%r13 \n\t"
4115 "mov %c[r14](%0), %%r14 \n\t"
4116 "mov %c[r15](%0), %%r15 \n\t"
4117 #endif
4118 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4119
4120 /* Enter guest mode */
4121 "jne .Llaunched \n\t"
4122 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4123 "jmp .Lkvm_vmx_return \n\t"
4124 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4125 ".Lkvm_vmx_return: "
4126 /* Save guest registers, load host registers, keep flags */
4127 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4128 "pop %0 \n\t"
4129 "mov %%"R"ax, %c[rax](%0) \n\t"
4130 "mov %%"R"bx, %c[rbx](%0) \n\t"
4131 "pop"Q" %c[rcx](%0) \n\t"
4132 "mov %%"R"dx, %c[rdx](%0) \n\t"
4133 "mov %%"R"si, %c[rsi](%0) \n\t"
4134 "mov %%"R"di, %c[rdi](%0) \n\t"
4135 "mov %%"R"bp, %c[rbp](%0) \n\t"
4136 #ifdef CONFIG_X86_64
4137 "mov %%r8, %c[r8](%0) \n\t"
4138 "mov %%r9, %c[r9](%0) \n\t"
4139 "mov %%r10, %c[r10](%0) \n\t"
4140 "mov %%r11, %c[r11](%0) \n\t"
4141 "mov %%r12, %c[r12](%0) \n\t"
4142 "mov %%r13, %c[r13](%0) \n\t"
4143 "mov %%r14, %c[r14](%0) \n\t"
4144 "mov %%r15, %c[r15](%0) \n\t"
4145 #endif
4146 "mov %%cr2, %%"R"ax \n\t"
4147 "mov %%"R"ax, %c[cr2](%0) \n\t"
4148
4149 "pop %%"R"bp; pop %%"R"dx \n\t"
4150 "setbe %c[fail](%0) \n\t"
4151 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4152 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4153 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4154 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4155 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4156 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4157 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4158 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4159 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4160 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4161 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4162 #ifdef CONFIG_X86_64
4163 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4164 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4165 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4166 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4167 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4168 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4169 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4170 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4171 #endif
4172 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4173 [wordsize]"i"(sizeof(ulong))
4174 : "cc", "memory"
4175 , R"ax", R"bx", R"di", R"si"
4176 #ifdef CONFIG_X86_64
4177 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4178 #endif
4179 );
4180
4181 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4182 | (1 << VCPU_EXREG_RFLAGS)
4183 | (1 << VCPU_EXREG_CPL)
4184 | (1 << VCPU_EXREG_PDPTR)
4185 | (1 << VCPU_EXREG_CR3));
4186 vcpu->arch.regs_dirty = 0;
4187
4188 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4189
4190 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4191 vmx->launched = 1;
4192
4193 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4194
4195 vmx_complete_atomic_exit(vmx);
4196 vmx_recover_nmi_blocking(vmx);
4197 vmx_complete_interrupts(vmx);
4198 }
4199
4200 #undef R
4201 #undef Q
4202
4203 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4204 {
4205 struct vcpu_vmx *vmx = to_vmx(vcpu);
4206
4207 if (vmx->vmcs) {
4208 vcpu_clear(vmx);
4209 free_vmcs(vmx->vmcs);
4210 vmx->vmcs = NULL;
4211 }
4212 }
4213
4214 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4215 {
4216 struct vcpu_vmx *vmx = to_vmx(vcpu);
4217
4218 free_vpid(vmx);
4219 vmx_free_vmcs(vcpu);
4220 kfree(vmx->guest_msrs);
4221 kvm_vcpu_uninit(vcpu);
4222 kmem_cache_free(kvm_vcpu_cache, vmx);
4223 }
4224
4225 static inline void vmcs_init(struct vmcs *vmcs)
4226 {
4227 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4228
4229 if (!vmm_exclusive)
4230 kvm_cpu_vmxon(phys_addr);
4231
4232 vmcs_clear(vmcs);
4233
4234 if (!vmm_exclusive)
4235 kvm_cpu_vmxoff();
4236 }
4237
4238 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4239 {
4240 int err;
4241 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4242 int cpu;
4243
4244 if (!vmx)
4245 return ERR_PTR(-ENOMEM);
4246
4247 allocate_vpid(vmx);
4248
4249 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4250 if (err)
4251 goto free_vcpu;
4252
4253 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4254 err = -ENOMEM;
4255 if (!vmx->guest_msrs) {
4256 goto uninit_vcpu;
4257 }
4258
4259 vmx->vmcs = alloc_vmcs();
4260 if (!vmx->vmcs)
4261 goto free_msrs;
4262
4263 vmcs_init(vmx->vmcs);
4264
4265 cpu = get_cpu();
4266 vmx_vcpu_load(&vmx->vcpu, cpu);
4267 vmx->vcpu.cpu = cpu;
4268 err = vmx_vcpu_setup(vmx);
4269 vmx_vcpu_put(&vmx->vcpu);
4270 put_cpu();
4271 if (err)
4272 goto free_vmcs;
4273 if (vm_need_virtualize_apic_accesses(kvm))
4274 err = alloc_apic_access_page(kvm);
4275 if (err)
4276 goto free_vmcs;
4277
4278 if (enable_ept) {
4279 if (!kvm->arch.ept_identity_map_addr)
4280 kvm->arch.ept_identity_map_addr =
4281 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4282 err = -ENOMEM;
4283 if (alloc_identity_pagetable(kvm) != 0)
4284 goto free_vmcs;
4285 if (!init_rmode_identity_map(kvm))
4286 goto free_vmcs;
4287 }
4288
4289 return &vmx->vcpu;
4290
4291 free_vmcs:
4292 free_vmcs(vmx->vmcs);
4293 free_msrs:
4294 kfree(vmx->guest_msrs);
4295 uninit_vcpu:
4296 kvm_vcpu_uninit(&vmx->vcpu);
4297 free_vcpu:
4298 free_vpid(vmx);
4299 kmem_cache_free(kvm_vcpu_cache, vmx);
4300 return ERR_PTR(err);
4301 }
4302
4303 static void __init vmx_check_processor_compat(void *rtn)
4304 {
4305 struct vmcs_config vmcs_conf;
4306
4307 *(int *)rtn = 0;
4308 if (setup_vmcs_config(&vmcs_conf) < 0)
4309 *(int *)rtn = -EIO;
4310 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4311 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4312 smp_processor_id());
4313 *(int *)rtn = -EIO;
4314 }
4315 }
4316
4317 static int get_ept_level(void)
4318 {
4319 return VMX_EPT_DEFAULT_GAW + 1;
4320 }
4321
4322 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4323 {
4324 u64 ret;
4325
4326 /* For VT-d and EPT combination
4327 * 1. MMIO: always map as UC
4328 * 2. EPT with VT-d:
4329 * a. VT-d without snooping control feature: can't guarantee the
4330 * result, try to trust guest.
4331 * b. VT-d with snooping control feature: snooping control feature of
4332 * VT-d engine can guarantee the cache correctness. Just set it
4333 * to WB to keep consistent with host. So the same as item 3.
4334 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4335 * consistent with host MTRR
4336 */
4337 if (is_mmio)
4338 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4339 else if (vcpu->kvm->arch.iommu_domain &&
4340 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4341 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4342 VMX_EPT_MT_EPTE_SHIFT;
4343 else
4344 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4345 | VMX_EPT_IPAT_BIT;
4346
4347 return ret;
4348 }
4349
4350 #define _ER(x) { EXIT_REASON_##x, #x }
4351
4352 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4353 _ER(EXCEPTION_NMI),
4354 _ER(EXTERNAL_INTERRUPT),
4355 _ER(TRIPLE_FAULT),
4356 _ER(PENDING_INTERRUPT),
4357 _ER(NMI_WINDOW),
4358 _ER(TASK_SWITCH),
4359 _ER(CPUID),
4360 _ER(HLT),
4361 _ER(INVLPG),
4362 _ER(RDPMC),
4363 _ER(RDTSC),
4364 _ER(VMCALL),
4365 _ER(VMCLEAR),
4366 _ER(VMLAUNCH),
4367 _ER(VMPTRLD),
4368 _ER(VMPTRST),
4369 _ER(VMREAD),
4370 _ER(VMRESUME),
4371 _ER(VMWRITE),
4372 _ER(VMOFF),
4373 _ER(VMON),
4374 _ER(CR_ACCESS),
4375 _ER(DR_ACCESS),
4376 _ER(IO_INSTRUCTION),
4377 _ER(MSR_READ),
4378 _ER(MSR_WRITE),
4379 _ER(MWAIT_INSTRUCTION),
4380 _ER(MONITOR_INSTRUCTION),
4381 _ER(PAUSE_INSTRUCTION),
4382 _ER(MCE_DURING_VMENTRY),
4383 _ER(TPR_BELOW_THRESHOLD),
4384 _ER(APIC_ACCESS),
4385 _ER(EPT_VIOLATION),
4386 _ER(EPT_MISCONFIG),
4387 _ER(WBINVD),
4388 { -1, NULL }
4389 };
4390
4391 #undef _ER
4392
4393 static int vmx_get_lpage_level(void)
4394 {
4395 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4396 return PT_DIRECTORY_LEVEL;
4397 else
4398 /* For shadow and EPT supported 1GB page */
4399 return PT_PDPE_LEVEL;
4400 }
4401
4402 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4403 {
4404 struct kvm_cpuid_entry2 *best;
4405 struct vcpu_vmx *vmx = to_vmx(vcpu);
4406 u32 exec_control;
4407
4408 vmx->rdtscp_enabled = false;
4409 if (vmx_rdtscp_supported()) {
4410 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4411 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4412 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4413 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4414 vmx->rdtscp_enabled = true;
4415 else {
4416 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4417 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4418 exec_control);
4419 }
4420 }
4421 }
4422 }
4423
4424 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4425 {
4426 }
4427
4428 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
4429 struct x86_instruction_info *info,
4430 enum x86_intercept_stage stage)
4431 {
4432 return X86EMUL_CONTINUE;
4433 }
4434
4435 static struct kvm_x86_ops vmx_x86_ops = {
4436 .cpu_has_kvm_support = cpu_has_kvm_support,
4437 .disabled_by_bios = vmx_disabled_by_bios,
4438 .hardware_setup = hardware_setup,
4439 .hardware_unsetup = hardware_unsetup,
4440 .check_processor_compatibility = vmx_check_processor_compat,
4441 .hardware_enable = hardware_enable,
4442 .hardware_disable = hardware_disable,
4443 .cpu_has_accelerated_tpr = report_flexpriority,
4444
4445 .vcpu_create = vmx_create_vcpu,
4446 .vcpu_free = vmx_free_vcpu,
4447 .vcpu_reset = vmx_vcpu_reset,
4448
4449 .prepare_guest_switch = vmx_save_host_state,
4450 .vcpu_load = vmx_vcpu_load,
4451 .vcpu_put = vmx_vcpu_put,
4452
4453 .set_guest_debug = set_guest_debug,
4454 .get_msr = vmx_get_msr,
4455 .set_msr = vmx_set_msr,
4456 .get_segment_base = vmx_get_segment_base,
4457 .get_segment = vmx_get_segment,
4458 .set_segment = vmx_set_segment,
4459 .get_cpl = vmx_get_cpl,
4460 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4461 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4462 .decache_cr3 = vmx_decache_cr3,
4463 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4464 .set_cr0 = vmx_set_cr0,
4465 .set_cr3 = vmx_set_cr3,
4466 .set_cr4 = vmx_set_cr4,
4467 .set_efer = vmx_set_efer,
4468 .get_idt = vmx_get_idt,
4469 .set_idt = vmx_set_idt,
4470 .get_gdt = vmx_get_gdt,
4471 .set_gdt = vmx_set_gdt,
4472 .set_dr7 = vmx_set_dr7,
4473 .cache_reg = vmx_cache_reg,
4474 .get_rflags = vmx_get_rflags,
4475 .set_rflags = vmx_set_rflags,
4476 .fpu_activate = vmx_fpu_activate,
4477 .fpu_deactivate = vmx_fpu_deactivate,
4478
4479 .tlb_flush = vmx_flush_tlb,
4480
4481 .run = vmx_vcpu_run,
4482 .handle_exit = vmx_handle_exit,
4483 .skip_emulated_instruction = skip_emulated_instruction,
4484 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4485 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4486 .patch_hypercall = vmx_patch_hypercall,
4487 .set_irq = vmx_inject_irq,
4488 .set_nmi = vmx_inject_nmi,
4489 .queue_exception = vmx_queue_exception,
4490 .cancel_injection = vmx_cancel_injection,
4491 .interrupt_allowed = vmx_interrupt_allowed,
4492 .nmi_allowed = vmx_nmi_allowed,
4493 .get_nmi_mask = vmx_get_nmi_mask,
4494 .set_nmi_mask = vmx_set_nmi_mask,
4495 .enable_nmi_window = enable_nmi_window,
4496 .enable_irq_window = enable_irq_window,
4497 .update_cr8_intercept = update_cr8_intercept,
4498
4499 .set_tss_addr = vmx_set_tss_addr,
4500 .get_tdp_level = get_ept_level,
4501 .get_mt_mask = vmx_get_mt_mask,
4502
4503 .get_exit_info = vmx_get_exit_info,
4504 .exit_reasons_str = vmx_exit_reasons_str,
4505
4506 .get_lpage_level = vmx_get_lpage_level,
4507
4508 .cpuid_update = vmx_cpuid_update,
4509
4510 .rdtscp_supported = vmx_rdtscp_supported,
4511
4512 .set_supported_cpuid = vmx_set_supported_cpuid,
4513
4514 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4515
4516 .set_tsc_khz = vmx_set_tsc_khz,
4517 .write_tsc_offset = vmx_write_tsc_offset,
4518 .adjust_tsc_offset = vmx_adjust_tsc_offset,
4519 .compute_tsc_offset = vmx_compute_tsc_offset,
4520
4521 .set_tdp_cr3 = vmx_set_cr3,
4522
4523 .check_intercept = vmx_check_intercept,
4524 };
4525
4526 static int __init vmx_init(void)
4527 {
4528 int r, i;
4529
4530 rdmsrl_safe(MSR_EFER, &host_efer);
4531
4532 for (i = 0; i < NR_VMX_MSR; ++i)
4533 kvm_define_shared_msr(i, vmx_msr_index[i]);
4534
4535 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4536 if (!vmx_io_bitmap_a)
4537 return -ENOMEM;
4538
4539 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4540 if (!vmx_io_bitmap_b) {
4541 r = -ENOMEM;
4542 goto out;
4543 }
4544
4545 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4546 if (!vmx_msr_bitmap_legacy) {
4547 r = -ENOMEM;
4548 goto out1;
4549 }
4550
4551 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4552 if (!vmx_msr_bitmap_longmode) {
4553 r = -ENOMEM;
4554 goto out2;
4555 }
4556
4557 /*
4558 * Allow direct access to the PC debug port (it is often used for I/O
4559 * delays, but the vmexits simply slow things down).
4560 */
4561 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4562 clear_bit(0x80, vmx_io_bitmap_a);
4563
4564 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4565
4566 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4567 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4568
4569 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4570
4571 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4572 __alignof__(struct vcpu_vmx), THIS_MODULE);
4573 if (r)
4574 goto out3;
4575
4576 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4577 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4578 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4579 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4580 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4581 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4582
4583 if (enable_ept) {
4584 bypass_guest_pf = 0;
4585 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4586 VMX_EPT_EXECUTABLE_MASK);
4587 kvm_enable_tdp();
4588 } else
4589 kvm_disable_tdp();
4590
4591 if (bypass_guest_pf)
4592 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4593
4594 return 0;
4595
4596 out3:
4597 free_page((unsigned long)vmx_msr_bitmap_longmode);
4598 out2:
4599 free_page((unsigned long)vmx_msr_bitmap_legacy);
4600 out1:
4601 free_page((unsigned long)vmx_io_bitmap_b);
4602 out:
4603 free_page((unsigned long)vmx_io_bitmap_a);
4604 return r;
4605 }
4606
4607 static void __exit vmx_exit(void)
4608 {
4609 free_page((unsigned long)vmx_msr_bitmap_legacy);
4610 free_page((unsigned long)vmx_msr_bitmap_longmode);
4611 free_page((unsigned long)vmx_io_bitmap_b);
4612 free_page((unsigned long)vmx_io_bitmap_a);
4613
4614 kvm_exit();
4615 }
4616
4617 module_init(vmx_init)
4618 module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)