2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/moduleparam.h>
33 #include <linux/export.h>
34 #include <linux/swap.h>
35 #include <linux/hugetlb.h>
36 #include <linux/compiler.h>
37 #include <linux/srcu.h>
38 #include <linux/slab.h>
39 #include <linux/sched/signal.h>
40 #include <linux/uaccess.h>
41 #include <linux/hash.h>
42 #include <linux/kern_levels.h>
45 #include <asm/cmpxchg.h>
48 #include <asm/kvm_page_track.h>
52 * When setting this variable to true it enables Two-Dimensional-Paging
53 * where the hardware walks 2 page tables:
54 * 1. the guest-virtual to guest-physical
55 * 2. while doing 1. it walks guest-physical to host-physical
56 * If the hardware supports that we don't need to do shadow paging.
58 bool tdp_enabled
= false;
62 AUDIT_POST_PAGE_FAULT
,
73 module_param(dbg
, bool, 0644);
75 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
76 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
77 #define MMU_WARN_ON(x) WARN_ON(x)
79 #define pgprintk(x...) do { } while (0)
80 #define rmap_printk(x...) do { } while (0)
81 #define MMU_WARN_ON(x) do { } while (0)
84 #define PTE_PREFETCH_NUM 8
86 #define PT_FIRST_AVAIL_BITS_SHIFT 10
87 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
89 #define PT64_LEVEL_BITS 9
91 #define PT64_LEVEL_SHIFT(level) \
92 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
94 #define PT64_INDEX(address, level)\
95 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
98 #define PT32_LEVEL_BITS 10
100 #define PT32_LEVEL_SHIFT(level) \
101 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
103 #define PT32_LVL_OFFSET_MASK(level) \
104 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
105 * PT32_LEVEL_BITS))) - 1))
107 #define PT32_INDEX(address, level)\
108 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
111 #define PT64_BASE_ADDR_MASK __sme_clr((((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)))
112 #define PT64_DIR_BASE_ADDR_MASK \
113 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
114 #define PT64_LVL_ADDR_MASK(level) \
115 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
116 * PT64_LEVEL_BITS))) - 1))
117 #define PT64_LVL_OFFSET_MASK(level) \
118 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
119 * PT64_LEVEL_BITS))) - 1))
121 #define PT32_BASE_ADDR_MASK PAGE_MASK
122 #define PT32_DIR_BASE_ADDR_MASK \
123 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
124 #define PT32_LVL_ADDR_MASK(level) \
125 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT32_LEVEL_BITS))) - 1))
128 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
129 | shadow_x_mask | shadow_nx_mask | shadow_me_mask)
131 #define ACC_EXEC_MASK 1
132 #define ACC_WRITE_MASK PT_WRITABLE_MASK
133 #define ACC_USER_MASK PT_USER_MASK
134 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
136 /* The mask for the R/X bits in EPT PTEs */
137 #define PT64_EPT_READABLE_MASK 0x1ull
138 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
140 #include <trace/events/kvm.h>
142 #define CREATE_TRACE_POINTS
143 #include "mmutrace.h"
145 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
146 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
148 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
150 /* make pte_list_desc fit well in cache line */
151 #define PTE_LIST_EXT 3
153 struct pte_list_desc
{
154 u64
*sptes
[PTE_LIST_EXT
];
155 struct pte_list_desc
*more
;
158 struct kvm_shadow_walk_iterator
{
166 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
167 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
168 shadow_walk_okay(&(_walker)); \
169 shadow_walk_next(&(_walker)))
171 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
172 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
173 shadow_walk_okay(&(_walker)) && \
174 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
175 __shadow_walk_next(&(_walker), spte))
177 static struct kmem_cache
*pte_list_desc_cache
;
178 static struct kmem_cache
*mmu_page_header_cache
;
179 static struct percpu_counter kvm_total_used_mmu_pages
;
181 static u64 __read_mostly shadow_nx_mask
;
182 static u64 __read_mostly shadow_x_mask
; /* mutual exclusive with nx_mask */
183 static u64 __read_mostly shadow_user_mask
;
184 static u64 __read_mostly shadow_accessed_mask
;
185 static u64 __read_mostly shadow_dirty_mask
;
186 static u64 __read_mostly shadow_mmio_mask
;
187 static u64 __read_mostly shadow_mmio_value
;
188 static u64 __read_mostly shadow_present_mask
;
189 static u64 __read_mostly shadow_me_mask
;
192 * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value.
193 * Non-present SPTEs with shadow_acc_track_value set are in place for access
196 static u64 __read_mostly shadow_acc_track_mask
;
197 static const u64 shadow_acc_track_value
= SPTE_SPECIAL_MASK
;
200 * The mask/shift to use for saving the original R/X bits when marking the PTE
201 * as not-present for access tracking purposes. We do not save the W bit as the
202 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
203 * restored only when a write is attempted to the page.
205 static const u64 shadow_acc_track_saved_bits_mask
= PT64_EPT_READABLE_MASK
|
206 PT64_EPT_EXECUTABLE_MASK
;
207 static const u64 shadow_acc_track_saved_bits_shift
= PT64_SECOND_AVAIL_BITS_SHIFT
;
209 static void mmu_spte_set(u64
*sptep
, u64 spte
);
210 static void mmu_free_roots(struct kvm_vcpu
*vcpu
);
212 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask
, u64 mmio_value
)
214 BUG_ON((mmio_mask
& mmio_value
) != mmio_value
);
215 shadow_mmio_value
= mmio_value
| SPTE_SPECIAL_MASK
;
216 shadow_mmio_mask
= mmio_mask
| SPTE_SPECIAL_MASK
;
218 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask
);
220 static inline bool sp_ad_disabled(struct kvm_mmu_page
*sp
)
222 return sp
->role
.ad_disabled
;
225 static inline bool spte_ad_enabled(u64 spte
)
227 MMU_WARN_ON((spte
& shadow_mmio_mask
) == shadow_mmio_value
);
228 return !(spte
& shadow_acc_track_value
);
231 static inline u64
spte_shadow_accessed_mask(u64 spte
)
233 MMU_WARN_ON((spte
& shadow_mmio_mask
) == shadow_mmio_value
);
234 return spte_ad_enabled(spte
) ? shadow_accessed_mask
: 0;
237 static inline u64
spte_shadow_dirty_mask(u64 spte
)
239 MMU_WARN_ON((spte
& shadow_mmio_mask
) == shadow_mmio_value
);
240 return spte_ad_enabled(spte
) ? shadow_dirty_mask
: 0;
243 static inline bool is_access_track_spte(u64 spte
)
245 return !spte_ad_enabled(spte
) && (spte
& shadow_acc_track_mask
) == 0;
249 * the low bit of the generation number is always presumed to be zero.
250 * This disables mmio caching during memslot updates. The concept is
251 * similar to a seqcount but instead of retrying the access we just punt
252 * and ignore the cache.
254 * spte bits 3-11 are used as bits 1-9 of the generation number,
255 * the bits 52-61 are used as bits 10-19 of the generation number.
257 #define MMIO_SPTE_GEN_LOW_SHIFT 2
258 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
260 #define MMIO_GEN_SHIFT 20
261 #define MMIO_GEN_LOW_SHIFT 10
262 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
263 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
265 static u64
generation_mmio_spte_mask(unsigned int gen
)
269 WARN_ON(gen
& ~MMIO_GEN_MASK
);
271 mask
= (gen
& MMIO_GEN_LOW_MASK
) << MMIO_SPTE_GEN_LOW_SHIFT
;
272 mask
|= ((u64
)gen
>> MMIO_GEN_LOW_SHIFT
) << MMIO_SPTE_GEN_HIGH_SHIFT
;
276 static unsigned int get_mmio_spte_generation(u64 spte
)
280 spte
&= ~shadow_mmio_mask
;
282 gen
= (spte
>> MMIO_SPTE_GEN_LOW_SHIFT
) & MMIO_GEN_LOW_MASK
;
283 gen
|= (spte
>> MMIO_SPTE_GEN_HIGH_SHIFT
) << MMIO_GEN_LOW_SHIFT
;
287 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu
*vcpu
)
289 return kvm_vcpu_memslots(vcpu
)->generation
& MMIO_GEN_MASK
;
292 static void mark_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 gfn
,
295 unsigned int gen
= kvm_current_mmio_generation(vcpu
);
296 u64 mask
= generation_mmio_spte_mask(gen
);
298 access
&= ACC_WRITE_MASK
| ACC_USER_MASK
;
299 mask
|= shadow_mmio_value
| access
| gfn
<< PAGE_SHIFT
;
301 trace_mark_mmio_spte(sptep
, gfn
, access
, gen
);
302 mmu_spte_set(sptep
, mask
);
305 static bool is_mmio_spte(u64 spte
)
307 return (spte
& shadow_mmio_mask
) == shadow_mmio_value
;
310 static gfn_t
get_mmio_spte_gfn(u64 spte
)
312 u64 mask
= generation_mmio_spte_mask(MMIO_GEN_MASK
) | shadow_mmio_mask
;
313 return (spte
& ~mask
) >> PAGE_SHIFT
;
316 static unsigned get_mmio_spte_access(u64 spte
)
318 u64 mask
= generation_mmio_spte_mask(MMIO_GEN_MASK
) | shadow_mmio_mask
;
319 return (spte
& ~mask
) & ~PAGE_MASK
;
322 static bool set_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
323 kvm_pfn_t pfn
, unsigned access
)
325 if (unlikely(is_noslot_pfn(pfn
))) {
326 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
333 static bool check_mmio_spte(struct kvm_vcpu
*vcpu
, u64 spte
)
335 unsigned int kvm_gen
, spte_gen
;
337 kvm_gen
= kvm_current_mmio_generation(vcpu
);
338 spte_gen
= get_mmio_spte_generation(spte
);
340 trace_check_mmio_spte(spte
, kvm_gen
, spte_gen
);
341 return likely(kvm_gen
== spte_gen
);
345 * Sets the shadow PTE masks used by the MMU.
348 * - Setting either @accessed_mask or @dirty_mask requires setting both
349 * - At least one of @accessed_mask or @acc_track_mask must be set
351 void kvm_mmu_set_mask_ptes(u64 user_mask
, u64 accessed_mask
,
352 u64 dirty_mask
, u64 nx_mask
, u64 x_mask
, u64 p_mask
,
353 u64 acc_track_mask
, u64 me_mask
)
355 BUG_ON(!dirty_mask
!= !accessed_mask
);
356 BUG_ON(!accessed_mask
&& !acc_track_mask
);
357 BUG_ON(acc_track_mask
& shadow_acc_track_value
);
359 shadow_user_mask
= user_mask
;
360 shadow_accessed_mask
= accessed_mask
;
361 shadow_dirty_mask
= dirty_mask
;
362 shadow_nx_mask
= nx_mask
;
363 shadow_x_mask
= x_mask
;
364 shadow_present_mask
= p_mask
;
365 shadow_acc_track_mask
= acc_track_mask
;
366 shadow_me_mask
= me_mask
;
368 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes
);
370 void kvm_mmu_clear_all_pte_masks(void)
372 shadow_user_mask
= 0;
373 shadow_accessed_mask
= 0;
374 shadow_dirty_mask
= 0;
377 shadow_mmio_mask
= 0;
378 shadow_present_mask
= 0;
379 shadow_acc_track_mask
= 0;
382 static int is_cpuid_PSE36(void)
387 static int is_nx(struct kvm_vcpu
*vcpu
)
389 return vcpu
->arch
.efer
& EFER_NX
;
392 static int is_shadow_present_pte(u64 pte
)
394 return (pte
!= 0) && !is_mmio_spte(pte
);
397 static int is_large_pte(u64 pte
)
399 return pte
& PT_PAGE_SIZE_MASK
;
402 static int is_last_spte(u64 pte
, int level
)
404 if (level
== PT_PAGE_TABLE_LEVEL
)
406 if (is_large_pte(pte
))
411 static bool is_executable_pte(u64 spte
)
413 return (spte
& (shadow_x_mask
| shadow_nx_mask
)) == shadow_x_mask
;
416 static kvm_pfn_t
spte_to_pfn(u64 pte
)
418 return (pte
& PT64_BASE_ADDR_MASK
) >> PAGE_SHIFT
;
421 static gfn_t
pse36_gfn_delta(u32 gpte
)
423 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
425 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
429 static void __set_spte(u64
*sptep
, u64 spte
)
431 WRITE_ONCE(*sptep
, spte
);
434 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
436 WRITE_ONCE(*sptep
, spte
);
439 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
441 return xchg(sptep
, spte
);
444 static u64
__get_spte_lockless(u64
*sptep
)
446 return ACCESS_ONCE(*sptep
);
457 static void count_spte_clear(u64
*sptep
, u64 spte
)
459 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
461 if (is_shadow_present_pte(spte
))
464 /* Ensure the spte is completely set before we increase the count */
466 sp
->clear_spte_count
++;
469 static void __set_spte(u64
*sptep
, u64 spte
)
471 union split_spte
*ssptep
, sspte
;
473 ssptep
= (union split_spte
*)sptep
;
474 sspte
= (union split_spte
)spte
;
476 ssptep
->spte_high
= sspte
.spte_high
;
479 * If we map the spte from nonpresent to present, We should store
480 * the high bits firstly, then set present bit, so cpu can not
481 * fetch this spte while we are setting the spte.
485 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
488 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
490 union split_spte
*ssptep
, sspte
;
492 ssptep
= (union split_spte
*)sptep
;
493 sspte
= (union split_spte
)spte
;
495 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
498 * If we map the spte from present to nonpresent, we should clear
499 * present bit firstly to avoid vcpu fetch the old high bits.
503 ssptep
->spte_high
= sspte
.spte_high
;
504 count_spte_clear(sptep
, spte
);
507 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
509 union split_spte
*ssptep
, sspte
, orig
;
511 ssptep
= (union split_spte
*)sptep
;
512 sspte
= (union split_spte
)spte
;
514 /* xchg acts as a barrier before the setting of the high bits */
515 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
516 orig
.spte_high
= ssptep
->spte_high
;
517 ssptep
->spte_high
= sspte
.spte_high
;
518 count_spte_clear(sptep
, spte
);
524 * The idea using the light way get the spte on x86_32 guest is from
525 * gup_get_pte(arch/x86/mm/gup.c).
527 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
528 * coalesces them and we are running out of the MMU lock. Therefore
529 * we need to protect against in-progress updates of the spte.
531 * Reading the spte while an update is in progress may get the old value
532 * for the high part of the spte. The race is fine for a present->non-present
533 * change (because the high part of the spte is ignored for non-present spte),
534 * but for a present->present change we must reread the spte.
536 * All such changes are done in two steps (present->non-present and
537 * non-present->present), hence it is enough to count the number of
538 * present->non-present updates: if it changed while reading the spte,
539 * we might have hit the race. This is done using clear_spte_count.
541 static u64
__get_spte_lockless(u64
*sptep
)
543 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
544 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
548 count
= sp
->clear_spte_count
;
551 spte
.spte_low
= orig
->spte_low
;
554 spte
.spte_high
= orig
->spte_high
;
557 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
558 count
!= sp
->clear_spte_count
))
565 static bool spte_can_locklessly_be_made_writable(u64 spte
)
567 return (spte
& (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
)) ==
568 (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
);
571 static bool spte_has_volatile_bits(u64 spte
)
573 if (!is_shadow_present_pte(spte
))
577 * Always atomically update spte if it can be updated
578 * out of mmu-lock, it can ensure dirty bit is not lost,
579 * also, it can help us to get a stable is_writable_pte()
580 * to ensure tlb flush is not missed.
582 if (spte_can_locklessly_be_made_writable(spte
) ||
583 is_access_track_spte(spte
))
586 if (spte_ad_enabled(spte
)) {
587 if ((spte
& shadow_accessed_mask
) == 0 ||
588 (is_writable_pte(spte
) && (spte
& shadow_dirty_mask
) == 0))
595 static bool is_accessed_spte(u64 spte
)
597 u64 accessed_mask
= spte_shadow_accessed_mask(spte
);
599 return accessed_mask
? spte
& accessed_mask
600 : !is_access_track_spte(spte
);
603 static bool is_dirty_spte(u64 spte
)
605 u64 dirty_mask
= spte_shadow_dirty_mask(spte
);
607 return dirty_mask
? spte
& dirty_mask
: spte
& PT_WRITABLE_MASK
;
610 /* Rules for using mmu_spte_set:
611 * Set the sptep from nonpresent to present.
612 * Note: the sptep being assigned *must* be either not present
613 * or in a state where the hardware will not attempt to update
616 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
618 WARN_ON(is_shadow_present_pte(*sptep
));
619 __set_spte(sptep
, new_spte
);
623 * Update the SPTE (excluding the PFN), but do not track changes in its
624 * accessed/dirty status.
626 static u64
mmu_spte_update_no_track(u64
*sptep
, u64 new_spte
)
628 u64 old_spte
= *sptep
;
630 WARN_ON(!is_shadow_present_pte(new_spte
));
632 if (!is_shadow_present_pte(old_spte
)) {
633 mmu_spte_set(sptep
, new_spte
);
637 if (!spte_has_volatile_bits(old_spte
))
638 __update_clear_spte_fast(sptep
, new_spte
);
640 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
642 WARN_ON(spte_to_pfn(old_spte
) != spte_to_pfn(new_spte
));
647 /* Rules for using mmu_spte_update:
648 * Update the state bits, it means the mapped pfn is not changed.
650 * Whenever we overwrite a writable spte with a read-only one we
651 * should flush remote TLBs. Otherwise rmap_write_protect
652 * will find a read-only spte, even though the writable spte
653 * might be cached on a CPU's TLB, the return value indicates this
656 * Returns true if the TLB needs to be flushed
658 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
661 u64 old_spte
= mmu_spte_update_no_track(sptep
, new_spte
);
663 if (!is_shadow_present_pte(old_spte
))
667 * For the spte updated out of mmu-lock is safe, since
668 * we always atomically update it, see the comments in
669 * spte_has_volatile_bits().
671 if (spte_can_locklessly_be_made_writable(old_spte
) &&
672 !is_writable_pte(new_spte
))
676 * Flush TLB when accessed/dirty states are changed in the page tables,
677 * to guarantee consistency between TLB and page tables.
680 if (is_accessed_spte(old_spte
) && !is_accessed_spte(new_spte
)) {
682 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
685 if (is_dirty_spte(old_spte
) && !is_dirty_spte(new_spte
)) {
687 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
694 * Rules for using mmu_spte_clear_track_bits:
695 * It sets the sptep from present to nonpresent, and track the
696 * state bits, it is used to clear the last level sptep.
697 * Returns non-zero if the PTE was previously valid.
699 static int mmu_spte_clear_track_bits(u64
*sptep
)
702 u64 old_spte
= *sptep
;
704 if (!spte_has_volatile_bits(old_spte
))
705 __update_clear_spte_fast(sptep
, 0ull);
707 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
709 if (!is_shadow_present_pte(old_spte
))
712 pfn
= spte_to_pfn(old_spte
);
715 * KVM does not hold the refcount of the page used by
716 * kvm mmu, before reclaiming the page, we should
717 * unmap it from mmu first.
719 WARN_ON(!kvm_is_reserved_pfn(pfn
) && !page_count(pfn_to_page(pfn
)));
721 if (is_accessed_spte(old_spte
))
722 kvm_set_pfn_accessed(pfn
);
724 if (is_dirty_spte(old_spte
))
725 kvm_set_pfn_dirty(pfn
);
731 * Rules for using mmu_spte_clear_no_track:
732 * Directly clear spte without caring the state bits of sptep,
733 * it is used to set the upper level spte.
735 static void mmu_spte_clear_no_track(u64
*sptep
)
737 __update_clear_spte_fast(sptep
, 0ull);
740 static u64
mmu_spte_get_lockless(u64
*sptep
)
742 return __get_spte_lockless(sptep
);
745 static u64
mark_spte_for_access_track(u64 spte
)
747 if (spte_ad_enabled(spte
))
748 return spte
& ~shadow_accessed_mask
;
750 if (is_access_track_spte(spte
))
754 * Making an Access Tracking PTE will result in removal of write access
755 * from the PTE. So, verify that we will be able to restore the write
756 * access in the fast page fault path later on.
758 WARN_ONCE((spte
& PT_WRITABLE_MASK
) &&
759 !spte_can_locklessly_be_made_writable(spte
),
760 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
762 WARN_ONCE(spte
& (shadow_acc_track_saved_bits_mask
<<
763 shadow_acc_track_saved_bits_shift
),
764 "kvm: Access Tracking saved bit locations are not zero\n");
766 spte
|= (spte
& shadow_acc_track_saved_bits_mask
) <<
767 shadow_acc_track_saved_bits_shift
;
768 spte
&= ~shadow_acc_track_mask
;
773 /* Restore an acc-track PTE back to a regular PTE */
774 static u64
restore_acc_track_spte(u64 spte
)
777 u64 saved_bits
= (spte
>> shadow_acc_track_saved_bits_shift
)
778 & shadow_acc_track_saved_bits_mask
;
780 WARN_ON_ONCE(spte_ad_enabled(spte
));
781 WARN_ON_ONCE(!is_access_track_spte(spte
));
783 new_spte
&= ~shadow_acc_track_mask
;
784 new_spte
&= ~(shadow_acc_track_saved_bits_mask
<<
785 shadow_acc_track_saved_bits_shift
);
786 new_spte
|= saved_bits
;
791 /* Returns the Accessed status of the PTE and resets it at the same time. */
792 static bool mmu_spte_age(u64
*sptep
)
794 u64 spte
= mmu_spte_get_lockless(sptep
);
796 if (!is_accessed_spte(spte
))
799 if (spte_ad_enabled(spte
)) {
800 clear_bit((ffs(shadow_accessed_mask
) - 1),
801 (unsigned long *)sptep
);
804 * Capture the dirty status of the page, so that it doesn't get
805 * lost when the SPTE is marked for access tracking.
807 if (is_writable_pte(spte
))
808 kvm_set_pfn_dirty(spte_to_pfn(spte
));
810 spte
= mark_spte_for_access_track(spte
);
811 mmu_spte_update_no_track(sptep
, spte
);
817 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
820 * Prevent page table teardown by making any free-er wait during
821 * kvm_flush_remote_tlbs() IPI to all active vcpus.
826 * Make sure a following spte read is not reordered ahead of the write
829 smp_store_mb(vcpu
->mode
, READING_SHADOW_PAGE_TABLES
);
832 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
835 * Make sure the write to vcpu->mode is not reordered in front of
836 * reads to sptes. If it does, kvm_commit_zap_page() can see us
837 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
839 smp_store_release(&vcpu
->mode
, OUTSIDE_GUEST_MODE
);
843 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache
*cache
,
844 struct kmem_cache
*base_cache
, int min
)
848 if (cache
->nobjs
>= min
)
850 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
851 obj
= kmem_cache_zalloc(base_cache
, GFP_KERNEL
);
854 cache
->objects
[cache
->nobjs
++] = obj
;
859 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache
*cache
)
864 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache
*mc
,
865 struct kmem_cache
*cache
)
868 kmem_cache_free(cache
, mc
->objects
[--mc
->nobjs
]);
871 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache
*cache
,
876 if (cache
->nobjs
>= min
)
878 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
879 page
= (void *)__get_free_page(GFP_KERNEL
);
882 cache
->objects
[cache
->nobjs
++] = page
;
887 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache
*mc
)
890 free_page((unsigned long)mc
->objects
[--mc
->nobjs
]);
893 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
)
897 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
898 pte_list_desc_cache
, 8 + PTE_PREFETCH_NUM
);
901 r
= mmu_topup_memory_cache_page(&vcpu
->arch
.mmu_page_cache
, 8);
904 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
905 mmu_page_header_cache
, 4);
910 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
912 mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
913 pte_list_desc_cache
);
914 mmu_free_memory_cache_page(&vcpu
->arch
.mmu_page_cache
);
915 mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
916 mmu_page_header_cache
);
919 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache
*mc
)
924 p
= mc
->objects
[--mc
->nobjs
];
928 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
930 return mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
933 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
935 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
938 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
940 if (!sp
->role
.direct
)
941 return sp
->gfns
[index
];
943 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
946 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
949 BUG_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
));
951 sp
->gfns
[index
] = gfn
;
955 * Return the pointer to the large page information for a given gfn,
956 * handling slots that are not large page aligned.
958 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
959 struct kvm_memory_slot
*slot
,
964 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
965 return &slot
->arch
.lpage_info
[level
- 2][idx
];
968 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot
*slot
,
969 gfn_t gfn
, int count
)
971 struct kvm_lpage_info
*linfo
;
974 for (i
= PT_DIRECTORY_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
975 linfo
= lpage_info_slot(gfn
, slot
, i
);
976 linfo
->disallow_lpage
+= count
;
977 WARN_ON(linfo
->disallow_lpage
< 0);
981 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
983 update_gfn_disallow_lpage_count(slot
, gfn
, 1);
986 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
988 update_gfn_disallow_lpage_count(slot
, gfn
, -1);
991 static void account_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
993 struct kvm_memslots
*slots
;
994 struct kvm_memory_slot
*slot
;
997 kvm
->arch
.indirect_shadow_pages
++;
999 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1000 slot
= __gfn_to_memslot(slots
, gfn
);
1002 /* the non-leaf shadow pages are keeping readonly. */
1003 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
1004 return kvm_slot_page_track_add_page(kvm
, slot
, gfn
,
1005 KVM_PAGE_TRACK_WRITE
);
1007 kvm_mmu_gfn_disallow_lpage(slot
, gfn
);
1010 static void unaccount_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1012 struct kvm_memslots
*slots
;
1013 struct kvm_memory_slot
*slot
;
1016 kvm
->arch
.indirect_shadow_pages
--;
1018 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1019 slot
= __gfn_to_memslot(slots
, gfn
);
1020 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
1021 return kvm_slot_page_track_remove_page(kvm
, slot
, gfn
,
1022 KVM_PAGE_TRACK_WRITE
);
1024 kvm_mmu_gfn_allow_lpage(slot
, gfn
);
1027 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn
, int level
,
1028 struct kvm_memory_slot
*slot
)
1030 struct kvm_lpage_info
*linfo
;
1033 linfo
= lpage_info_slot(gfn
, slot
, level
);
1034 return !!linfo
->disallow_lpage
;
1040 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1043 struct kvm_memory_slot
*slot
;
1045 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1046 return __mmu_gfn_lpage_is_disallowed(gfn
, level
, slot
);
1049 static int host_mapping_level(struct kvm
*kvm
, gfn_t gfn
)
1051 unsigned long page_size
;
1054 page_size
= kvm_host_page_size(kvm
, gfn
);
1056 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
1057 if (page_size
>= KVM_HPAGE_SIZE(i
))
1066 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot
*slot
,
1069 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
)
1071 if (no_dirty_log
&& slot
->dirty_bitmap
)
1077 static struct kvm_memory_slot
*
1078 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1081 struct kvm_memory_slot
*slot
;
1083 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1084 if (!memslot_valid_for_gpte(slot
, no_dirty_log
))
1090 static int mapping_level(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
,
1091 bool *force_pt_level
)
1093 int host_level
, level
, max_level
;
1094 struct kvm_memory_slot
*slot
;
1096 if (unlikely(*force_pt_level
))
1097 return PT_PAGE_TABLE_LEVEL
;
1099 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, large_gfn
);
1100 *force_pt_level
= !memslot_valid_for_gpte(slot
, true);
1101 if (unlikely(*force_pt_level
))
1102 return PT_PAGE_TABLE_LEVEL
;
1104 host_level
= host_mapping_level(vcpu
->kvm
, large_gfn
);
1106 if (host_level
== PT_PAGE_TABLE_LEVEL
)
1109 max_level
= min(kvm_x86_ops
->get_lpage_level(), host_level
);
1111 for (level
= PT_DIRECTORY_LEVEL
; level
<= max_level
; ++level
)
1112 if (__mmu_gfn_lpage_is_disallowed(large_gfn
, level
, slot
))
1119 * About rmap_head encoding:
1121 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1122 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1123 * pte_list_desc containing more mappings.
1127 * Returns the number of pointers in the rmap chain, not counting the new one.
1129 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
1130 struct kvm_rmap_head
*rmap_head
)
1132 struct pte_list_desc
*desc
;
1135 if (!rmap_head
->val
) {
1136 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
1137 rmap_head
->val
= (unsigned long)spte
;
1138 } else if (!(rmap_head
->val
& 1)) {
1139 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
1140 desc
= mmu_alloc_pte_list_desc(vcpu
);
1141 desc
->sptes
[0] = (u64
*)rmap_head
->val
;
1142 desc
->sptes
[1] = spte
;
1143 rmap_head
->val
= (unsigned long)desc
| 1;
1146 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
1147 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1148 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
1150 count
+= PTE_LIST_EXT
;
1152 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
1153 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
1156 for (i
= 0; desc
->sptes
[i
]; ++i
)
1158 desc
->sptes
[i
] = spte
;
1164 pte_list_desc_remove_entry(struct kvm_rmap_head
*rmap_head
,
1165 struct pte_list_desc
*desc
, int i
,
1166 struct pte_list_desc
*prev_desc
)
1170 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
1172 desc
->sptes
[i
] = desc
->sptes
[j
];
1173 desc
->sptes
[j
] = NULL
;
1176 if (!prev_desc
&& !desc
->more
)
1177 rmap_head
->val
= (unsigned long)desc
->sptes
[0];
1180 prev_desc
->more
= desc
->more
;
1182 rmap_head
->val
= (unsigned long)desc
->more
| 1;
1183 mmu_free_pte_list_desc(desc
);
1186 static void pte_list_remove(u64
*spte
, struct kvm_rmap_head
*rmap_head
)
1188 struct pte_list_desc
*desc
;
1189 struct pte_list_desc
*prev_desc
;
1192 if (!rmap_head
->val
) {
1193 printk(KERN_ERR
"pte_list_remove: %p 0->BUG\n", spte
);
1195 } else if (!(rmap_head
->val
& 1)) {
1196 rmap_printk("pte_list_remove: %p 1->0\n", spte
);
1197 if ((u64
*)rmap_head
->val
!= spte
) {
1198 printk(KERN_ERR
"pte_list_remove: %p 1->BUG\n", spte
);
1203 rmap_printk("pte_list_remove: %p many->many\n", spte
);
1204 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1207 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
) {
1208 if (desc
->sptes
[i
] == spte
) {
1209 pte_list_desc_remove_entry(rmap_head
,
1210 desc
, i
, prev_desc
);
1217 pr_err("pte_list_remove: %p many->many\n", spte
);
1222 static struct kvm_rmap_head
*__gfn_to_rmap(gfn_t gfn
, int level
,
1223 struct kvm_memory_slot
*slot
)
1227 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
1228 return &slot
->arch
.rmap
[level
- PT_PAGE_TABLE_LEVEL
][idx
];
1231 static struct kvm_rmap_head
*gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
,
1232 struct kvm_mmu_page
*sp
)
1234 struct kvm_memslots
*slots
;
1235 struct kvm_memory_slot
*slot
;
1237 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1238 slot
= __gfn_to_memslot(slots
, gfn
);
1239 return __gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
1242 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
1244 struct kvm_mmu_memory_cache
*cache
;
1246 cache
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
1247 return mmu_memory_cache_free_objects(cache
);
1250 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1252 struct kvm_mmu_page
*sp
;
1253 struct kvm_rmap_head
*rmap_head
;
1255 sp
= page_header(__pa(spte
));
1256 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
1257 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1258 return pte_list_add(vcpu
, spte
, rmap_head
);
1261 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1263 struct kvm_mmu_page
*sp
;
1265 struct kvm_rmap_head
*rmap_head
;
1267 sp
= page_header(__pa(spte
));
1268 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1269 rmap_head
= gfn_to_rmap(kvm
, gfn
, sp
);
1270 pte_list_remove(spte
, rmap_head
);
1274 * Used by the following functions to iterate through the sptes linked by a
1275 * rmap. All fields are private and not assumed to be used outside.
1277 struct rmap_iterator
{
1278 /* private fields */
1279 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1280 int pos
; /* index of the sptep */
1284 * Iteration must be started by this function. This should also be used after
1285 * removing/dropping sptes from the rmap link because in such cases the
1286 * information in the itererator may not be valid.
1288 * Returns sptep if found, NULL otherwise.
1290 static u64
*rmap_get_first(struct kvm_rmap_head
*rmap_head
,
1291 struct rmap_iterator
*iter
)
1295 if (!rmap_head
->val
)
1298 if (!(rmap_head
->val
& 1)) {
1300 sptep
= (u64
*)rmap_head
->val
;
1304 iter
->desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1306 sptep
= iter
->desc
->sptes
[iter
->pos
];
1308 BUG_ON(!is_shadow_present_pte(*sptep
));
1313 * Must be used with a valid iterator: e.g. after rmap_get_first().
1315 * Returns sptep if found, NULL otherwise.
1317 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1322 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1324 sptep
= iter
->desc
->sptes
[iter
->pos
];
1329 iter
->desc
= iter
->desc
->more
;
1333 /* desc->sptes[0] cannot be NULL */
1334 sptep
= iter
->desc
->sptes
[iter
->pos
];
1341 BUG_ON(!is_shadow_present_pte(*sptep
));
1345 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1346 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1347 _spte_; _spte_ = rmap_get_next(_iter_))
1349 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1351 if (mmu_spte_clear_track_bits(sptep
))
1352 rmap_remove(kvm
, sptep
);
1356 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1358 if (is_large_pte(*sptep
)) {
1359 WARN_ON(page_header(__pa(sptep
))->role
.level
==
1360 PT_PAGE_TABLE_LEVEL
);
1361 drop_spte(kvm
, sptep
);
1369 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1371 if (__drop_large_spte(vcpu
->kvm
, sptep
))
1372 kvm_flush_remote_tlbs(vcpu
->kvm
);
1376 * Write-protect on the specified @sptep, @pt_protect indicates whether
1377 * spte write-protection is caused by protecting shadow page table.
1379 * Note: write protection is difference between dirty logging and spte
1381 * - for dirty logging, the spte can be set to writable at anytime if
1382 * its dirty bitmap is properly set.
1383 * - for spte protection, the spte can be writable only after unsync-ing
1386 * Return true if tlb need be flushed.
1388 static bool spte_write_protect(u64
*sptep
, bool pt_protect
)
1392 if (!is_writable_pte(spte
) &&
1393 !(pt_protect
&& spte_can_locklessly_be_made_writable(spte
)))
1396 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep
, *sptep
);
1399 spte
&= ~SPTE_MMU_WRITEABLE
;
1400 spte
= spte
& ~PT_WRITABLE_MASK
;
1402 return mmu_spte_update(sptep
, spte
);
1405 static bool __rmap_write_protect(struct kvm
*kvm
,
1406 struct kvm_rmap_head
*rmap_head
,
1410 struct rmap_iterator iter
;
1413 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1414 flush
|= spte_write_protect(sptep
, pt_protect
);
1419 static bool spte_clear_dirty(u64
*sptep
)
1423 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep
, *sptep
);
1425 spte
&= ~shadow_dirty_mask
;
1427 return mmu_spte_update(sptep
, spte
);
1430 static bool wrprot_ad_disabled_spte(u64
*sptep
)
1432 bool was_writable
= test_and_clear_bit(PT_WRITABLE_SHIFT
,
1433 (unsigned long *)sptep
);
1435 kvm_set_pfn_dirty(spte_to_pfn(*sptep
));
1437 return was_writable
;
1441 * Gets the GFN ready for another round of dirty logging by clearing the
1442 * - D bit on ad-enabled SPTEs, and
1443 * - W bit on ad-disabled SPTEs.
1444 * Returns true iff any D or W bits were cleared.
1446 static bool __rmap_clear_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1449 struct rmap_iterator iter
;
1452 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1453 if (spte_ad_enabled(*sptep
))
1454 flush
|= spte_clear_dirty(sptep
);
1456 flush
|= wrprot_ad_disabled_spte(sptep
);
1461 static bool spte_set_dirty(u64
*sptep
)
1465 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep
, *sptep
);
1467 spte
|= shadow_dirty_mask
;
1469 return mmu_spte_update(sptep
, spte
);
1472 static bool __rmap_set_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1475 struct rmap_iterator iter
;
1478 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1479 if (spte_ad_enabled(*sptep
))
1480 flush
|= spte_set_dirty(sptep
);
1486 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1487 * @kvm: kvm instance
1488 * @slot: slot to protect
1489 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1490 * @mask: indicates which pages we should protect
1492 * Used when we do not need to care about huge page mappings: e.g. during dirty
1493 * logging we do not have any such mappings.
1495 static void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1496 struct kvm_memory_slot
*slot
,
1497 gfn_t gfn_offset
, unsigned long mask
)
1499 struct kvm_rmap_head
*rmap_head
;
1502 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1503 PT_PAGE_TABLE_LEVEL
, slot
);
1504 __rmap_write_protect(kvm
, rmap_head
, false);
1506 /* clear the first set bit */
1512 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1513 * protect the page if the D-bit isn't supported.
1514 * @kvm: kvm instance
1515 * @slot: slot to clear D-bit
1516 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1517 * @mask: indicates which pages we should clear D-bit
1519 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1521 void kvm_mmu_clear_dirty_pt_masked(struct kvm
*kvm
,
1522 struct kvm_memory_slot
*slot
,
1523 gfn_t gfn_offset
, unsigned long mask
)
1525 struct kvm_rmap_head
*rmap_head
;
1528 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1529 PT_PAGE_TABLE_LEVEL
, slot
);
1530 __rmap_clear_dirty(kvm
, rmap_head
);
1532 /* clear the first set bit */
1536 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked
);
1539 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1542 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1543 * enable dirty logging for them.
1545 * Used when we do not need to care about huge page mappings: e.g. during dirty
1546 * logging we do not have any such mappings.
1548 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm
*kvm
,
1549 struct kvm_memory_slot
*slot
,
1550 gfn_t gfn_offset
, unsigned long mask
)
1552 if (kvm_x86_ops
->enable_log_dirty_pt_masked
)
1553 kvm_x86_ops
->enable_log_dirty_pt_masked(kvm
, slot
, gfn_offset
,
1556 kvm_mmu_write_protect_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1560 * kvm_arch_write_log_dirty - emulate dirty page logging
1561 * @vcpu: Guest mode vcpu
1563 * Emulate arch specific page modification logging for the
1566 int kvm_arch_write_log_dirty(struct kvm_vcpu
*vcpu
)
1568 if (kvm_x86_ops
->write_log_dirty
)
1569 return kvm_x86_ops
->write_log_dirty(vcpu
);
1574 bool kvm_mmu_slot_gfn_write_protect(struct kvm
*kvm
,
1575 struct kvm_memory_slot
*slot
, u64 gfn
)
1577 struct kvm_rmap_head
*rmap_head
;
1579 bool write_protected
= false;
1581 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
1582 rmap_head
= __gfn_to_rmap(gfn
, i
, slot
);
1583 write_protected
|= __rmap_write_protect(kvm
, rmap_head
, true);
1586 return write_protected
;
1589 static bool rmap_write_protect(struct kvm_vcpu
*vcpu
, u64 gfn
)
1591 struct kvm_memory_slot
*slot
;
1593 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1594 return kvm_mmu_slot_gfn_write_protect(vcpu
->kvm
, slot
, gfn
);
1597 static bool kvm_zap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1600 struct rmap_iterator iter
;
1603 while ((sptep
= rmap_get_first(rmap_head
, &iter
))) {
1604 rmap_printk("%s: spte %p %llx.\n", __func__
, sptep
, *sptep
);
1606 drop_spte(kvm
, sptep
);
1613 static int kvm_unmap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1614 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1617 return kvm_zap_rmapp(kvm
, rmap_head
);
1620 static int kvm_set_pte_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1621 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1625 struct rmap_iterator iter
;
1628 pte_t
*ptep
= (pte_t
*)data
;
1631 WARN_ON(pte_huge(*ptep
));
1632 new_pfn
= pte_pfn(*ptep
);
1635 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1636 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1637 sptep
, *sptep
, gfn
, level
);
1641 if (pte_write(*ptep
)) {
1642 drop_spte(kvm
, sptep
);
1645 new_spte
= *sptep
& ~PT64_BASE_ADDR_MASK
;
1646 new_spte
|= (u64
)new_pfn
<< PAGE_SHIFT
;
1648 new_spte
&= ~PT_WRITABLE_MASK
;
1649 new_spte
&= ~SPTE_HOST_WRITEABLE
;
1651 new_spte
= mark_spte_for_access_track(new_spte
);
1653 mmu_spte_clear_track_bits(sptep
);
1654 mmu_spte_set(sptep
, new_spte
);
1659 kvm_flush_remote_tlbs(kvm
);
1664 struct slot_rmap_walk_iterator
{
1666 struct kvm_memory_slot
*slot
;
1672 /* output fields. */
1674 struct kvm_rmap_head
*rmap
;
1677 /* private field. */
1678 struct kvm_rmap_head
*end_rmap
;
1682 rmap_walk_init_level(struct slot_rmap_walk_iterator
*iterator
, int level
)
1684 iterator
->level
= level
;
1685 iterator
->gfn
= iterator
->start_gfn
;
1686 iterator
->rmap
= __gfn_to_rmap(iterator
->gfn
, level
, iterator
->slot
);
1687 iterator
->end_rmap
= __gfn_to_rmap(iterator
->end_gfn
, level
,
1692 slot_rmap_walk_init(struct slot_rmap_walk_iterator
*iterator
,
1693 struct kvm_memory_slot
*slot
, int start_level
,
1694 int end_level
, gfn_t start_gfn
, gfn_t end_gfn
)
1696 iterator
->slot
= slot
;
1697 iterator
->start_level
= start_level
;
1698 iterator
->end_level
= end_level
;
1699 iterator
->start_gfn
= start_gfn
;
1700 iterator
->end_gfn
= end_gfn
;
1702 rmap_walk_init_level(iterator
, iterator
->start_level
);
1705 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator
*iterator
)
1707 return !!iterator
->rmap
;
1710 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator
*iterator
)
1712 if (++iterator
->rmap
<= iterator
->end_rmap
) {
1713 iterator
->gfn
+= (1UL << KVM_HPAGE_GFN_SHIFT(iterator
->level
));
1717 if (++iterator
->level
> iterator
->end_level
) {
1718 iterator
->rmap
= NULL
;
1722 rmap_walk_init_level(iterator
, iterator
->level
);
1725 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1726 _start_gfn, _end_gfn, _iter_) \
1727 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1728 _end_level_, _start_gfn, _end_gfn); \
1729 slot_rmap_walk_okay(_iter_); \
1730 slot_rmap_walk_next(_iter_))
1732 static int kvm_handle_hva_range(struct kvm
*kvm
,
1733 unsigned long start
,
1736 int (*handler
)(struct kvm
*kvm
,
1737 struct kvm_rmap_head
*rmap_head
,
1738 struct kvm_memory_slot
*slot
,
1741 unsigned long data
))
1743 struct kvm_memslots
*slots
;
1744 struct kvm_memory_slot
*memslot
;
1745 struct slot_rmap_walk_iterator iterator
;
1749 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
1750 slots
= __kvm_memslots(kvm
, i
);
1751 kvm_for_each_memslot(memslot
, slots
) {
1752 unsigned long hva_start
, hva_end
;
1753 gfn_t gfn_start
, gfn_end
;
1755 hva_start
= max(start
, memslot
->userspace_addr
);
1756 hva_end
= min(end
, memslot
->userspace_addr
+
1757 (memslot
->npages
<< PAGE_SHIFT
));
1758 if (hva_start
>= hva_end
)
1761 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1762 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1764 gfn_start
= hva_to_gfn_memslot(hva_start
, memslot
);
1765 gfn_end
= hva_to_gfn_memslot(hva_end
+ PAGE_SIZE
- 1, memslot
);
1767 for_each_slot_rmap_range(memslot
, PT_PAGE_TABLE_LEVEL
,
1768 PT_MAX_HUGEPAGE_LEVEL
,
1769 gfn_start
, gfn_end
- 1,
1771 ret
|= handler(kvm
, iterator
.rmap
, memslot
,
1772 iterator
.gfn
, iterator
.level
, data
);
1779 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1781 int (*handler
)(struct kvm
*kvm
,
1782 struct kvm_rmap_head
*rmap_head
,
1783 struct kvm_memory_slot
*slot
,
1784 gfn_t gfn
, int level
,
1785 unsigned long data
))
1787 return kvm_handle_hva_range(kvm
, hva
, hva
+ 1, data
, handler
);
1790 int kvm_unmap_hva(struct kvm
*kvm
, unsigned long hva
)
1792 return kvm_handle_hva(kvm
, hva
, 0, kvm_unmap_rmapp
);
1795 int kvm_unmap_hva_range(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1797 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_unmap_rmapp
);
1800 void kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1802 kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1805 static int kvm_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1806 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1810 struct rmap_iterator
uninitialized_var(iter
);
1813 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1814 young
|= mmu_spte_age(sptep
);
1816 trace_kvm_age_page(gfn
, level
, slot
, young
);
1820 static int kvm_test_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1821 struct kvm_memory_slot
*slot
, gfn_t gfn
,
1822 int level
, unsigned long data
)
1825 struct rmap_iterator iter
;
1827 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1828 if (is_accessed_spte(*sptep
))
1833 #define RMAP_RECYCLE_THRESHOLD 1000
1835 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1837 struct kvm_rmap_head
*rmap_head
;
1838 struct kvm_mmu_page
*sp
;
1840 sp
= page_header(__pa(spte
));
1842 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1844 kvm_unmap_rmapp(vcpu
->kvm
, rmap_head
, NULL
, gfn
, sp
->role
.level
, 0);
1845 kvm_flush_remote_tlbs(vcpu
->kvm
);
1848 int kvm_age_hva(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1850 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_age_rmapp
);
1853 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1855 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1859 static int is_empty_shadow_page(u64
*spt
)
1864 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1865 if (is_shadow_present_pte(*pos
)) {
1866 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1875 * This value is the sum of all of the kvm instances's
1876 * kvm->arch.n_used_mmu_pages values. We need a global,
1877 * aggregate version in order to make the slab shrinker
1880 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, int nr
)
1882 kvm
->arch
.n_used_mmu_pages
+= nr
;
1883 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1886 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1888 MMU_WARN_ON(!is_empty_shadow_page(sp
->spt
));
1889 hlist_del(&sp
->hash_link
);
1890 list_del(&sp
->link
);
1891 free_page((unsigned long)sp
->spt
);
1892 if (!sp
->role
.direct
)
1893 free_page((unsigned long)sp
->gfns
);
1894 kmem_cache_free(mmu_page_header_cache
, sp
);
1897 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1899 return hash_64(gfn
, KVM_MMU_HASH_SHIFT
);
1902 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1903 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1908 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1911 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1914 pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1917 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1920 mmu_page_remove_parent_pte(sp
, parent_pte
);
1921 mmu_spte_clear_no_track(parent_pte
);
1924 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
, int direct
)
1926 struct kvm_mmu_page
*sp
;
1928 sp
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1929 sp
->spt
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1931 sp
->gfns
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1932 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1935 * The active_mmu_pages list is the FIFO list, do not move the
1936 * page until it is zapped. kvm_zap_obsolete_pages depends on
1937 * this feature. See the comments in kvm_zap_obsolete_pages().
1939 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1940 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1944 static void mark_unsync(u64
*spte
);
1945 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1948 struct rmap_iterator iter
;
1950 for_each_rmap_spte(&sp
->parent_ptes
, &iter
, sptep
) {
1955 static void mark_unsync(u64
*spte
)
1957 struct kvm_mmu_page
*sp
;
1960 sp
= page_header(__pa(spte
));
1961 index
= spte
- sp
->spt
;
1962 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1964 if (sp
->unsync_children
++)
1966 kvm_mmu_mark_parents_unsync(sp
);
1969 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1970 struct kvm_mmu_page
*sp
)
1975 static void nonpaging_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
1979 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
1980 struct kvm_mmu_page
*sp
, u64
*spte
,
1986 #define KVM_PAGE_ARRAY_NR 16
1988 struct kvm_mmu_pages
{
1989 struct mmu_page_and_offset
{
1990 struct kvm_mmu_page
*sp
;
1992 } page
[KVM_PAGE_ARRAY_NR
];
1996 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
2002 for (i
=0; i
< pvec
->nr
; i
++)
2003 if (pvec
->page
[i
].sp
== sp
)
2006 pvec
->page
[pvec
->nr
].sp
= sp
;
2007 pvec
->page
[pvec
->nr
].idx
= idx
;
2009 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
2012 static inline void clear_unsync_child_bit(struct kvm_mmu_page
*sp
, int idx
)
2014 --sp
->unsync_children
;
2015 WARN_ON((int)sp
->unsync_children
< 0);
2016 __clear_bit(idx
, sp
->unsync_child_bitmap
);
2019 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
2020 struct kvm_mmu_pages
*pvec
)
2022 int i
, ret
, nr_unsync_leaf
= 0;
2024 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
2025 struct kvm_mmu_page
*child
;
2026 u64 ent
= sp
->spt
[i
];
2028 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
)) {
2029 clear_unsync_child_bit(sp
, i
);
2033 child
= page_header(ent
& PT64_BASE_ADDR_MASK
);
2035 if (child
->unsync_children
) {
2036 if (mmu_pages_add(pvec
, child
, i
))
2039 ret
= __mmu_unsync_walk(child
, pvec
);
2041 clear_unsync_child_bit(sp
, i
);
2043 } else if (ret
> 0) {
2044 nr_unsync_leaf
+= ret
;
2047 } else if (child
->unsync
) {
2049 if (mmu_pages_add(pvec
, child
, i
))
2052 clear_unsync_child_bit(sp
, i
);
2055 return nr_unsync_leaf
;
2058 #define INVALID_INDEX (-1)
2060 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
2061 struct kvm_mmu_pages
*pvec
)
2064 if (!sp
->unsync_children
)
2067 mmu_pages_add(pvec
, sp
, INVALID_INDEX
);
2068 return __mmu_unsync_walk(sp
, pvec
);
2071 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2073 WARN_ON(!sp
->unsync
);
2074 trace_kvm_mmu_sync_page(sp
);
2076 --kvm
->stat
.mmu_unsync
;
2079 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2080 struct list_head
*invalid_list
);
2081 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2082 struct list_head
*invalid_list
);
2085 * NOTE: we should pay more attention on the zapped-obsolete page
2086 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
2087 * since it has been deleted from active_mmu_pages but still can be found
2090 * for_each_valid_sp() has skipped that kind of pages.
2092 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2093 hlist_for_each_entry(_sp, \
2094 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2095 if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \
2098 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2099 for_each_valid_sp(_kvm, _sp, _gfn) \
2100 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2102 /* @sp->gfn should be write-protected at the call site */
2103 static bool __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2104 struct list_head
*invalid_list
)
2106 if (sp
->role
.cr4_pae
!= !!is_pae(vcpu
)) {
2107 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
2111 if (vcpu
->arch
.mmu
.sync_page(vcpu
, sp
) == 0) {
2112 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
2119 static void kvm_mmu_flush_or_zap(struct kvm_vcpu
*vcpu
,
2120 struct list_head
*invalid_list
,
2121 bool remote_flush
, bool local_flush
)
2123 if (!list_empty(invalid_list
)) {
2124 kvm_mmu_commit_zap_page(vcpu
->kvm
, invalid_list
);
2129 kvm_flush_remote_tlbs(vcpu
->kvm
);
2130 else if (local_flush
)
2131 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2134 #ifdef CONFIG_KVM_MMU_AUDIT
2135 #include "mmu_audit.c"
2137 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
2138 static void mmu_audit_disable(void) { }
2141 static bool is_obsolete_sp(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2143 return unlikely(sp
->mmu_valid_gen
!= kvm
->arch
.mmu_valid_gen
);
2146 static bool kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2147 struct list_head
*invalid_list
)
2149 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
2150 return __kvm_sync_page(vcpu
, sp
, invalid_list
);
2153 /* @gfn should be write-protected at the call site */
2154 static bool kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2155 struct list_head
*invalid_list
)
2157 struct kvm_mmu_page
*s
;
2160 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
) {
2164 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2165 ret
|= kvm_sync_page(vcpu
, s
, invalid_list
);
2171 struct mmu_page_path
{
2172 struct kvm_mmu_page
*parent
[PT64_ROOT_MAX_LEVEL
];
2173 unsigned int idx
[PT64_ROOT_MAX_LEVEL
];
2176 #define for_each_sp(pvec, sp, parents, i) \
2177 for (i = mmu_pages_first(&pvec, &parents); \
2178 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2179 i = mmu_pages_next(&pvec, &parents, i))
2181 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
2182 struct mmu_page_path
*parents
,
2187 for (n
= i
+1; n
< pvec
->nr
; n
++) {
2188 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
2189 unsigned idx
= pvec
->page
[n
].idx
;
2190 int level
= sp
->role
.level
;
2192 parents
->idx
[level
-1] = idx
;
2193 if (level
== PT_PAGE_TABLE_LEVEL
)
2196 parents
->parent
[level
-2] = sp
;
2202 static int mmu_pages_first(struct kvm_mmu_pages
*pvec
,
2203 struct mmu_page_path
*parents
)
2205 struct kvm_mmu_page
*sp
;
2211 WARN_ON(pvec
->page
[0].idx
!= INVALID_INDEX
);
2213 sp
= pvec
->page
[0].sp
;
2214 level
= sp
->role
.level
;
2215 WARN_ON(level
== PT_PAGE_TABLE_LEVEL
);
2217 parents
->parent
[level
-2] = sp
;
2219 /* Also set up a sentinel. Further entries in pvec are all
2220 * children of sp, so this element is never overwritten.
2222 parents
->parent
[level
-1] = NULL
;
2223 return mmu_pages_next(pvec
, parents
, 0);
2226 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
2228 struct kvm_mmu_page
*sp
;
2229 unsigned int level
= 0;
2232 unsigned int idx
= parents
->idx
[level
];
2233 sp
= parents
->parent
[level
];
2237 WARN_ON(idx
== INVALID_INDEX
);
2238 clear_unsync_child_bit(sp
, idx
);
2240 } while (!sp
->unsync_children
);
2243 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
2244 struct kvm_mmu_page
*parent
)
2247 struct kvm_mmu_page
*sp
;
2248 struct mmu_page_path parents
;
2249 struct kvm_mmu_pages pages
;
2250 LIST_HEAD(invalid_list
);
2253 while (mmu_unsync_walk(parent
, &pages
)) {
2254 bool protected = false;
2256 for_each_sp(pages
, sp
, parents
, i
)
2257 protected |= rmap_write_protect(vcpu
, sp
->gfn
);
2260 kvm_flush_remote_tlbs(vcpu
->kvm
);
2264 for_each_sp(pages
, sp
, parents
, i
) {
2265 flush
|= kvm_sync_page(vcpu
, sp
, &invalid_list
);
2266 mmu_pages_clear_parents(&parents
);
2268 if (need_resched() || spin_needbreak(&vcpu
->kvm
->mmu_lock
)) {
2269 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2270 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
2275 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2278 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
2280 atomic_set(&sp
->write_flooding_count
, 0);
2283 static void clear_sp_write_flooding_count(u64
*spte
)
2285 struct kvm_mmu_page
*sp
= page_header(__pa(spte
));
2287 __clear_sp_write_flooding_count(sp
);
2290 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
2297 union kvm_mmu_page_role role
;
2299 struct kvm_mmu_page
*sp
;
2300 bool need_sync
= false;
2303 LIST_HEAD(invalid_list
);
2305 role
= vcpu
->arch
.mmu
.base_role
;
2307 role
.direct
= direct
;
2310 role
.access
= access
;
2311 if (!vcpu
->arch
.mmu
.direct_map
2312 && vcpu
->arch
.mmu
.root_level
<= PT32_ROOT_LEVEL
) {
2313 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
2314 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
2315 role
.quadrant
= quadrant
;
2317 for_each_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2318 if (sp
->gfn
!= gfn
) {
2323 if (!need_sync
&& sp
->unsync
)
2326 if (sp
->role
.word
!= role
.word
)
2330 /* The page is good, but __kvm_sync_page might still end
2331 * up zapping it. If so, break in order to rebuild it.
2333 if (!__kvm_sync_page(vcpu
, sp
, &invalid_list
))
2336 WARN_ON(!list_empty(&invalid_list
));
2337 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2340 if (sp
->unsync_children
)
2341 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
2343 __clear_sp_write_flooding_count(sp
);
2344 trace_kvm_mmu_get_page(sp
, false);
2348 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
2350 sp
= kvm_mmu_alloc_page(vcpu
, direct
);
2354 hlist_add_head(&sp
->hash_link
,
2355 &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)]);
2358 * we should do write protection before syncing pages
2359 * otherwise the content of the synced shadow page may
2360 * be inconsistent with guest page table.
2362 account_shadowed(vcpu
->kvm
, sp
);
2363 if (level
== PT_PAGE_TABLE_LEVEL
&&
2364 rmap_write_protect(vcpu
, gfn
))
2365 kvm_flush_remote_tlbs(vcpu
->kvm
);
2367 if (level
> PT_PAGE_TABLE_LEVEL
&& need_sync
)
2368 flush
|= kvm_sync_pages(vcpu
, gfn
, &invalid_list
);
2370 sp
->mmu_valid_gen
= vcpu
->kvm
->arch
.mmu_valid_gen
;
2371 clear_page(sp
->spt
);
2372 trace_kvm_mmu_get_page(sp
, true);
2374 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2376 if (collisions
> vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
)
2377 vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
= collisions
;
2381 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
2382 struct kvm_vcpu
*vcpu
, u64 addr
)
2384 iterator
->addr
= addr
;
2385 iterator
->shadow_addr
= vcpu
->arch
.mmu
.root_hpa
;
2386 iterator
->level
= vcpu
->arch
.mmu
.shadow_root_level
;
2388 if (iterator
->level
== PT64_ROOT_4LEVEL
&&
2389 vcpu
->arch
.mmu
.root_level
< PT64_ROOT_4LEVEL
&&
2390 !vcpu
->arch
.mmu
.direct_map
)
2393 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
2394 iterator
->shadow_addr
2395 = vcpu
->arch
.mmu
.pae_root
[(addr
>> 30) & 3];
2396 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
2398 if (!iterator
->shadow_addr
)
2399 iterator
->level
= 0;
2403 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
2405 if (iterator
->level
< PT_PAGE_TABLE_LEVEL
)
2408 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
2409 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
2413 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
2416 if (is_last_spte(spte
, iterator
->level
)) {
2417 iterator
->level
= 0;
2421 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
2425 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
2427 return __shadow_walk_next(iterator
, *iterator
->sptep
);
2430 static void link_shadow_page(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2431 struct kvm_mmu_page
*sp
)
2435 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK
!= PT_WRITABLE_MASK
);
2437 spte
= __pa(sp
->spt
) | shadow_present_mask
| PT_WRITABLE_MASK
|
2438 shadow_user_mask
| shadow_x_mask
| shadow_me_mask
;
2440 if (sp_ad_disabled(sp
))
2441 spte
|= shadow_acc_track_value
;
2443 spte
|= shadow_accessed_mask
;
2445 mmu_spte_set(sptep
, spte
);
2447 mmu_page_add_parent_pte(vcpu
, sp
, sptep
);
2449 if (sp
->unsync_children
|| sp
->unsync
)
2453 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2454 unsigned direct_access
)
2456 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
2457 struct kvm_mmu_page
*child
;
2460 * For the direct sp, if the guest pte's dirty bit
2461 * changed form clean to dirty, it will corrupt the
2462 * sp's access: allow writable in the read-only sp,
2463 * so we should update the spte at this point to get
2464 * a new sp with the correct access.
2466 child
= page_header(*sptep
& PT64_BASE_ADDR_MASK
);
2467 if (child
->role
.access
== direct_access
)
2470 drop_parent_pte(child
, sptep
);
2471 kvm_flush_remote_tlbs(vcpu
->kvm
);
2475 static bool mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2479 struct kvm_mmu_page
*child
;
2482 if (is_shadow_present_pte(pte
)) {
2483 if (is_last_spte(pte
, sp
->role
.level
)) {
2484 drop_spte(kvm
, spte
);
2485 if (is_large_pte(pte
))
2488 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2489 drop_parent_pte(child
, spte
);
2494 if (is_mmio_spte(pte
))
2495 mmu_spte_clear_no_track(spte
);
2500 static void kvm_mmu_page_unlink_children(struct kvm
*kvm
,
2501 struct kvm_mmu_page
*sp
)
2505 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
2506 mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
);
2509 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2512 struct rmap_iterator iter
;
2514 while ((sptep
= rmap_get_first(&sp
->parent_ptes
, &iter
)))
2515 drop_parent_pte(sp
, sptep
);
2518 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2519 struct kvm_mmu_page
*parent
,
2520 struct list_head
*invalid_list
)
2523 struct mmu_page_path parents
;
2524 struct kvm_mmu_pages pages
;
2526 if (parent
->role
.level
== PT_PAGE_TABLE_LEVEL
)
2529 while (mmu_unsync_walk(parent
, &pages
)) {
2530 struct kvm_mmu_page
*sp
;
2532 for_each_sp(pages
, sp
, parents
, i
) {
2533 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2534 mmu_pages_clear_parents(&parents
);
2542 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2543 struct list_head
*invalid_list
)
2547 trace_kvm_mmu_prepare_zap_page(sp
);
2548 ++kvm
->stat
.mmu_shadow_zapped
;
2549 ret
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2550 kvm_mmu_page_unlink_children(kvm
, sp
);
2551 kvm_mmu_unlink_parents(kvm
, sp
);
2553 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2554 unaccount_shadowed(kvm
, sp
);
2557 kvm_unlink_unsync_page(kvm
, sp
);
2558 if (!sp
->root_count
) {
2561 list_move(&sp
->link
, invalid_list
);
2562 kvm_mod_used_mmu_pages(kvm
, -1);
2564 list_move(&sp
->link
, &kvm
->arch
.active_mmu_pages
);
2567 * The obsolete pages can not be used on any vcpus.
2568 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2570 if (!sp
->role
.invalid
&& !is_obsolete_sp(kvm
, sp
))
2571 kvm_reload_remote_mmus(kvm
);
2574 sp
->role
.invalid
= 1;
2578 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2579 struct list_head
*invalid_list
)
2581 struct kvm_mmu_page
*sp
, *nsp
;
2583 if (list_empty(invalid_list
))
2587 * We need to make sure everyone sees our modifications to
2588 * the page tables and see changes to vcpu->mode here. The barrier
2589 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2590 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2592 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2593 * guest mode and/or lockless shadow page table walks.
2595 kvm_flush_remote_tlbs(kvm
);
2597 list_for_each_entry_safe(sp
, nsp
, invalid_list
, link
) {
2598 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2599 kvm_mmu_free_page(sp
);
2603 static bool prepare_zap_oldest_mmu_page(struct kvm
*kvm
,
2604 struct list_head
*invalid_list
)
2606 struct kvm_mmu_page
*sp
;
2608 if (list_empty(&kvm
->arch
.active_mmu_pages
))
2611 sp
= list_last_entry(&kvm
->arch
.active_mmu_pages
,
2612 struct kvm_mmu_page
, link
);
2613 return kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2617 * Changing the number of mmu pages allocated to the vm
2618 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2620 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned int goal_nr_mmu_pages
)
2622 LIST_HEAD(invalid_list
);
2624 spin_lock(&kvm
->mmu_lock
);
2626 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2627 /* Need to free some mmu pages to achieve the goal. */
2628 while (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
)
2629 if (!prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
2632 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2633 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2636 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2638 spin_unlock(&kvm
->mmu_lock
);
2641 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2643 struct kvm_mmu_page
*sp
;
2644 LIST_HEAD(invalid_list
);
2647 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2649 spin_lock(&kvm
->mmu_lock
);
2650 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
) {
2651 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2654 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2656 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2657 spin_unlock(&kvm
->mmu_lock
);
2661 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page
);
2663 static void kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2665 trace_kvm_mmu_unsync_page(sp
);
2666 ++vcpu
->kvm
->stat
.mmu_unsync
;
2669 kvm_mmu_mark_parents_unsync(sp
);
2672 static bool mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2675 struct kvm_mmu_page
*sp
;
2677 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
2680 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2687 WARN_ON(sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2688 kvm_unsync_page(vcpu
, sp
);
2694 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn
)
2697 return !is_zero_pfn(pfn
) && PageReserved(pfn_to_page(pfn
));
2702 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2703 unsigned pte_access
, int level
,
2704 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2705 bool can_unsync
, bool host_writable
)
2709 struct kvm_mmu_page
*sp
;
2711 if (set_mmio_spte(vcpu
, sptep
, gfn
, pfn
, pte_access
))
2714 sp
= page_header(__pa(sptep
));
2715 if (sp_ad_disabled(sp
))
2716 spte
|= shadow_acc_track_value
;
2719 * For the EPT case, shadow_present_mask is 0 if hardware
2720 * supports exec-only page table entries. In that case,
2721 * ACC_USER_MASK and shadow_user_mask are used to represent
2722 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2724 spte
|= shadow_present_mask
;
2726 spte
|= spte_shadow_accessed_mask(spte
);
2728 if (pte_access
& ACC_EXEC_MASK
)
2729 spte
|= shadow_x_mask
;
2731 spte
|= shadow_nx_mask
;
2733 if (pte_access
& ACC_USER_MASK
)
2734 spte
|= shadow_user_mask
;
2736 if (level
> PT_PAGE_TABLE_LEVEL
)
2737 spte
|= PT_PAGE_SIZE_MASK
;
2739 spte
|= kvm_x86_ops
->get_mt_mask(vcpu
, gfn
,
2740 kvm_is_mmio_pfn(pfn
));
2743 spte
|= SPTE_HOST_WRITEABLE
;
2745 pte_access
&= ~ACC_WRITE_MASK
;
2747 spte
|= (u64
)pfn
<< PAGE_SHIFT
;
2748 spte
|= shadow_me_mask
;
2750 if (pte_access
& ACC_WRITE_MASK
) {
2753 * Other vcpu creates new sp in the window between
2754 * mapping_level() and acquiring mmu-lock. We can
2755 * allow guest to retry the access, the mapping can
2756 * be fixed if guest refault.
2758 if (level
> PT_PAGE_TABLE_LEVEL
&&
2759 mmu_gfn_lpage_is_disallowed(vcpu
, gfn
, level
))
2762 spte
|= PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
;
2765 * Optimization: for pte sync, if spte was writable the hash
2766 * lookup is unnecessary (and expensive). Write protection
2767 * is responsibility of mmu_get_page / kvm_sync_page.
2768 * Same reasoning can be applied to dirty page accounting.
2770 if (!can_unsync
&& is_writable_pte(*sptep
))
2773 if (mmu_need_write_protect(vcpu
, gfn
, can_unsync
)) {
2774 pgprintk("%s: found shadow page for %llx, marking ro\n",
2777 pte_access
&= ~ACC_WRITE_MASK
;
2778 spte
&= ~(PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
);
2782 if (pte_access
& ACC_WRITE_MASK
) {
2783 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
2784 spte
|= spte_shadow_dirty_mask(spte
);
2788 spte
= mark_spte_for_access_track(spte
);
2791 if (mmu_spte_update(sptep
, spte
))
2792 kvm_flush_remote_tlbs(vcpu
->kvm
);
2797 static bool mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, unsigned pte_access
,
2798 int write_fault
, int level
, gfn_t gfn
, kvm_pfn_t pfn
,
2799 bool speculative
, bool host_writable
)
2801 int was_rmapped
= 0;
2803 bool emulate
= false;
2805 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__
,
2806 *sptep
, write_fault
, gfn
);
2808 if (is_shadow_present_pte(*sptep
)) {
2810 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2811 * the parent of the now unreachable PTE.
2813 if (level
> PT_PAGE_TABLE_LEVEL
&&
2814 !is_large_pte(*sptep
)) {
2815 struct kvm_mmu_page
*child
;
2818 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2819 drop_parent_pte(child
, sptep
);
2820 kvm_flush_remote_tlbs(vcpu
->kvm
);
2821 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2822 pgprintk("hfn old %llx new %llx\n",
2823 spte_to_pfn(*sptep
), pfn
);
2824 drop_spte(vcpu
->kvm
, sptep
);
2825 kvm_flush_remote_tlbs(vcpu
->kvm
);
2830 if (set_spte(vcpu
, sptep
, pte_access
, level
, gfn
, pfn
, speculative
,
2831 true, host_writable
)) {
2834 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2837 if (unlikely(is_mmio_spte(*sptep
)))
2840 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2841 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2842 is_large_pte(*sptep
)? "2MB" : "4kB",
2843 *sptep
& PT_WRITABLE_MASK
? "RW" : "R", gfn
,
2845 if (!was_rmapped
&& is_large_pte(*sptep
))
2846 ++vcpu
->kvm
->stat
.lpages
;
2848 if (is_shadow_present_pte(*sptep
)) {
2850 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2851 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2852 rmap_recycle(vcpu
, sptep
, gfn
);
2856 kvm_release_pfn_clean(pfn
);
2861 static kvm_pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2864 struct kvm_memory_slot
*slot
;
2866 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2868 return KVM_PFN_ERR_FAULT
;
2870 return gfn_to_pfn_memslot_atomic(slot
, gfn
);
2873 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2874 struct kvm_mmu_page
*sp
,
2875 u64
*start
, u64
*end
)
2877 struct page
*pages
[PTE_PREFETCH_NUM
];
2878 struct kvm_memory_slot
*slot
;
2879 unsigned access
= sp
->role
.access
;
2883 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2884 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
);
2888 ret
= gfn_to_page_many_atomic(slot
, gfn
, pages
, end
- start
);
2892 for (i
= 0; i
< ret
; i
++, gfn
++, start
++)
2893 mmu_set_spte(vcpu
, start
, access
, 0, sp
->role
.level
, gfn
,
2894 page_to_pfn(pages
[i
]), true, true);
2899 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2900 struct kvm_mmu_page
*sp
, u64
*sptep
)
2902 u64
*spte
, *start
= NULL
;
2905 WARN_ON(!sp
->role
.direct
);
2907 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2910 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2911 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2914 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2922 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2924 struct kvm_mmu_page
*sp
;
2926 sp
= page_header(__pa(sptep
));
2929 * Without accessed bits, there's no way to distinguish between
2930 * actually accessed translations and prefetched, so disable pte
2931 * prefetch if accessed bits aren't available.
2933 if (sp_ad_disabled(sp
))
2936 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2939 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2942 static int __direct_map(struct kvm_vcpu
*vcpu
, int write
, int map_writable
,
2943 int level
, gfn_t gfn
, kvm_pfn_t pfn
, bool prefault
)
2945 struct kvm_shadow_walk_iterator iterator
;
2946 struct kvm_mmu_page
*sp
;
2950 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2953 for_each_shadow_entry(vcpu
, (u64
)gfn
<< PAGE_SHIFT
, iterator
) {
2954 if (iterator
.level
== level
) {
2955 emulate
= mmu_set_spte(vcpu
, iterator
.sptep
, ACC_ALL
,
2956 write
, level
, gfn
, pfn
, prefault
,
2958 direct_pte_prefetch(vcpu
, iterator
.sptep
);
2959 ++vcpu
->stat
.pf_fixed
;
2963 drop_large_spte(vcpu
, iterator
.sptep
);
2964 if (!is_shadow_present_pte(*iterator
.sptep
)) {
2965 u64 base_addr
= iterator
.addr
;
2967 base_addr
&= PT64_LVL_ADDR_MASK(iterator
.level
);
2968 pseudo_gfn
= base_addr
>> PAGE_SHIFT
;
2969 sp
= kvm_mmu_get_page(vcpu
, pseudo_gfn
, iterator
.addr
,
2970 iterator
.level
- 1, 1, ACC_ALL
);
2972 link_shadow_page(vcpu
, iterator
.sptep
, sp
);
2978 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2982 info
.si_signo
= SIGBUS
;
2984 info
.si_code
= BUS_MCEERR_AR
;
2985 info
.si_addr
= (void __user
*)address
;
2986 info
.si_addr_lsb
= PAGE_SHIFT
;
2988 send_sig_info(SIGBUS
, &info
, tsk
);
2991 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, kvm_pfn_t pfn
)
2994 * Do not cache the mmio info caused by writing the readonly gfn
2995 * into the spte otherwise read access on readonly gfn also can
2996 * caused mmio page fault and treat it as mmio access.
2997 * Return 1 to tell kvm to emulate it.
2999 if (pfn
== KVM_PFN_ERR_RO_FAULT
)
3002 if (pfn
== KVM_PFN_ERR_HWPOISON
) {
3003 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu
, gfn
), current
);
3010 static void transparent_hugepage_adjust(struct kvm_vcpu
*vcpu
,
3011 gfn_t
*gfnp
, kvm_pfn_t
*pfnp
,
3014 kvm_pfn_t pfn
= *pfnp
;
3016 int level
= *levelp
;
3019 * Check if it's a transparent hugepage. If this would be an
3020 * hugetlbfs page, level wouldn't be set to
3021 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
3024 if (!is_error_noslot_pfn(pfn
) && !kvm_is_reserved_pfn(pfn
) &&
3025 level
== PT_PAGE_TABLE_LEVEL
&&
3026 PageTransCompoundMap(pfn_to_page(pfn
)) &&
3027 !mmu_gfn_lpage_is_disallowed(vcpu
, gfn
, PT_DIRECTORY_LEVEL
)) {
3030 * mmu_notifier_retry was successful and we hold the
3031 * mmu_lock here, so the pmd can't become splitting
3032 * from under us, and in turn
3033 * __split_huge_page_refcount() can't run from under
3034 * us and we can safely transfer the refcount from
3035 * PG_tail to PG_head as we switch the pfn to tail to
3038 *levelp
= level
= PT_DIRECTORY_LEVEL
;
3039 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
3040 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
3044 kvm_release_pfn_clean(pfn
);
3052 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
3053 kvm_pfn_t pfn
, unsigned access
, int *ret_val
)
3055 /* The pfn is invalid, report the error! */
3056 if (unlikely(is_error_pfn(pfn
))) {
3057 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
3061 if (unlikely(is_noslot_pfn(pfn
)))
3062 vcpu_cache_mmio_info(vcpu
, gva
, gfn
, access
);
3067 static bool page_fault_can_be_fast(u32 error_code
)
3070 * Do not fix the mmio spte with invalid generation number which
3071 * need to be updated by slow page fault path.
3073 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3076 /* See if the page fault is due to an NX violation */
3077 if (unlikely(((error_code
& (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))
3078 == (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))))
3082 * #PF can be fast if:
3083 * 1. The shadow page table entry is not present, which could mean that
3084 * the fault is potentially caused by access tracking (if enabled).
3085 * 2. The shadow page table entry is present and the fault
3086 * is caused by write-protect, that means we just need change the W
3087 * bit of the spte which can be done out of mmu-lock.
3089 * However, if access tracking is disabled we know that a non-present
3090 * page must be a genuine page fault where we have to create a new SPTE.
3091 * So, if access tracking is disabled, we return true only for write
3092 * accesses to a present page.
3095 return shadow_acc_track_mask
!= 0 ||
3096 ((error_code
& (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
))
3097 == (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
));
3101 * Returns true if the SPTE was fixed successfully. Otherwise,
3102 * someone else modified the SPTE from its original value.
3105 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
3106 u64
*sptep
, u64 old_spte
, u64 new_spte
)
3110 WARN_ON(!sp
->role
.direct
);
3113 * Theoretically we could also set dirty bit (and flush TLB) here in
3114 * order to eliminate unnecessary PML logging. See comments in
3115 * set_spte. But fast_page_fault is very unlikely to happen with PML
3116 * enabled, so we do not do this. This might result in the same GPA
3117 * to be logged in PML buffer again when the write really happens, and
3118 * eventually to be called by mark_page_dirty twice. But it's also no
3119 * harm. This also avoids the TLB flush needed after setting dirty bit
3120 * so non-PML cases won't be impacted.
3122 * Compare with set_spte where instead shadow_dirty_mask is set.
3124 if (cmpxchg64(sptep
, old_spte
, new_spte
) != old_spte
)
3127 if (is_writable_pte(new_spte
) && !is_writable_pte(old_spte
)) {
3129 * The gfn of direct spte is stable since it is
3130 * calculated by sp->gfn.
3132 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
3133 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
3139 static bool is_access_allowed(u32 fault_err_code
, u64 spte
)
3141 if (fault_err_code
& PFERR_FETCH_MASK
)
3142 return is_executable_pte(spte
);
3144 if (fault_err_code
& PFERR_WRITE_MASK
)
3145 return is_writable_pte(spte
);
3147 /* Fault was on Read access */
3148 return spte
& PT_PRESENT_MASK
;
3153 * - true: let the vcpu to access on the same address again.
3154 * - false: let the real page fault path to fix it.
3156 static bool fast_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
, int level
,
3159 struct kvm_shadow_walk_iterator iterator
;
3160 struct kvm_mmu_page
*sp
;
3161 bool fault_handled
= false;
3163 uint retry_count
= 0;
3165 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3168 if (!page_fault_can_be_fast(error_code
))
3171 walk_shadow_page_lockless_begin(vcpu
);
3176 for_each_shadow_entry_lockless(vcpu
, gva
, iterator
, spte
)
3177 if (!is_shadow_present_pte(spte
) ||
3178 iterator
.level
< level
)
3181 sp
= page_header(__pa(iterator
.sptep
));
3182 if (!is_last_spte(spte
, sp
->role
.level
))
3186 * Check whether the memory access that caused the fault would
3187 * still cause it if it were to be performed right now. If not,
3188 * then this is a spurious fault caused by TLB lazily flushed,
3189 * or some other CPU has already fixed the PTE after the
3190 * current CPU took the fault.
3192 * Need not check the access of upper level table entries since
3193 * they are always ACC_ALL.
3195 if (is_access_allowed(error_code
, spte
)) {
3196 fault_handled
= true;
3202 if (is_access_track_spte(spte
))
3203 new_spte
= restore_acc_track_spte(new_spte
);
3206 * Currently, to simplify the code, write-protection can
3207 * be removed in the fast path only if the SPTE was
3208 * write-protected for dirty-logging or access tracking.
3210 if ((error_code
& PFERR_WRITE_MASK
) &&
3211 spte_can_locklessly_be_made_writable(spte
))
3213 new_spte
|= PT_WRITABLE_MASK
;
3216 * Do not fix write-permission on the large spte. Since
3217 * we only dirty the first page into the dirty-bitmap in
3218 * fast_pf_fix_direct_spte(), other pages are missed
3219 * if its slot has dirty logging enabled.
3221 * Instead, we let the slow page fault path create a
3222 * normal spte to fix the access.
3224 * See the comments in kvm_arch_commit_memory_region().
3226 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
3230 /* Verify that the fault can be handled in the fast path */
3231 if (new_spte
== spte
||
3232 !is_access_allowed(error_code
, new_spte
))
3236 * Currently, fast page fault only works for direct mapping
3237 * since the gfn is not stable for indirect shadow page. See
3238 * Documentation/virtual/kvm/locking.txt to get more detail.
3240 fault_handled
= fast_pf_fix_direct_spte(vcpu
, sp
,
3241 iterator
.sptep
, spte
,
3246 if (++retry_count
> 4) {
3247 printk_once(KERN_WARNING
3248 "kvm: Fast #PF retrying more than 4 times.\n");
3254 trace_fast_page_fault(vcpu
, gva
, error_code
, iterator
.sptep
,
3255 spte
, fault_handled
);
3256 walk_shadow_page_lockless_end(vcpu
);
3258 return fault_handled
;
3261 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3262 gva_t gva
, kvm_pfn_t
*pfn
, bool write
, bool *writable
);
3263 static int make_mmu_pages_available(struct kvm_vcpu
*vcpu
);
3265 static int nonpaging_map(struct kvm_vcpu
*vcpu
, gva_t v
, u32 error_code
,
3266 gfn_t gfn
, bool prefault
)
3270 bool force_pt_level
= false;
3272 unsigned long mmu_seq
;
3273 bool map_writable
, write
= error_code
& PFERR_WRITE_MASK
;
3275 level
= mapping_level(vcpu
, gfn
, &force_pt_level
);
3276 if (likely(!force_pt_level
)) {
3278 * This path builds a PAE pagetable - so we can map
3279 * 2mb pages at maximum. Therefore check if the level
3280 * is larger than that.
3282 if (level
> PT_DIRECTORY_LEVEL
)
3283 level
= PT_DIRECTORY_LEVEL
;
3285 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3288 if (fast_page_fault(vcpu
, v
, level
, error_code
))
3291 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3294 if (try_async_pf(vcpu
, prefault
, gfn
, v
, &pfn
, write
, &map_writable
))
3297 if (handle_abnormal_pfn(vcpu
, v
, gfn
, pfn
, ACC_ALL
, &r
))
3300 spin_lock(&vcpu
->kvm
->mmu_lock
);
3301 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3303 if (make_mmu_pages_available(vcpu
) < 0)
3305 if (likely(!force_pt_level
))
3306 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3307 r
= __direct_map(vcpu
, write
, map_writable
, level
, gfn
, pfn
, prefault
);
3308 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3313 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3314 kvm_release_pfn_clean(pfn
);
3319 static void mmu_free_roots(struct kvm_vcpu
*vcpu
)
3322 struct kvm_mmu_page
*sp
;
3323 LIST_HEAD(invalid_list
);
3325 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3328 if (vcpu
->arch
.mmu
.shadow_root_level
>= PT64_ROOT_4LEVEL
&&
3329 (vcpu
->arch
.mmu
.root_level
>= PT64_ROOT_4LEVEL
||
3330 vcpu
->arch
.mmu
.direct_map
)) {
3331 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3333 spin_lock(&vcpu
->kvm
->mmu_lock
);
3334 sp
= page_header(root
);
3336 if (!sp
->root_count
&& sp
->role
.invalid
) {
3337 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
3338 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3340 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3341 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
3345 spin_lock(&vcpu
->kvm
->mmu_lock
);
3346 for (i
= 0; i
< 4; ++i
) {
3347 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3350 root
&= PT64_BASE_ADDR_MASK
;
3351 sp
= page_header(root
);
3353 if (!sp
->root_count
&& sp
->role
.invalid
)
3354 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
3357 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
3359 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3360 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3361 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
3364 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
3368 if (!kvm_is_visible_gfn(vcpu
->kvm
, root_gfn
)) {
3369 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3376 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
3378 struct kvm_mmu_page
*sp
;
3381 if (vcpu
->arch
.mmu
.shadow_root_level
>= PT64_ROOT_4LEVEL
) {
3382 spin_lock(&vcpu
->kvm
->mmu_lock
);
3383 if(make_mmu_pages_available(vcpu
) < 0) {
3384 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3387 sp
= kvm_mmu_get_page(vcpu
, 0, 0,
3388 vcpu
->arch
.mmu
.shadow_root_level
, 1, ACC_ALL
);
3390 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3391 vcpu
->arch
.mmu
.root_hpa
= __pa(sp
->spt
);
3392 } else if (vcpu
->arch
.mmu
.shadow_root_level
== PT32E_ROOT_LEVEL
) {
3393 for (i
= 0; i
< 4; ++i
) {
3394 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3396 MMU_WARN_ON(VALID_PAGE(root
));
3397 spin_lock(&vcpu
->kvm
->mmu_lock
);
3398 if (make_mmu_pages_available(vcpu
) < 0) {
3399 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3402 sp
= kvm_mmu_get_page(vcpu
, i
<< (30 - PAGE_SHIFT
),
3403 i
<< 30, PT32_ROOT_LEVEL
, 1, ACC_ALL
);
3404 root
= __pa(sp
->spt
);
3406 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3407 vcpu
->arch
.mmu
.pae_root
[i
] = root
| PT_PRESENT_MASK
;
3409 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3416 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
3418 struct kvm_mmu_page
*sp
;
3423 root_gfn
= vcpu
->arch
.mmu
.get_cr3(vcpu
) >> PAGE_SHIFT
;
3425 if (mmu_check_root(vcpu
, root_gfn
))
3429 * Do we shadow a long mode page table? If so we need to
3430 * write-protect the guests page table root.
3432 if (vcpu
->arch
.mmu
.root_level
>= PT64_ROOT_4LEVEL
) {
3433 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3435 MMU_WARN_ON(VALID_PAGE(root
));
3437 spin_lock(&vcpu
->kvm
->mmu_lock
);
3438 if (make_mmu_pages_available(vcpu
) < 0) {
3439 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3442 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, 0,
3443 vcpu
->arch
.mmu
.shadow_root_level
, 0, ACC_ALL
);
3444 root
= __pa(sp
->spt
);
3446 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3447 vcpu
->arch
.mmu
.root_hpa
= root
;
3452 * We shadow a 32 bit page table. This may be a legacy 2-level
3453 * or a PAE 3-level page table. In either case we need to be aware that
3454 * the shadow page table may be a PAE or a long mode page table.
3456 pm_mask
= PT_PRESENT_MASK
;
3457 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_4LEVEL
)
3458 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
3460 for (i
= 0; i
< 4; ++i
) {
3461 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3463 MMU_WARN_ON(VALID_PAGE(root
));
3464 if (vcpu
->arch
.mmu
.root_level
== PT32E_ROOT_LEVEL
) {
3465 pdptr
= vcpu
->arch
.mmu
.get_pdptr(vcpu
, i
);
3466 if (!(pdptr
& PT_PRESENT_MASK
)) {
3467 vcpu
->arch
.mmu
.pae_root
[i
] = 0;
3470 root_gfn
= pdptr
>> PAGE_SHIFT
;
3471 if (mmu_check_root(vcpu
, root_gfn
))
3474 spin_lock(&vcpu
->kvm
->mmu_lock
);
3475 if (make_mmu_pages_available(vcpu
) < 0) {
3476 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3479 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, i
<< 30, PT32_ROOT_LEVEL
,
3481 root
= __pa(sp
->spt
);
3483 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3485 vcpu
->arch
.mmu
.pae_root
[i
] = root
| pm_mask
;
3487 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3490 * If we shadow a 32 bit page table with a long mode page
3491 * table we enter this path.
3493 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_4LEVEL
) {
3494 if (vcpu
->arch
.mmu
.lm_root
== NULL
) {
3496 * The additional page necessary for this is only
3497 * allocated on demand.
3502 lm_root
= (void*)get_zeroed_page(GFP_KERNEL
);
3503 if (lm_root
== NULL
)
3506 lm_root
[0] = __pa(vcpu
->arch
.mmu
.pae_root
) | pm_mask
;
3508 vcpu
->arch
.mmu
.lm_root
= lm_root
;
3511 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.lm_root
);
3517 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
3519 if (vcpu
->arch
.mmu
.direct_map
)
3520 return mmu_alloc_direct_roots(vcpu
);
3522 return mmu_alloc_shadow_roots(vcpu
);
3525 static void mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3528 struct kvm_mmu_page
*sp
;
3530 if (vcpu
->arch
.mmu
.direct_map
)
3533 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3536 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
3537 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3538 if (vcpu
->arch
.mmu
.root_level
>= PT64_ROOT_4LEVEL
) {
3539 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3540 sp
= page_header(root
);
3541 mmu_sync_children(vcpu
, sp
);
3542 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3545 for (i
= 0; i
< 4; ++i
) {
3546 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3548 if (root
&& VALID_PAGE(root
)) {
3549 root
&= PT64_BASE_ADDR_MASK
;
3550 sp
= page_header(root
);
3551 mmu_sync_children(vcpu
, sp
);
3554 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3557 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3559 spin_lock(&vcpu
->kvm
->mmu_lock
);
3560 mmu_sync_roots(vcpu
);
3561 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3563 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots
);
3565 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3566 u32 access
, struct x86_exception
*exception
)
3569 exception
->error_code
= 0;
3573 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3575 struct x86_exception
*exception
)
3578 exception
->error_code
= 0;
3579 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
, exception
);
3583 __is_rsvd_bits_set(struct rsvd_bits_validate
*rsvd_check
, u64 pte
, int level
)
3585 int bit7
= (pte
>> 7) & 1, low6
= pte
& 0x3f;
3587 return (pte
& rsvd_check
->rsvd_bits_mask
[bit7
][level
-1]) |
3588 ((rsvd_check
->bad_mt_xwr
& (1ull << low6
)) != 0);
3591 static bool is_rsvd_bits_set(struct kvm_mmu
*mmu
, u64 gpte
, int level
)
3593 return __is_rsvd_bits_set(&mmu
->guest_rsvd_check
, gpte
, level
);
3596 static bool is_shadow_zero_bits_set(struct kvm_mmu
*mmu
, u64 spte
, int level
)
3598 return __is_rsvd_bits_set(&mmu
->shadow_zero_check
, spte
, level
);
3601 static bool mmio_info_in_cache(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3604 * A nested guest cannot use the MMIO cache if it is using nested
3605 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3607 if (mmu_is_nested(vcpu
))
3611 return vcpu_match_mmio_gpa(vcpu
, addr
);
3613 return vcpu_match_mmio_gva(vcpu
, addr
);
3616 /* return true if reserved bit is detected on spte. */
3618 walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptep
)
3620 struct kvm_shadow_walk_iterator iterator
;
3621 u64 sptes
[PT64_ROOT_MAX_LEVEL
], spte
= 0ull;
3623 bool reserved
= false;
3625 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3628 walk_shadow_page_lockless_begin(vcpu
);
3630 for (shadow_walk_init(&iterator
, vcpu
, addr
),
3631 leaf
= root
= iterator
.level
;
3632 shadow_walk_okay(&iterator
);
3633 __shadow_walk_next(&iterator
, spte
)) {
3634 spte
= mmu_spte_get_lockless(iterator
.sptep
);
3636 sptes
[leaf
- 1] = spte
;
3639 if (!is_shadow_present_pte(spte
))
3642 reserved
|= is_shadow_zero_bits_set(&vcpu
->arch
.mmu
, spte
,
3646 walk_shadow_page_lockless_end(vcpu
);
3649 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3651 while (root
> leaf
) {
3652 pr_err("------ spte 0x%llx level %d.\n",
3653 sptes
[root
- 1], root
);
3663 * Return values of handle_mmio_page_fault:
3664 * RET_MMIO_PF_EMULATE: it is a real mmio page fault, emulate the instruction
3666 * RET_MMIO_PF_INVALID: invalid spte is detected then let the real page
3667 * fault path update the mmio spte.
3668 * RET_MMIO_PF_RETRY: let CPU fault again on the address.
3669 * RET_MMIO_PF_BUG: a bug was detected (and a WARN was printed).
3672 RET_MMIO_PF_EMULATE
= 1,
3673 RET_MMIO_PF_INVALID
= 2,
3674 RET_MMIO_PF_RETRY
= 0,
3675 RET_MMIO_PF_BUG
= -1
3678 static int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3683 if (mmio_info_in_cache(vcpu
, addr
, direct
))
3684 return RET_MMIO_PF_EMULATE
;
3686 reserved
= walk_shadow_page_get_mmio_spte(vcpu
, addr
, &spte
);
3687 if (WARN_ON(reserved
))
3688 return RET_MMIO_PF_BUG
;
3690 if (is_mmio_spte(spte
)) {
3691 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3692 unsigned access
= get_mmio_spte_access(spte
);
3694 if (!check_mmio_spte(vcpu
, spte
))
3695 return RET_MMIO_PF_INVALID
;
3700 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3701 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3702 return RET_MMIO_PF_EMULATE
;
3706 * If the page table is zapped by other cpus, let CPU fault again on
3709 return RET_MMIO_PF_RETRY
;
3711 EXPORT_SYMBOL_GPL(handle_mmio_page_fault
);
3713 static bool page_fault_handle_page_track(struct kvm_vcpu
*vcpu
,
3714 u32 error_code
, gfn_t gfn
)
3716 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3719 if (!(error_code
& PFERR_PRESENT_MASK
) ||
3720 !(error_code
& PFERR_WRITE_MASK
))
3724 * guest is writing the page which is write tracked which can
3725 * not be fixed by page fault handler.
3727 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
3733 static void shadow_page_table_clear_flood(struct kvm_vcpu
*vcpu
, gva_t addr
)
3735 struct kvm_shadow_walk_iterator iterator
;
3738 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3741 walk_shadow_page_lockless_begin(vcpu
);
3742 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
3743 clear_sp_write_flooding_count(iterator
.sptep
);
3744 if (!is_shadow_present_pte(spte
))
3747 walk_shadow_page_lockless_end(vcpu
);
3750 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
,
3751 u32 error_code
, bool prefault
)
3753 gfn_t gfn
= gva
>> PAGE_SHIFT
;
3756 pgprintk("%s: gva %lx error %x\n", __func__
, gva
, error_code
);
3758 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3761 r
= mmu_topup_memory_caches(vcpu
);
3765 MMU_WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3768 return nonpaging_map(vcpu
, gva
& PAGE_MASK
,
3769 error_code
, gfn
, prefault
);
3772 static int kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
)
3774 struct kvm_arch_async_pf arch
;
3776 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3778 arch
.direct_map
= vcpu
->arch
.mmu
.direct_map
;
3779 arch
.cr3
= vcpu
->arch
.mmu
.get_cr3(vcpu
);
3781 return kvm_setup_async_pf(vcpu
, gva
, kvm_vcpu_gfn_to_hva(vcpu
, gfn
), &arch
);
3784 bool kvm_can_do_async_pf(struct kvm_vcpu
*vcpu
)
3786 if (unlikely(!lapic_in_kernel(vcpu
) ||
3787 kvm_event_needs_reinjection(vcpu
)))
3790 if (!vcpu
->arch
.apf
.delivery_as_pf_vmexit
&& is_guest_mode(vcpu
))
3793 return kvm_x86_ops
->interrupt_allowed(vcpu
);
3796 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3797 gva_t gva
, kvm_pfn_t
*pfn
, bool write
, bool *writable
)
3799 struct kvm_memory_slot
*slot
;
3802 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
3804 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, &async
, write
, writable
);
3806 return false; /* *pfn has correct page already */
3808 if (!prefault
&& kvm_can_do_async_pf(vcpu
)) {
3809 trace_kvm_try_async_get_page(gva
, gfn
);
3810 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3811 trace_kvm_async_pf_doublefault(gva
, gfn
);
3812 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3814 } else if (kvm_arch_setup_async_pf(vcpu
, gva
, gfn
))
3818 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, NULL
, write
, writable
);
3822 int kvm_handle_page_fault(struct kvm_vcpu
*vcpu
, u64 error_code
,
3823 u64 fault_address
, char *insn
, int insn_len
,
3824 bool need_unprotect
)
3828 switch (vcpu
->arch
.apf
.host_apf_reason
) {
3830 trace_kvm_page_fault(fault_address
, error_code
);
3832 if (need_unprotect
&& kvm_event_needs_reinjection(vcpu
))
3833 kvm_mmu_unprotect_page_virt(vcpu
, fault_address
);
3834 r
= kvm_mmu_page_fault(vcpu
, fault_address
, error_code
, insn
,
3837 case KVM_PV_REASON_PAGE_NOT_PRESENT
:
3838 vcpu
->arch
.apf
.host_apf_reason
= 0;
3839 local_irq_disable();
3840 kvm_async_pf_task_wait(fault_address
);
3843 case KVM_PV_REASON_PAGE_READY
:
3844 vcpu
->arch
.apf
.host_apf_reason
= 0;
3845 local_irq_disable();
3846 kvm_async_pf_task_wake(fault_address
);
3852 EXPORT_SYMBOL_GPL(kvm_handle_page_fault
);
3855 check_hugepage_cache_consistency(struct kvm_vcpu
*vcpu
, gfn_t gfn
, int level
)
3857 int page_num
= KVM_PAGES_PER_HPAGE(level
);
3859 gfn
&= ~(page_num
- 1);
3861 return kvm_mtrr_check_gfn_range_consistency(vcpu
, gfn
, page_num
);
3864 static int tdp_page_fault(struct kvm_vcpu
*vcpu
, gva_t gpa
, u32 error_code
,
3870 bool force_pt_level
;
3871 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3872 unsigned long mmu_seq
;
3873 int write
= error_code
& PFERR_WRITE_MASK
;
3876 MMU_WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3878 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3881 r
= mmu_topup_memory_caches(vcpu
);
3885 force_pt_level
= !check_hugepage_cache_consistency(vcpu
, gfn
,
3886 PT_DIRECTORY_LEVEL
);
3887 level
= mapping_level(vcpu
, gfn
, &force_pt_level
);
3888 if (likely(!force_pt_level
)) {
3889 if (level
> PT_DIRECTORY_LEVEL
&&
3890 !check_hugepage_cache_consistency(vcpu
, gfn
, level
))
3891 level
= PT_DIRECTORY_LEVEL
;
3892 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3895 if (fast_page_fault(vcpu
, gpa
, level
, error_code
))
3898 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3901 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
3904 if (handle_abnormal_pfn(vcpu
, 0, gfn
, pfn
, ACC_ALL
, &r
))
3907 spin_lock(&vcpu
->kvm
->mmu_lock
);
3908 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3910 if (make_mmu_pages_available(vcpu
) < 0)
3912 if (likely(!force_pt_level
))
3913 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3914 r
= __direct_map(vcpu
, write
, map_writable
, level
, gfn
, pfn
, prefault
);
3915 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3920 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3921 kvm_release_pfn_clean(pfn
);
3925 static void nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3926 struct kvm_mmu
*context
)
3928 context
->page_fault
= nonpaging_page_fault
;
3929 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3930 context
->sync_page
= nonpaging_sync_page
;
3931 context
->invlpg
= nonpaging_invlpg
;
3932 context
->update_pte
= nonpaging_update_pte
;
3933 context
->root_level
= 0;
3934 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3935 context
->root_hpa
= INVALID_PAGE
;
3936 context
->direct_map
= true;
3937 context
->nx
= false;
3940 void kvm_mmu_new_cr3(struct kvm_vcpu
*vcpu
)
3942 mmu_free_roots(vcpu
);
3945 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
3947 return kvm_read_cr3(vcpu
);
3950 static void inject_page_fault(struct kvm_vcpu
*vcpu
,
3951 struct x86_exception
*fault
)
3953 vcpu
->arch
.mmu
.inject_page_fault(vcpu
, fault
);
3956 static bool sync_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
3957 unsigned access
, int *nr_present
)
3959 if (unlikely(is_mmio_spte(*sptep
))) {
3960 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
3961 mmu_spte_clear_no_track(sptep
);
3966 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
3973 static inline bool is_last_gpte(struct kvm_mmu
*mmu
,
3974 unsigned level
, unsigned gpte
)
3977 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
3978 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
3979 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
3981 gpte
|= level
- PT_PAGE_TABLE_LEVEL
- 1;
3984 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3985 * If it is clear, there are no large pages at this level, so clear
3986 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3988 gpte
&= level
- mmu
->last_nonleaf_level
;
3990 return gpte
& PT_PAGE_SIZE_MASK
;
3993 #define PTTYPE_EPT 18 /* arbitrary */
3994 #define PTTYPE PTTYPE_EPT
3995 #include "paging_tmpl.h"
3999 #include "paging_tmpl.h"
4003 #include "paging_tmpl.h"
4007 __reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
4008 struct rsvd_bits_validate
*rsvd_check
,
4009 int maxphyaddr
, int level
, bool nx
, bool gbpages
,
4012 u64 exb_bit_rsvd
= 0;
4013 u64 gbpages_bit_rsvd
= 0;
4014 u64 nonleaf_bit8_rsvd
= 0;
4016 rsvd_check
->bad_mt_xwr
= 0;
4019 exb_bit_rsvd
= rsvd_bits(63, 63);
4021 gbpages_bit_rsvd
= rsvd_bits(7, 7);
4024 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4025 * leaf entries) on AMD CPUs only.
4028 nonleaf_bit8_rsvd
= rsvd_bits(8, 8);
4031 case PT32_ROOT_LEVEL
:
4032 /* no rsvd bits for 2 level 4K page table entries */
4033 rsvd_check
->rsvd_bits_mask
[0][1] = 0;
4034 rsvd_check
->rsvd_bits_mask
[0][0] = 0;
4035 rsvd_check
->rsvd_bits_mask
[1][0] =
4036 rsvd_check
->rsvd_bits_mask
[0][0];
4039 rsvd_check
->rsvd_bits_mask
[1][1] = 0;
4043 if (is_cpuid_PSE36())
4044 /* 36bits PSE 4MB page */
4045 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
4047 /* 32 bits PSE 4MB page */
4048 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
4050 case PT32E_ROOT_LEVEL
:
4051 rsvd_check
->rsvd_bits_mask
[0][2] =
4052 rsvd_bits(maxphyaddr
, 63) |
4053 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
4054 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
4055 rsvd_bits(maxphyaddr
, 62); /* PDE */
4056 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
4057 rsvd_bits(maxphyaddr
, 62); /* PTE */
4058 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
4059 rsvd_bits(maxphyaddr
, 62) |
4060 rsvd_bits(13, 20); /* large page */
4061 rsvd_check
->rsvd_bits_mask
[1][0] =
4062 rsvd_check
->rsvd_bits_mask
[0][0];
4064 case PT64_ROOT_5LEVEL
:
4065 rsvd_check
->rsvd_bits_mask
[0][4] = exb_bit_rsvd
|
4066 nonleaf_bit8_rsvd
| rsvd_bits(7, 7) |
4067 rsvd_bits(maxphyaddr
, 51);
4068 rsvd_check
->rsvd_bits_mask
[1][4] =
4069 rsvd_check
->rsvd_bits_mask
[0][4];
4070 case PT64_ROOT_4LEVEL
:
4071 rsvd_check
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
4072 nonleaf_bit8_rsvd
| rsvd_bits(7, 7) |
4073 rsvd_bits(maxphyaddr
, 51);
4074 rsvd_check
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
4075 nonleaf_bit8_rsvd
| gbpages_bit_rsvd
|
4076 rsvd_bits(maxphyaddr
, 51);
4077 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
4078 rsvd_bits(maxphyaddr
, 51);
4079 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
4080 rsvd_bits(maxphyaddr
, 51);
4081 rsvd_check
->rsvd_bits_mask
[1][3] =
4082 rsvd_check
->rsvd_bits_mask
[0][3];
4083 rsvd_check
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
4084 gbpages_bit_rsvd
| rsvd_bits(maxphyaddr
, 51) |
4086 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
4087 rsvd_bits(maxphyaddr
, 51) |
4088 rsvd_bits(13, 20); /* large page */
4089 rsvd_check
->rsvd_bits_mask
[1][0] =
4090 rsvd_check
->rsvd_bits_mask
[0][0];
4095 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
4096 struct kvm_mmu
*context
)
4098 __reset_rsvds_bits_mask(vcpu
, &context
->guest_rsvd_check
,
4099 cpuid_maxphyaddr(vcpu
), context
->root_level
,
4101 guest_cpuid_has(vcpu
, X86_FEATURE_GBPAGES
),
4102 is_pse(vcpu
), guest_cpuid_is_amd(vcpu
));
4106 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate
*rsvd_check
,
4107 int maxphyaddr
, bool execonly
)
4111 rsvd_check
->rsvd_bits_mask
[0][4] =
4112 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 7);
4113 rsvd_check
->rsvd_bits_mask
[0][3] =
4114 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 7);
4115 rsvd_check
->rsvd_bits_mask
[0][2] =
4116 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
4117 rsvd_check
->rsvd_bits_mask
[0][1] =
4118 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
4119 rsvd_check
->rsvd_bits_mask
[0][0] = rsvd_bits(maxphyaddr
, 51);
4122 rsvd_check
->rsvd_bits_mask
[1][4] = rsvd_check
->rsvd_bits_mask
[0][4];
4123 rsvd_check
->rsvd_bits_mask
[1][3] = rsvd_check
->rsvd_bits_mask
[0][3];
4124 rsvd_check
->rsvd_bits_mask
[1][2] =
4125 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 29);
4126 rsvd_check
->rsvd_bits_mask
[1][1] =
4127 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 20);
4128 rsvd_check
->rsvd_bits_mask
[1][0] = rsvd_check
->rsvd_bits_mask
[0][0];
4130 bad_mt_xwr
= 0xFFull
<< (2 * 8); /* bits 3..5 must not be 2 */
4131 bad_mt_xwr
|= 0xFFull
<< (3 * 8); /* bits 3..5 must not be 3 */
4132 bad_mt_xwr
|= 0xFFull
<< (7 * 8); /* bits 3..5 must not be 7 */
4133 bad_mt_xwr
|= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4134 bad_mt_xwr
|= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4136 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4137 bad_mt_xwr
|= REPEAT_BYTE(1ull << 4);
4139 rsvd_check
->bad_mt_xwr
= bad_mt_xwr
;
4142 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu
*vcpu
,
4143 struct kvm_mmu
*context
, bool execonly
)
4145 __reset_rsvds_bits_mask_ept(&context
->guest_rsvd_check
,
4146 cpuid_maxphyaddr(vcpu
), execonly
);
4150 * the page table on host is the shadow page table for the page
4151 * table in guest or amd nested guest, its mmu features completely
4152 * follow the features in guest.
4155 reset_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
4157 bool uses_nx
= context
->nx
|| context
->base_role
.smep_andnot_wp
;
4158 struct rsvd_bits_validate
*shadow_zero_check
;
4162 * Passing "true" to the last argument is okay; it adds a check
4163 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4165 shadow_zero_check
= &context
->shadow_zero_check
;
4166 __reset_rsvds_bits_mask(vcpu
, shadow_zero_check
,
4167 boot_cpu_data
.x86_phys_bits
,
4168 context
->shadow_root_level
, uses_nx
,
4169 guest_cpuid_has(vcpu
, X86_FEATURE_GBPAGES
),
4170 is_pse(vcpu
), true);
4172 if (!shadow_me_mask
)
4175 for (i
= context
->shadow_root_level
; --i
>= 0;) {
4176 shadow_zero_check
->rsvd_bits_mask
[0][i
] &= ~shadow_me_mask
;
4177 shadow_zero_check
->rsvd_bits_mask
[1][i
] &= ~shadow_me_mask
;
4181 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask
);
4183 static inline bool boot_cpu_is_amd(void)
4185 WARN_ON_ONCE(!tdp_enabled
);
4186 return shadow_x_mask
== 0;
4190 * the direct page table on host, use as much mmu features as
4191 * possible, however, kvm currently does not do execution-protection.
4194 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4195 struct kvm_mmu
*context
)
4197 struct rsvd_bits_validate
*shadow_zero_check
;
4200 shadow_zero_check
= &context
->shadow_zero_check
;
4202 if (boot_cpu_is_amd())
4203 __reset_rsvds_bits_mask(vcpu
, shadow_zero_check
,
4204 boot_cpu_data
.x86_phys_bits
,
4205 context
->shadow_root_level
, false,
4206 boot_cpu_has(X86_FEATURE_GBPAGES
),
4209 __reset_rsvds_bits_mask_ept(shadow_zero_check
,
4210 boot_cpu_data
.x86_phys_bits
,
4213 if (!shadow_me_mask
)
4216 for (i
= context
->shadow_root_level
; --i
>= 0;) {
4217 shadow_zero_check
->rsvd_bits_mask
[0][i
] &= ~shadow_me_mask
;
4218 shadow_zero_check
->rsvd_bits_mask
[1][i
] &= ~shadow_me_mask
;
4223 * as the comments in reset_shadow_zero_bits_mask() except it
4224 * is the shadow page table for intel nested guest.
4227 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4228 struct kvm_mmu
*context
, bool execonly
)
4230 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
4231 boot_cpu_data
.x86_phys_bits
, execonly
);
4234 #define BYTE_MASK(access) \
4235 ((1 & (access) ? 2 : 0) | \
4236 (2 & (access) ? 4 : 0) | \
4237 (3 & (access) ? 8 : 0) | \
4238 (4 & (access) ? 16 : 0) | \
4239 (5 & (access) ? 32 : 0) | \
4240 (6 & (access) ? 64 : 0) | \
4241 (7 & (access) ? 128 : 0))
4244 static void update_permission_bitmask(struct kvm_vcpu
*vcpu
,
4245 struct kvm_mmu
*mmu
, bool ept
)
4249 const u8 x
= BYTE_MASK(ACC_EXEC_MASK
);
4250 const u8 w
= BYTE_MASK(ACC_WRITE_MASK
);
4251 const u8 u
= BYTE_MASK(ACC_USER_MASK
);
4253 bool cr4_smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
) != 0;
4254 bool cr4_smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
) != 0;
4255 bool cr0_wp
= is_write_protection(vcpu
);
4257 for (byte
= 0; byte
< ARRAY_SIZE(mmu
->permissions
); ++byte
) {
4258 unsigned pfec
= byte
<< 1;
4261 * Each "*f" variable has a 1 bit for each UWX value
4262 * that causes a fault with the given PFEC.
4265 /* Faults from writes to non-writable pages */
4266 u8 wf
= (pfec
& PFERR_WRITE_MASK
) ? ~w
: 0;
4267 /* Faults from user mode accesses to supervisor pages */
4268 u8 uf
= (pfec
& PFERR_USER_MASK
) ? ~u
: 0;
4269 /* Faults from fetches of non-executable pages*/
4270 u8 ff
= (pfec
& PFERR_FETCH_MASK
) ? ~x
: 0;
4271 /* Faults from kernel mode fetches of user pages */
4273 /* Faults from kernel mode accesses of user pages */
4277 /* Faults from kernel mode accesses to user pages */
4278 u8 kf
= (pfec
& PFERR_USER_MASK
) ? 0 : u
;
4280 /* Not really needed: !nx will cause pte.nx to fault */
4284 /* Allow supervisor writes if !cr0.wp */
4286 wf
= (pfec
& PFERR_USER_MASK
) ? wf
: 0;
4288 /* Disallow supervisor fetches of user code if cr4.smep */
4290 smepf
= (pfec
& PFERR_FETCH_MASK
) ? kf
: 0;
4293 * SMAP:kernel-mode data accesses from user-mode
4294 * mappings should fault. A fault is considered
4295 * as a SMAP violation if all of the following
4296 * conditions are ture:
4297 * - X86_CR4_SMAP is set in CR4
4298 * - A user page is accessed
4299 * - The access is not a fetch
4300 * - Page fault in kernel mode
4301 * - if CPL = 3 or X86_EFLAGS_AC is clear
4303 * Here, we cover the first three conditions.
4304 * The fourth is computed dynamically in permission_fault();
4305 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4306 * *not* subject to SMAP restrictions.
4309 smapf
= (pfec
& (PFERR_RSVD_MASK
|PFERR_FETCH_MASK
)) ? 0 : kf
;
4312 mmu
->permissions
[byte
] = ff
| uf
| wf
| smepf
| smapf
;
4317 * PKU is an additional mechanism by which the paging controls access to
4318 * user-mode addresses based on the value in the PKRU register. Protection
4319 * key violations are reported through a bit in the page fault error code.
4320 * Unlike other bits of the error code, the PK bit is not known at the
4321 * call site of e.g. gva_to_gpa; it must be computed directly in
4322 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4323 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4325 * In particular the following conditions come from the error code, the
4326 * page tables and the machine state:
4327 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4328 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4329 * - PK is always zero if U=0 in the page tables
4330 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4332 * The PKRU bitmask caches the result of these four conditions. The error
4333 * code (minus the P bit) and the page table's U bit form an index into the
4334 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4335 * with the two bits of the PKRU register corresponding to the protection key.
4336 * For the first three conditions above the bits will be 00, thus masking
4337 * away both AD and WD. For all reads or if the last condition holds, WD
4338 * only will be masked away.
4340 static void update_pkru_bitmask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
4351 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4352 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) || !is_long_mode(vcpu
)) {
4357 wp
= is_write_protection(vcpu
);
4359 for (bit
= 0; bit
< ARRAY_SIZE(mmu
->permissions
); ++bit
) {
4360 unsigned pfec
, pkey_bits
;
4361 bool check_pkey
, check_write
, ff
, uf
, wf
, pte_user
;
4364 ff
= pfec
& PFERR_FETCH_MASK
;
4365 uf
= pfec
& PFERR_USER_MASK
;
4366 wf
= pfec
& PFERR_WRITE_MASK
;
4368 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4369 pte_user
= pfec
& PFERR_RSVD_MASK
;
4372 * Only need to check the access which is not an
4373 * instruction fetch and is to a user page.
4375 check_pkey
= (!ff
&& pte_user
);
4377 * write access is controlled by PKRU if it is a
4378 * user access or CR0.WP = 1.
4380 check_write
= check_pkey
&& wf
&& (uf
|| wp
);
4382 /* PKRU.AD stops both read and write access. */
4383 pkey_bits
= !!check_pkey
;
4384 /* PKRU.WD stops write access. */
4385 pkey_bits
|= (!!check_write
) << 1;
4387 mmu
->pkru_mask
|= (pkey_bits
& 3) << pfec
;
4391 static void update_last_nonleaf_level(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
4393 unsigned root_level
= mmu
->root_level
;
4395 mmu
->last_nonleaf_level
= root_level
;
4396 if (root_level
== PT32_ROOT_LEVEL
&& is_pse(vcpu
))
4397 mmu
->last_nonleaf_level
++;
4400 static void paging64_init_context_common(struct kvm_vcpu
*vcpu
,
4401 struct kvm_mmu
*context
,
4404 context
->nx
= is_nx(vcpu
);
4405 context
->root_level
= level
;
4407 reset_rsvds_bits_mask(vcpu
, context
);
4408 update_permission_bitmask(vcpu
, context
, false);
4409 update_pkru_bitmask(vcpu
, context
, false);
4410 update_last_nonleaf_level(vcpu
, context
);
4412 MMU_WARN_ON(!is_pae(vcpu
));
4413 context
->page_fault
= paging64_page_fault
;
4414 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4415 context
->sync_page
= paging64_sync_page
;
4416 context
->invlpg
= paging64_invlpg
;
4417 context
->update_pte
= paging64_update_pte
;
4418 context
->shadow_root_level
= level
;
4419 context
->root_hpa
= INVALID_PAGE
;
4420 context
->direct_map
= false;
4423 static void paging64_init_context(struct kvm_vcpu
*vcpu
,
4424 struct kvm_mmu
*context
)
4426 int root_level
= is_la57_mode(vcpu
) ?
4427 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4429 paging64_init_context_common(vcpu
, context
, root_level
);
4432 static void paging32_init_context(struct kvm_vcpu
*vcpu
,
4433 struct kvm_mmu
*context
)
4435 context
->nx
= false;
4436 context
->root_level
= PT32_ROOT_LEVEL
;
4438 reset_rsvds_bits_mask(vcpu
, context
);
4439 update_permission_bitmask(vcpu
, context
, false);
4440 update_pkru_bitmask(vcpu
, context
, false);
4441 update_last_nonleaf_level(vcpu
, context
);
4443 context
->page_fault
= paging32_page_fault
;
4444 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4445 context
->sync_page
= paging32_sync_page
;
4446 context
->invlpg
= paging32_invlpg
;
4447 context
->update_pte
= paging32_update_pte
;
4448 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
4449 context
->root_hpa
= INVALID_PAGE
;
4450 context
->direct_map
= false;
4453 static void paging32E_init_context(struct kvm_vcpu
*vcpu
,
4454 struct kvm_mmu
*context
)
4456 paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
4459 static void init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
4461 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4463 context
->base_role
.word
= 0;
4464 context
->base_role
.smm
= is_smm(vcpu
);
4465 context
->base_role
.ad_disabled
= (shadow_accessed_mask
== 0);
4466 context
->page_fault
= tdp_page_fault
;
4467 context
->sync_page
= nonpaging_sync_page
;
4468 context
->invlpg
= nonpaging_invlpg
;
4469 context
->update_pte
= nonpaging_update_pte
;
4470 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level(vcpu
);
4471 context
->root_hpa
= INVALID_PAGE
;
4472 context
->direct_map
= true;
4473 context
->set_cr3
= kvm_x86_ops
->set_tdp_cr3
;
4474 context
->get_cr3
= get_cr3
;
4475 context
->get_pdptr
= kvm_pdptr_read
;
4476 context
->inject_page_fault
= kvm_inject_page_fault
;
4478 if (!is_paging(vcpu
)) {
4479 context
->nx
= false;
4480 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4481 context
->root_level
= 0;
4482 } else if (is_long_mode(vcpu
)) {
4483 context
->nx
= is_nx(vcpu
);
4484 context
->root_level
= is_la57_mode(vcpu
) ?
4485 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4486 reset_rsvds_bits_mask(vcpu
, context
);
4487 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4488 } else if (is_pae(vcpu
)) {
4489 context
->nx
= is_nx(vcpu
);
4490 context
->root_level
= PT32E_ROOT_LEVEL
;
4491 reset_rsvds_bits_mask(vcpu
, context
);
4492 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4494 context
->nx
= false;
4495 context
->root_level
= PT32_ROOT_LEVEL
;
4496 reset_rsvds_bits_mask(vcpu
, context
);
4497 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4500 update_permission_bitmask(vcpu
, context
, false);
4501 update_pkru_bitmask(vcpu
, context
, false);
4502 update_last_nonleaf_level(vcpu
, context
);
4503 reset_tdp_shadow_zero_bits_mask(vcpu
, context
);
4506 void kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
)
4508 bool smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
4509 bool smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
4510 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4512 MMU_WARN_ON(VALID_PAGE(context
->root_hpa
));
4514 if (!is_paging(vcpu
))
4515 nonpaging_init_context(vcpu
, context
);
4516 else if (is_long_mode(vcpu
))
4517 paging64_init_context(vcpu
, context
);
4518 else if (is_pae(vcpu
))
4519 paging32E_init_context(vcpu
, context
);
4521 paging32_init_context(vcpu
, context
);
4523 context
->base_role
.nxe
= is_nx(vcpu
);
4524 context
->base_role
.cr4_pae
= !!is_pae(vcpu
);
4525 context
->base_role
.cr0_wp
= is_write_protection(vcpu
);
4526 context
->base_role
.smep_andnot_wp
4527 = smep
&& !is_write_protection(vcpu
);
4528 context
->base_role
.smap_andnot_wp
4529 = smap
&& !is_write_protection(vcpu
);
4530 context
->base_role
.smm
= is_smm(vcpu
);
4531 reset_shadow_zero_bits_mask(vcpu
, context
);
4533 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu
);
4535 void kvm_init_shadow_ept_mmu(struct kvm_vcpu
*vcpu
, bool execonly
,
4536 bool accessed_dirty
)
4538 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4540 MMU_WARN_ON(VALID_PAGE(context
->root_hpa
));
4542 context
->shadow_root_level
= PT64_ROOT_4LEVEL
;
4545 context
->ept_ad
= accessed_dirty
;
4546 context
->page_fault
= ept_page_fault
;
4547 context
->gva_to_gpa
= ept_gva_to_gpa
;
4548 context
->sync_page
= ept_sync_page
;
4549 context
->invlpg
= ept_invlpg
;
4550 context
->update_pte
= ept_update_pte
;
4551 context
->root_level
= PT64_ROOT_4LEVEL
;
4552 context
->root_hpa
= INVALID_PAGE
;
4553 context
->direct_map
= false;
4554 context
->base_role
.ad_disabled
= !accessed_dirty
;
4556 update_permission_bitmask(vcpu
, context
, true);
4557 update_pkru_bitmask(vcpu
, context
, true);
4558 reset_rsvds_bits_mask_ept(vcpu
, context
, execonly
);
4559 reset_ept_shadow_zero_bits_mask(vcpu
, context
, execonly
);
4561 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu
);
4563 static void init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
4565 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4567 kvm_init_shadow_mmu(vcpu
);
4568 context
->set_cr3
= kvm_x86_ops
->set_cr3
;
4569 context
->get_cr3
= get_cr3
;
4570 context
->get_pdptr
= kvm_pdptr_read
;
4571 context
->inject_page_fault
= kvm_inject_page_fault
;
4574 static void init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
4576 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
4578 g_context
->get_cr3
= get_cr3
;
4579 g_context
->get_pdptr
= kvm_pdptr_read
;
4580 g_context
->inject_page_fault
= kvm_inject_page_fault
;
4583 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4584 * L1's nested page tables (e.g. EPT12). The nested translation
4585 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4586 * L2's page tables as the first level of translation and L1's
4587 * nested page tables as the second level of translation. Basically
4588 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4590 if (!is_paging(vcpu
)) {
4591 g_context
->nx
= false;
4592 g_context
->root_level
= 0;
4593 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
4594 } else if (is_long_mode(vcpu
)) {
4595 g_context
->nx
= is_nx(vcpu
);
4596 g_context
->root_level
= is_la57_mode(vcpu
) ?
4597 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4598 reset_rsvds_bits_mask(vcpu
, g_context
);
4599 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4600 } else if (is_pae(vcpu
)) {
4601 g_context
->nx
= is_nx(vcpu
);
4602 g_context
->root_level
= PT32E_ROOT_LEVEL
;
4603 reset_rsvds_bits_mask(vcpu
, g_context
);
4604 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4606 g_context
->nx
= false;
4607 g_context
->root_level
= PT32_ROOT_LEVEL
;
4608 reset_rsvds_bits_mask(vcpu
, g_context
);
4609 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
4612 update_permission_bitmask(vcpu
, g_context
, false);
4613 update_pkru_bitmask(vcpu
, g_context
, false);
4614 update_last_nonleaf_level(vcpu
, g_context
);
4617 static void init_kvm_mmu(struct kvm_vcpu
*vcpu
)
4619 if (mmu_is_nested(vcpu
))
4620 init_kvm_nested_mmu(vcpu
);
4621 else if (tdp_enabled
)
4622 init_kvm_tdp_mmu(vcpu
);
4624 init_kvm_softmmu(vcpu
);
4627 void kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
4629 kvm_mmu_unload(vcpu
);
4632 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
4634 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
4638 r
= mmu_topup_memory_caches(vcpu
);
4641 r
= mmu_alloc_roots(vcpu
);
4642 kvm_mmu_sync_roots(vcpu
);
4645 /* set_cr3() should ensure TLB has been flushed */
4646 vcpu
->arch
.mmu
.set_cr3(vcpu
, vcpu
->arch
.mmu
.root_hpa
);
4650 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
4652 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
4654 mmu_free_roots(vcpu
);
4655 WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4657 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
4659 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
4660 struct kvm_mmu_page
*sp
, u64
*spte
,
4663 if (sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
) {
4664 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
4668 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
4669 vcpu
->arch
.mmu
.update_pte(vcpu
, sp
, spte
, new);
4672 static bool need_remote_flush(u64 old
, u64
new)
4674 if (!is_shadow_present_pte(old
))
4676 if (!is_shadow_present_pte(new))
4678 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
4680 old
^= shadow_nx_mask
;
4681 new ^= shadow_nx_mask
;
4682 return (old
& ~new & PT64_PERM_MASK
) != 0;
4685 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
4686 const u8
*new, int *bytes
)
4692 * Assume that the pte write on a page table of the same type
4693 * as the current vcpu paging mode since we update the sptes only
4694 * when they have the same mode.
4696 if (is_pae(vcpu
) && *bytes
== 4) {
4697 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4700 r
= kvm_vcpu_read_guest(vcpu
, *gpa
, &gentry
, 8);
4703 new = (const u8
*)&gentry
;
4708 gentry
= *(const u32
*)new;
4711 gentry
= *(const u64
*)new;
4722 * If we're seeing too many writes to a page, it may no longer be a page table,
4723 * or we may be forking, in which case it is better to unmap the page.
4725 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
4728 * Skip write-flooding detected for the sp whose level is 1, because
4729 * it can become unsync, then the guest page is not write-protected.
4731 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
)
4734 atomic_inc(&sp
->write_flooding_count
);
4735 return atomic_read(&sp
->write_flooding_count
) >= 3;
4739 * Misaligned accesses are too much trouble to fix up; also, they usually
4740 * indicate a page is not used as a page table.
4742 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
4745 unsigned offset
, pte_size
, misaligned
;
4747 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4748 gpa
, bytes
, sp
->role
.word
);
4750 offset
= offset_in_page(gpa
);
4751 pte_size
= sp
->role
.cr4_pae
? 8 : 4;
4754 * Sometimes, the OS only writes the last one bytes to update status
4755 * bits, for example, in linux, andb instruction is used in clear_bit().
4757 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
4760 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
4761 misaligned
|= bytes
< 4;
4766 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
4768 unsigned page_offset
, quadrant
;
4772 page_offset
= offset_in_page(gpa
);
4773 level
= sp
->role
.level
;
4775 if (!sp
->role
.cr4_pae
) {
4776 page_offset
<<= 1; /* 32->64 */
4778 * A 32-bit pde maps 4MB while the shadow pdes map
4779 * only 2MB. So we need to double the offset again
4780 * and zap two pdes instead of one.
4782 if (level
== PT32_ROOT_LEVEL
) {
4783 page_offset
&= ~7; /* kill rounding error */
4787 quadrant
= page_offset
>> PAGE_SHIFT
;
4788 page_offset
&= ~PAGE_MASK
;
4789 if (quadrant
!= sp
->role
.quadrant
)
4793 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
4797 static void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
4798 const u8
*new, int bytes
,
4799 struct kvm_page_track_notifier_node
*node
)
4801 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
4802 struct kvm_mmu_page
*sp
;
4803 LIST_HEAD(invalid_list
);
4804 u64 entry
, gentry
, *spte
;
4806 bool remote_flush
, local_flush
;
4807 union kvm_mmu_page_role mask
= { };
4812 mask
.smep_andnot_wp
= 1;
4813 mask
.smap_andnot_wp
= 1;
4815 mask
.ad_disabled
= 1;
4818 * If we don't have indirect shadow pages, it means no page is
4819 * write-protected, so we can exit simply.
4821 if (!ACCESS_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
4824 remote_flush
= local_flush
= false;
4826 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
4828 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, new, &bytes
);
4831 * No need to care whether allocation memory is successful
4832 * or not since pte prefetch is skiped if it does not have
4833 * enough objects in the cache.
4835 mmu_topup_memory_caches(vcpu
);
4837 spin_lock(&vcpu
->kvm
->mmu_lock
);
4838 ++vcpu
->kvm
->stat
.mmu_pte_write
;
4839 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
4841 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
4842 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
4843 detect_write_flooding(sp
)) {
4844 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
4845 ++vcpu
->kvm
->stat
.mmu_flooded
;
4849 spte
= get_written_sptes(sp
, gpa
, &npte
);
4856 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
);
4858 !((sp
->role
.word
^ vcpu
->arch
.mmu
.base_role
.word
)
4859 & mask
.word
) && rmap_can_add(vcpu
))
4860 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
4861 if (need_remote_flush(entry
, *spte
))
4862 remote_flush
= true;
4866 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, remote_flush
, local_flush
);
4867 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
4868 spin_unlock(&vcpu
->kvm
->mmu_lock
);
4871 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
4876 if (vcpu
->arch
.mmu
.direct_map
)
4879 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
4881 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
4885 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
4887 static int make_mmu_pages_available(struct kvm_vcpu
*vcpu
)
4889 LIST_HEAD(invalid_list
);
4891 if (likely(kvm_mmu_available_pages(vcpu
->kvm
) >= KVM_MIN_FREE_MMU_PAGES
))
4894 while (kvm_mmu_available_pages(vcpu
->kvm
) < KVM_REFILL_PAGES
) {
4895 if (!prepare_zap_oldest_mmu_page(vcpu
->kvm
, &invalid_list
))
4898 ++vcpu
->kvm
->stat
.mmu_recycled
;
4900 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
4902 if (!kvm_mmu_available_pages(vcpu
->kvm
))
4907 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gva_t cr2
, u64 error_code
,
4908 void *insn
, int insn_len
)
4910 int r
, emulation_type
= EMULTYPE_RETRY
;
4911 enum emulation_result er
;
4912 bool direct
= vcpu
->arch
.mmu
.direct_map
;
4914 /* With shadow page tables, fault_address contains a GVA or nGPA. */
4915 if (vcpu
->arch
.mmu
.direct_map
) {
4916 vcpu
->arch
.gpa_available
= true;
4917 vcpu
->arch
.gpa_val
= cr2
;
4920 if (unlikely(error_code
& PFERR_RSVD_MASK
)) {
4921 r
= handle_mmio_page_fault(vcpu
, cr2
, direct
);
4922 if (r
== RET_MMIO_PF_EMULATE
) {
4926 if (r
== RET_MMIO_PF_RETRY
)
4930 /* Must be RET_MMIO_PF_INVALID. */
4933 r
= vcpu
->arch
.mmu
.page_fault(vcpu
, cr2
, lower_32_bits(error_code
),
4941 * Before emulating the instruction, check if the error code
4942 * was due to a RO violation while translating the guest page.
4943 * This can occur when using nested virtualization with nested
4944 * paging in both guests. If true, we simply unprotect the page
4945 * and resume the guest.
4947 if (vcpu
->arch
.mmu
.direct_map
&&
4948 (error_code
& PFERR_NESTED_GUEST_PAGE
) == PFERR_NESTED_GUEST_PAGE
) {
4949 kvm_mmu_unprotect_page(vcpu
->kvm
, gpa_to_gfn(cr2
));
4953 if (mmio_info_in_cache(vcpu
, cr2
, direct
))
4956 er
= x86_emulate_instruction(vcpu
, cr2
, emulation_type
, insn
, insn_len
);
4961 case EMULATE_USER_EXIT
:
4962 ++vcpu
->stat
.mmio_exits
;
4970 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
4972 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
4974 vcpu
->arch
.mmu
.invlpg(vcpu
, gva
);
4975 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
4976 ++vcpu
->stat
.invlpg
;
4978 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
4980 void kvm_enable_tdp(void)
4984 EXPORT_SYMBOL_GPL(kvm_enable_tdp
);
4986 void kvm_disable_tdp(void)
4988 tdp_enabled
= false;
4990 EXPORT_SYMBOL_GPL(kvm_disable_tdp
);
4992 static void free_mmu_pages(struct kvm_vcpu
*vcpu
)
4994 free_page((unsigned long)vcpu
->arch
.mmu
.pae_root
);
4995 if (vcpu
->arch
.mmu
.lm_root
!= NULL
)
4996 free_page((unsigned long)vcpu
->arch
.mmu
.lm_root
);
4999 static int alloc_mmu_pages(struct kvm_vcpu
*vcpu
)
5005 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
5006 * Therefore we need to allocate shadow page tables in the first
5007 * 4GB of memory, which happens to fit the DMA32 zone.
5009 page
= alloc_page(GFP_KERNEL
| __GFP_DMA32
);
5013 vcpu
->arch
.mmu
.pae_root
= page_address(page
);
5014 for (i
= 0; i
< 4; ++i
)
5015 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
5020 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
5022 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
5023 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
5024 vcpu
->arch
.mmu
.translate_gpa
= translate_gpa
;
5025 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
5027 return alloc_mmu_pages(vcpu
);
5030 void kvm_mmu_setup(struct kvm_vcpu
*vcpu
)
5032 MMU_WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
5037 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm
*kvm
,
5038 struct kvm_memory_slot
*slot
,
5039 struct kvm_page_track_notifier_node
*node
)
5041 kvm_mmu_invalidate_zap_all_pages(kvm
);
5044 void kvm_mmu_init_vm(struct kvm
*kvm
)
5046 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5048 node
->track_write
= kvm_mmu_pte_write
;
5049 node
->track_flush_slot
= kvm_mmu_invalidate_zap_pages_in_memslot
;
5050 kvm_page_track_register_notifier(kvm
, node
);
5053 void kvm_mmu_uninit_vm(struct kvm
*kvm
)
5055 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5057 kvm_page_track_unregister_notifier(kvm
, node
);
5060 /* The return value indicates if tlb flush on all vcpus is needed. */
5061 typedef bool (*slot_level_handler
) (struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
);
5063 /* The caller should hold mmu-lock before calling this function. */
5065 slot_handle_level_range(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5066 slot_level_handler fn
, int start_level
, int end_level
,
5067 gfn_t start_gfn
, gfn_t end_gfn
, bool lock_flush_tlb
)
5069 struct slot_rmap_walk_iterator iterator
;
5072 for_each_slot_rmap_range(memslot
, start_level
, end_level
, start_gfn
,
5073 end_gfn
, &iterator
) {
5075 flush
|= fn(kvm
, iterator
.rmap
);
5077 if (need_resched() || spin_needbreak(&kvm
->mmu_lock
)) {
5078 if (flush
&& lock_flush_tlb
) {
5079 kvm_flush_remote_tlbs(kvm
);
5082 cond_resched_lock(&kvm
->mmu_lock
);
5086 if (flush
&& lock_flush_tlb
) {
5087 kvm_flush_remote_tlbs(kvm
);
5095 slot_handle_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5096 slot_level_handler fn
, int start_level
, int end_level
,
5097 bool lock_flush_tlb
)
5099 return slot_handle_level_range(kvm
, memslot
, fn
, start_level
,
5100 end_level
, memslot
->base_gfn
,
5101 memslot
->base_gfn
+ memslot
->npages
- 1,
5106 slot_handle_all_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5107 slot_level_handler fn
, bool lock_flush_tlb
)
5109 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
5110 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
5114 slot_handle_large_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5115 slot_level_handler fn
, bool lock_flush_tlb
)
5117 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
+ 1,
5118 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
5122 slot_handle_leaf(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5123 slot_level_handler fn
, bool lock_flush_tlb
)
5125 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
5126 PT_PAGE_TABLE_LEVEL
, lock_flush_tlb
);
5129 void kvm_zap_gfn_range(struct kvm
*kvm
, gfn_t gfn_start
, gfn_t gfn_end
)
5131 struct kvm_memslots
*slots
;
5132 struct kvm_memory_slot
*memslot
;
5135 spin_lock(&kvm
->mmu_lock
);
5136 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5137 slots
= __kvm_memslots(kvm
, i
);
5138 kvm_for_each_memslot(memslot
, slots
) {
5141 start
= max(gfn_start
, memslot
->base_gfn
);
5142 end
= min(gfn_end
, memslot
->base_gfn
+ memslot
->npages
);
5146 slot_handle_level_range(kvm
, memslot
, kvm_zap_rmapp
,
5147 PT_PAGE_TABLE_LEVEL
, PT_MAX_HUGEPAGE_LEVEL
,
5148 start
, end
- 1, true);
5152 spin_unlock(&kvm
->mmu_lock
);
5155 static bool slot_rmap_write_protect(struct kvm
*kvm
,
5156 struct kvm_rmap_head
*rmap_head
)
5158 return __rmap_write_protect(kvm
, rmap_head
, false);
5161 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
,
5162 struct kvm_memory_slot
*memslot
)
5166 spin_lock(&kvm
->mmu_lock
);
5167 flush
= slot_handle_all_level(kvm
, memslot
, slot_rmap_write_protect
,
5169 spin_unlock(&kvm
->mmu_lock
);
5172 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
5173 * which do tlb flush out of mmu-lock should be serialized by
5174 * kvm->slots_lock otherwise tlb flush would be missed.
5176 lockdep_assert_held(&kvm
->slots_lock
);
5179 * We can flush all the TLBs out of the mmu lock without TLB
5180 * corruption since we just change the spte from writable to
5181 * readonly so that we only need to care the case of changing
5182 * spte from present to present (changing the spte from present
5183 * to nonpresent will flush all the TLBs immediately), in other
5184 * words, the only case we care is mmu_spte_update() where we
5185 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5186 * instead of PT_WRITABLE_MASK, that means it does not depend
5187 * on PT_WRITABLE_MASK anymore.
5190 kvm_flush_remote_tlbs(kvm
);
5193 static bool kvm_mmu_zap_collapsible_spte(struct kvm
*kvm
,
5194 struct kvm_rmap_head
*rmap_head
)
5197 struct rmap_iterator iter
;
5198 int need_tlb_flush
= 0;
5200 struct kvm_mmu_page
*sp
;
5203 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
5204 sp
= page_header(__pa(sptep
));
5205 pfn
= spte_to_pfn(*sptep
);
5208 * We cannot do huge page mapping for indirect shadow pages,
5209 * which are found on the last rmap (level = 1) when not using
5210 * tdp; such shadow pages are synced with the page table in
5211 * the guest, and the guest page table is using 4K page size
5212 * mapping if the indirect sp has level = 1.
5214 if (sp
->role
.direct
&&
5215 !kvm_is_reserved_pfn(pfn
) &&
5216 PageTransCompoundMap(pfn_to_page(pfn
))) {
5217 drop_spte(kvm
, sptep
);
5223 return need_tlb_flush
;
5226 void kvm_mmu_zap_collapsible_sptes(struct kvm
*kvm
,
5227 const struct kvm_memory_slot
*memslot
)
5229 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5230 spin_lock(&kvm
->mmu_lock
);
5231 slot_handle_leaf(kvm
, (struct kvm_memory_slot
*)memslot
,
5232 kvm_mmu_zap_collapsible_spte
, true);
5233 spin_unlock(&kvm
->mmu_lock
);
5236 void kvm_mmu_slot_leaf_clear_dirty(struct kvm
*kvm
,
5237 struct kvm_memory_slot
*memslot
)
5241 spin_lock(&kvm
->mmu_lock
);
5242 flush
= slot_handle_leaf(kvm
, memslot
, __rmap_clear_dirty
, false);
5243 spin_unlock(&kvm
->mmu_lock
);
5245 lockdep_assert_held(&kvm
->slots_lock
);
5248 * It's also safe to flush TLBs out of mmu lock here as currently this
5249 * function is only used for dirty logging, in which case flushing TLB
5250 * out of mmu lock also guarantees no dirty pages will be lost in
5254 kvm_flush_remote_tlbs(kvm
);
5256 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty
);
5258 void kvm_mmu_slot_largepage_remove_write_access(struct kvm
*kvm
,
5259 struct kvm_memory_slot
*memslot
)
5263 spin_lock(&kvm
->mmu_lock
);
5264 flush
= slot_handle_large_level(kvm
, memslot
, slot_rmap_write_protect
,
5266 spin_unlock(&kvm
->mmu_lock
);
5268 /* see kvm_mmu_slot_remove_write_access */
5269 lockdep_assert_held(&kvm
->slots_lock
);
5272 kvm_flush_remote_tlbs(kvm
);
5274 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access
);
5276 void kvm_mmu_slot_set_dirty(struct kvm
*kvm
,
5277 struct kvm_memory_slot
*memslot
)
5281 spin_lock(&kvm
->mmu_lock
);
5282 flush
= slot_handle_all_level(kvm
, memslot
, __rmap_set_dirty
, false);
5283 spin_unlock(&kvm
->mmu_lock
);
5285 lockdep_assert_held(&kvm
->slots_lock
);
5287 /* see kvm_mmu_slot_leaf_clear_dirty */
5289 kvm_flush_remote_tlbs(kvm
);
5291 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty
);
5293 #define BATCH_ZAP_PAGES 10
5294 static void kvm_zap_obsolete_pages(struct kvm
*kvm
)
5296 struct kvm_mmu_page
*sp
, *node
;
5300 list_for_each_entry_safe_reverse(sp
, node
,
5301 &kvm
->arch
.active_mmu_pages
, link
) {
5305 * No obsolete page exists before new created page since
5306 * active_mmu_pages is the FIFO list.
5308 if (!is_obsolete_sp(kvm
, sp
))
5312 * Since we are reversely walking the list and the invalid
5313 * list will be moved to the head, skip the invalid page
5314 * can help us to avoid the infinity list walking.
5316 if (sp
->role
.invalid
)
5320 * Need not flush tlb since we only zap the sp with invalid
5321 * generation number.
5323 if (batch
>= BATCH_ZAP_PAGES
&&
5324 cond_resched_lock(&kvm
->mmu_lock
)) {
5329 ret
= kvm_mmu_prepare_zap_page(kvm
, sp
,
5330 &kvm
->arch
.zapped_obsolete_pages
);
5338 * Should flush tlb before free page tables since lockless-walking
5339 * may use the pages.
5341 kvm_mmu_commit_zap_page(kvm
, &kvm
->arch
.zapped_obsolete_pages
);
5345 * Fast invalidate all shadow pages and use lock-break technique
5346 * to zap obsolete pages.
5348 * It's required when memslot is being deleted or VM is being
5349 * destroyed, in these cases, we should ensure that KVM MMU does
5350 * not use any resource of the being-deleted slot or all slots
5351 * after calling the function.
5353 void kvm_mmu_invalidate_zap_all_pages(struct kvm
*kvm
)
5355 spin_lock(&kvm
->mmu_lock
);
5356 trace_kvm_mmu_invalidate_zap_all_pages(kvm
);
5357 kvm
->arch
.mmu_valid_gen
++;
5360 * Notify all vcpus to reload its shadow page table
5361 * and flush TLB. Then all vcpus will switch to new
5362 * shadow page table with the new mmu_valid_gen.
5364 * Note: we should do this under the protection of
5365 * mmu-lock, otherwise, vcpu would purge shadow page
5366 * but miss tlb flush.
5368 kvm_reload_remote_mmus(kvm
);
5370 kvm_zap_obsolete_pages(kvm
);
5371 spin_unlock(&kvm
->mmu_lock
);
5374 static bool kvm_has_zapped_obsolete_pages(struct kvm
*kvm
)
5376 return unlikely(!list_empty_careful(&kvm
->arch
.zapped_obsolete_pages
));
5379 void kvm_mmu_invalidate_mmio_sptes(struct kvm
*kvm
, struct kvm_memslots
*slots
)
5382 * The very rare case: if the generation-number is round,
5383 * zap all shadow pages.
5385 if (unlikely((slots
->generation
& MMIO_GEN_MASK
) == 0)) {
5386 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5387 kvm_mmu_invalidate_zap_all_pages(kvm
);
5391 static unsigned long
5392 mmu_shrink_scan(struct shrinker
*shrink
, struct shrink_control
*sc
)
5395 int nr_to_scan
= sc
->nr_to_scan
;
5396 unsigned long freed
= 0;
5398 spin_lock(&kvm_lock
);
5400 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
5402 LIST_HEAD(invalid_list
);
5405 * Never scan more than sc->nr_to_scan VM instances.
5406 * Will not hit this condition practically since we do not try
5407 * to shrink more than one VM and it is very unlikely to see
5408 * !n_used_mmu_pages so many times.
5413 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5414 * here. We may skip a VM instance errorneosly, but we do not
5415 * want to shrink a VM that only started to populate its MMU
5418 if (!kvm
->arch
.n_used_mmu_pages
&&
5419 !kvm_has_zapped_obsolete_pages(kvm
))
5422 idx
= srcu_read_lock(&kvm
->srcu
);
5423 spin_lock(&kvm
->mmu_lock
);
5425 if (kvm_has_zapped_obsolete_pages(kvm
)) {
5426 kvm_mmu_commit_zap_page(kvm
,
5427 &kvm
->arch
.zapped_obsolete_pages
);
5431 if (prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
5433 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
5436 spin_unlock(&kvm
->mmu_lock
);
5437 srcu_read_unlock(&kvm
->srcu
, idx
);
5440 * unfair on small ones
5441 * per-vm shrinkers cry out
5442 * sadness comes quickly
5444 list_move_tail(&kvm
->vm_list
, &vm_list
);
5448 spin_unlock(&kvm_lock
);
5452 static unsigned long
5453 mmu_shrink_count(struct shrinker
*shrink
, struct shrink_control
*sc
)
5455 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
5458 static struct shrinker mmu_shrinker
= {
5459 .count_objects
= mmu_shrink_count
,
5460 .scan_objects
= mmu_shrink_scan
,
5461 .seeks
= DEFAULT_SEEKS
* 10,
5464 static void mmu_destroy_caches(void)
5466 if (pte_list_desc_cache
)
5467 kmem_cache_destroy(pte_list_desc_cache
);
5468 if (mmu_page_header_cache
)
5469 kmem_cache_destroy(mmu_page_header_cache
);
5472 int kvm_mmu_module_init(void)
5474 kvm_mmu_clear_all_pte_masks();
5476 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
5477 sizeof(struct pte_list_desc
),
5479 if (!pte_list_desc_cache
)
5482 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
5483 sizeof(struct kvm_mmu_page
),
5485 if (!mmu_page_header_cache
)
5488 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0, GFP_KERNEL
))
5491 register_shrinker(&mmu_shrinker
);
5496 mmu_destroy_caches();
5501 * Caculate mmu pages needed for kvm.
5503 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm
*kvm
)
5505 unsigned int nr_mmu_pages
;
5506 unsigned int nr_pages
= 0;
5507 struct kvm_memslots
*slots
;
5508 struct kvm_memory_slot
*memslot
;
5511 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5512 slots
= __kvm_memslots(kvm
, i
);
5514 kvm_for_each_memslot(memslot
, slots
)
5515 nr_pages
+= memslot
->npages
;
5518 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
5519 nr_mmu_pages
= max(nr_mmu_pages
,
5520 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES
);
5522 return nr_mmu_pages
;
5525 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
5527 kvm_mmu_unload(vcpu
);
5528 free_mmu_pages(vcpu
);
5529 mmu_free_memory_caches(vcpu
);
5532 void kvm_mmu_module_exit(void)
5534 mmu_destroy_caches();
5535 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
5536 unregister_shrinker(&mmu_shrinker
);
5537 mmu_audit_disable();