KVM: x86: fix memory leak in vmx_init
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / lapic.h
1 #ifndef __KVM_X86_LAPIC_H
2 #define __KVM_X86_LAPIC_H
3
4 #include "iodev.h"
5
6 #include <linux/kvm_host.h>
7
8 #define KVM_APIC_INIT 0
9 #define KVM_APIC_SIPI 1
10
11 struct kvm_timer {
12 struct hrtimer timer;
13 s64 period; /* unit: ns */
14 u32 timer_mode_mask;
15 u64 tscdeadline;
16 atomic_t pending; /* accumulated triggered timers */
17 };
18
19 struct kvm_lapic {
20 unsigned long base_address;
21 struct kvm_io_device dev;
22 struct kvm_timer lapic_timer;
23 u32 divide_count;
24 struct kvm_vcpu *vcpu;
25 bool irr_pending;
26 /* Number of bits set in ISR. */
27 s16 isr_count;
28 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
29 int highest_isr_cache;
30 /**
31 * APIC register page. The layout matches the register layout seen by
32 * the guest 1:1, because it is accessed by the vmx microcode.
33 * Note: Only one register, the TPR, is used by the microcode.
34 */
35 void *regs;
36 gpa_t vapic_addr;
37 struct page *vapic_page;
38 unsigned long pending_events;
39 unsigned int sipi_vector;
40 };
41 int kvm_create_lapic(struct kvm_vcpu *vcpu);
42 void kvm_free_lapic(struct kvm_vcpu *vcpu);
43
44 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
45 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
46 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
47 void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
48 void kvm_lapic_reset(struct kvm_vcpu *vcpu);
49 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
50 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
51 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
52 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
53 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
54 void kvm_apic_set_version(struct kvm_vcpu *vcpu);
55
56 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
57 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
58 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq);
59 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
60
61 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
62 struct kvm_lapic_irq *irq, int *r);
63
64 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
65 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
66 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
67 struct kvm_lapic_state *s);
68 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
69
70 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
71 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
72
73 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
74 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
75
76 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
77 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
78 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
79
80 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
81 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
82
83 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
84 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
85
86 static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
87 {
88 return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE;
89 }
90
91 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
92 void kvm_lapic_init(void);
93
94 static inline u32 kvm_apic_get_reg(struct kvm_lapic *apic, int reg_off)
95 {
96 return *((u32 *) (apic->regs + reg_off));
97 }
98
99 extern struct static_key kvm_no_apic_vcpu;
100
101 static inline bool kvm_vcpu_has_lapic(struct kvm_vcpu *vcpu)
102 {
103 if (static_key_false(&kvm_no_apic_vcpu))
104 return vcpu->arch.apic;
105 return true;
106 }
107
108 extern struct static_key_deferred apic_hw_disabled;
109
110 static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
111 {
112 if (static_key_false(&apic_hw_disabled.key))
113 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
114 return MSR_IA32_APICBASE_ENABLE;
115 }
116
117 extern struct static_key_deferred apic_sw_disabled;
118
119 static inline int kvm_apic_sw_enabled(struct kvm_lapic *apic)
120 {
121 if (static_key_false(&apic_sw_disabled.key))
122 return kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
123 return APIC_SPIV_APIC_ENABLED;
124 }
125
126 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
127 {
128 return kvm_vcpu_has_lapic(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
129 }
130
131 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
132 {
133 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
134 }
135
136 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
137 {
138 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
139 }
140
141 static inline bool kvm_apic_vid_enabled(struct kvm *kvm)
142 {
143 return kvm_x86_ops->vm_has_apicv(kvm);
144 }
145
146 static inline u16 apic_cluster_id(struct kvm_apic_map *map, u32 ldr)
147 {
148 u16 cid;
149 ldr >>= 32 - map->ldr_bits;
150 cid = (ldr >> map->cid_shift) & map->cid_mask;
151
152 BUG_ON(cid >= ARRAY_SIZE(map->logical_map));
153
154 return cid;
155 }
156
157 static inline u16 apic_logical_id(struct kvm_apic_map *map, u32 ldr)
158 {
159 ldr >>= (32 - map->ldr_bits);
160 return ldr & map->lid_mask;
161 }
162
163 static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
164 {
165 return vcpu->arch.apic->pending_events;
166 }
167
168 #endif