x86: remove explicit C3 TSC check on 64bit
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / tsc_64.c
1 #include <linux/kernel.h>
2 #include <linux/sched.h>
3 #include <linux/interrupt.h>
4 #include <linux/init.h>
5 #include <linux/clocksource.h>
6 #include <linux/time.h>
7 #include <linux/acpi.h>
8 #include <linux/cpufreq.h>
9 #include <linux/acpi_pmtmr.h>
10
11 #include <asm/hpet.h>
12 #include <asm/timex.h>
13 #include <asm/timer.h>
14
15 static int notsc __initdata = 0;
16
17 unsigned int cpu_khz; /* TSC clocks / usec, not used here */
18 EXPORT_SYMBOL(cpu_khz);
19 unsigned int tsc_khz;
20 EXPORT_SYMBOL(tsc_khz);
21
22 /* Accelerators for sched_clock()
23 * convert from cycles(64bits) => nanoseconds (64bits)
24 * basic equation:
25 * ns = cycles / (freq / ns_per_sec)
26 * ns = cycles * (ns_per_sec / freq)
27 * ns = cycles * (10^9 / (cpu_khz * 10^3))
28 * ns = cycles * (10^6 / cpu_khz)
29 *
30 * Then we use scaling math (suggested by george@mvista.com) to get:
31 * ns = cycles * (10^6 * SC / cpu_khz) / SC
32 * ns = cycles * cyc2ns_scale / SC
33 *
34 * And since SC is a constant power of two, we can convert the div
35 * into a shift.
36 *
37 * We can use khz divisor instead of mhz to keep a better precision, since
38 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
39 * (mathieu.desnoyers@polymtl.ca)
40 *
41 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
42 */
43 DEFINE_PER_CPU(unsigned long, cyc2ns);
44
45 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
46 {
47 unsigned long flags, prev_scale, *scale;
48 unsigned long long tsc_now, ns_now;
49
50 local_irq_save(flags);
51 sched_clock_idle_sleep_event();
52
53 scale = &per_cpu(cyc2ns, cpu);
54
55 rdtscll(tsc_now);
56 ns_now = __cycles_2_ns(tsc_now);
57
58 prev_scale = *scale;
59 if (cpu_khz)
60 *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
61
62 sched_clock_idle_wakeup_event(0);
63 local_irq_restore(flags);
64 }
65
66 unsigned long long native_sched_clock(void)
67 {
68 unsigned long a = 0;
69
70 /* Could do CPU core sync here. Opteron can execute rdtsc speculatively,
71 * which means it is not completely exact and may not be monotonous
72 * between CPUs. But the errors should be too small to matter for
73 * scheduling purposes.
74 */
75
76 rdtscll(a);
77 return cycles_2_ns(a);
78 }
79
80 /* We need to define a real function for sched_clock, to override the
81 weak default version */
82 #ifdef CONFIG_PARAVIRT
83 unsigned long long sched_clock(void)
84 {
85 return paravirt_sched_clock();
86 }
87 #else
88 unsigned long long
89 sched_clock(void) __attribute__((alias("native_sched_clock")));
90 #endif
91
92
93 static int tsc_unstable;
94
95 inline int check_tsc_unstable(void)
96 {
97 return tsc_unstable;
98 }
99 #ifdef CONFIG_CPU_FREQ
100
101 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
102 * changes.
103 *
104 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
105 * not that important because current Opteron setups do not support
106 * scaling on SMP anyroads.
107 *
108 * Should fix up last_tsc too. Currently gettimeofday in the
109 * first tick after the change will be slightly wrong.
110 */
111
112 static unsigned int ref_freq;
113 static unsigned long loops_per_jiffy_ref;
114 static unsigned long tsc_khz_ref;
115
116 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
117 void *data)
118 {
119 struct cpufreq_freqs *freq = data;
120 unsigned long *lpj, dummy;
121
122 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
123 return 0;
124
125 lpj = &dummy;
126 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
127 #ifdef CONFIG_SMP
128 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
129 #else
130 lpj = &boot_cpu_data.loops_per_jiffy;
131 #endif
132
133 if (!ref_freq) {
134 ref_freq = freq->old;
135 loops_per_jiffy_ref = *lpj;
136 tsc_khz_ref = tsc_khz;
137 }
138 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
139 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
140 (val == CPUFREQ_RESUMECHANGE)) {
141 *lpj =
142 cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
143
144 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
145 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
146 mark_tsc_unstable("cpufreq changes");
147 }
148
149 preempt_disable();
150 set_cyc2ns_scale(tsc_khz_ref, smp_processor_id());
151 preempt_enable();
152
153 return 0;
154 }
155
156 static struct notifier_block time_cpufreq_notifier_block = {
157 .notifier_call = time_cpufreq_notifier
158 };
159
160 static int __init cpufreq_tsc(void)
161 {
162 cpufreq_register_notifier(&time_cpufreq_notifier_block,
163 CPUFREQ_TRANSITION_NOTIFIER);
164 return 0;
165 }
166
167 core_initcall(cpufreq_tsc);
168
169 #endif
170
171 #define MAX_RETRIES 5
172 #define SMI_TRESHOLD 50000
173
174 /*
175 * Read TSC and the reference counters. Take care of SMI disturbance
176 */
177 static unsigned long __init tsc_read_refs(unsigned long *pm,
178 unsigned long *hpet)
179 {
180 unsigned long t1, t2;
181 int i;
182
183 for (i = 0; i < MAX_RETRIES; i++) {
184 t1 = get_cycles();
185 if (hpet)
186 *hpet = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
187 else
188 *pm = acpi_pm_read_early();
189 t2 = get_cycles();
190 if ((t2 - t1) < SMI_TRESHOLD)
191 return t2;
192 }
193 return ULONG_MAX;
194 }
195
196 /**
197 * tsc_calibrate - calibrate the tsc on boot
198 */
199 void __init tsc_calibrate(void)
200 {
201 unsigned long flags, tsc1, tsc2, tr1, tr2, pm1, pm2, hpet1, hpet2;
202 int hpet = is_hpet_enabled(), cpu;
203
204 local_irq_save(flags);
205
206 tsc1 = tsc_read_refs(&pm1, hpet ? &hpet1 : NULL);
207
208 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
209
210 outb(0xb0, 0x43);
211 outb((CLOCK_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
212 outb((CLOCK_TICK_RATE / (1000 / 50)) >> 8, 0x42);
213 tr1 = get_cycles();
214 while ((inb(0x61) & 0x20) == 0);
215 tr2 = get_cycles();
216
217 tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL);
218
219 local_irq_restore(flags);
220
221 /*
222 * Preset the result with the raw and inaccurate PIT
223 * calibration value
224 */
225 tsc_khz = (tr2 - tr1) / 50;
226
227 /* hpet or pmtimer available ? */
228 if (!hpet && !pm1 && !pm2) {
229 printk(KERN_INFO "TSC calibrated against PIT\n");
230 return;
231 }
232
233 /* Check, whether the sampling was disturbed by an SMI */
234 if (tsc1 == ULONG_MAX || tsc2 == ULONG_MAX) {
235 printk(KERN_WARNING "TSC calibration disturbed by SMI, "
236 "using PIT calibration result\n");
237 return;
238 }
239
240 tsc2 = (tsc2 - tsc1) * 1000000L;
241
242 if (hpet) {
243 printk(KERN_INFO "TSC calibrated against HPET\n");
244 if (hpet2 < hpet1)
245 hpet2 += 0x100000000;
246 hpet2 -= hpet1;
247 tsc1 = (hpet2 * hpet_readl(HPET_PERIOD)) / 1000000;
248 } else {
249 printk(KERN_INFO "TSC calibrated against PM_TIMER\n");
250 if (pm2 < pm1)
251 pm2 += ACPI_PM_OVRRUN;
252 pm2 -= pm1;
253 tsc1 = (pm2 * 1000000000) / PMTMR_TICKS_PER_SEC;
254 }
255
256 tsc_khz = tsc2 / tsc1;
257
258 for_each_possible_cpu(cpu)
259 set_cyc2ns_scale(tsc_khz, cpu);
260 }
261
262 /*
263 * Make an educated guess if the TSC is trustworthy and synchronized
264 * over all CPUs.
265 */
266 __cpuinit int unsynchronized_tsc(void)
267 {
268 if (tsc_unstable)
269 return 1;
270
271 #ifdef CONFIG_SMP
272 if (apic_is_clustered_box())
273 return 1;
274 #endif
275
276 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
277 return 0;
278
279 /* Assume multi socket systems are not synchronized */
280 return num_present_cpus() > 1;
281 }
282
283 int __init notsc_setup(char *s)
284 {
285 notsc = 1;
286 return 1;
287 }
288
289 __setup("notsc", notsc_setup);
290
291
292 /* clock source code: */
293 static cycle_t read_tsc(void)
294 {
295 cycle_t ret = (cycle_t)get_cycles();
296 return ret;
297 }
298
299 static cycle_t __vsyscall_fn vread_tsc(void)
300 {
301 cycle_t ret = (cycle_t)vget_cycles();
302 return ret;
303 }
304
305 static struct clocksource clocksource_tsc = {
306 .name = "tsc",
307 .rating = 300,
308 .read = read_tsc,
309 .mask = CLOCKSOURCE_MASK(64),
310 .shift = 22,
311 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
312 CLOCK_SOURCE_MUST_VERIFY,
313 .vread = vread_tsc,
314 };
315
316 void mark_tsc_unstable(char *reason)
317 {
318 if (!tsc_unstable) {
319 tsc_unstable = 1;
320 printk("Marking TSC unstable due to %s\n", reason);
321 /* Change only the rating, when not registered */
322 if (clocksource_tsc.mult)
323 clocksource_change_rating(&clocksource_tsc, 0);
324 else
325 clocksource_tsc.rating = 0;
326 }
327 }
328 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
329
330 void __init init_tsc_clocksource(void)
331 {
332 if (!notsc) {
333 clocksource_tsc.mult = clocksource_khz2mult(tsc_khz,
334 clocksource_tsc.shift);
335 if (check_tsc_unstable())
336 clocksource_tsc.rating = 0;
337
338 clocksource_register(&clocksource_tsc);
339 }
340 }