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x86: add set/clear_cpu_cap operations
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / setup_64.c
1 /*
2 * Copyright (C) 1995 Linus Torvalds
3 */
4
5 /*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
12 #include <linux/mm.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/a.out.h>
19 #include <linux/screen_info.h>
20 #include <linux/ioport.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/initrd.h>
24 #include <linux/highmem.h>
25 #include <linux/bootmem.h>
26 #include <linux/module.h>
27 #include <asm/processor.h>
28 #include <linux/console.h>
29 #include <linux/seq_file.h>
30 #include <linux/crash_dump.h>
31 #include <linux/root_dev.h>
32 #include <linux/pci.h>
33 #include <linux/acpi.h>
34 #include <linux/kallsyms.h>
35 #include <linux/edd.h>
36 #include <linux/mmzone.h>
37 #include <linux/kexec.h>
38 #include <linux/cpufreq.h>
39 #include <linux/dmi.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/ctype.h>
42
43 #include <asm/mtrr.h>
44 #include <asm/uaccess.h>
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/smp.h>
48 #include <asm/msr.h>
49 #include <asm/desc.h>
50 #include <video/edid.h>
51 #include <asm/e820.h>
52 #include <asm/dma.h>
53 #include <asm/mpspec.h>
54 #include <asm/mmu_context.h>
55 #include <asm/proto.h>
56 #include <asm/setup.h>
57 #include <asm/mach_apic.h>
58 #include <asm/numa.h>
59 #include <asm/sections.h>
60 #include <asm/dmi.h>
61 #include <asm/cacheflush.h>
62 #include <asm/mce.h>
63
64 /*
65 * Machine setup..
66 */
67
68 struct cpuinfo_x86 boot_cpu_data __read_mostly;
69 EXPORT_SYMBOL(boot_cpu_data);
70
71 unsigned long mmu_cr4_features;
72
73 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
74 int bootloader_type;
75
76 unsigned long saved_video_mode;
77
78 int force_mwait __cpuinitdata;
79
80 /*
81 * Early DMI memory
82 */
83 int dmi_alloc_index;
84 char dmi_alloc_data[DMI_MAX_DATA];
85
86 /*
87 * Setup options
88 */
89 struct screen_info screen_info;
90 EXPORT_SYMBOL(screen_info);
91 struct sys_desc_table_struct {
92 unsigned short length;
93 unsigned char table[0];
94 };
95
96 struct edid_info edid_info;
97 EXPORT_SYMBOL_GPL(edid_info);
98
99 extern int root_mountflags;
100
101 char __initdata command_line[COMMAND_LINE_SIZE];
102
103 struct resource standard_io_resources[] = {
104 { .name = "dma1", .start = 0x00, .end = 0x1f,
105 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
106 { .name = "pic1", .start = 0x20, .end = 0x21,
107 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
108 { .name = "timer0", .start = 0x40, .end = 0x43,
109 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
110 { .name = "timer1", .start = 0x50, .end = 0x53,
111 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
112 { .name = "keyboard", .start = 0x60, .end = 0x6f,
113 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
114 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
115 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
116 { .name = "pic2", .start = 0xa0, .end = 0xa1,
117 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
118 { .name = "dma2", .start = 0xc0, .end = 0xdf,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "fpu", .start = 0xf0, .end = 0xff,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
122 };
123
124 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
125
126 static struct resource data_resource = {
127 .name = "Kernel data",
128 .start = 0,
129 .end = 0,
130 .flags = IORESOURCE_RAM,
131 };
132 static struct resource code_resource = {
133 .name = "Kernel code",
134 .start = 0,
135 .end = 0,
136 .flags = IORESOURCE_RAM,
137 };
138 static struct resource bss_resource = {
139 .name = "Kernel bss",
140 .start = 0,
141 .end = 0,
142 .flags = IORESOURCE_RAM,
143 };
144
145 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
146
147 #ifdef CONFIG_PROC_VMCORE
148 /* elfcorehdr= specifies the location of elf core header
149 * stored by the crashed kernel. This option will be passed
150 * by kexec loader to the capture kernel.
151 */
152 static int __init setup_elfcorehdr(char *arg)
153 {
154 char *end;
155 if (!arg)
156 return -EINVAL;
157 elfcorehdr_addr = memparse(arg, &end);
158 return end > arg ? 0 : -EINVAL;
159 }
160 early_param("elfcorehdr", setup_elfcorehdr);
161 #endif
162
163 #ifndef CONFIG_NUMA
164 static void __init
165 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
166 {
167 unsigned long bootmap_size, bootmap;
168
169 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
170 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
171 if (bootmap == -1L)
172 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
173 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
174 e820_register_active_regions(0, start_pfn, end_pfn);
175 free_bootmem_with_active_regions(0, end_pfn);
176 reserve_bootmem(bootmap, bootmap_size);
177 }
178 #endif
179
180 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
181 struct edd edd;
182 #ifdef CONFIG_EDD_MODULE
183 EXPORT_SYMBOL(edd);
184 #endif
185 /**
186 * copy_edd() - Copy the BIOS EDD information
187 * from boot_params into a safe place.
188 *
189 */
190 static inline void copy_edd(void)
191 {
192 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
193 sizeof(edd.mbr_signature));
194 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
195 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
196 edd.edd_info_nr = boot_params.eddbuf_entries;
197 }
198 #else
199 static inline void copy_edd(void)
200 {
201 }
202 #endif
203
204 #ifdef CONFIG_KEXEC
205 static void __init reserve_crashkernel(void)
206 {
207 unsigned long long free_mem;
208 unsigned long long crash_size, crash_base;
209 int ret;
210
211 free_mem =
212 ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
213
214 ret = parse_crashkernel(boot_command_line, free_mem,
215 &crash_size, &crash_base);
216 if (ret == 0 && crash_size) {
217 if (crash_base > 0) {
218 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
219 "for crashkernel (System RAM: %ldMB)\n",
220 (unsigned long)(crash_size >> 20),
221 (unsigned long)(crash_base >> 20),
222 (unsigned long)(free_mem >> 20));
223 crashk_res.start = crash_base;
224 crashk_res.end = crash_base + crash_size - 1;
225 reserve_bootmem(crash_base, crash_size);
226 } else
227 printk(KERN_INFO "crashkernel reservation failed - "
228 "you have to specify a base address\n");
229 }
230 }
231 #else
232 static inline void __init reserve_crashkernel(void)
233 {}
234 #endif
235
236 #define EBDA_ADDR_POINTER 0x40E
237
238 unsigned __initdata ebda_addr;
239 unsigned __initdata ebda_size;
240
241 static void discover_ebda(void)
242 {
243 /*
244 * there is a real-mode segmented pointer pointing to the
245 * 4K EBDA area at 0x40E
246 */
247 ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
248 ebda_addr <<= 4;
249
250 ebda_size = *(unsigned short *)__va(ebda_addr);
251
252 /* Round EBDA up to pages */
253 if (ebda_size == 0)
254 ebda_size = 1;
255 ebda_size <<= 10;
256 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
257 if (ebda_size > 64*1024)
258 ebda_size = 64*1024;
259 }
260
261 void __init setup_arch(char **cmdline_p)
262 {
263 unsigned i;
264
265 printk(KERN_INFO "Command line: %s\n", boot_command_line);
266
267 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
268 screen_info = boot_params.screen_info;
269 edid_info = boot_params.edid_info;
270 saved_video_mode = boot_params.hdr.vid_mode;
271 bootloader_type = boot_params.hdr.type_of_loader;
272
273 #ifdef CONFIG_BLK_DEV_RAM
274 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
275 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
276 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
277 #endif
278 setup_memory_region();
279 copy_edd();
280
281 if (!boot_params.hdr.root_flags)
282 root_mountflags &= ~MS_RDONLY;
283 init_mm.start_code = (unsigned long) &_text;
284 init_mm.end_code = (unsigned long) &_etext;
285 init_mm.end_data = (unsigned long) &_edata;
286 init_mm.brk = (unsigned long) &_end;
287
288 code_resource.start = virt_to_phys(&_text);
289 code_resource.end = virt_to_phys(&_etext)-1;
290 data_resource.start = virt_to_phys(&_etext);
291 data_resource.end = virt_to_phys(&_edata)-1;
292 bss_resource.start = virt_to_phys(&__bss_start);
293 bss_resource.end = virt_to_phys(&__bss_stop)-1;
294
295 early_identify_cpu(&boot_cpu_data);
296
297 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
298 *cmdline_p = command_line;
299
300 parse_early_param();
301
302 finish_e820_parsing();
303
304 e820_register_active_regions(0, 0, -1UL);
305 /*
306 * partially used pages are not usable - thus
307 * we are rounding upwards:
308 */
309 end_pfn = e820_end_of_ram();
310 num_physpages = end_pfn;
311
312 check_efer();
313
314 discover_ebda();
315
316 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
317
318 dmi_scan_machine();
319
320 io_delay_init();
321
322 #ifdef CONFIG_SMP
323 /* setup to use the static apicid table during kernel startup */
324 x86_cpu_to_apicid_ptr = (void *)&x86_cpu_to_apicid_init;
325 #endif
326
327 #ifdef CONFIG_ACPI
328 /*
329 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
330 * Call this early for SRAT node setup.
331 */
332 acpi_boot_table_init();
333 #endif
334
335 /* How many end-of-memory variables you have, grandma! */
336 max_low_pfn = end_pfn;
337 max_pfn = end_pfn;
338 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
339
340 /* Remove active ranges so rediscovery with NUMA-awareness happens */
341 remove_all_active_ranges();
342
343 #ifdef CONFIG_ACPI_NUMA
344 /*
345 * Parse SRAT to discover nodes.
346 */
347 acpi_numa_init();
348 #endif
349
350 #ifdef CONFIG_NUMA
351 numa_initmem_init(0, end_pfn);
352 #else
353 contig_initmem_init(0, end_pfn);
354 #endif
355
356 /* Reserve direct mapping */
357 reserve_bootmem_generic(table_start << PAGE_SHIFT,
358 (table_end - table_start) << PAGE_SHIFT);
359
360 /* reserve kernel */
361 reserve_bootmem_generic(__pa_symbol(&_text),
362 __pa_symbol(&_end) - __pa_symbol(&_text));
363
364 /*
365 * reserve physical page 0 - it's a special BIOS page on many boxes,
366 * enabling clean reboots, SMP operation, laptop functions.
367 */
368 reserve_bootmem_generic(0, PAGE_SIZE);
369
370 /* reserve ebda region */
371 if (ebda_addr)
372 reserve_bootmem_generic(ebda_addr, ebda_size);
373 #ifdef CONFIG_NUMA
374 /* reserve nodemap region */
375 if (nodemap_addr)
376 reserve_bootmem_generic(nodemap_addr, nodemap_size);
377 #endif
378
379 #ifdef CONFIG_SMP
380 /* Reserve SMP trampoline */
381 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
382 #endif
383
384 #ifdef CONFIG_ACPI_SLEEP
385 /*
386 * Reserve low memory region for sleep support.
387 */
388 acpi_reserve_bootmem();
389 #endif
390 /*
391 * Find and reserve possible boot-time SMP configuration:
392 */
393 find_smp_config();
394 #ifdef CONFIG_BLK_DEV_INITRD
395 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
396 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
397 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
398 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
399 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
400
401 if (ramdisk_end <= end_of_mem) {
402 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
403 initrd_start = ramdisk_image + PAGE_OFFSET;
404 initrd_end = initrd_start+ramdisk_size;
405 } else {
406 printk(KERN_ERR "initrd extends beyond end of memory "
407 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
408 ramdisk_end, end_of_mem);
409 initrd_start = 0;
410 }
411 }
412 #endif
413 reserve_crashkernel();
414 paging_init();
415
416 early_quirks();
417
418 /*
419 * set this early, so we dont allocate cpu0
420 * if MADT list doesnt list BSP first
421 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
422 */
423 cpu_set(0, cpu_present_map);
424 #ifdef CONFIG_ACPI
425 /*
426 * Read APIC and some other early information from ACPI tables.
427 */
428 acpi_boot_init();
429 #endif
430
431 init_cpu_to_node();
432
433 /*
434 * get boot-time SMP configuration:
435 */
436 if (smp_found_config)
437 get_smp_config();
438 init_apic_mappings();
439 ioapic_init_mappings();
440
441 /*
442 * We trust e820 completely. No explicit ROM probing in memory.
443 */
444 e820_reserve_resources(&code_resource, &data_resource, &bss_resource);
445 e820_mark_nosave_regions();
446
447 /* request I/O space for devices used on all i[345]86 PCs */
448 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
449 request_resource(&ioport_resource, &standard_io_resources[i]);
450
451 e820_setup_gap();
452
453 #ifdef CONFIG_VT
454 #if defined(CONFIG_VGA_CONSOLE)
455 conswitchp = &vga_con;
456 #elif defined(CONFIG_DUMMY_CONSOLE)
457 conswitchp = &dummy_con;
458 #endif
459 #endif
460 }
461
462 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
463 {
464 unsigned int *v;
465
466 if (c->extended_cpuid_level < 0x80000004)
467 return 0;
468
469 v = (unsigned int *) c->x86_model_id;
470 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
471 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
472 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
473 c->x86_model_id[48] = 0;
474 return 1;
475 }
476
477
478 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
479 {
480 unsigned int n, dummy, eax, ebx, ecx, edx;
481
482 n = c->extended_cpuid_level;
483
484 if (n >= 0x80000005) {
485 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
486 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
487 "D cache %dK (%d bytes/line)\n",
488 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
489 c->x86_cache_size = (ecx>>24) + (edx>>24);
490 /* On K8 L1 TLB is inclusive, so don't count it */
491 c->x86_tlbsize = 0;
492 }
493
494 if (n >= 0x80000006) {
495 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
496 ecx = cpuid_ecx(0x80000006);
497 c->x86_cache_size = ecx >> 16;
498 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
499
500 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
501 c->x86_cache_size, ecx & 0xFF);
502 }
503
504 if (n >= 0x80000007)
505 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
506 if (n >= 0x80000008) {
507 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
508 c->x86_virt_bits = (eax >> 8) & 0xff;
509 c->x86_phys_bits = eax & 0xff;
510 }
511 }
512
513 #ifdef CONFIG_NUMA
514 static int nearby_node(int apicid)
515 {
516 int i, node;
517
518 for (i = apicid - 1; i >= 0; i--) {
519 node = apicid_to_node[i];
520 if (node != NUMA_NO_NODE && node_online(node))
521 return node;
522 }
523 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
524 node = apicid_to_node[i];
525 if (node != NUMA_NO_NODE && node_online(node))
526 return node;
527 }
528 return first_node(node_online_map); /* Shouldn't happen */
529 }
530 #endif
531
532 /*
533 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
534 * Assumes number of cores is a power of two.
535 */
536 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
537 {
538 #ifdef CONFIG_SMP
539 unsigned bits;
540 #ifdef CONFIG_NUMA
541 int cpu = smp_processor_id();
542 int node = 0;
543 unsigned apicid = hard_smp_processor_id();
544 #endif
545 bits = c->x86_coreid_bits;
546
547 /* Low order bits define the core id (index of core in socket) */
548 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
549 /* Convert the APIC ID into the socket ID */
550 c->phys_proc_id = phys_pkg_id(bits);
551
552 #ifdef CONFIG_NUMA
553 node = c->phys_proc_id;
554 if (apicid_to_node[apicid] != NUMA_NO_NODE)
555 node = apicid_to_node[apicid];
556 if (!node_online(node)) {
557 /* Two possibilities here:
558 - The CPU is missing memory and no node was created.
559 In that case try picking one from a nearby CPU
560 - The APIC IDs differ from the HyperTransport node IDs
561 which the K8 northbridge parsing fills in.
562 Assume they are all increased by a constant offset,
563 but in the same order as the HT nodeids.
564 If that doesn't result in a usable node fall back to the
565 path for the previous case. */
566
567 int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
568
569 if (ht_nodeid >= 0 &&
570 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
571 node = apicid_to_node[ht_nodeid];
572 /* Pick a nearby node */
573 if (!node_online(node))
574 node = nearby_node(apicid);
575 }
576 numa_set_node(cpu, node);
577
578 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
579 #endif
580 #endif
581 }
582
583 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
584 {
585 #ifdef CONFIG_SMP
586 unsigned bits, ecx;
587
588 /* Multi core CPU? */
589 if (c->extended_cpuid_level < 0x80000008)
590 return;
591
592 ecx = cpuid_ecx(0x80000008);
593
594 c->x86_max_cores = (ecx & 0xff) + 1;
595
596 /* CPU telling us the core id bits shift? */
597 bits = (ecx >> 12) & 0xF;
598
599 /* Otherwise recompute */
600 if (bits == 0) {
601 while ((1 << bits) < c->x86_max_cores)
602 bits++;
603 }
604
605 c->x86_coreid_bits = bits;
606
607 #endif
608 }
609
610 #define ENABLE_C1E_MASK 0x18000000
611 #define CPUID_PROCESSOR_SIGNATURE 1
612 #define CPUID_XFAM 0x0ff00000
613 #define CPUID_XFAM_K8 0x00000000
614 #define CPUID_XFAM_10H 0x00100000
615 #define CPUID_XFAM_11H 0x00200000
616 #define CPUID_XMOD 0x000f0000
617 #define CPUID_XMOD_REV_F 0x00040000
618
619 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
620 static __cpuinit int amd_apic_timer_broken(void)
621 {
622 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
623
624 switch (eax & CPUID_XFAM) {
625 case CPUID_XFAM_K8:
626 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
627 break;
628 case CPUID_XFAM_10H:
629 case CPUID_XFAM_11H:
630 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
631 if (lo & ENABLE_C1E_MASK)
632 return 1;
633 break;
634 default:
635 /* err on the side of caution */
636 return 1;
637 }
638 return 0;
639 }
640
641 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
642 {
643 unsigned level;
644
645 #ifdef CONFIG_SMP
646 unsigned long value;
647
648 /*
649 * Disable TLB flush filter by setting HWCR.FFDIS on K8
650 * bit 6 of msr C001_0015
651 *
652 * Errata 63 for SH-B3 steppings
653 * Errata 122 for all steppings (F+ have it disabled by default)
654 */
655 if (c->x86 == 15) {
656 rdmsrl(MSR_K8_HWCR, value);
657 value |= 1 << 6;
658 wrmsrl(MSR_K8_HWCR, value);
659 }
660 #endif
661
662 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
663 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
664 clear_bit(0*32+31, (unsigned long *)&c->x86_capability);
665
666 /* On C+ stepping K8 rep microcode works well for copy/memset */
667 level = cpuid_eax(1);
668 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
669 level >= 0x0f58))
670 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
671 if (c->x86 == 0x10 || c->x86 == 0x11)
672 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
673
674 /* Enable workaround for FXSAVE leak */
675 if (c->x86 >= 6)
676 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
677
678 level = get_model_name(c);
679 if (!level) {
680 switch (c->x86) {
681 case 15:
682 /* Should distinguish Models here, but this is only
683 a fallback anyways. */
684 strcpy(c->x86_model_id, "Hammer");
685 break;
686 }
687 }
688 display_cacheinfo(c);
689
690 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
691 if (c->x86_power & (1<<8))
692 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
693
694 /* Multi core CPU? */
695 if (c->extended_cpuid_level >= 0x80000008)
696 amd_detect_cmp(c);
697
698 if (c->extended_cpuid_level >= 0x80000006 &&
699 (cpuid_edx(0x80000006) & 0xf000))
700 num_cache_leaves = 4;
701 else
702 num_cache_leaves = 3;
703
704 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
705 set_cpu_cap(c, X86_FEATURE_K8);
706
707 /* RDTSC can be speculated around */
708 clear_cpu_cap(c, X86_FEATURE_SYNC_RDTSC);
709
710 /* Family 10 doesn't support C states in MWAIT so don't use it */
711 if (c->x86 == 0x10 && !force_mwait)
712 clear_cpu_cap(c, X86_FEATURE_MWAIT);
713
714 if (amd_apic_timer_broken())
715 disable_apic_timer = 1;
716 }
717
718 static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
719 {
720 #ifdef CONFIG_SMP
721 u32 eax, ebx, ecx, edx;
722 int index_msb, core_bits;
723
724 cpuid(1, &eax, &ebx, &ecx, &edx);
725
726
727 if (!cpu_has(c, X86_FEATURE_HT))
728 return;
729 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
730 goto out;
731
732 smp_num_siblings = (ebx & 0xff0000) >> 16;
733
734 if (smp_num_siblings == 1) {
735 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
736 } else if (smp_num_siblings > 1) {
737
738 if (smp_num_siblings > NR_CPUS) {
739 printk(KERN_WARNING "CPU: Unsupported number of "
740 "siblings %d", smp_num_siblings);
741 smp_num_siblings = 1;
742 return;
743 }
744
745 index_msb = get_count_order(smp_num_siblings);
746 c->phys_proc_id = phys_pkg_id(index_msb);
747
748 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
749
750 index_msb = get_count_order(smp_num_siblings);
751
752 core_bits = get_count_order(c->x86_max_cores);
753
754 c->cpu_core_id = phys_pkg_id(index_msb) &
755 ((1 << core_bits) - 1);
756 }
757 out:
758 if ((c->x86_max_cores * smp_num_siblings) > 1) {
759 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
760 c->phys_proc_id);
761 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
762 c->cpu_core_id);
763 }
764
765 #endif
766 }
767
768 /*
769 * find out the number of processor cores on the die
770 */
771 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
772 {
773 unsigned int eax, t;
774
775 if (c->cpuid_level < 4)
776 return 1;
777
778 cpuid_count(4, 0, &eax, &t, &t, &t);
779
780 if (eax & 0x1f)
781 return ((eax >> 26) + 1);
782 else
783 return 1;
784 }
785
786 static void srat_detect_node(void)
787 {
788 #ifdef CONFIG_NUMA
789 unsigned node;
790 int cpu = smp_processor_id();
791 int apicid = hard_smp_processor_id();
792
793 /* Don't do the funky fallback heuristics the AMD version employs
794 for now. */
795 node = apicid_to_node[apicid];
796 if (node == NUMA_NO_NODE)
797 node = first_node(node_online_map);
798 numa_set_node(cpu, node);
799
800 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
801 #endif
802 }
803
804 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
805 {
806 /* Cache sizes */
807 unsigned n;
808
809 init_intel_cacheinfo(c);
810 if (c->cpuid_level > 9) {
811 unsigned eax = cpuid_eax(10);
812 /* Check for version and the number of counters */
813 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
814 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
815 }
816
817 if (cpu_has_ds) {
818 unsigned int l1, l2;
819 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
820 if (!(l1 & (1<<11)))
821 set_cpu_cap(c, X86_FEATURE_BTS);
822 if (!(l1 & (1<<12)))
823 set_cpu_cap(c, X86_FEATURE_PEBS);
824 }
825
826 n = c->extended_cpuid_level;
827 if (n >= 0x80000008) {
828 unsigned eax = cpuid_eax(0x80000008);
829 c->x86_virt_bits = (eax >> 8) & 0xff;
830 c->x86_phys_bits = eax & 0xff;
831 /* CPUID workaround for Intel 0F34 CPU */
832 if (c->x86_vendor == X86_VENDOR_INTEL &&
833 c->x86 == 0xF && c->x86_model == 0x3 &&
834 c->x86_mask == 0x4)
835 c->x86_phys_bits = 36;
836 }
837
838 if (c->x86 == 15)
839 c->x86_cache_alignment = c->x86_clflush_size * 2;
840 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
841 (c->x86 == 0x6 && c->x86_model >= 0x0e))
842 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
843 if (c->x86 == 6)
844 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
845 if (c->x86 == 15)
846 set_cpu_cap(c, X86_FEATURE_SYNC_RDTSC);
847 else
848 clear_cpu_cap(c, X86_FEATURE_SYNC_RDTSC);
849 c->x86_max_cores = intel_num_cpu_cores(c);
850
851 srat_detect_node();
852 }
853
854 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
855 {
856 char *v = c->x86_vendor_id;
857
858 if (!strcmp(v, "AuthenticAMD"))
859 c->x86_vendor = X86_VENDOR_AMD;
860 else if (!strcmp(v, "GenuineIntel"))
861 c->x86_vendor = X86_VENDOR_INTEL;
862 else
863 c->x86_vendor = X86_VENDOR_UNKNOWN;
864 }
865
866 struct cpu_model_info {
867 int vendor;
868 int family;
869 char *model_names[16];
870 };
871
872 /* Do some early cpuid on the boot CPU to get some parameter that are
873 needed before check_bugs. Everything advanced is in identify_cpu
874 below. */
875 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
876 {
877 u32 tfms, xlvl;
878
879 c->loops_per_jiffy = loops_per_jiffy;
880 c->x86_cache_size = -1;
881 c->x86_vendor = X86_VENDOR_UNKNOWN;
882 c->x86_model = c->x86_mask = 0; /* So far unknown... */
883 c->x86_vendor_id[0] = '\0'; /* Unset */
884 c->x86_model_id[0] = '\0'; /* Unset */
885 c->x86_clflush_size = 64;
886 c->x86_cache_alignment = c->x86_clflush_size;
887 c->x86_max_cores = 1;
888 c->x86_coreid_bits = 0;
889 c->extended_cpuid_level = 0;
890 memset(&c->x86_capability, 0, sizeof c->x86_capability);
891
892 /* Get vendor name */
893 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
894 (unsigned int *)&c->x86_vendor_id[0],
895 (unsigned int *)&c->x86_vendor_id[8],
896 (unsigned int *)&c->x86_vendor_id[4]);
897
898 get_cpu_vendor(c);
899
900 /* Initialize the standard set of capabilities */
901 /* Note that the vendor-specific code below might override */
902
903 /* Intel-defined flags: level 0x00000001 */
904 if (c->cpuid_level >= 0x00000001) {
905 __u32 misc;
906 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
907 &c->x86_capability[0]);
908 c->x86 = (tfms >> 8) & 0xf;
909 c->x86_model = (tfms >> 4) & 0xf;
910 c->x86_mask = tfms & 0xf;
911 if (c->x86 == 0xf)
912 c->x86 += (tfms >> 20) & 0xff;
913 if (c->x86 >= 0x6)
914 c->x86_model += ((tfms >> 16) & 0xF) << 4;
915 if (c->x86_capability[0] & (1<<19))
916 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
917 } else {
918 /* Have CPUID level 0 only - unheard of */
919 c->x86 = 4;
920 }
921
922 #ifdef CONFIG_SMP
923 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
924 #endif
925 /* AMD-defined flags: level 0x80000001 */
926 xlvl = cpuid_eax(0x80000000);
927 c->extended_cpuid_level = xlvl;
928 if ((xlvl & 0xffff0000) == 0x80000000) {
929 if (xlvl >= 0x80000001) {
930 c->x86_capability[1] = cpuid_edx(0x80000001);
931 c->x86_capability[6] = cpuid_ecx(0x80000001);
932 }
933 if (xlvl >= 0x80000004)
934 get_model_name(c); /* Default name */
935 }
936
937 /* Transmeta-defined flags: level 0x80860001 */
938 xlvl = cpuid_eax(0x80860000);
939 if ((xlvl & 0xffff0000) == 0x80860000) {
940 /* Don't set x86_cpuid_level here for now to not confuse. */
941 if (xlvl >= 0x80860001)
942 c->x86_capability[2] = cpuid_edx(0x80860001);
943 }
944
945 switch (c->x86_vendor) {
946 case X86_VENDOR_AMD:
947 early_init_amd(c);
948 break;
949 }
950
951 }
952
953 /*
954 * This does the hard work of actually picking apart the CPU stuff...
955 */
956 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
957 {
958 int i;
959
960 early_identify_cpu(c);
961
962 init_scattered_cpuid_features(c);
963
964 c->apicid = phys_pkg_id(0);
965
966 /*
967 * Vendor-specific initialization. In this section we
968 * canonicalize the feature flags, meaning if there are
969 * features a certain CPU supports which CPUID doesn't
970 * tell us, CPUID claiming incorrect flags, or other bugs,
971 * we handle them here.
972 *
973 * At the end of this section, c->x86_capability better
974 * indicate the features this CPU genuinely supports!
975 */
976 switch (c->x86_vendor) {
977 case X86_VENDOR_AMD:
978 init_amd(c);
979 break;
980
981 case X86_VENDOR_INTEL:
982 init_intel(c);
983 break;
984
985 case X86_VENDOR_UNKNOWN:
986 default:
987 display_cacheinfo(c);
988 break;
989 }
990
991 select_idle_routine(c);
992 detect_ht(c);
993
994 /*
995 * On SMP, boot_cpu_data holds the common feature set between
996 * all CPUs; so make sure that we indicate which features are
997 * common between the CPUs. The first time this routine gets
998 * executed, c == &boot_cpu_data.
999 */
1000 if (c != &boot_cpu_data) {
1001 /* AND the already accumulated flags with these */
1002 for (i = 0; i < NCAPINTS; i++)
1003 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1004 }
1005
1006 #ifdef CONFIG_X86_MCE
1007 mcheck_init(c);
1008 #endif
1009 if (c != &boot_cpu_data)
1010 mtrr_ap_init();
1011 #ifdef CONFIG_NUMA
1012 numa_add_cpu(smp_processor_id());
1013 #endif
1014 }
1015
1016 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1017 {
1018 if (c->x86_model_id[0])
1019 printk(KERN_INFO "%s", c->x86_model_id);
1020
1021 if (c->x86_mask || c->cpuid_level >= 0)
1022 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1023 else
1024 printk(KERN_CONT "\n");
1025 }
1026
1027 /*
1028 * Get CPU information for use by the procfs.
1029 */
1030
1031 static int show_cpuinfo(struct seq_file *m, void *v)
1032 {
1033 struct cpuinfo_x86 *c = v;
1034 int cpu = 0, i;
1035
1036 /*
1037 * These flag bits must match the definitions in <asm/cpufeature.h>.
1038 * NULL means this bit is undefined or reserved; either way it doesn't
1039 * have meaning as far as Linux is concerned. Note that it's important
1040 * to realize there is a difference between this table and CPUID -- if
1041 * applications want to get the raw CPUID data, they should access
1042 * /dev/cpu/<cpu_nr>/cpuid instead.
1043 */
1044 static const char *const x86_cap_flags[] = {
1045 /* Intel-defined */
1046 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1047 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1048 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1049 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
1050
1051 /* AMD-defined */
1052 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1053 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1054 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
1055 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
1056 "3dnowext", "3dnow",
1057
1058 /* Transmeta-defined */
1059 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1060 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1061 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1062 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1063
1064 /* Other (Linux-defined) */
1065 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
1066 NULL, NULL, NULL, NULL,
1067 "constant_tsc", "up", NULL, "arch_perfmon",
1068 "pebs", "bts", NULL, "sync_rdtsc",
1069 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1070 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1071
1072 /* Intel-defined (#2) */
1073 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
1074 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
1075 NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt",
1076 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1077
1078 /* VIA/Cyrix/Centaur-defined */
1079 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1080 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
1081 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1082 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1083
1084 /* AMD-defined (#2) */
1085 "lahf_lm", "cmp_legacy", "svm", "extapic",
1086 "cr8_legacy", "abm", "sse4a", "misalignsse",
1087 "3dnowprefetch", "osvw", "ibs", "sse5",
1088 "skinit", "wdt", NULL, NULL,
1089 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1090 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1091
1092 /* Auxiliary (Linux-defined) */
1093 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1094 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1095 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1096 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1097 };
1098 static const char *const x86_power_flags[] = {
1099 "ts", /* temperature sensor */
1100 "fid", /* frequency id control */
1101 "vid", /* voltage id control */
1102 "ttp", /* thermal trip */
1103 "tm",
1104 "stc",
1105 "100mhzsteps",
1106 "hwpstate",
1107 "", /* tsc invariant mapped to constant_tsc */
1108 /* nothing */
1109 };
1110
1111
1112 #ifdef CONFIG_SMP
1113 cpu = c->cpu_index;
1114 #endif
1115
1116 seq_printf(m, "processor\t: %u\n"
1117 "vendor_id\t: %s\n"
1118 "cpu family\t: %d\n"
1119 "model\t\t: %d\n"
1120 "model name\t: %s\n",
1121 (unsigned)cpu,
1122 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1123 c->x86,
1124 (int)c->x86_model,
1125 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1126
1127 if (c->x86_mask || c->cpuid_level >= 0)
1128 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1129 else
1130 seq_printf(m, "stepping\t: unknown\n");
1131
1132 if (cpu_has(c, X86_FEATURE_TSC)) {
1133 unsigned int freq = cpufreq_quick_get((unsigned)cpu);
1134
1135 if (!freq)
1136 freq = cpu_khz;
1137 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1138 freq / 1000, (freq % 1000));
1139 }
1140
1141 /* Cache size */
1142 if (c->x86_cache_size >= 0)
1143 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1144
1145 #ifdef CONFIG_SMP
1146 if (smp_num_siblings * c->x86_max_cores > 1) {
1147 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1148 seq_printf(m, "siblings\t: %d\n",
1149 cpus_weight(per_cpu(cpu_core_map, cpu)));
1150 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1151 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1152 }
1153 #endif
1154
1155 seq_printf(m,
1156 "fpu\t\t: yes\n"
1157 "fpu_exception\t: yes\n"
1158 "cpuid level\t: %d\n"
1159 "wp\t\t: yes\n"
1160 "flags\t\t:",
1161 c->cpuid_level);
1162
1163 for (i = 0; i < 32*NCAPINTS; i++)
1164 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1165 seq_printf(m, " %s", x86_cap_flags[i]);
1166
1167 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1168 c->loops_per_jiffy/(500000/HZ),
1169 (c->loops_per_jiffy/(5000/HZ)) % 100);
1170
1171 if (c->x86_tlbsize > 0)
1172 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1173 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1174 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1175
1176 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1177 c->x86_phys_bits, c->x86_virt_bits);
1178
1179 seq_printf(m, "power management:");
1180 for (i = 0; i < 32; i++) {
1181 if (c->x86_power & (1 << i)) {
1182 if (i < ARRAY_SIZE(x86_power_flags) &&
1183 x86_power_flags[i])
1184 seq_printf(m, "%s%s",
1185 x86_power_flags[i][0]?" ":"",
1186 x86_power_flags[i]);
1187 else
1188 seq_printf(m, " [%d]", i);
1189 }
1190 }
1191
1192 seq_printf(m, "\n\n");
1193
1194 return 0;
1195 }
1196
1197 static void *c_start(struct seq_file *m, loff_t *pos)
1198 {
1199 if (*pos == 0) /* just in case, cpu 0 is not the first */
1200 *pos = first_cpu(cpu_online_map);
1201 if ((*pos) < NR_CPUS && cpu_online(*pos))
1202 return &cpu_data(*pos);
1203 return NULL;
1204 }
1205
1206 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1207 {
1208 *pos = next_cpu(*pos, cpu_online_map);
1209 return c_start(m, pos);
1210 }
1211
1212 static void c_stop(struct seq_file *m, void *v)
1213 {
1214 }
1215
1216 struct seq_operations cpuinfo_op = {
1217 .start = c_start,
1218 .next = c_next,
1219 .stop = c_stop,
1220 .show = show_cpuinfo,
1221 };
kernel source for telekom puls (alcatel/mediatek)