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x86: clean up max_pfn_mapped usage - 64-bit
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / setup_64.c
1 /*
2 * Copyright (C) 1995 Linus Torvalds
3 */
4
5 /*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
12 #include <linux/mm.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/screen_info.h>
19 #include <linux/ioport.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/initrd.h>
23 #include <linux/highmem.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
26 #include <asm/processor.h>
27 #include <linux/console.h>
28 #include <linux/seq_file.h>
29 #include <linux/crash_dump.h>
30 #include <linux/root_dev.h>
31 #include <linux/pci.h>
32 #include <asm/pci-direct.h>
33 #include <linux/efi.h>
34 #include <linux/acpi.h>
35 #include <linux/kallsyms.h>
36 #include <linux/edd.h>
37 #include <linux/iscsi_ibft.h>
38 #include <linux/mmzone.h>
39 #include <linux/kexec.h>
40 #include <linux/cpufreq.h>
41 #include <linux/dmi.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/ctype.h>
44 #include <linux/sort.h>
45 #include <linux/uaccess.h>
46 #include <linux/init_ohci1394_dma.h>
47 #include <linux/kvm_para.h>
48
49 #include <asm/mtrr.h>
50 #include <asm/uaccess.h>
51 #include <asm/system.h>
52 #include <asm/vsyscall.h>
53 #include <asm/io.h>
54 #include <asm/smp.h>
55 #include <asm/msr.h>
56 #include <asm/desc.h>
57 #include <video/edid.h>
58 #include <asm/e820.h>
59 #include <asm/mpspec.h>
60 #include <asm/dma.h>
61 #include <asm/gart.h>
62 #include <asm/mpspec.h>
63 #include <asm/mmu_context.h>
64 #include <asm/proto.h>
65 #include <asm/setup.h>
66 #include <asm/numa.h>
67 #include <asm/sections.h>
68 #include <asm/dmi.h>
69 #include <asm/cacheflush.h>
70 #include <asm/mce.h>
71 #include <asm/ds.h>
72 #include <asm/topology.h>
73 #include <asm/trampoline.h>
74 #include <asm/pat.h>
75
76 #include <mach_apic.h>
77 #ifdef CONFIG_PARAVIRT
78 #include <asm/paravirt.h>
79 #else
80 #define ARCH_SETUP
81 #endif
82
83 /*
84 * Machine setup..
85 */
86
87 struct cpuinfo_x86 boot_cpu_data __read_mostly;
88 EXPORT_SYMBOL(boot_cpu_data);
89
90 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
91
92 unsigned long mmu_cr4_features;
93
94 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
95 int bootloader_type;
96
97 unsigned long saved_video_mode;
98
99 int force_mwait __cpuinitdata;
100
101 /*
102 * Early DMI memory
103 */
104 int dmi_alloc_index;
105 char dmi_alloc_data[DMI_MAX_DATA];
106
107 /*
108 * Setup options
109 */
110 struct screen_info screen_info;
111 EXPORT_SYMBOL(screen_info);
112 struct sys_desc_table_struct {
113 unsigned short length;
114 unsigned char table[0];
115 };
116
117 struct edid_info edid_info;
118 EXPORT_SYMBOL_GPL(edid_info);
119
120 extern int root_mountflags;
121
122 char __initdata command_line[COMMAND_LINE_SIZE];
123
124 static struct resource standard_io_resources[] = {
125 { .name = "dma1", .start = 0x00, .end = 0x1f,
126 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
127 { .name = "pic1", .start = 0x20, .end = 0x21,
128 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
129 { .name = "timer0", .start = 0x40, .end = 0x43,
130 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
131 { .name = "timer1", .start = 0x50, .end = 0x53,
132 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
133 { .name = "keyboard", .start = 0x60, .end = 0x60,
134 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
135 { .name = "keyboard", .start = 0x64, .end = 0x64,
136 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
137 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
138 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
139 { .name = "pic2", .start = 0xa0, .end = 0xa1,
140 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
141 { .name = "dma2", .start = 0xc0, .end = 0xdf,
142 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
143 { .name = "fpu", .start = 0xf0, .end = 0xff,
144 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
145 };
146
147 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
148
149 static struct resource data_resource = {
150 .name = "Kernel data",
151 .start = 0,
152 .end = 0,
153 .flags = IORESOURCE_RAM,
154 };
155 static struct resource code_resource = {
156 .name = "Kernel code",
157 .start = 0,
158 .end = 0,
159 .flags = IORESOURCE_RAM,
160 };
161 static struct resource bss_resource = {
162 .name = "Kernel bss",
163 .start = 0,
164 .end = 0,
165 .flags = IORESOURCE_RAM,
166 };
167
168 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
169
170 #ifdef CONFIG_PROC_VMCORE
171 /* elfcorehdr= specifies the location of elf core header
172 * stored by the crashed kernel. This option will be passed
173 * by kexec loader to the capture kernel.
174 */
175 static int __init setup_elfcorehdr(char *arg)
176 {
177 char *end;
178 if (!arg)
179 return -EINVAL;
180 elfcorehdr_addr = memparse(arg, &end);
181 return end > arg ? 0 : -EINVAL;
182 }
183 early_param("elfcorehdr", setup_elfcorehdr);
184 #endif
185
186 #ifndef CONFIG_NUMA
187 static void __init
188 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
189 {
190 unsigned long bootmap_size, bootmap;
191
192 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
193 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
194 PAGE_SIZE);
195 if (bootmap == -1L)
196 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
197 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
198 e820_register_active_regions(0, start_pfn, end_pfn);
199 free_bootmem_with_active_regions(0, end_pfn);
200 early_res_to_bootmem(0, end_pfn<<PAGE_SHIFT);
201 reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
202 }
203 #endif
204
205 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
206 struct edd edd;
207 #ifdef CONFIG_EDD_MODULE
208 EXPORT_SYMBOL(edd);
209 #endif
210 /**
211 * copy_edd() - Copy the BIOS EDD information
212 * from boot_params into a safe place.
213 *
214 */
215 static inline void copy_edd(void)
216 {
217 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
218 sizeof(edd.mbr_signature));
219 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
220 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
221 edd.edd_info_nr = boot_params.eddbuf_entries;
222 }
223 #else
224 static inline void copy_edd(void)
225 {
226 }
227 #endif
228
229 #ifdef CONFIG_KEXEC
230 static void __init reserve_crashkernel(void)
231 {
232 unsigned long long total_mem;
233 unsigned long long crash_size, crash_base;
234 int ret;
235
236 total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
237
238 ret = parse_crashkernel(boot_command_line, total_mem,
239 &crash_size, &crash_base);
240 if (ret == 0 && crash_size) {
241 if (crash_base <= 0) {
242 printk(KERN_INFO "crashkernel reservation failed - "
243 "you have to specify a base address\n");
244 return;
245 }
246
247 if (reserve_bootmem(crash_base, crash_size,
248 BOOTMEM_EXCLUSIVE) < 0) {
249 printk(KERN_INFO "crashkernel reservation failed - "
250 "memory is in use\n");
251 return;
252 }
253
254 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
255 "for crashkernel (System RAM: %ldMB)\n",
256 (unsigned long)(crash_size >> 20),
257 (unsigned long)(crash_base >> 20),
258 (unsigned long)(total_mem >> 20));
259 crashk_res.start = crash_base;
260 crashk_res.end = crash_base + crash_size - 1;
261 insert_resource(&iomem_resource, &crashk_res);
262 }
263 }
264 #else
265 static inline void __init reserve_crashkernel(void)
266 {}
267 #endif
268
269 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
270 void __attribute__((weak)) __init memory_setup(void)
271 {
272 machine_specific_memory_setup();
273 }
274
275 static void __init parse_setup_data(void)
276 {
277 struct setup_data *data;
278 unsigned long pa_data;
279
280 if (boot_params.hdr.version < 0x0209)
281 return;
282 pa_data = boot_params.hdr.setup_data;
283 while (pa_data) {
284 data = early_ioremap(pa_data, PAGE_SIZE);
285 switch (data->type) {
286 default:
287 break;
288 }
289 #ifndef CONFIG_DEBUG_BOOT_PARAMS
290 free_early(pa_data, pa_data+sizeof(*data)+data->len);
291 #endif
292 pa_data = data->next;
293 early_iounmap(data, PAGE_SIZE);
294 }
295 }
296
297 #ifdef CONFIG_PCI_MMCONFIG
298 extern void __cpuinit fam10h_check_enable_mmcfg(void);
299 extern void __init check_enable_amd_mmconf_dmi(void);
300 #else
301 void __cpuinit fam10h_check_enable_mmcfg(void)
302 {
303 }
304 void __init check_enable_amd_mmconf_dmi(void)
305 {
306 }
307 #endif
308
309 /*
310 * setup_arch - architecture-specific boot-time initializations
311 *
312 * Note: On x86_64, fixmaps are ready for use even before this is called.
313 */
314 void __init setup_arch(char **cmdline_p)
315 {
316 unsigned i;
317
318 printk(KERN_INFO "Command line: %s\n", boot_command_line);
319
320 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
321 screen_info = boot_params.screen_info;
322 edid_info = boot_params.edid_info;
323 saved_video_mode = boot_params.hdr.vid_mode;
324 bootloader_type = boot_params.hdr.type_of_loader;
325
326 #ifdef CONFIG_BLK_DEV_RAM
327 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
328 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
329 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
330 #endif
331 #ifdef CONFIG_EFI
332 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
333 "EL64", 4))
334 efi_enabled = 1;
335 #endif
336
337 ARCH_SETUP
338
339 memory_setup();
340 copy_edd();
341
342 if (!boot_params.hdr.root_flags)
343 root_mountflags &= ~MS_RDONLY;
344 init_mm.start_code = (unsigned long) &_text;
345 init_mm.end_code = (unsigned long) &_etext;
346 init_mm.end_data = (unsigned long) &_edata;
347 init_mm.brk = (unsigned long) &_end;
348
349 code_resource.start = virt_to_phys(&_text);
350 code_resource.end = virt_to_phys(&_etext)-1;
351 data_resource.start = virt_to_phys(&_etext);
352 data_resource.end = virt_to_phys(&_edata)-1;
353 bss_resource.start = virt_to_phys(&__bss_start);
354 bss_resource.end = virt_to_phys(&__bss_stop)-1;
355
356 early_identify_cpu(&boot_cpu_data);
357
358 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
359 *cmdline_p = command_line;
360
361 parse_setup_data();
362
363 parse_early_param();
364
365 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
366 if (init_ohci1394_dma_early)
367 init_ohci1394_dma_on_all_controllers();
368 #endif
369
370 finish_e820_parsing();
371
372 /* after parse_early_param, so could debug it */
373 insert_resource(&iomem_resource, &code_resource);
374 insert_resource(&iomem_resource, &data_resource);
375 insert_resource(&iomem_resource, &bss_resource);
376
377 early_gart_iommu_check();
378
379 e820_register_active_regions(0, 0, -1UL);
380 /*
381 * partially used pages are not usable - thus
382 * we are rounding upwards:
383 */
384 end_pfn = e820_end_of_ram();
385
386 /* pre allocte 4k for mptable mpc */
387 early_reserve_e820_mpc_new();
388 /* update e820 for memory not covered by WB MTRRs */
389 mtrr_bp_init();
390 if (mtrr_trim_uncached_memory(end_pfn)) {
391 e820_register_active_regions(0, 0, -1UL);
392 end_pfn = e820_end_of_ram();
393 }
394
395 num_physpages = end_pfn;
396
397 check_efer();
398
399 max_pfn_mapped = init_memory_mapping(0, (end_pfn << PAGE_SHIFT));
400 if (efi_enabled)
401 efi_init();
402
403 vsmp_init();
404
405 dmi_scan_machine();
406
407 io_delay_init();
408
409 #ifdef CONFIG_KVM_CLOCK
410 kvmclock_init();
411 #endif
412
413 #ifdef CONFIG_SMP
414 /* setup to use the early static init tables during kernel startup */
415 x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
416 x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
417 #ifdef CONFIG_NUMA
418 x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
419 #endif
420 #endif
421
422 #ifdef CONFIG_ACPI
423 /*
424 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
425 * Call this early for SRAT node setup.
426 */
427 acpi_boot_table_init();
428 #endif
429
430 /* How many end-of-memory variables you have, grandma! */
431 max_low_pfn = end_pfn;
432 max_pfn = end_pfn;
433 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
434
435 /* Remove active ranges so rediscovery with NUMA-awareness happens */
436 remove_all_active_ranges();
437
438 #ifdef CONFIG_ACPI_NUMA
439 /*
440 * Parse SRAT to discover nodes.
441 */
442 acpi_numa_init();
443 #endif
444
445 #ifdef CONFIG_NUMA
446 numa_initmem_init(0, end_pfn);
447 #else
448 contig_initmem_init(0, end_pfn);
449 #endif
450
451 dma32_reserve_bootmem();
452
453 #ifdef CONFIG_ACPI_SLEEP
454 /*
455 * Reserve low memory region for sleep support.
456 */
457 acpi_reserve_bootmem();
458 #endif
459
460 if (efi_enabled)
461 efi_reserve_bootmem();
462
463 #ifdef CONFIG_X86_MPPARSE
464 /*
465 * Find and reserve possible boot-time SMP configuration:
466 */
467 find_smp_config();
468 #endif
469 #ifdef CONFIG_BLK_DEV_INITRD
470 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
471 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
472 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
473 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
474 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
475
476 if (ramdisk_end <= end_of_mem) {
477 /*
478 * don't need to reserve again, already reserved early
479 * in x86_64_start_kernel, and early_res_to_bootmem
480 * convert that to reserved in bootmem
481 */
482 initrd_start = ramdisk_image + PAGE_OFFSET;
483 initrd_end = initrd_start+ramdisk_size;
484 } else {
485 free_bootmem(ramdisk_image, ramdisk_size);
486 printk(KERN_ERR "initrd extends beyond end of memory "
487 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
488 ramdisk_end, end_of_mem);
489 initrd_start = 0;
490 }
491 }
492 #endif
493 reserve_crashkernel();
494
495 reserve_ibft_region();
496
497 paging_init();
498 map_vsyscall();
499
500 early_quirks();
501
502 #ifdef CONFIG_ACPI
503 /*
504 * Read APIC and some other early information from ACPI tables.
505 */
506 acpi_boot_init();
507 #endif
508
509 init_cpu_to_node();
510
511 #ifdef CONFIG_X86_MPPARSE
512 /*
513 * get boot-time SMP configuration:
514 */
515 if (smp_found_config)
516 get_smp_config();
517 #endif
518 init_apic_mappings();
519 ioapic_init_mappings();
520
521 kvm_guest_init();
522
523 /*
524 * We trust e820 completely. No explicit ROM probing in memory.
525 */
526 e820_reserve_resources();
527 e820_mark_nosave_regions(end_pfn);
528
529 /* request I/O space for devices used on all i[345]86 PCs */
530 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
531 request_resource(&ioport_resource, &standard_io_resources[i]);
532
533 e820_setup_gap();
534
535 #ifdef CONFIG_VT
536 #if defined(CONFIG_VGA_CONSOLE)
537 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
538 conswitchp = &vga_con;
539 #elif defined(CONFIG_DUMMY_CONSOLE)
540 conswitchp = &dummy_con;
541 #endif
542 #endif
543
544 /* do this before identify_cpu for boot cpu */
545 check_enable_amd_mmconf_dmi();
546 }
547
548 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
549 {
550 unsigned int *v;
551
552 if (c->extended_cpuid_level < 0x80000004)
553 return 0;
554
555 v = (unsigned int *) c->x86_model_id;
556 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
557 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
558 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
559 c->x86_model_id[48] = 0;
560 return 1;
561 }
562
563
564 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
565 {
566 unsigned int n, dummy, eax, ebx, ecx, edx;
567
568 n = c->extended_cpuid_level;
569
570 if (n >= 0x80000005) {
571 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
572 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
573 "D cache %dK (%d bytes/line)\n",
574 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
575 c->x86_cache_size = (ecx>>24) + (edx>>24);
576 /* On K8 L1 TLB is inclusive, so don't count it */
577 c->x86_tlbsize = 0;
578 }
579
580 if (n >= 0x80000006) {
581 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
582 ecx = cpuid_ecx(0x80000006);
583 c->x86_cache_size = ecx >> 16;
584 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
585
586 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
587 c->x86_cache_size, ecx & 0xFF);
588 }
589 if (n >= 0x80000008) {
590 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
591 c->x86_virt_bits = (eax >> 8) & 0xff;
592 c->x86_phys_bits = eax & 0xff;
593 }
594 }
595
596 #ifdef CONFIG_NUMA
597 static int __cpuinit nearby_node(int apicid)
598 {
599 int i, node;
600
601 for (i = apicid - 1; i >= 0; i--) {
602 node = apicid_to_node[i];
603 if (node != NUMA_NO_NODE && node_online(node))
604 return node;
605 }
606 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
607 node = apicid_to_node[i];
608 if (node != NUMA_NO_NODE && node_online(node))
609 return node;
610 }
611 return first_node(node_online_map); /* Shouldn't happen */
612 }
613 #endif
614
615 /*
616 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
617 * Assumes number of cores is a power of two.
618 */
619 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
620 {
621 #ifdef CONFIG_SMP
622 unsigned bits;
623 #ifdef CONFIG_NUMA
624 int cpu = smp_processor_id();
625 int node = 0;
626 unsigned apicid = hard_smp_processor_id();
627 #endif
628 bits = c->x86_coreid_bits;
629
630 /* Low order bits define the core id (index of core in socket) */
631 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
632 /* Convert the initial APIC ID into the socket ID */
633 c->phys_proc_id = c->initial_apicid >> bits;
634
635 #ifdef CONFIG_NUMA
636 node = c->phys_proc_id;
637 if (apicid_to_node[apicid] != NUMA_NO_NODE)
638 node = apicid_to_node[apicid];
639 if (!node_online(node)) {
640 /* Two possibilities here:
641 - The CPU is missing memory and no node was created.
642 In that case try picking one from a nearby CPU
643 - The APIC IDs differ from the HyperTransport node IDs
644 which the K8 northbridge parsing fills in.
645 Assume they are all increased by a constant offset,
646 but in the same order as the HT nodeids.
647 If that doesn't result in a usable node fall back to the
648 path for the previous case. */
649
650 int ht_nodeid = c->initial_apicid;
651
652 if (ht_nodeid >= 0 &&
653 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
654 node = apicid_to_node[ht_nodeid];
655 /* Pick a nearby node */
656 if (!node_online(node))
657 node = nearby_node(apicid);
658 }
659 numa_set_node(cpu, node);
660
661 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
662 #endif
663 #endif
664 }
665
666 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
667 {
668 #ifdef CONFIG_SMP
669 unsigned bits, ecx;
670
671 /* Multi core CPU? */
672 if (c->extended_cpuid_level < 0x80000008)
673 return;
674
675 ecx = cpuid_ecx(0x80000008);
676
677 c->x86_max_cores = (ecx & 0xff) + 1;
678
679 /* CPU telling us the core id bits shift? */
680 bits = (ecx >> 12) & 0xF;
681
682 /* Otherwise recompute */
683 if (bits == 0) {
684 while ((1 << bits) < c->x86_max_cores)
685 bits++;
686 }
687
688 c->x86_coreid_bits = bits;
689
690 #endif
691 }
692
693 #define ENABLE_C1E_MASK 0x18000000
694 #define CPUID_PROCESSOR_SIGNATURE 1
695 #define CPUID_XFAM 0x0ff00000
696 #define CPUID_XFAM_K8 0x00000000
697 #define CPUID_XFAM_10H 0x00100000
698 #define CPUID_XFAM_11H 0x00200000
699 #define CPUID_XMOD 0x000f0000
700 #define CPUID_XMOD_REV_F 0x00040000
701
702 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
703 static __cpuinit int amd_apic_timer_broken(void)
704 {
705 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
706
707 switch (eax & CPUID_XFAM) {
708 case CPUID_XFAM_K8:
709 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
710 break;
711 case CPUID_XFAM_10H:
712 case CPUID_XFAM_11H:
713 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
714 if (lo & ENABLE_C1E_MASK)
715 return 1;
716 break;
717 default:
718 /* err on the side of caution */
719 return 1;
720 }
721 return 0;
722 }
723
724 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
725 {
726 early_init_amd_mc(c);
727
728 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
729 if (c->x86_power & (1<<8))
730 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
731 }
732
733 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
734 {
735 unsigned level;
736
737 #ifdef CONFIG_SMP
738 unsigned long value;
739
740 /*
741 * Disable TLB flush filter by setting HWCR.FFDIS on K8
742 * bit 6 of msr C001_0015
743 *
744 * Errata 63 for SH-B3 steppings
745 * Errata 122 for all steppings (F+ have it disabled by default)
746 */
747 if (c->x86 == 15) {
748 rdmsrl(MSR_K8_HWCR, value);
749 value |= 1 << 6;
750 wrmsrl(MSR_K8_HWCR, value);
751 }
752 #endif
753
754 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
755 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
756 clear_cpu_cap(c, 0*32+31);
757
758 /* On C+ stepping K8 rep microcode works well for copy/memset */
759 level = cpuid_eax(1);
760 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
761 level >= 0x0f58))
762 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
763 if (c->x86 == 0x10 || c->x86 == 0x11)
764 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
765
766 /* Enable workaround for FXSAVE leak */
767 if (c->x86 >= 6)
768 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
769
770 level = get_model_name(c);
771 if (!level) {
772 switch (c->x86) {
773 case 15:
774 /* Should distinguish Models here, but this is only
775 a fallback anyways. */
776 strcpy(c->x86_model_id, "Hammer");
777 break;
778 }
779 }
780 display_cacheinfo(c);
781
782 /* Multi core CPU? */
783 if (c->extended_cpuid_level >= 0x80000008)
784 amd_detect_cmp(c);
785
786 if (c->extended_cpuid_level >= 0x80000006 &&
787 (cpuid_edx(0x80000006) & 0xf000))
788 num_cache_leaves = 4;
789 else
790 num_cache_leaves = 3;
791
792 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
793 set_cpu_cap(c, X86_FEATURE_K8);
794
795 /* MFENCE stops RDTSC speculation */
796 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
797
798 if (c->x86 == 0x10)
799 fam10h_check_enable_mmcfg();
800
801 if (amd_apic_timer_broken())
802 disable_apic_timer = 1;
803
804 if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
805 unsigned long long tseg;
806
807 /*
808 * Split up direct mapping around the TSEG SMM area.
809 * Don't do it for gbpages because there seems very little
810 * benefit in doing so.
811 */
812 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
813 (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
814 set_memory_4k((unsigned long)__va(tseg), 1);
815 }
816 }
817
818 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
819 {
820 #ifdef CONFIG_SMP
821 u32 eax, ebx, ecx, edx;
822 int index_msb, core_bits;
823
824 cpuid(1, &eax, &ebx, &ecx, &edx);
825
826
827 if (!cpu_has(c, X86_FEATURE_HT))
828 return;
829 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
830 goto out;
831
832 smp_num_siblings = (ebx & 0xff0000) >> 16;
833
834 if (smp_num_siblings == 1) {
835 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
836 } else if (smp_num_siblings > 1) {
837
838 if (smp_num_siblings > NR_CPUS) {
839 printk(KERN_WARNING "CPU: Unsupported number of "
840 "siblings %d", smp_num_siblings);
841 smp_num_siblings = 1;
842 return;
843 }
844
845 index_msb = get_count_order(smp_num_siblings);
846 c->phys_proc_id = phys_pkg_id(index_msb);
847
848 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
849
850 index_msb = get_count_order(smp_num_siblings);
851
852 core_bits = get_count_order(c->x86_max_cores);
853
854 c->cpu_core_id = phys_pkg_id(index_msb) &
855 ((1 << core_bits) - 1);
856 }
857 out:
858 if ((c->x86_max_cores * smp_num_siblings) > 1) {
859 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
860 c->phys_proc_id);
861 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
862 c->cpu_core_id);
863 }
864
865 #endif
866 }
867
868 /*
869 * find out the number of processor cores on the die
870 */
871 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
872 {
873 unsigned int eax, t;
874
875 if (c->cpuid_level < 4)
876 return 1;
877
878 cpuid_count(4, 0, &eax, &t, &t, &t);
879
880 if (eax & 0x1f)
881 return ((eax >> 26) + 1);
882 else
883 return 1;
884 }
885
886 static void __cpuinit srat_detect_node(void)
887 {
888 #ifdef CONFIG_NUMA
889 unsigned node;
890 int cpu = smp_processor_id();
891 int apicid = hard_smp_processor_id();
892
893 /* Don't do the funky fallback heuristics the AMD version employs
894 for now. */
895 node = apicid_to_node[apicid];
896 if (node == NUMA_NO_NODE || !node_online(node))
897 node = first_node(node_online_map);
898 numa_set_node(cpu, node);
899
900 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
901 #endif
902 }
903
904 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
905 {
906 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
907 (c->x86 == 0x6 && c->x86_model >= 0x0e))
908 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
909 }
910
911 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
912 {
913 /* Cache sizes */
914 unsigned n;
915
916 init_intel_cacheinfo(c);
917 if (c->cpuid_level > 9) {
918 unsigned eax = cpuid_eax(10);
919 /* Check for version and the number of counters */
920 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
921 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
922 }
923
924 if (cpu_has_ds) {
925 unsigned int l1, l2;
926 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
927 if (!(l1 & (1<<11)))
928 set_cpu_cap(c, X86_FEATURE_BTS);
929 if (!(l1 & (1<<12)))
930 set_cpu_cap(c, X86_FEATURE_PEBS);
931 }
932
933
934 if (cpu_has_bts)
935 ds_init_intel(c);
936
937 n = c->extended_cpuid_level;
938 if (n >= 0x80000008) {
939 unsigned eax = cpuid_eax(0x80000008);
940 c->x86_virt_bits = (eax >> 8) & 0xff;
941 c->x86_phys_bits = eax & 0xff;
942 /* CPUID workaround for Intel 0F34 CPU */
943 if (c->x86_vendor == X86_VENDOR_INTEL &&
944 c->x86 == 0xF && c->x86_model == 0x3 &&
945 c->x86_mask == 0x4)
946 c->x86_phys_bits = 36;
947 }
948
949 if (c->x86 == 15)
950 c->x86_cache_alignment = c->x86_clflush_size * 2;
951 if (c->x86 == 6)
952 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
953 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
954 c->x86_max_cores = intel_num_cpu_cores(c);
955
956 srat_detect_node();
957 }
958
959 static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
960 {
961 if (c->x86 == 0x6 && c->x86_model >= 0xf)
962 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
963 }
964
965 static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
966 {
967 /* Cache sizes */
968 unsigned n;
969
970 n = c->extended_cpuid_level;
971 if (n >= 0x80000008) {
972 unsigned eax = cpuid_eax(0x80000008);
973 c->x86_virt_bits = (eax >> 8) & 0xff;
974 c->x86_phys_bits = eax & 0xff;
975 }
976
977 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
978 c->x86_cache_alignment = c->x86_clflush_size * 2;
979 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
980 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
981 }
982 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
983 }
984
985 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
986 {
987 char *v = c->x86_vendor_id;
988
989 if (!strcmp(v, "AuthenticAMD"))
990 c->x86_vendor = X86_VENDOR_AMD;
991 else if (!strcmp(v, "GenuineIntel"))
992 c->x86_vendor = X86_VENDOR_INTEL;
993 else if (!strcmp(v, "CentaurHauls"))
994 c->x86_vendor = X86_VENDOR_CENTAUR;
995 else
996 c->x86_vendor = X86_VENDOR_UNKNOWN;
997 }
998
999 /* Do some early cpuid on the boot CPU to get some parameter that are
1000 needed before check_bugs. Everything advanced is in identify_cpu
1001 below. */
1002 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
1003 {
1004 u32 tfms, xlvl;
1005
1006 c->loops_per_jiffy = loops_per_jiffy;
1007 c->x86_cache_size = -1;
1008 c->x86_vendor = X86_VENDOR_UNKNOWN;
1009 c->x86_model = c->x86_mask = 0; /* So far unknown... */
1010 c->x86_vendor_id[0] = '\0'; /* Unset */
1011 c->x86_model_id[0] = '\0'; /* Unset */
1012 c->x86_clflush_size = 64;
1013 c->x86_cache_alignment = c->x86_clflush_size;
1014 c->x86_max_cores = 1;
1015 c->x86_coreid_bits = 0;
1016 c->extended_cpuid_level = 0;
1017 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1018
1019 /* Get vendor name */
1020 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
1021 (unsigned int *)&c->x86_vendor_id[0],
1022 (unsigned int *)&c->x86_vendor_id[8],
1023 (unsigned int *)&c->x86_vendor_id[4]);
1024
1025 get_cpu_vendor(c);
1026
1027 /* Initialize the standard set of capabilities */
1028 /* Note that the vendor-specific code below might override */
1029
1030 /* Intel-defined flags: level 0x00000001 */
1031 if (c->cpuid_level >= 0x00000001) {
1032 __u32 misc;
1033 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
1034 &c->x86_capability[0]);
1035 c->x86 = (tfms >> 8) & 0xf;
1036 c->x86_model = (tfms >> 4) & 0xf;
1037 c->x86_mask = tfms & 0xf;
1038 if (c->x86 == 0xf)
1039 c->x86 += (tfms >> 20) & 0xff;
1040 if (c->x86 >= 0x6)
1041 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1042 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
1043 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1044 } else {
1045 /* Have CPUID level 0 only - unheard of */
1046 c->x86 = 4;
1047 }
1048
1049 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
1050 #ifdef CONFIG_SMP
1051 c->phys_proc_id = c->initial_apicid;
1052 #endif
1053 /* AMD-defined flags: level 0x80000001 */
1054 xlvl = cpuid_eax(0x80000000);
1055 c->extended_cpuid_level = xlvl;
1056 if ((xlvl & 0xffff0000) == 0x80000000) {
1057 if (xlvl >= 0x80000001) {
1058 c->x86_capability[1] = cpuid_edx(0x80000001);
1059 c->x86_capability[6] = cpuid_ecx(0x80000001);
1060 }
1061 if (xlvl >= 0x80000004)
1062 get_model_name(c); /* Default name */
1063 }
1064
1065 /* Transmeta-defined flags: level 0x80860001 */
1066 xlvl = cpuid_eax(0x80860000);
1067 if ((xlvl & 0xffff0000) == 0x80860000) {
1068 /* Don't set x86_cpuid_level here for now to not confuse. */
1069 if (xlvl >= 0x80860001)
1070 c->x86_capability[2] = cpuid_edx(0x80860001);
1071 }
1072
1073 c->extended_cpuid_level = cpuid_eax(0x80000000);
1074 if (c->extended_cpuid_level >= 0x80000007)
1075 c->x86_power = cpuid_edx(0x80000007);
1076
1077 switch (c->x86_vendor) {
1078 case X86_VENDOR_AMD:
1079 early_init_amd(c);
1080 break;
1081 case X86_VENDOR_INTEL:
1082 early_init_intel(c);
1083 break;
1084 case X86_VENDOR_CENTAUR:
1085 early_init_centaur(c);
1086 break;
1087 }
1088
1089 validate_pat_support(c);
1090 }
1091
1092 /*
1093 * This does the hard work of actually picking apart the CPU stuff...
1094 */
1095 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1096 {
1097 int i;
1098
1099 early_identify_cpu(c);
1100
1101 init_scattered_cpuid_features(c);
1102
1103 c->apicid = phys_pkg_id(0);
1104
1105 /*
1106 * Vendor-specific initialization. In this section we
1107 * canonicalize the feature flags, meaning if there are
1108 * features a certain CPU supports which CPUID doesn't
1109 * tell us, CPUID claiming incorrect flags, or other bugs,
1110 * we handle them here.
1111 *
1112 * At the end of this section, c->x86_capability better
1113 * indicate the features this CPU genuinely supports!
1114 */
1115 switch (c->x86_vendor) {
1116 case X86_VENDOR_AMD:
1117 init_amd(c);
1118 break;
1119
1120 case X86_VENDOR_INTEL:
1121 init_intel(c);
1122 break;
1123
1124 case X86_VENDOR_CENTAUR:
1125 init_centaur(c);
1126 break;
1127
1128 case X86_VENDOR_UNKNOWN:
1129 default:
1130 display_cacheinfo(c);
1131 break;
1132 }
1133
1134 detect_ht(c);
1135
1136 /*
1137 * On SMP, boot_cpu_data holds the common feature set between
1138 * all CPUs; so make sure that we indicate which features are
1139 * common between the CPUs. The first time this routine gets
1140 * executed, c == &boot_cpu_data.
1141 */
1142 if (c != &boot_cpu_data) {
1143 /* AND the already accumulated flags with these */
1144 for (i = 0; i < NCAPINTS; i++)
1145 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1146 }
1147
1148 /* Clear all flags overriden by options */
1149 for (i = 0; i < NCAPINTS; i++)
1150 c->x86_capability[i] &= ~cleared_cpu_caps[i];
1151
1152 #ifdef CONFIG_X86_MCE
1153 mcheck_init(c);
1154 #endif
1155 select_idle_routine(c);
1156
1157 #ifdef CONFIG_NUMA
1158 numa_add_cpu(smp_processor_id());
1159 #endif
1160
1161 }
1162
1163 void __cpuinit identify_boot_cpu(void)
1164 {
1165 identify_cpu(&boot_cpu_data);
1166 }
1167
1168 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1169 {
1170 BUG_ON(c == &boot_cpu_data);
1171 identify_cpu(c);
1172 mtrr_ap_init();
1173 }
1174
1175 static __init int setup_noclflush(char *arg)
1176 {
1177 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1178 return 1;
1179 }
1180 __setup("noclflush", setup_noclflush);
1181
1182 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1183 {
1184 if (c->x86_model_id[0])
1185 printk(KERN_CONT "%s", c->x86_model_id);
1186
1187 if (c->x86_mask || c->cpuid_level >= 0)
1188 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1189 else
1190 printk(KERN_CONT "\n");
1191 }
1192
1193 static __init int setup_disablecpuid(char *arg)
1194 {
1195 int bit;
1196 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1197 setup_clear_cpu_cap(bit);
1198 else
1199 return 0;
1200 return 1;
1201 }
1202 __setup("clearcpuid=", setup_disablecpuid);
kernel source for telekom puls (alcatel/mediatek)