arch/x86/kernel/irqinit.c

   1 #include <linux/linkage.h>
   2 #include <linux/errno.h>
   3 #include <linux/signal.h>
   4 #include <linux/sched.h>
   5 #include <linux/ioport.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/timex.h>
   8 #include <linux/slab.h>
   9 #include <linux/random.h>
  10 #include <linux/kprobes.h>
  11 #include <linux/init.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/sysdev.h>
  14 #include <linux/bitops.h>
  15 #include <linux/acpi.h>
  16 #include <linux/io.h>
  17 #include <linux/delay.h>
  18
  19 #include <asm/atomic.h>
  20 #include <asm/system.h>
  21 #include <asm/timer.h>
  22 #include <asm/hw_irq.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/desc.h>
  25 #include <asm/apic.h>
  26 #include <asm/setup.h>
  27 #include <asm/i8259.h>
  28 #include <asm/traps.h>
  29
  30 /*
  31  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  32  * (these are usually mapped to vectors 0x30-0x3f)
  33  */
  34
  35 /*
  36  * The IO-APIC gives us many more interrupt sources. Most of these
  37  * are unused but an SMP system is supposed to have enough memory ...
  38  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  39  * across the spectrum, so we really want to be prepared to get all
  40  * of these. Plus, more powerful systems might have more than 64
  41  * IO-APIC registers.
  42  *
  43  * (these are usually mapped into the 0x30-0xff vector range)
  44  */
  45
  46 #ifdef CONFIG_X86_32
  47 /*
  48  * Note that on a 486, we don't want to do a SIGFPE on an irq13
  49  * as the irq is unreliable, and exception 16 works correctly
  50  * (ie as explained in the intel literature). On a 386, you
  51  * can't use exception 16 due to bad IBM design, so we have to
  52  * rely on the less exact irq13.
  53  *
  54  * Careful.. Not only is IRQ13 unreliable, but it is also
  55  * leads to races. IBM designers who came up with it should
  56  * be shot.
  57  */
  58
  59 static irqreturn_t math_error_irq(int cpl, void *dev_id)
  60 {
  61         outb(0, 0xF0);
  62         if (ignore_fpu_irq || !boot_cpu_data.hard_math)
  63                 return IRQ_NONE;
  64         math_error((void __user *)get_irq_regs()->ip);
  65         return IRQ_HANDLED;
  66 }
  67
  68 /*
  69  * New motherboards sometimes make IRQ 13 be a PCI interrupt,
  70  * so allow interrupt sharing.
  71  */
  72 static struct irqaction fpu_irq = {
  73         .handler = math_error_irq,
  74         .name = "fpu",
  75 };
  76 #endif
  77
  78 /*
  79  * IRQ2 is cascade interrupt to second interrupt controller
  80  */
  81 static struct irqaction irq2 = {
  82         .handler = no_action,
  83         .name = "cascade",
  84 };
  85
  86 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
  87         [0 ... NR_VECTORS - 1] = -1,
  88 };
  89
  90 int vector_used_by_percpu_irq(unsigned int vector)
  91 {
  92         int cpu;
  93
  94         for_each_online_cpu(cpu) {
  95                 if (per_cpu(vector_irq, cpu)[vector] != -1)
  96                         return 1;
  97         }
  98
  99         return 0;
 100 }
 101
 102 void __init init_ISA_irqs(void)
 103 {
 104         int i;
 105
 106 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
 107         init_bsp_APIC();
 108 #endif
 109         legacy_pic->init(0);
 110
 111         /*
 112          * 16 old-style INTA-cycle interrupts:
 113          */
 114         for (i = 0; i < legacy_pic->nr_legacy_irqs; i++) {
 115                 struct irq_desc *desc = irq_to_desc(i);
 116
 117                 desc->status = IRQ_DISABLED;
 118                 desc->action = NULL;
 119                 desc->depth = 1;
 120
 121                 set_irq_chip_and_handler_name(i, &i8259A_chip,
 122                                               handle_level_irq, "XT");
 123         }
 124 }
 125
 126 void __init init_IRQ(void)
 127 {
 128         int i;
 129
 130         /*
 131          * On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15.
 132          * If these IRQ's are handled by legacy interrupt-controllers like PIC,
 133          * then this configuration will likely be static after the boot. If
 134          * these IRQ's are handled by more mordern controllers like IO-APIC,
 135          * then this vector space can be freed and re-used dynamically as the
 136          * irq's migrate etc.
 137          */
 138         for (i = 0; i < legacy_pic->nr_legacy_irqs; i++)
 139                 per_cpu(vector_irq, 0)[IRQ0_VECTOR + i] = i;
 140
 141         x86_init.irqs.intr_init();
 142 }
 143
 144 /*
 145  * Setup the vector to irq mappings.
 146  */
 147 void setup_vector_irq(int cpu)
 148 {
 149 #ifndef CONFIG_X86_IO_APIC
 150         int irq;
 151
 152         /*
 153          * On most of the platforms, legacy PIC delivers the interrupts on the
 154          * boot cpu. But there are certain platforms where PIC interrupts are
 155          * delivered to multiple cpu's. If the legacy IRQ is handled by the
 156          * legacy PIC, for the new cpu that is coming online, setup the static
 157          * legacy vector to irq mapping:
 158          */
 159         for (irq = 0; irq < legacy_pic->nr_legacy_irqs; irq++)
 160                 per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq;
 161 #endif
 162
 163         __setup_vector_irq(cpu);
 164 }
 165
 166 static void __init smp_intr_init(void)
 167 {
 168 #ifdef CONFIG_SMP
 169 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
 170         /*
 171          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 172          * IPI, driven by wakeup.
 173          */
 174         alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 175
 176         /* IPIs for invalidation */
 177         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
 178         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
 179         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
 180         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
 181         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
 182         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
 183         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
 184         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
 185
 186         /* IPI for generic function call */
 187         alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 188
 189         /* IPI for generic single function call */
 190         alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
 191                         call_function_single_interrupt);
 192
 193         /* Low priority IPI to cleanup after moving an irq */
 194         set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
 195         set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
 196
 197         /* IPI used for rebooting/stopping */
 198         alloc_intr_gate(REBOOT_VECTOR, reboot_interrupt);
 199 #endif
 200 #endif /* CONFIG_SMP */
 201 }
 202
 203 static void __init apic_intr_init(void)
 204 {
 205         smp_intr_init();
 206
 207 #ifdef CONFIG_X86_THERMAL_VECTOR
 208         alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 209 #endif
 210 #ifdef CONFIG_X86_MCE_THRESHOLD
 211         alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
 212 #endif
 213 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_LOCAL_APIC)
 214         alloc_intr_gate(MCE_SELF_VECTOR, mce_self_interrupt);
 215 #endif
 216
 217 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
 218         /* self generated IPI for local APIC timer */
 219         alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 220
 221         /* IPI for X86 platform specific use */
 222         alloc_intr_gate(X86_PLATFORM_IPI_VECTOR, x86_platform_ipi);
 223
 224         /* IPI vectors for APIC spurious and error interrupts */
 225         alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 226         alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 227
 228         /* Performance monitoring interrupts: */
 229 # ifdef CONFIG_PERF_EVENTS
 230         alloc_intr_gate(LOCAL_PENDING_VECTOR, perf_pending_interrupt);
 231 # endif
 232
 233 #endif
 234 }
 235
 236 void __init native_init_IRQ(void)
 237 {
 238         int i;
 239
 240         /* Execute any quirks before the call gates are initialised: */
 241         x86_init.irqs.pre_vector_init();
 242
 243         apic_intr_init();
 244
 245         /*
 246          * Cover the whole vector space, no vector can escape
 247          * us. (some of these will be overridden and become
 248          * 'special' SMP interrupts)
 249          */
 250         for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
 251                 /* IA32_SYSCALL_VECTOR could be used in trap_init already. */
 252                 if (!test_bit(i, used_vectors))
 253                         set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
 254         }
 255
 256         if (!acpi_ioapic)
 257                 setup_irq(2, &irq2);
 258
 259 #ifdef CONFIG_X86_32
 260         /*
 261          * External FPU? Set up irq13 if so, for
 262          * original braindamaged IBM FERR coupling.
 263          */
 264         if (boot_cpu_data.hard_math && !cpu_has_fpu)
 265                 setup_irq(FPU_IRQ, &fpu_irq);
 266
 267         irq_ctx_init(smp_processor_id());
 268 #endif
 269 }