1 #include <linux/linkage.h>
2 #include <linux/errno.h>
3 #include <linux/signal.h>
4 #include <linux/sched.h>
5 #include <linux/ioport.h>
6 #include <linux/interrupt.h>
7 #include <linux/timex.h>
8 #include <linux/slab.h>
9 #include <linux/random.h>
10 #include <linux/kprobes.h>
11 #include <linux/init.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/sysdev.h>
14 #include <linux/bitops.h>
15 #include <linux/acpi.h>
17 #include <linux/delay.h>
19 #include <asm/atomic.h>
20 #include <asm/system.h>
21 #include <asm/timer.h>
22 #include <asm/hw_irq.h>
23 #include <asm/pgtable.h>
26 #include <asm/setup.h>
27 #include <asm/i8259.h>
28 #include <asm/traps.h>
31 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
32 * (these are usually mapped to vectors 0x30-0x3f)
36 * The IO-APIC gives us many more interrupt sources. Most of these
37 * are unused but an SMP system is supposed to have enough memory ...
38 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
39 * across the spectrum, so we really want to be prepared to get all
40 * of these. Plus, more powerful systems might have more than 64
43 * (these are usually mapped into the 0x30-0xff vector range)
48 * Note that on a 486, we don't want to do a SIGFPE on an irq13
49 * as the irq is unreliable, and exception 16 works correctly
50 * (ie as explained in the intel literature). On a 386, you
51 * can't use exception 16 due to bad IBM design, so we have to
52 * rely on the less exact irq13.
54 * Careful.. Not only is IRQ13 unreliable, but it is also
55 * leads to races. IBM designers who came up with it should
59 static irqreturn_t
math_error_irq(int cpl
, void *dev_id
)
62 if (ignore_fpu_irq
|| !boot_cpu_data
.hard_math
)
64 math_error((void __user
*)get_irq_regs()->ip
);
69 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
70 * so allow interrupt sharing.
72 static struct irqaction fpu_irq
= {
73 .handler
= math_error_irq
,
79 * IRQ2 is cascade interrupt to second interrupt controller
81 static struct irqaction irq2
= {
86 DEFINE_PER_CPU(vector_irq_t
, vector_irq
) = {
87 [0 ... NR_VECTORS
- 1] = -1,
90 int vector_used_by_percpu_irq(unsigned int vector
)
94 for_each_online_cpu(cpu
) {
95 if (per_cpu(vector_irq
, cpu
)[vector
] != -1)
102 void __init
init_ISA_irqs(void)
106 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
112 * 16 old-style INTA-cycle interrupts:
114 for (i
= 0; i
< legacy_pic
->nr_legacy_irqs
; i
++) {
115 struct irq_desc
*desc
= irq_to_desc(i
);
117 desc
->status
= IRQ_DISABLED
;
121 set_irq_chip_and_handler_name(i
, &i8259A_chip
,
122 handle_level_irq
, "XT");
126 void __init
init_IRQ(void)
131 * On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15.
132 * If these IRQ's are handled by legacy interrupt-controllers like PIC,
133 * then this configuration will likely be static after the boot. If
134 * these IRQ's are handled by more mordern controllers like IO-APIC,
135 * then this vector space can be freed and re-used dynamically as the
138 for (i
= 0; i
< legacy_pic
->nr_legacy_irqs
; i
++)
139 per_cpu(vector_irq
, 0)[IRQ0_VECTOR
+ i
] = i
;
141 x86_init
.irqs
.intr_init();
144 static void __init
smp_intr_init(void)
147 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
149 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
150 * IPI, driven by wakeup.
152 alloc_intr_gate(RESCHEDULE_VECTOR
, reschedule_interrupt
);
154 /* IPIs for invalidation */
155 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+0, invalidate_interrupt0
);
156 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+1, invalidate_interrupt1
);
157 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+2, invalidate_interrupt2
);
158 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+3, invalidate_interrupt3
);
159 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+4, invalidate_interrupt4
);
160 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+5, invalidate_interrupt5
);
161 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+6, invalidate_interrupt6
);
162 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+7, invalidate_interrupt7
);
164 /* IPI for generic function call */
165 alloc_intr_gate(CALL_FUNCTION_VECTOR
, call_function_interrupt
);
167 /* IPI for generic single function call */
168 alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR
,
169 call_function_single_interrupt
);
171 /* Low priority IPI to cleanup after moving an irq */
172 set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR
, irq_move_cleanup_interrupt
);
173 set_bit(IRQ_MOVE_CLEANUP_VECTOR
, used_vectors
);
175 /* IPI used for rebooting/stopping */
176 alloc_intr_gate(REBOOT_VECTOR
, reboot_interrupt
);
178 #endif /* CONFIG_SMP */
181 static void __init
apic_intr_init(void)
185 #ifdef CONFIG_X86_THERMAL_VECTOR
186 alloc_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
188 #ifdef CONFIG_X86_MCE_THRESHOLD
189 alloc_intr_gate(THRESHOLD_APIC_VECTOR
, threshold_interrupt
);
191 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_LOCAL_APIC)
192 alloc_intr_gate(MCE_SELF_VECTOR
, mce_self_interrupt
);
195 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
196 /* self generated IPI for local APIC timer */
197 alloc_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
199 /* IPI for X86 platform specific use */
200 alloc_intr_gate(X86_PLATFORM_IPI_VECTOR
, x86_platform_ipi
);
202 /* IPI vectors for APIC spurious and error interrupts */
203 alloc_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
204 alloc_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
206 /* Performance monitoring interrupts: */
207 # ifdef CONFIG_PERF_EVENTS
208 alloc_intr_gate(LOCAL_PENDING_VECTOR
, perf_pending_interrupt
);
214 void __init
native_init_IRQ(void)
218 /* Execute any quirks before the call gates are initialised: */
219 x86_init
.irqs
.pre_vector_init();
224 * Cover the whole vector space, no vector can escape
225 * us. (some of these will be overridden and become
226 * 'special' SMP interrupts)
228 for (i
= FIRST_EXTERNAL_VECTOR
; i
< NR_VECTORS
; i
++) {
229 /* IA32_SYSCALL_VECTOR could be used in trap_init already. */
230 if (!test_bit(i
, used_vectors
))
231 set_intr_gate(i
, interrupt
[i
-FIRST_EXTERNAL_VECTOR
]);
239 * External FPU? Set up irq13 if so, for
240 * original braindamaged IBM FERR coupling.
242 if (boot_cpu_data
.hard_math
&& !cpu_has_fpu
)
243 setup_irq(FPU_IRQ
, &fpu_irq
);
245 irq_ctx_init(smp_processor_id());