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[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / arch / x86 / kernel / io_apic_64.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #ifdef CONFIG_ACPI
35 #include <acpi/acpi_bus.h>
36 #endif
37
38 #include <asm/idle.h>
39 #include <asm/io.h>
40 #include <asm/smp.h>
41 #include <asm/desc.h>
42 #include <asm/proto.h>
43 #include <asm/mach_apic.h>
44 #include <asm/acpi.h>
45 #include <asm/dma.h>
46 #include <asm/nmi.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49
50 struct irq_cfg {
51 cpumask_t domain;
52 cpumask_t old_domain;
53 unsigned move_cleanup_count;
54 u8 vector;
55 u8 move_in_progress : 1;
56 };
57
58 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
59 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
60 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
61 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
62 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
63 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
64 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
65 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
66 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
67 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
68 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
69 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
70 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
71 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
72 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
73 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
74 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
75 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
76 };
77
78 static int assign_irq_vector(int irq, cpumask_t mask);
79
80 #define __apicdebuginit __init
81
82 int sis_apic_bug; /* not actually supported, dummy for compile */
83
84 static int no_timer_check;
85
86 static int disable_timer_pin_1 __initdata;
87
88 int timer_over_8254 __initdata = 1;
89
90 /* Where if anywhere is the i8259 connect in external int mode */
91 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
92
93 static DEFINE_SPINLOCK(ioapic_lock);
94 DEFINE_SPINLOCK(vector_lock);
95
96 /*
97 * # of IRQ routing registers
98 */
99 int nr_ioapic_registers[MAX_IO_APICS];
100
101 /*
102 * Rough estimation of how many shared IRQs there are, can
103 * be changed anytime.
104 */
105 #define MAX_PLUS_SHARED_IRQS NR_IRQS
106 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
107
108 /*
109 * This is performance-critical, we want to do it O(1)
110 *
111 * the indexing order of this array favors 1:1 mappings
112 * between pins and IRQs.
113 */
114
115 static struct irq_pin_list {
116 short apic, pin, next;
117 } irq_2_pin[PIN_MAP_SIZE];
118
119 struct io_apic {
120 unsigned int index;
121 unsigned int unused[3];
122 unsigned int data;
123 };
124
125 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
126 {
127 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
128 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
129 }
130
131 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
132 {
133 struct io_apic __iomem *io_apic = io_apic_base(apic);
134 writel(reg, &io_apic->index);
135 return readl(&io_apic->data);
136 }
137
138 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
139 {
140 struct io_apic __iomem *io_apic = io_apic_base(apic);
141 writel(reg, &io_apic->index);
142 writel(value, &io_apic->data);
143 }
144
145 /*
146 * Re-write a value: to be used for read-modify-write
147 * cycles where the read already set up the index register.
148 */
149 static inline void io_apic_modify(unsigned int apic, unsigned int value)
150 {
151 struct io_apic __iomem *io_apic = io_apic_base(apic);
152 writel(value, &io_apic->data);
153 }
154
155 static int io_apic_level_ack_pending(unsigned int irq)
156 {
157 struct irq_pin_list *entry;
158 unsigned long flags;
159 int pending = 0;
160
161 spin_lock_irqsave(&ioapic_lock, flags);
162 entry = irq_2_pin + irq;
163 for (;;) {
164 unsigned int reg;
165 int pin;
166
167 pin = entry->pin;
168 if (pin == -1)
169 break;
170 reg = io_apic_read(entry->apic, 0x10 + pin*2);
171 /* Is the remote IRR bit set? */
172 pending |= (reg >> 14) & 1;
173 if (!entry->next)
174 break;
175 entry = irq_2_pin + entry->next;
176 }
177 spin_unlock_irqrestore(&ioapic_lock, flags);
178 return pending;
179 }
180
181 /*
182 * Synchronize the IO-APIC and the CPU by doing
183 * a dummy read from the IO-APIC
184 */
185 static inline void io_apic_sync(unsigned int apic)
186 {
187 struct io_apic __iomem *io_apic = io_apic_base(apic);
188 readl(&io_apic->data);
189 }
190
191 #define __DO_ACTION(R, ACTION, FINAL) \
192 \
193 { \
194 int pin; \
195 struct irq_pin_list *entry = irq_2_pin + irq; \
196 \
197 BUG_ON(irq >= NR_IRQS); \
198 for (;;) { \
199 unsigned int reg; \
200 pin = entry->pin; \
201 if (pin == -1) \
202 break; \
203 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
204 reg ACTION; \
205 io_apic_modify(entry->apic, reg); \
206 FINAL; \
207 if (!entry->next) \
208 break; \
209 entry = irq_2_pin + entry->next; \
210 } \
211 }
212
213 union entry_union {
214 struct { u32 w1, w2; };
215 struct IO_APIC_route_entry entry;
216 };
217
218 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
219 {
220 union entry_union eu;
221 unsigned long flags;
222 spin_lock_irqsave(&ioapic_lock, flags);
223 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
224 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
225 spin_unlock_irqrestore(&ioapic_lock, flags);
226 return eu.entry;
227 }
228
229 /*
230 * When we write a new IO APIC routing entry, we need to write the high
231 * word first! If the mask bit in the low word is clear, we will enable
232 * the interrupt, and we need to make sure the entry is fully populated
233 * before that happens.
234 */
235 static void
236 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
237 {
238 union entry_union eu;
239 eu.entry = e;
240 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
241 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
242 }
243
244 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
245 {
246 unsigned long flags;
247 spin_lock_irqsave(&ioapic_lock, flags);
248 __ioapic_write_entry(apic, pin, e);
249 spin_unlock_irqrestore(&ioapic_lock, flags);
250 }
251
252 /*
253 * When we mask an IO APIC routing entry, we need to write the low
254 * word first, in order to set the mask bit before we change the
255 * high bits!
256 */
257 static void ioapic_mask_entry(int apic, int pin)
258 {
259 unsigned long flags;
260 union entry_union eu = { .entry.mask = 1 };
261
262 spin_lock_irqsave(&ioapic_lock, flags);
263 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
264 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
265 spin_unlock_irqrestore(&ioapic_lock, flags);
266 }
267
268 #ifdef CONFIG_SMP
269 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
270 {
271 int apic, pin;
272 struct irq_pin_list *entry = irq_2_pin + irq;
273
274 BUG_ON(irq >= NR_IRQS);
275 for (;;) {
276 unsigned int reg;
277 apic = entry->apic;
278 pin = entry->pin;
279 if (pin == -1)
280 break;
281 io_apic_write(apic, 0x11 + pin*2, dest);
282 reg = io_apic_read(apic, 0x10 + pin*2);
283 reg &= ~0x000000ff;
284 reg |= vector;
285 io_apic_modify(apic, reg);
286 if (!entry->next)
287 break;
288 entry = irq_2_pin + entry->next;
289 }
290 }
291
292 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
293 {
294 struct irq_cfg *cfg = irq_cfg + irq;
295 unsigned long flags;
296 unsigned int dest;
297 cpumask_t tmp;
298
299 cpus_and(tmp, mask, cpu_online_map);
300 if (cpus_empty(tmp))
301 return;
302
303 if (assign_irq_vector(irq, mask))
304 return;
305
306 cpus_and(tmp, cfg->domain, mask);
307 dest = cpu_mask_to_apicid(tmp);
308
309 /*
310 * Only the high 8 bits are valid.
311 */
312 dest = SET_APIC_LOGICAL_ID(dest);
313
314 spin_lock_irqsave(&ioapic_lock, flags);
315 __target_IO_APIC_irq(irq, dest, cfg->vector);
316 irq_desc[irq].affinity = mask;
317 spin_unlock_irqrestore(&ioapic_lock, flags);
318 }
319 #endif
320
321 /*
322 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
323 * shared ISA-space IRQs, so we have to support them. We are super
324 * fast in the common case, and fast for shared ISA-space IRQs.
325 */
326 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
327 {
328 static int first_free_entry = NR_IRQS;
329 struct irq_pin_list *entry = irq_2_pin + irq;
330
331 BUG_ON(irq >= NR_IRQS);
332 while (entry->next)
333 entry = irq_2_pin + entry->next;
334
335 if (entry->pin != -1) {
336 entry->next = first_free_entry;
337 entry = irq_2_pin + entry->next;
338 if (++first_free_entry >= PIN_MAP_SIZE)
339 panic("io_apic.c: ran out of irq_2_pin entries!");
340 }
341 entry->apic = apic;
342 entry->pin = pin;
343 }
344
345
346 #define DO_ACTION(name,R,ACTION, FINAL) \
347 \
348 static void name##_IO_APIC_irq (unsigned int irq) \
349 __DO_ACTION(R, ACTION, FINAL)
350
351 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
352 /* mask = 1 */
353 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
354 /* mask = 0 */
355
356 static void mask_IO_APIC_irq (unsigned int irq)
357 {
358 unsigned long flags;
359
360 spin_lock_irqsave(&ioapic_lock, flags);
361 __mask_IO_APIC_irq(irq);
362 spin_unlock_irqrestore(&ioapic_lock, flags);
363 }
364
365 static void unmask_IO_APIC_irq (unsigned int irq)
366 {
367 unsigned long flags;
368
369 spin_lock_irqsave(&ioapic_lock, flags);
370 __unmask_IO_APIC_irq(irq);
371 spin_unlock_irqrestore(&ioapic_lock, flags);
372 }
373
374 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
375 {
376 struct IO_APIC_route_entry entry;
377
378 /* Check delivery_mode to be sure we're not clearing an SMI pin */
379 entry = ioapic_read_entry(apic, pin);
380 if (entry.delivery_mode == dest_SMI)
381 return;
382 /*
383 * Disable it in the IO-APIC irq-routing table:
384 */
385 ioapic_mask_entry(apic, pin);
386 }
387
388 static void clear_IO_APIC (void)
389 {
390 int apic, pin;
391
392 for (apic = 0; apic < nr_ioapics; apic++)
393 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
394 clear_IO_APIC_pin(apic, pin);
395 }
396
397 int skip_ioapic_setup;
398 int ioapic_force;
399
400 static int __init parse_noapic(char *str)
401 {
402 disable_ioapic_setup();
403 return 0;
404 }
405 early_param("noapic", parse_noapic);
406
407 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
408 static int __init disable_timer_pin_setup(char *arg)
409 {
410 disable_timer_pin_1 = 1;
411 return 1;
412 }
413 __setup("disable_timer_pin_1", disable_timer_pin_setup);
414
415 static int __init setup_disable_8254_timer(char *s)
416 {
417 timer_over_8254 = -1;
418 return 1;
419 }
420 static int __init setup_enable_8254_timer(char *s)
421 {
422 timer_over_8254 = 2;
423 return 1;
424 }
425
426 __setup("disable_8254_timer", setup_disable_8254_timer);
427 __setup("enable_8254_timer", setup_enable_8254_timer);
428
429
430 /*
431 * Find the IRQ entry number of a certain pin.
432 */
433 static int find_irq_entry(int apic, int pin, int type)
434 {
435 int i;
436
437 for (i = 0; i < mp_irq_entries; i++)
438 if (mp_irqs[i].mpc_irqtype == type &&
439 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
440 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
441 mp_irqs[i].mpc_dstirq == pin)
442 return i;
443
444 return -1;
445 }
446
447 /*
448 * Find the pin to which IRQ[irq] (ISA) is connected
449 */
450 static int __init find_isa_irq_pin(int irq, int type)
451 {
452 int i;
453
454 for (i = 0; i < mp_irq_entries; i++) {
455 int lbus = mp_irqs[i].mpc_srcbus;
456
457 if (test_bit(lbus, mp_bus_not_pci) &&
458 (mp_irqs[i].mpc_irqtype == type) &&
459 (mp_irqs[i].mpc_srcbusirq == irq))
460
461 return mp_irqs[i].mpc_dstirq;
462 }
463 return -1;
464 }
465
466 static int __init find_isa_irq_apic(int irq, int type)
467 {
468 int i;
469
470 for (i = 0; i < mp_irq_entries; i++) {
471 int lbus = mp_irqs[i].mpc_srcbus;
472
473 if (test_bit(lbus, mp_bus_not_pci) &&
474 (mp_irqs[i].mpc_irqtype == type) &&
475 (mp_irqs[i].mpc_srcbusirq == irq))
476 break;
477 }
478 if (i < mp_irq_entries) {
479 int apic;
480 for(apic = 0; apic < nr_ioapics; apic++) {
481 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
482 return apic;
483 }
484 }
485
486 return -1;
487 }
488
489 /*
490 * Find a specific PCI IRQ entry.
491 * Not an __init, possibly needed by modules
492 */
493 static int pin_2_irq(int idx, int apic, int pin);
494
495 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
496 {
497 int apic, i, best_guess = -1;
498
499 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
500 bus, slot, pin);
501 if (mp_bus_id_to_pci_bus[bus] == -1) {
502 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
503 return -1;
504 }
505 for (i = 0; i < mp_irq_entries; i++) {
506 int lbus = mp_irqs[i].mpc_srcbus;
507
508 for (apic = 0; apic < nr_ioapics; apic++)
509 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
510 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
511 break;
512
513 if (!test_bit(lbus, mp_bus_not_pci) &&
514 !mp_irqs[i].mpc_irqtype &&
515 (bus == lbus) &&
516 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
517 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
518
519 if (!(apic || IO_APIC_IRQ(irq)))
520 continue;
521
522 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
523 return irq;
524 /*
525 * Use the first all-but-pin matching entry as a
526 * best-guess fuzzy result for broken mptables.
527 */
528 if (best_guess < 0)
529 best_guess = irq;
530 }
531 }
532 BUG_ON(best_guess >= NR_IRQS);
533 return best_guess;
534 }
535
536 /* ISA interrupts are always polarity zero edge triggered,
537 * when listed as conforming in the MP table. */
538
539 #define default_ISA_trigger(idx) (0)
540 #define default_ISA_polarity(idx) (0)
541
542 /* PCI interrupts are always polarity one level triggered,
543 * when listed as conforming in the MP table. */
544
545 #define default_PCI_trigger(idx) (1)
546 #define default_PCI_polarity(idx) (1)
547
548 static int __init MPBIOS_polarity(int idx)
549 {
550 int bus = mp_irqs[idx].mpc_srcbus;
551 int polarity;
552
553 /*
554 * Determine IRQ line polarity (high active or low active):
555 */
556 switch (mp_irqs[idx].mpc_irqflag & 3)
557 {
558 case 0: /* conforms, ie. bus-type dependent polarity */
559 if (test_bit(bus, mp_bus_not_pci))
560 polarity = default_ISA_polarity(idx);
561 else
562 polarity = default_PCI_polarity(idx);
563 break;
564 case 1: /* high active */
565 {
566 polarity = 0;
567 break;
568 }
569 case 2: /* reserved */
570 {
571 printk(KERN_WARNING "broken BIOS!!\n");
572 polarity = 1;
573 break;
574 }
575 case 3: /* low active */
576 {
577 polarity = 1;
578 break;
579 }
580 default: /* invalid */
581 {
582 printk(KERN_WARNING "broken BIOS!!\n");
583 polarity = 1;
584 break;
585 }
586 }
587 return polarity;
588 }
589
590 static int MPBIOS_trigger(int idx)
591 {
592 int bus = mp_irqs[idx].mpc_srcbus;
593 int trigger;
594
595 /*
596 * Determine IRQ trigger mode (edge or level sensitive):
597 */
598 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
599 {
600 case 0: /* conforms, ie. bus-type dependent */
601 if (test_bit(bus, mp_bus_not_pci))
602 trigger = default_ISA_trigger(idx);
603 else
604 trigger = default_PCI_trigger(idx);
605 break;
606 case 1: /* edge */
607 {
608 trigger = 0;
609 break;
610 }
611 case 2: /* reserved */
612 {
613 printk(KERN_WARNING "broken BIOS!!\n");
614 trigger = 1;
615 break;
616 }
617 case 3: /* level */
618 {
619 trigger = 1;
620 break;
621 }
622 default: /* invalid */
623 {
624 printk(KERN_WARNING "broken BIOS!!\n");
625 trigger = 0;
626 break;
627 }
628 }
629 return trigger;
630 }
631
632 static inline int irq_polarity(int idx)
633 {
634 return MPBIOS_polarity(idx);
635 }
636
637 static inline int irq_trigger(int idx)
638 {
639 return MPBIOS_trigger(idx);
640 }
641
642 static int pin_2_irq(int idx, int apic, int pin)
643 {
644 int irq, i;
645 int bus = mp_irqs[idx].mpc_srcbus;
646
647 /*
648 * Debugging check, we are in big trouble if this message pops up!
649 */
650 if (mp_irqs[idx].mpc_dstirq != pin)
651 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
652
653 if (test_bit(bus, mp_bus_not_pci)) {
654 irq = mp_irqs[idx].mpc_srcbusirq;
655 } else {
656 /*
657 * PCI IRQs are mapped in order
658 */
659 i = irq = 0;
660 while (i < apic)
661 irq += nr_ioapic_registers[i++];
662 irq += pin;
663 }
664 BUG_ON(irq >= NR_IRQS);
665 return irq;
666 }
667
668 static int __assign_irq_vector(int irq, cpumask_t mask)
669 {
670 /*
671 * NOTE! The local APIC isn't very good at handling
672 * multiple interrupts at the same interrupt level.
673 * As the interrupt level is determined by taking the
674 * vector number and shifting that right by 4, we
675 * want to spread these out a bit so that they don't
676 * all fall in the same interrupt level.
677 *
678 * Also, we've got to be careful not to trash gate
679 * 0x80, because int 0x80 is hm, kind of importantish. ;)
680 */
681 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
682 unsigned int old_vector;
683 int cpu;
684 struct irq_cfg *cfg;
685
686 BUG_ON((unsigned)irq >= NR_IRQS);
687 cfg = &irq_cfg[irq];
688
689 /* Only try and allocate irqs on cpus that are present */
690 cpus_and(mask, mask, cpu_online_map);
691
692 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
693 return -EBUSY;
694
695 old_vector = cfg->vector;
696 if (old_vector) {
697 cpumask_t tmp;
698 cpus_and(tmp, cfg->domain, mask);
699 if (!cpus_empty(tmp))
700 return 0;
701 }
702
703 for_each_cpu_mask(cpu, mask) {
704 cpumask_t domain, new_mask;
705 int new_cpu;
706 int vector, offset;
707
708 domain = vector_allocation_domain(cpu);
709 cpus_and(new_mask, domain, cpu_online_map);
710
711 vector = current_vector;
712 offset = current_offset;
713 next:
714 vector += 8;
715 if (vector >= FIRST_SYSTEM_VECTOR) {
716 /* If we run out of vectors on large boxen, must share them. */
717 offset = (offset + 1) % 8;
718 vector = FIRST_DEVICE_VECTOR + offset;
719 }
720 if (unlikely(current_vector == vector))
721 continue;
722 if (vector == IA32_SYSCALL_VECTOR)
723 goto next;
724 for_each_cpu_mask(new_cpu, new_mask)
725 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
726 goto next;
727 /* Found one! */
728 current_vector = vector;
729 current_offset = offset;
730 if (old_vector) {
731 cfg->move_in_progress = 1;
732 cfg->old_domain = cfg->domain;
733 }
734 for_each_cpu_mask(new_cpu, new_mask)
735 per_cpu(vector_irq, new_cpu)[vector] = irq;
736 cfg->vector = vector;
737 cfg->domain = domain;
738 return 0;
739 }
740 return -ENOSPC;
741 }
742
743 static int assign_irq_vector(int irq, cpumask_t mask)
744 {
745 int err;
746 unsigned long flags;
747
748 spin_lock_irqsave(&vector_lock, flags);
749 err = __assign_irq_vector(irq, mask);
750 spin_unlock_irqrestore(&vector_lock, flags);
751 return err;
752 }
753
754 static void __clear_irq_vector(int irq)
755 {
756 struct irq_cfg *cfg;
757 cpumask_t mask;
758 int cpu, vector;
759
760 BUG_ON((unsigned)irq >= NR_IRQS);
761 cfg = &irq_cfg[irq];
762 BUG_ON(!cfg->vector);
763
764 vector = cfg->vector;
765 cpus_and(mask, cfg->domain, cpu_online_map);
766 for_each_cpu_mask(cpu, mask)
767 per_cpu(vector_irq, cpu)[vector] = -1;
768
769 cfg->vector = 0;
770 cfg->domain = CPU_MASK_NONE;
771 }
772
773 void __setup_vector_irq(int cpu)
774 {
775 /* Initialize vector_irq on a new cpu */
776 /* This function must be called with vector_lock held */
777 int irq, vector;
778
779 /* Mark the inuse vectors */
780 for (irq = 0; irq < NR_IRQS; ++irq) {
781 if (!cpu_isset(cpu, irq_cfg[irq].domain))
782 continue;
783 vector = irq_cfg[irq].vector;
784 per_cpu(vector_irq, cpu)[vector] = irq;
785 }
786 /* Mark the free vectors */
787 for (vector = 0; vector < NR_VECTORS; ++vector) {
788 irq = per_cpu(vector_irq, cpu)[vector];
789 if (irq < 0)
790 continue;
791 if (!cpu_isset(cpu, irq_cfg[irq].domain))
792 per_cpu(vector_irq, cpu)[vector] = -1;
793 }
794 }
795
796
797 static struct irq_chip ioapic_chip;
798
799 static void ioapic_register_intr(int irq, unsigned long trigger)
800 {
801 if (trigger) {
802 irq_desc[irq].status |= IRQ_LEVEL;
803 set_irq_chip_and_handler_name(irq, &ioapic_chip,
804 handle_fasteoi_irq, "fasteoi");
805 } else {
806 irq_desc[irq].status &= ~IRQ_LEVEL;
807 set_irq_chip_and_handler_name(irq, &ioapic_chip,
808 handle_edge_irq, "edge");
809 }
810 }
811
812 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
813 int trigger, int polarity)
814 {
815 struct irq_cfg *cfg = irq_cfg + irq;
816 struct IO_APIC_route_entry entry;
817 cpumask_t mask;
818
819 if (!IO_APIC_IRQ(irq))
820 return;
821
822 mask = TARGET_CPUS;
823 if (assign_irq_vector(irq, mask))
824 return;
825
826 cpus_and(mask, cfg->domain, mask);
827
828 apic_printk(APIC_VERBOSE,KERN_DEBUG
829 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
830 "IRQ %d Mode:%i Active:%i)\n",
831 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
832 irq, trigger, polarity);
833
834 /*
835 * add it to the IO-APIC irq-routing table:
836 */
837 memset(&entry,0,sizeof(entry));
838
839 entry.delivery_mode = INT_DELIVERY_MODE;
840 entry.dest_mode = INT_DEST_MODE;
841 entry.dest = cpu_mask_to_apicid(mask);
842 entry.mask = 0; /* enable IRQ */
843 entry.trigger = trigger;
844 entry.polarity = polarity;
845 entry.vector = cfg->vector;
846
847 /* Mask level triggered irqs.
848 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
849 */
850 if (trigger)
851 entry.mask = 1;
852
853 ioapic_register_intr(irq, trigger);
854 if (irq < 16)
855 disable_8259A_irq(irq);
856
857 ioapic_write_entry(apic, pin, entry);
858 }
859
860 static void __init setup_IO_APIC_irqs(void)
861 {
862 int apic, pin, idx, irq, first_notcon = 1;
863
864 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
865
866 for (apic = 0; apic < nr_ioapics; apic++) {
867 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
868
869 idx = find_irq_entry(apic,pin,mp_INT);
870 if (idx == -1) {
871 if (first_notcon) {
872 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
873 first_notcon = 0;
874 } else
875 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
876 continue;
877 }
878 if (!first_notcon) {
879 apic_printk(APIC_VERBOSE, " not connected.\n");
880 first_notcon = 1;
881 }
882
883 irq = pin_2_irq(idx, apic, pin);
884 add_pin_to_irq(irq, apic, pin);
885
886 setup_IO_APIC_irq(apic, pin, irq,
887 irq_trigger(idx), irq_polarity(idx));
888 }
889 }
890
891 if (!first_notcon)
892 apic_printk(APIC_VERBOSE, " not connected.\n");
893 }
894
895 /*
896 * Set up the 8259A-master output pin as broadcast to all
897 * CPUs.
898 */
899 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
900 {
901 struct IO_APIC_route_entry entry;
902 unsigned long flags;
903
904 memset(&entry,0,sizeof(entry));
905
906 disable_8259A_irq(0);
907
908 /* mask LVT0 */
909 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
910
911 /*
912 * We use logical delivery to get the timer IRQ
913 * to the first CPU.
914 */
915 entry.dest_mode = INT_DEST_MODE;
916 entry.mask = 0; /* unmask IRQ now */
917 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
918 entry.delivery_mode = INT_DELIVERY_MODE;
919 entry.polarity = 0;
920 entry.trigger = 0;
921 entry.vector = vector;
922
923 /*
924 * The timer IRQ doesn't have to know that behind the
925 * scene we have a 8259A-master in AEOI mode ...
926 */
927 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
928
929 /*
930 * Add it to the IO-APIC irq-routing table:
931 */
932 spin_lock_irqsave(&ioapic_lock, flags);
933 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
934 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
935 spin_unlock_irqrestore(&ioapic_lock, flags);
936
937 enable_8259A_irq(0);
938 }
939
940 void __apicdebuginit print_IO_APIC(void)
941 {
942 int apic, i;
943 union IO_APIC_reg_00 reg_00;
944 union IO_APIC_reg_01 reg_01;
945 union IO_APIC_reg_02 reg_02;
946 unsigned long flags;
947
948 if (apic_verbosity == APIC_QUIET)
949 return;
950
951 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
952 for (i = 0; i < nr_ioapics; i++)
953 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
954 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
955
956 /*
957 * We are a bit conservative about what we expect. We have to
958 * know about every hardware change ASAP.
959 */
960 printk(KERN_INFO "testing the IO APIC.......................\n");
961
962 for (apic = 0; apic < nr_ioapics; apic++) {
963
964 spin_lock_irqsave(&ioapic_lock, flags);
965 reg_00.raw = io_apic_read(apic, 0);
966 reg_01.raw = io_apic_read(apic, 1);
967 if (reg_01.bits.version >= 0x10)
968 reg_02.raw = io_apic_read(apic, 2);
969 spin_unlock_irqrestore(&ioapic_lock, flags);
970
971 printk("\n");
972 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
973 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
974 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
975
976 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
977 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
978
979 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
980 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
981
982 if (reg_01.bits.version >= 0x10) {
983 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
984 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
985 }
986
987 printk(KERN_DEBUG ".... IRQ redirection table:\n");
988
989 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
990 " Stat Dmod Deli Vect: \n");
991
992 for (i = 0; i <= reg_01.bits.entries; i++) {
993 struct IO_APIC_route_entry entry;
994
995 entry = ioapic_read_entry(apic, i);
996
997 printk(KERN_DEBUG " %02x %03X ",
998 i,
999 entry.dest
1000 );
1001
1002 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1003 entry.mask,
1004 entry.trigger,
1005 entry.irr,
1006 entry.polarity,
1007 entry.delivery_status,
1008 entry.dest_mode,
1009 entry.delivery_mode,
1010 entry.vector
1011 );
1012 }
1013 }
1014 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1015 for (i = 0; i < NR_IRQS; i++) {
1016 struct irq_pin_list *entry = irq_2_pin + i;
1017 if (entry->pin < 0)
1018 continue;
1019 printk(KERN_DEBUG "IRQ%d ", i);
1020 for (;;) {
1021 printk("-> %d:%d", entry->apic, entry->pin);
1022 if (!entry->next)
1023 break;
1024 entry = irq_2_pin + entry->next;
1025 }
1026 printk("\n");
1027 }
1028
1029 printk(KERN_INFO ".................................... done.\n");
1030
1031 return;
1032 }
1033
1034 #if 0
1035
1036 static __apicdebuginit void print_APIC_bitfield (int base)
1037 {
1038 unsigned int v;
1039 int i, j;
1040
1041 if (apic_verbosity == APIC_QUIET)
1042 return;
1043
1044 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1045 for (i = 0; i < 8; i++) {
1046 v = apic_read(base + i*0x10);
1047 for (j = 0; j < 32; j++) {
1048 if (v & (1<<j))
1049 printk("1");
1050 else
1051 printk("0");
1052 }
1053 printk("\n");
1054 }
1055 }
1056
1057 void __apicdebuginit print_local_APIC(void * dummy)
1058 {
1059 unsigned int v, ver, maxlvt;
1060
1061 if (apic_verbosity == APIC_QUIET)
1062 return;
1063
1064 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1065 smp_processor_id(), hard_smp_processor_id());
1066 v = apic_read(APIC_ID);
1067 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1068 v = apic_read(APIC_LVR);
1069 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1070 ver = GET_APIC_VERSION(v);
1071 maxlvt = get_maxlvt();
1072
1073 v = apic_read(APIC_TASKPRI);
1074 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1075
1076 v = apic_read(APIC_ARBPRI);
1077 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1078 v & APIC_ARBPRI_MASK);
1079 v = apic_read(APIC_PROCPRI);
1080 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1081
1082 v = apic_read(APIC_EOI);
1083 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1084 v = apic_read(APIC_RRR);
1085 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1086 v = apic_read(APIC_LDR);
1087 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1088 v = apic_read(APIC_DFR);
1089 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1090 v = apic_read(APIC_SPIV);
1091 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1092
1093 printk(KERN_DEBUG "... APIC ISR field:\n");
1094 print_APIC_bitfield(APIC_ISR);
1095 printk(KERN_DEBUG "... APIC TMR field:\n");
1096 print_APIC_bitfield(APIC_TMR);
1097 printk(KERN_DEBUG "... APIC IRR field:\n");
1098 print_APIC_bitfield(APIC_IRR);
1099
1100 v = apic_read(APIC_ESR);
1101 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1102
1103 v = apic_read(APIC_ICR);
1104 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1105 v = apic_read(APIC_ICR2);
1106 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1107
1108 v = apic_read(APIC_LVTT);
1109 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1110
1111 if (maxlvt > 3) { /* PC is LVT#4. */
1112 v = apic_read(APIC_LVTPC);
1113 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1114 }
1115 v = apic_read(APIC_LVT0);
1116 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1117 v = apic_read(APIC_LVT1);
1118 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1119
1120 if (maxlvt > 2) { /* ERR is LVT#3. */
1121 v = apic_read(APIC_LVTERR);
1122 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1123 }
1124
1125 v = apic_read(APIC_TMICT);
1126 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1127 v = apic_read(APIC_TMCCT);
1128 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1129 v = apic_read(APIC_TDCR);
1130 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1131 printk("\n");
1132 }
1133
1134 void print_all_local_APICs (void)
1135 {
1136 on_each_cpu(print_local_APIC, NULL, 1, 1);
1137 }
1138
1139 void __apicdebuginit print_PIC(void)
1140 {
1141 unsigned int v;
1142 unsigned long flags;
1143
1144 if (apic_verbosity == APIC_QUIET)
1145 return;
1146
1147 printk(KERN_DEBUG "\nprinting PIC contents\n");
1148
1149 spin_lock_irqsave(&i8259A_lock, flags);
1150
1151 v = inb(0xa1) << 8 | inb(0x21);
1152 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1153
1154 v = inb(0xa0) << 8 | inb(0x20);
1155 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1156
1157 outb(0x0b,0xa0);
1158 outb(0x0b,0x20);
1159 v = inb(0xa0) << 8 | inb(0x20);
1160 outb(0x0a,0xa0);
1161 outb(0x0a,0x20);
1162
1163 spin_unlock_irqrestore(&i8259A_lock, flags);
1164
1165 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1166
1167 v = inb(0x4d1) << 8 | inb(0x4d0);
1168 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1169 }
1170
1171 #endif /* 0 */
1172
1173 static void __init enable_IO_APIC(void)
1174 {
1175 union IO_APIC_reg_01 reg_01;
1176 int i8259_apic, i8259_pin;
1177 int i, apic;
1178 unsigned long flags;
1179
1180 for (i = 0; i < PIN_MAP_SIZE; i++) {
1181 irq_2_pin[i].pin = -1;
1182 irq_2_pin[i].next = 0;
1183 }
1184
1185 /*
1186 * The number of IO-APIC IRQ registers (== #pins):
1187 */
1188 for (apic = 0; apic < nr_ioapics; apic++) {
1189 spin_lock_irqsave(&ioapic_lock, flags);
1190 reg_01.raw = io_apic_read(apic, 1);
1191 spin_unlock_irqrestore(&ioapic_lock, flags);
1192 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1193 }
1194 for(apic = 0; apic < nr_ioapics; apic++) {
1195 int pin;
1196 /* See if any of the pins is in ExtINT mode */
1197 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1198 struct IO_APIC_route_entry entry;
1199 entry = ioapic_read_entry(apic, pin);
1200
1201 /* If the interrupt line is enabled and in ExtInt mode
1202 * I have found the pin where the i8259 is connected.
1203 */
1204 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1205 ioapic_i8259.apic = apic;
1206 ioapic_i8259.pin = pin;
1207 goto found_i8259;
1208 }
1209 }
1210 }
1211 found_i8259:
1212 /* Look to see what if the MP table has reported the ExtINT */
1213 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1214 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1215 /* Trust the MP table if nothing is setup in the hardware */
1216 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1217 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1218 ioapic_i8259.pin = i8259_pin;
1219 ioapic_i8259.apic = i8259_apic;
1220 }
1221 /* Complain if the MP table and the hardware disagree */
1222 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1223 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1224 {
1225 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1226 }
1227
1228 /*
1229 * Do not trust the IO-APIC being empty at bootup
1230 */
1231 clear_IO_APIC();
1232 }
1233
1234 /*
1235 * Not an __init, needed by the reboot code
1236 */
1237 void disable_IO_APIC(void)
1238 {
1239 /*
1240 * Clear the IO-APIC before rebooting:
1241 */
1242 clear_IO_APIC();
1243
1244 /*
1245 * If the i8259 is routed through an IOAPIC
1246 * Put that IOAPIC in virtual wire mode
1247 * so legacy interrupts can be delivered.
1248 */
1249 if (ioapic_i8259.pin != -1) {
1250 struct IO_APIC_route_entry entry;
1251
1252 memset(&entry, 0, sizeof(entry));
1253 entry.mask = 0; /* Enabled */
1254 entry.trigger = 0; /* Edge */
1255 entry.irr = 0;
1256 entry.polarity = 0; /* High */
1257 entry.delivery_status = 0;
1258 entry.dest_mode = 0; /* Physical */
1259 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1260 entry.vector = 0;
1261 entry.dest = GET_APIC_ID(apic_read(APIC_ID));
1262
1263 /*
1264 * Add it to the IO-APIC irq-routing table:
1265 */
1266 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1267 }
1268
1269 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1270 }
1271
1272 /*
1273 * There is a nasty bug in some older SMP boards, their mptable lies
1274 * about the timer IRQ. We do the following to work around the situation:
1275 *
1276 * - timer IRQ defaults to IO-APIC IRQ
1277 * - if this function detects that timer IRQs are defunct, then we fall
1278 * back to ISA timer IRQs
1279 */
1280 static int __init timer_irq_works(void)
1281 {
1282 unsigned long t1 = jiffies;
1283
1284 local_irq_enable();
1285 /* Let ten ticks pass... */
1286 mdelay((10 * 1000) / HZ);
1287
1288 /*
1289 * Expect a few ticks at least, to be sure some possible
1290 * glue logic does not lock up after one or two first
1291 * ticks in a non-ExtINT mode. Also the local APIC
1292 * might have cached one ExtINT interrupt. Finally, at
1293 * least one tick may be lost due to delays.
1294 */
1295
1296 /* jiffies wrap? */
1297 if (jiffies - t1 > 4)
1298 return 1;
1299 return 0;
1300 }
1301
1302 /*
1303 * In the SMP+IOAPIC case it might happen that there are an unspecified
1304 * number of pending IRQ events unhandled. These cases are very rare,
1305 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1306 * better to do it this way as thus we do not have to be aware of
1307 * 'pending' interrupts in the IRQ path, except at this point.
1308 */
1309 /*
1310 * Edge triggered needs to resend any interrupt
1311 * that was delayed but this is now handled in the device
1312 * independent code.
1313 */
1314
1315 /*
1316 * Starting up a edge-triggered IO-APIC interrupt is
1317 * nasty - we need to make sure that we get the edge.
1318 * If it is already asserted for some reason, we need
1319 * return 1 to indicate that is was pending.
1320 *
1321 * This is not complete - we should be able to fake
1322 * an edge even if it isn't on the 8259A...
1323 */
1324
1325 static unsigned int startup_ioapic_irq(unsigned int irq)
1326 {
1327 int was_pending = 0;
1328 unsigned long flags;
1329
1330 spin_lock_irqsave(&ioapic_lock, flags);
1331 if (irq < 16) {
1332 disable_8259A_irq(irq);
1333 if (i8259A_irq_pending(irq))
1334 was_pending = 1;
1335 }
1336 __unmask_IO_APIC_irq(irq);
1337 spin_unlock_irqrestore(&ioapic_lock, flags);
1338
1339 return was_pending;
1340 }
1341
1342 static int ioapic_retrigger_irq(unsigned int irq)
1343 {
1344 struct irq_cfg *cfg = &irq_cfg[irq];
1345 cpumask_t mask;
1346 unsigned long flags;
1347
1348 spin_lock_irqsave(&vector_lock, flags);
1349 cpus_clear(mask);
1350 cpu_set(first_cpu(cfg->domain), mask);
1351
1352 send_IPI_mask(mask, cfg->vector);
1353 spin_unlock_irqrestore(&vector_lock, flags);
1354
1355 return 1;
1356 }
1357
1358 /*
1359 * Level and edge triggered IO-APIC interrupts need different handling,
1360 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1361 * handled with the level-triggered descriptor, but that one has slightly
1362 * more overhead. Level-triggered interrupts cannot be handled with the
1363 * edge-triggered handler, without risking IRQ storms and other ugly
1364 * races.
1365 */
1366
1367 #ifdef CONFIG_SMP
1368 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1369 {
1370 unsigned vector, me;
1371 ack_APIC_irq();
1372 exit_idle();
1373 irq_enter();
1374
1375 me = smp_processor_id();
1376 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1377 unsigned int irq;
1378 struct irq_desc *desc;
1379 struct irq_cfg *cfg;
1380 irq = __get_cpu_var(vector_irq)[vector];
1381 if (irq >= NR_IRQS)
1382 continue;
1383
1384 desc = irq_desc + irq;
1385 cfg = irq_cfg + irq;
1386 spin_lock(&desc->lock);
1387 if (!cfg->move_cleanup_count)
1388 goto unlock;
1389
1390 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1391 goto unlock;
1392
1393 __get_cpu_var(vector_irq)[vector] = -1;
1394 cfg->move_cleanup_count--;
1395 unlock:
1396 spin_unlock(&desc->lock);
1397 }
1398
1399 irq_exit();
1400 }
1401
1402 static void irq_complete_move(unsigned int irq)
1403 {
1404 struct irq_cfg *cfg = irq_cfg + irq;
1405 unsigned vector, me;
1406
1407 if (likely(!cfg->move_in_progress))
1408 return;
1409
1410 vector = ~get_irq_regs()->orig_rax;
1411 me = smp_processor_id();
1412 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1413 cpumask_t cleanup_mask;
1414
1415 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1416 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1417 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1418 cfg->move_in_progress = 0;
1419 }
1420 }
1421 #else
1422 static inline void irq_complete_move(unsigned int irq) {}
1423 #endif
1424
1425 static void ack_apic_edge(unsigned int irq)
1426 {
1427 irq_complete_move(irq);
1428 move_native_irq(irq);
1429 ack_APIC_irq();
1430 }
1431
1432 static void ack_apic_level(unsigned int irq)
1433 {
1434 int do_unmask_irq = 0;
1435
1436 irq_complete_move(irq);
1437 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1438 /* If we are moving the irq we need to mask it */
1439 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1440 do_unmask_irq = 1;
1441 mask_IO_APIC_irq(irq);
1442 }
1443 #endif
1444
1445 /*
1446 * We must acknowledge the irq before we move it or the acknowledge will
1447 * not propagate properly.
1448 */
1449 ack_APIC_irq();
1450
1451 /* Now we can move and renable the irq */
1452 if (unlikely(do_unmask_irq)) {
1453 /* Only migrate the irq if the ack has been received.
1454 *
1455 * On rare occasions the broadcast level triggered ack gets
1456 * delayed going to ioapics, and if we reprogram the
1457 * vector while Remote IRR is still set the irq will never
1458 * fire again.
1459 *
1460 * To prevent this scenario we read the Remote IRR bit
1461 * of the ioapic. This has two effects.
1462 * - On any sane system the read of the ioapic will
1463 * flush writes (and acks) going to the ioapic from
1464 * this cpu.
1465 * - We get to see if the ACK has actually been delivered.
1466 *
1467 * Based on failed experiments of reprogramming the
1468 * ioapic entry from outside of irq context starting
1469 * with masking the ioapic entry and then polling until
1470 * Remote IRR was clear before reprogramming the
1471 * ioapic I don't trust the Remote IRR bit to be
1472 * completey accurate.
1473 *
1474 * However there appears to be no other way to plug
1475 * this race, so if the Remote IRR bit is not
1476 * accurate and is causing problems then it is a hardware bug
1477 * and you can go talk to the chipset vendor about it.
1478 */
1479 if (!io_apic_level_ack_pending(irq))
1480 move_masked_irq(irq);
1481 unmask_IO_APIC_irq(irq);
1482 }
1483 }
1484
1485 static struct irq_chip ioapic_chip __read_mostly = {
1486 .name = "IO-APIC",
1487 .startup = startup_ioapic_irq,
1488 .mask = mask_IO_APIC_irq,
1489 .unmask = unmask_IO_APIC_irq,
1490 .ack = ack_apic_edge,
1491 .eoi = ack_apic_level,
1492 #ifdef CONFIG_SMP
1493 .set_affinity = set_ioapic_affinity_irq,
1494 #endif
1495 .retrigger = ioapic_retrigger_irq,
1496 };
1497
1498 static inline void init_IO_APIC_traps(void)
1499 {
1500 int irq;
1501
1502 /*
1503 * NOTE! The local APIC isn't very good at handling
1504 * multiple interrupts at the same interrupt level.
1505 * As the interrupt level is determined by taking the
1506 * vector number and shifting that right by 4, we
1507 * want to spread these out a bit so that they don't
1508 * all fall in the same interrupt level.
1509 *
1510 * Also, we've got to be careful not to trash gate
1511 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1512 */
1513 for (irq = 0; irq < NR_IRQS ; irq++) {
1514 int tmp = irq;
1515 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1516 /*
1517 * Hmm.. We don't have an entry for this,
1518 * so default to an old-fashioned 8259
1519 * interrupt if we can..
1520 */
1521 if (irq < 16)
1522 make_8259A_irq(irq);
1523 else
1524 /* Strange. Oh, well.. */
1525 irq_desc[irq].chip = &no_irq_chip;
1526 }
1527 }
1528 }
1529
1530 static void enable_lapic_irq (unsigned int irq)
1531 {
1532 unsigned long v;
1533
1534 v = apic_read(APIC_LVT0);
1535 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1536 }
1537
1538 static void disable_lapic_irq (unsigned int irq)
1539 {
1540 unsigned long v;
1541
1542 v = apic_read(APIC_LVT0);
1543 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1544 }
1545
1546 static void ack_lapic_irq (unsigned int irq)
1547 {
1548 ack_APIC_irq();
1549 }
1550
1551 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1552
1553 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1554 .name = "local-APIC",
1555 .typename = "local-APIC-edge",
1556 .startup = NULL, /* startup_irq() not used for IRQ0 */
1557 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1558 .enable = enable_lapic_irq,
1559 .disable = disable_lapic_irq,
1560 .ack = ack_lapic_irq,
1561 .end = end_lapic_irq,
1562 };
1563
1564 static void setup_nmi (void)
1565 {
1566 /*
1567 * Dirty trick to enable the NMI watchdog ...
1568 * We put the 8259A master into AEOI mode and
1569 * unmask on all local APICs LVT0 as NMI.
1570 *
1571 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1572 * is from Maciej W. Rozycki - so we do not have to EOI from
1573 * the NMI handler or the timer interrupt.
1574 */
1575 printk(KERN_INFO "activating NMI Watchdog ...");
1576
1577 enable_NMI_through_LVT0(NULL);
1578
1579 printk(" done.\n");
1580 }
1581
1582 /*
1583 * This looks a bit hackish but it's about the only one way of sending
1584 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1585 * not support the ExtINT mode, unfortunately. We need to send these
1586 * cycles as some i82489DX-based boards have glue logic that keeps the
1587 * 8259A interrupt line asserted until INTA. --macro
1588 */
1589 static inline void unlock_ExtINT_logic(void)
1590 {
1591 int apic, pin, i;
1592 struct IO_APIC_route_entry entry0, entry1;
1593 unsigned char save_control, save_freq_select;
1594 unsigned long flags;
1595
1596 pin = find_isa_irq_pin(8, mp_INT);
1597 apic = find_isa_irq_apic(8, mp_INT);
1598 if (pin == -1)
1599 return;
1600
1601 spin_lock_irqsave(&ioapic_lock, flags);
1602 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1603 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1604 spin_unlock_irqrestore(&ioapic_lock, flags);
1605 clear_IO_APIC_pin(apic, pin);
1606
1607 memset(&entry1, 0, sizeof(entry1));
1608
1609 entry1.dest_mode = 0; /* physical delivery */
1610 entry1.mask = 0; /* unmask IRQ now */
1611 entry1.dest = hard_smp_processor_id();
1612 entry1.delivery_mode = dest_ExtINT;
1613 entry1.polarity = entry0.polarity;
1614 entry1.trigger = 0;
1615 entry1.vector = 0;
1616
1617 spin_lock_irqsave(&ioapic_lock, flags);
1618 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1619 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1620 spin_unlock_irqrestore(&ioapic_lock, flags);
1621
1622 save_control = CMOS_READ(RTC_CONTROL);
1623 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1624 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1625 RTC_FREQ_SELECT);
1626 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1627
1628 i = 100;
1629 while (i-- > 0) {
1630 mdelay(10);
1631 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1632 i -= 10;
1633 }
1634
1635 CMOS_WRITE(save_control, RTC_CONTROL);
1636 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1637 clear_IO_APIC_pin(apic, pin);
1638
1639 spin_lock_irqsave(&ioapic_lock, flags);
1640 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1641 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1642 spin_unlock_irqrestore(&ioapic_lock, flags);
1643 }
1644
1645 /*
1646 * This code may look a bit paranoid, but it's supposed to cooperate with
1647 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1648 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1649 * fanatically on his truly buggy board.
1650 *
1651 * FIXME: really need to revamp this for modern platforms only.
1652 */
1653 static inline void check_timer(void)
1654 {
1655 struct irq_cfg *cfg = irq_cfg + 0;
1656 int apic1, pin1, apic2, pin2;
1657
1658 /*
1659 * get/set the timer IRQ vector:
1660 */
1661 disable_8259A_irq(0);
1662 assign_irq_vector(0, TARGET_CPUS);
1663
1664 /*
1665 * Subtle, code in do_timer_interrupt() expects an AEOI
1666 * mode for the 8259A whenever interrupts are routed
1667 * through I/O APICs. Also IRQ0 has to be enabled in
1668 * the 8259A which implies the virtual wire has to be
1669 * disabled in the local APIC.
1670 */
1671 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1672 init_8259A(1);
1673 if (timer_over_8254 > 0)
1674 enable_8259A_irq(0);
1675
1676 pin1 = find_isa_irq_pin(0, mp_INT);
1677 apic1 = find_isa_irq_apic(0, mp_INT);
1678 pin2 = ioapic_i8259.pin;
1679 apic2 = ioapic_i8259.apic;
1680
1681 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1682 cfg->vector, apic1, pin1, apic2, pin2);
1683
1684 if (pin1 != -1) {
1685 /*
1686 * Ok, does IRQ0 through the IOAPIC work?
1687 */
1688 unmask_IO_APIC_irq(0);
1689 if (!no_timer_check && timer_irq_works()) {
1690 nmi_watchdog_default();
1691 if (nmi_watchdog == NMI_IO_APIC) {
1692 disable_8259A_irq(0);
1693 setup_nmi();
1694 enable_8259A_irq(0);
1695 }
1696 if (disable_timer_pin_1 > 0)
1697 clear_IO_APIC_pin(0, pin1);
1698 return;
1699 }
1700 clear_IO_APIC_pin(apic1, pin1);
1701 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1702 "connected to IO-APIC\n");
1703 }
1704
1705 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1706 "through the 8259A ... ");
1707 if (pin2 != -1) {
1708 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1709 apic2, pin2);
1710 /*
1711 * legacy devices should be connected to IO APIC #0
1712 */
1713 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1714 if (timer_irq_works()) {
1715 apic_printk(APIC_VERBOSE," works.\n");
1716 nmi_watchdog_default();
1717 if (nmi_watchdog == NMI_IO_APIC) {
1718 setup_nmi();
1719 }
1720 return;
1721 }
1722 /*
1723 * Cleanup, just in case ...
1724 */
1725 clear_IO_APIC_pin(apic2, pin2);
1726 }
1727 apic_printk(APIC_VERBOSE," failed.\n");
1728
1729 if (nmi_watchdog == NMI_IO_APIC) {
1730 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1731 nmi_watchdog = 0;
1732 }
1733
1734 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1735
1736 disable_8259A_irq(0);
1737 irq_desc[0].chip = &lapic_irq_type;
1738 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1739 enable_8259A_irq(0);
1740
1741 if (timer_irq_works()) {
1742 apic_printk(APIC_VERBOSE," works.\n");
1743 return;
1744 }
1745 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1746 apic_printk(APIC_VERBOSE," failed.\n");
1747
1748 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1749
1750 init_8259A(0);
1751 make_8259A_irq(0);
1752 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1753
1754 unlock_ExtINT_logic();
1755
1756 if (timer_irq_works()) {
1757 apic_printk(APIC_VERBOSE," works.\n");
1758 return;
1759 }
1760 apic_printk(APIC_VERBOSE," failed :(.\n");
1761 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1762 }
1763
1764 static int __init notimercheck(char *s)
1765 {
1766 no_timer_check = 1;
1767 return 1;
1768 }
1769 __setup("no_timer_check", notimercheck);
1770
1771 /*
1772 *
1773 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1774 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1775 * Linux doesn't really care, as it's not actually used
1776 * for any interrupt handling anyway.
1777 */
1778 #define PIC_IRQS (1<<2)
1779
1780 void __init setup_IO_APIC(void)
1781 {
1782 enable_IO_APIC();
1783
1784 if (acpi_ioapic)
1785 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1786 else
1787 io_apic_irqs = ~PIC_IRQS;
1788
1789 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1790
1791 sync_Arb_IDs();
1792 setup_IO_APIC_irqs();
1793 init_IO_APIC_traps();
1794 check_timer();
1795 if (!acpi_ioapic)
1796 print_IO_APIC();
1797 }
1798
1799 struct sysfs_ioapic_data {
1800 struct sys_device dev;
1801 struct IO_APIC_route_entry entry[0];
1802 };
1803 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1804
1805 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1806 {
1807 struct IO_APIC_route_entry *entry;
1808 struct sysfs_ioapic_data *data;
1809 int i;
1810
1811 data = container_of(dev, struct sysfs_ioapic_data, dev);
1812 entry = data->entry;
1813 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1814 *entry = ioapic_read_entry(dev->id, i);
1815
1816 return 0;
1817 }
1818
1819 static int ioapic_resume(struct sys_device *dev)
1820 {
1821 struct IO_APIC_route_entry *entry;
1822 struct sysfs_ioapic_data *data;
1823 unsigned long flags;
1824 union IO_APIC_reg_00 reg_00;
1825 int i;
1826
1827 data = container_of(dev, struct sysfs_ioapic_data, dev);
1828 entry = data->entry;
1829
1830 spin_lock_irqsave(&ioapic_lock, flags);
1831 reg_00.raw = io_apic_read(dev->id, 0);
1832 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1833 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1834 io_apic_write(dev->id, 0, reg_00.raw);
1835 }
1836 spin_unlock_irqrestore(&ioapic_lock, flags);
1837 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1838 ioapic_write_entry(dev->id, i, entry[i]);
1839
1840 return 0;
1841 }
1842
1843 static struct sysdev_class ioapic_sysdev_class = {
1844 set_kset_name("ioapic"),
1845 .suspend = ioapic_suspend,
1846 .resume = ioapic_resume,
1847 };
1848
1849 static int __init ioapic_init_sysfs(void)
1850 {
1851 struct sys_device * dev;
1852 int i, size, error;
1853
1854 error = sysdev_class_register(&ioapic_sysdev_class);
1855 if (error)
1856 return error;
1857
1858 for (i = 0; i < nr_ioapics; i++ ) {
1859 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1860 * sizeof(struct IO_APIC_route_entry);
1861 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1862 if (!mp_ioapic_data[i]) {
1863 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1864 continue;
1865 }
1866 dev = &mp_ioapic_data[i]->dev;
1867 dev->id = i;
1868 dev->cls = &ioapic_sysdev_class;
1869 error = sysdev_register(dev);
1870 if (error) {
1871 kfree(mp_ioapic_data[i]);
1872 mp_ioapic_data[i] = NULL;
1873 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1874 continue;
1875 }
1876 }
1877
1878 return 0;
1879 }
1880
1881 device_initcall(ioapic_init_sysfs);
1882
1883 /*
1884 * Dynamic irq allocate and deallocation
1885 */
1886 int create_irq(void)
1887 {
1888 /* Allocate an unused irq */
1889 int irq;
1890 int new;
1891 unsigned long flags;
1892
1893 irq = -ENOSPC;
1894 spin_lock_irqsave(&vector_lock, flags);
1895 for (new = (NR_IRQS - 1); new >= 0; new--) {
1896 if (platform_legacy_irq(new))
1897 continue;
1898 if (irq_cfg[new].vector != 0)
1899 continue;
1900 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1901 irq = new;
1902 break;
1903 }
1904 spin_unlock_irqrestore(&vector_lock, flags);
1905
1906 if (irq >= 0) {
1907 dynamic_irq_init(irq);
1908 }
1909 return irq;
1910 }
1911
1912 void destroy_irq(unsigned int irq)
1913 {
1914 unsigned long flags;
1915
1916 dynamic_irq_cleanup(irq);
1917
1918 spin_lock_irqsave(&vector_lock, flags);
1919 __clear_irq_vector(irq);
1920 spin_unlock_irqrestore(&vector_lock, flags);
1921 }
1922
1923 /*
1924 * MSI message composition
1925 */
1926 #ifdef CONFIG_PCI_MSI
1927 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1928 {
1929 struct irq_cfg *cfg = irq_cfg + irq;
1930 int err;
1931 unsigned dest;
1932 cpumask_t tmp;
1933
1934 tmp = TARGET_CPUS;
1935 err = assign_irq_vector(irq, tmp);
1936 if (!err) {
1937 cpus_and(tmp, cfg->domain, tmp);
1938 dest = cpu_mask_to_apicid(tmp);
1939
1940 msg->address_hi = MSI_ADDR_BASE_HI;
1941 msg->address_lo =
1942 MSI_ADDR_BASE_LO |
1943 ((INT_DEST_MODE == 0) ?
1944 MSI_ADDR_DEST_MODE_PHYSICAL:
1945 MSI_ADDR_DEST_MODE_LOGICAL) |
1946 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1947 MSI_ADDR_REDIRECTION_CPU:
1948 MSI_ADDR_REDIRECTION_LOWPRI) |
1949 MSI_ADDR_DEST_ID(dest);
1950
1951 msg->data =
1952 MSI_DATA_TRIGGER_EDGE |
1953 MSI_DATA_LEVEL_ASSERT |
1954 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1955 MSI_DATA_DELIVERY_FIXED:
1956 MSI_DATA_DELIVERY_LOWPRI) |
1957 MSI_DATA_VECTOR(cfg->vector);
1958 }
1959 return err;
1960 }
1961
1962 #ifdef CONFIG_SMP
1963 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1964 {
1965 struct irq_cfg *cfg = irq_cfg + irq;
1966 struct msi_msg msg;
1967 unsigned int dest;
1968 cpumask_t tmp;
1969
1970 cpus_and(tmp, mask, cpu_online_map);
1971 if (cpus_empty(tmp))
1972 return;
1973
1974 if (assign_irq_vector(irq, mask))
1975 return;
1976
1977 cpus_and(tmp, cfg->domain, mask);
1978 dest = cpu_mask_to_apicid(tmp);
1979
1980 read_msi_msg(irq, &msg);
1981
1982 msg.data &= ~MSI_DATA_VECTOR_MASK;
1983 msg.data |= MSI_DATA_VECTOR(cfg->vector);
1984 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1985 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1986
1987 write_msi_msg(irq, &msg);
1988 irq_desc[irq].affinity = mask;
1989 }
1990 #endif /* CONFIG_SMP */
1991
1992 /*
1993 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1994 * which implement the MSI or MSI-X Capability Structure.
1995 */
1996 static struct irq_chip msi_chip = {
1997 .name = "PCI-MSI",
1998 .unmask = unmask_msi_irq,
1999 .mask = mask_msi_irq,
2000 .ack = ack_apic_edge,
2001 #ifdef CONFIG_SMP
2002 .set_affinity = set_msi_irq_affinity,
2003 #endif
2004 .retrigger = ioapic_retrigger_irq,
2005 };
2006
2007 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2008 {
2009 struct msi_msg msg;
2010 int irq, ret;
2011 irq = create_irq();
2012 if (irq < 0)
2013 return irq;
2014
2015 ret = msi_compose_msg(dev, irq, &msg);
2016 if (ret < 0) {
2017 destroy_irq(irq);
2018 return ret;
2019 }
2020
2021 set_irq_msi(irq, desc);
2022 write_msi_msg(irq, &msg);
2023
2024 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2025
2026 return 0;
2027 }
2028
2029 void arch_teardown_msi_irq(unsigned int irq)
2030 {
2031 destroy_irq(irq);
2032 }
2033
2034 #endif /* CONFIG_PCI_MSI */
2035
2036 /*
2037 * Hypertransport interrupt support
2038 */
2039 #ifdef CONFIG_HT_IRQ
2040
2041 #ifdef CONFIG_SMP
2042
2043 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2044 {
2045 struct ht_irq_msg msg;
2046 fetch_ht_irq_msg(irq, &msg);
2047
2048 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2049 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2050
2051 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2052 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2053
2054 write_ht_irq_msg(irq, &msg);
2055 }
2056
2057 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2058 {
2059 struct irq_cfg *cfg = irq_cfg + irq;
2060 unsigned int dest;
2061 cpumask_t tmp;
2062
2063 cpus_and(tmp, mask, cpu_online_map);
2064 if (cpus_empty(tmp))
2065 return;
2066
2067 if (assign_irq_vector(irq, mask))
2068 return;
2069
2070 cpus_and(tmp, cfg->domain, mask);
2071 dest = cpu_mask_to_apicid(tmp);
2072
2073 target_ht_irq(irq, dest, cfg->vector);
2074 irq_desc[irq].affinity = mask;
2075 }
2076 #endif
2077
2078 static struct irq_chip ht_irq_chip = {
2079 .name = "PCI-HT",
2080 .mask = mask_ht_irq,
2081 .unmask = unmask_ht_irq,
2082 .ack = ack_apic_edge,
2083 #ifdef CONFIG_SMP
2084 .set_affinity = set_ht_irq_affinity,
2085 #endif
2086 .retrigger = ioapic_retrigger_irq,
2087 };
2088
2089 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2090 {
2091 struct irq_cfg *cfg = irq_cfg + irq;
2092 int err;
2093 cpumask_t tmp;
2094
2095 tmp = TARGET_CPUS;
2096 err = assign_irq_vector(irq, tmp);
2097 if (!err) {
2098 struct ht_irq_msg msg;
2099 unsigned dest;
2100
2101 cpus_and(tmp, cfg->domain, tmp);
2102 dest = cpu_mask_to_apicid(tmp);
2103
2104 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2105
2106 msg.address_lo =
2107 HT_IRQ_LOW_BASE |
2108 HT_IRQ_LOW_DEST_ID(dest) |
2109 HT_IRQ_LOW_VECTOR(cfg->vector) |
2110 ((INT_DEST_MODE == 0) ?
2111 HT_IRQ_LOW_DM_PHYSICAL :
2112 HT_IRQ_LOW_DM_LOGICAL) |
2113 HT_IRQ_LOW_RQEOI_EDGE |
2114 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2115 HT_IRQ_LOW_MT_FIXED :
2116 HT_IRQ_LOW_MT_ARBITRATED) |
2117 HT_IRQ_LOW_IRQ_MASKED;
2118
2119 write_ht_irq_msg(irq, &msg);
2120
2121 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2122 handle_edge_irq, "edge");
2123 }
2124 return err;
2125 }
2126 #endif /* CONFIG_HT_IRQ */
2127
2128 /* --------------------------------------------------------------------------
2129 ACPI-based IOAPIC Configuration
2130 -------------------------------------------------------------------------- */
2131
2132 #ifdef CONFIG_ACPI
2133
2134 #define IO_APIC_MAX_ID 0xFE
2135
2136 int __init io_apic_get_redir_entries (int ioapic)
2137 {
2138 union IO_APIC_reg_01 reg_01;
2139 unsigned long flags;
2140
2141 spin_lock_irqsave(&ioapic_lock, flags);
2142 reg_01.raw = io_apic_read(ioapic, 1);
2143 spin_unlock_irqrestore(&ioapic_lock, flags);
2144
2145 return reg_01.bits.entries;
2146 }
2147
2148
2149 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2150 {
2151 if (!IO_APIC_IRQ(irq)) {
2152 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2153 ioapic);
2154 return -EINVAL;
2155 }
2156
2157 /*
2158 * IRQs < 16 are already in the irq_2_pin[] map
2159 */
2160 if (irq >= 16)
2161 add_pin_to_irq(irq, ioapic, pin);
2162
2163 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2164
2165 return 0;
2166 }
2167
2168 #endif /* CONFIG_ACPI */
2169
2170
2171 /*
2172 * This function currently is only a helper for the i386 smp boot process where
2173 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2174 * so mask in all cases should simply be TARGET_CPUS
2175 */
2176 #ifdef CONFIG_SMP
2177 void __init setup_ioapic_dest(void)
2178 {
2179 int pin, ioapic, irq, irq_entry;
2180
2181 if (skip_ioapic_setup == 1)
2182 return;
2183
2184 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2185 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2186 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2187 if (irq_entry == -1)
2188 continue;
2189 irq = pin_2_irq(irq_entry, ioapic, pin);
2190
2191 /* setup_IO_APIC_irqs could fail to get vector for some device
2192 * when you have too many devices, because at that time only boot
2193 * cpu is online.
2194 */
2195 if (!irq_cfg[irq].vector)
2196 setup_IO_APIC_irq(ioapic, pin, irq,
2197 irq_trigger(irq_entry),
2198 irq_polarity(irq_entry));
2199 else
2200 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2201 }
2202
2203 }
2204 }
2205 #endif