1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/sysdev.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/slab.h>
8 #include <linux/hpet.h>
9 #include <linux/init.h>
10 #include <linux/cpu.h>
14 #include <asm/fixmap.h>
15 #include <asm/i8253.h>
18 #define HPET_MASK CLOCKSOURCE_MASK(32)
22 #define FSEC_PER_NSEC 1000000L
24 #define HPET_DEV_USED_BIT 2
25 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
26 #define HPET_DEV_VALID 0x8
27 #define HPET_DEV_FSB_CAP 0x1000
28 #define HPET_DEV_PERI_CAP 0x2000
30 #define HPET_MIN_CYCLES 128
31 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
33 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
36 * HPET address is set in acpi/boot.c, when an ACPI entry exists
38 unsigned long hpet_address
;
39 u8 hpet_blockid
; /* OS timer block num */
43 static unsigned long hpet_num_timers
;
45 static void __iomem
*hpet_virt_address
;
48 struct clock_event_device evt
;
56 inline unsigned int hpet_readl(unsigned int a
)
58 return readl(hpet_virt_address
+ a
);
61 static inline void hpet_writel(unsigned int d
, unsigned int a
)
63 writel(d
, hpet_virt_address
+ a
);
67 #include <asm/pgtable.h>
70 static inline void hpet_set_mapping(void)
72 hpet_virt_address
= ioremap_nocache(hpet_address
, HPET_MMAP_SIZE
);
74 __set_fixmap(VSYSCALL_HPET
, hpet_address
, PAGE_KERNEL_VVAR_NOCACHE
);
78 static inline void hpet_clear_mapping(void)
80 iounmap(hpet_virt_address
);
81 hpet_virt_address
= NULL
;
85 * HPET command line enable / disable
87 static int boot_hpet_disable
;
89 static int hpet_verbose
;
91 static int __init
hpet_setup(char *str
)
94 if (!strncmp("disable", str
, 7))
95 boot_hpet_disable
= 1;
96 if (!strncmp("force", str
, 5))
98 if (!strncmp("verbose", str
, 7))
103 __setup("hpet=", hpet_setup
);
105 static int __init
disable_hpet(char *str
)
107 boot_hpet_disable
= 1;
110 __setup("nohpet", disable_hpet
);
112 static inline int is_hpet_capable(void)
114 return !boot_hpet_disable
&& hpet_address
;
118 * HPET timer interrupt enable / disable
120 static int hpet_legacy_int_enabled
;
123 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
125 int is_hpet_enabled(void)
127 return is_hpet_capable() && hpet_legacy_int_enabled
;
129 EXPORT_SYMBOL_GPL(is_hpet_enabled
);
131 static void _hpet_print_config(const char *function
, int line
)
134 printk(KERN_INFO
"hpet: %s(%d):\n", function
, line
);
135 l
= hpet_readl(HPET_ID
);
136 h
= hpet_readl(HPET_PERIOD
);
137 timers
= ((l
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
) + 1;
138 printk(KERN_INFO
"hpet: ID: 0x%x, PERIOD: 0x%x\n", l
, h
);
139 l
= hpet_readl(HPET_CFG
);
140 h
= hpet_readl(HPET_STATUS
);
141 printk(KERN_INFO
"hpet: CFG: 0x%x, STATUS: 0x%x\n", l
, h
);
142 l
= hpet_readl(HPET_COUNTER
);
143 h
= hpet_readl(HPET_COUNTER
+4);
144 printk(KERN_INFO
"hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l
, h
);
146 for (i
= 0; i
< timers
; i
++) {
147 l
= hpet_readl(HPET_Tn_CFG(i
));
148 h
= hpet_readl(HPET_Tn_CFG(i
)+4);
149 printk(KERN_INFO
"hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
151 l
= hpet_readl(HPET_Tn_CMP(i
));
152 h
= hpet_readl(HPET_Tn_CMP(i
)+4);
153 printk(KERN_INFO
"hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
155 l
= hpet_readl(HPET_Tn_ROUTE(i
));
156 h
= hpet_readl(HPET_Tn_ROUTE(i
)+4);
157 printk(KERN_INFO
"hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
162 #define hpet_print_config() \
165 _hpet_print_config(__FUNCTION__, __LINE__); \
169 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
170 * timer 0 and timer 1 in case of RTC emulation.
174 static void hpet_reserve_msi_timers(struct hpet_data
*hd
);
176 static void hpet_reserve_platform_timers(unsigned int id
)
178 struct hpet __iomem
*hpet
= hpet_virt_address
;
179 struct hpet_timer __iomem
*timer
= &hpet
->hpet_timers
[2];
180 unsigned int nrtimers
, i
;
183 nrtimers
= ((id
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
) + 1;
185 memset(&hd
, 0, sizeof(hd
));
186 hd
.hd_phys_address
= hpet_address
;
187 hd
.hd_address
= hpet
;
188 hd
.hd_nirqs
= nrtimers
;
189 hpet_reserve_timer(&hd
, 0);
191 #ifdef CONFIG_HPET_EMULATE_RTC
192 hpet_reserve_timer(&hd
, 1);
196 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
197 * is wrong for i8259!) not the output IRQ. Many BIOS writers
198 * don't bother configuring *any* comparator interrupts.
200 hd
.hd_irq
[0] = HPET_LEGACY_8254
;
201 hd
.hd_irq
[1] = HPET_LEGACY_RTC
;
203 for (i
= 2; i
< nrtimers
; timer
++, i
++) {
204 hd
.hd_irq
[i
] = (readl(&timer
->hpet_config
) &
205 Tn_INT_ROUTE_CNF_MASK
) >> Tn_INT_ROUTE_CNF_SHIFT
;
208 hpet_reserve_msi_timers(&hd
);
214 static void hpet_reserve_platform_timers(unsigned int id
) { }
220 static unsigned long hpet_freq
;
222 static void hpet_legacy_set_mode(enum clock_event_mode mode
,
223 struct clock_event_device
*evt
);
224 static int hpet_legacy_next_event(unsigned long delta
,
225 struct clock_event_device
*evt
);
228 * The hpet clock event device
230 static struct clock_event_device hpet_clockevent
= {
232 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
233 .set_mode
= hpet_legacy_set_mode
,
234 .set_next_event
= hpet_legacy_next_event
,
239 static void hpet_stop_counter(void)
241 unsigned long cfg
= hpet_readl(HPET_CFG
);
242 cfg
&= ~HPET_CFG_ENABLE
;
243 hpet_writel(cfg
, HPET_CFG
);
246 static void hpet_reset_counter(void)
248 hpet_writel(0, HPET_COUNTER
);
249 hpet_writel(0, HPET_COUNTER
+ 4);
252 static void hpet_start_counter(void)
254 unsigned int cfg
= hpet_readl(HPET_CFG
);
255 cfg
|= HPET_CFG_ENABLE
;
256 hpet_writel(cfg
, HPET_CFG
);
259 static void hpet_restart_counter(void)
262 hpet_reset_counter();
263 hpet_start_counter();
266 static void hpet_resume_device(void)
271 static void hpet_resume_counter(struct clocksource
*cs
)
273 hpet_resume_device();
274 hpet_restart_counter();
277 static void hpet_enable_legacy_int(void)
279 unsigned int cfg
= hpet_readl(HPET_CFG
);
281 cfg
|= HPET_CFG_LEGACY
;
282 hpet_writel(cfg
, HPET_CFG
);
283 hpet_legacy_int_enabled
= 1;
286 static void hpet_legacy_clockevent_register(void)
288 /* Start HPET legacy interrupts */
289 hpet_enable_legacy_int();
292 * Start hpet with the boot cpu mask and make it
293 * global after the IO_APIC has been initialized.
295 hpet_clockevent
.cpumask
= cpumask_of(smp_processor_id());
296 clockevents_config_and_register(&hpet_clockevent
, hpet_freq
,
297 HPET_MIN_PROG_DELTA
, 0x7FFFFFFF);
298 global_clock_event
= &hpet_clockevent
;
299 printk(KERN_DEBUG
"hpet clockevent registered\n");
302 static int hpet_setup_msi_irq(unsigned int irq
);
304 static void hpet_set_mode(enum clock_event_mode mode
,
305 struct clock_event_device
*evt
, int timer
)
307 unsigned int cfg
, cmp
, now
;
311 case CLOCK_EVT_MODE_PERIODIC
:
313 delta
= ((uint64_t)(NSEC_PER_SEC
/HZ
)) * evt
->mult
;
314 delta
>>= evt
->shift
;
315 now
= hpet_readl(HPET_COUNTER
);
316 cmp
= now
+ (unsigned int) delta
;
317 cfg
= hpet_readl(HPET_Tn_CFG(timer
));
318 /* Make sure we use edge triggered interrupts */
319 cfg
&= ~HPET_TN_LEVEL
;
320 cfg
|= HPET_TN_ENABLE
| HPET_TN_PERIODIC
|
321 HPET_TN_SETVAL
| HPET_TN_32BIT
;
322 hpet_writel(cfg
, HPET_Tn_CFG(timer
));
323 hpet_writel(cmp
, HPET_Tn_CMP(timer
));
326 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
327 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
328 * bit is automatically cleared after the first write.
329 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
330 * Publication # 24674)
332 hpet_writel((unsigned int) delta
, HPET_Tn_CMP(timer
));
333 hpet_start_counter();
337 case CLOCK_EVT_MODE_ONESHOT
:
338 cfg
= hpet_readl(HPET_Tn_CFG(timer
));
339 cfg
&= ~HPET_TN_PERIODIC
;
340 cfg
|= HPET_TN_ENABLE
| HPET_TN_32BIT
;
341 hpet_writel(cfg
, HPET_Tn_CFG(timer
));
344 case CLOCK_EVT_MODE_UNUSED
:
345 case CLOCK_EVT_MODE_SHUTDOWN
:
346 cfg
= hpet_readl(HPET_Tn_CFG(timer
));
347 cfg
&= ~HPET_TN_ENABLE
;
348 hpet_writel(cfg
, HPET_Tn_CFG(timer
));
351 case CLOCK_EVT_MODE_RESUME
:
353 hpet_enable_legacy_int();
355 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
356 hpet_setup_msi_irq(hdev
->irq
);
357 disable_irq(hdev
->irq
);
358 irq_set_affinity(hdev
->irq
, cpumask_of(hdev
->cpu
));
359 enable_irq(hdev
->irq
);
366 static int hpet_next_event(unsigned long delta
,
367 struct clock_event_device
*evt
, int timer
)
372 cnt
= hpet_readl(HPET_COUNTER
);
374 hpet_writel(cnt
, HPET_Tn_CMP(timer
));
377 * HPETs are a complete disaster. The compare register is
378 * based on a equal comparison and neither provides a less
379 * than or equal functionality (which would require to take
380 * the wraparound into account) nor a simple count down event
381 * mode. Further the write to the comparator register is
382 * delayed internally up to two HPET clock cycles in certain
383 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
384 * longer delays. We worked around that by reading back the
385 * compare register, but that required another workaround for
386 * ICH9,10 chips where the first readout after write can
387 * return the old stale value. We already had a minimum
388 * programming delta of 5us enforced, but a NMI or SMI hitting
389 * between the counter readout and the comparator write can
390 * move us behind that point easily. Now instead of reading
391 * the compare register back several times, we make the ETIME
392 * decision based on the following: Return ETIME if the
393 * counter value after the write is less than HPET_MIN_CYCLES
394 * away from the event or if the counter is already ahead of
395 * the event. The minimum programming delta for the generic
396 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
398 res
= (s32
)(cnt
- hpet_readl(HPET_COUNTER
));
400 return res
< HPET_MIN_CYCLES
? -ETIME
: 0;
403 static void hpet_legacy_set_mode(enum clock_event_mode mode
,
404 struct clock_event_device
*evt
)
406 hpet_set_mode(mode
, evt
, 0);
409 static int hpet_legacy_next_event(unsigned long delta
,
410 struct clock_event_device
*evt
)
412 return hpet_next_event(delta
, evt
, 0);
418 #ifdef CONFIG_PCI_MSI
420 static DEFINE_PER_CPU(struct hpet_dev
*, cpu_hpet_dev
);
421 static struct hpet_dev
*hpet_devs
;
423 void hpet_msi_unmask(struct irq_data
*data
)
425 struct hpet_dev
*hdev
= data
->handler_data
;
429 cfg
= hpet_readl(HPET_Tn_CFG(hdev
->num
));
431 hpet_writel(cfg
, HPET_Tn_CFG(hdev
->num
));
434 void hpet_msi_mask(struct irq_data
*data
)
436 struct hpet_dev
*hdev
= data
->handler_data
;
440 cfg
= hpet_readl(HPET_Tn_CFG(hdev
->num
));
442 hpet_writel(cfg
, HPET_Tn_CFG(hdev
->num
));
445 void hpet_msi_write(struct hpet_dev
*hdev
, struct msi_msg
*msg
)
447 hpet_writel(msg
->data
, HPET_Tn_ROUTE(hdev
->num
));
448 hpet_writel(msg
->address_lo
, HPET_Tn_ROUTE(hdev
->num
) + 4);
451 void hpet_msi_read(struct hpet_dev
*hdev
, struct msi_msg
*msg
)
453 msg
->data
= hpet_readl(HPET_Tn_ROUTE(hdev
->num
));
454 msg
->address_lo
= hpet_readl(HPET_Tn_ROUTE(hdev
->num
) + 4);
458 static void hpet_msi_set_mode(enum clock_event_mode mode
,
459 struct clock_event_device
*evt
)
461 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
462 hpet_set_mode(mode
, evt
, hdev
->num
);
465 static int hpet_msi_next_event(unsigned long delta
,
466 struct clock_event_device
*evt
)
468 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
469 return hpet_next_event(delta
, evt
, hdev
->num
);
472 static int hpet_setup_msi_irq(unsigned int irq
)
474 if (arch_setup_hpet_msi(irq
, hpet_blockid
)) {
481 static int hpet_assign_irq(struct hpet_dev
*dev
)
485 irq
= create_irq_nr(0, -1);
489 irq_set_handler_data(irq
, dev
);
491 if (hpet_setup_msi_irq(irq
))
498 static irqreturn_t
hpet_interrupt_handler(int irq
, void *data
)
500 struct hpet_dev
*dev
= (struct hpet_dev
*)data
;
501 struct clock_event_device
*hevt
= &dev
->evt
;
503 if (!hevt
->event_handler
) {
504 printk(KERN_INFO
"Spurious HPET timer interrupt on HPET timer %d\n",
509 hevt
->event_handler(hevt
);
513 static int hpet_setup_irq(struct hpet_dev
*dev
)
516 if (request_irq(dev
->irq
, hpet_interrupt_handler
,
517 IRQF_TIMER
| IRQF_DISABLED
| IRQF_NOBALANCING
,
521 disable_irq(dev
->irq
);
522 irq_set_affinity(dev
->irq
, cpumask_of(dev
->cpu
));
523 enable_irq(dev
->irq
);
525 printk(KERN_DEBUG
"hpet: %s irq %d for MSI\n",
526 dev
->name
, dev
->irq
);
531 /* This should be called in specific @cpu */
532 static void init_one_hpet_msi_clockevent(struct hpet_dev
*hdev
, int cpu
)
534 struct clock_event_device
*evt
= &hdev
->evt
;
536 WARN_ON(cpu
!= smp_processor_id());
537 if (!(hdev
->flags
& HPET_DEV_VALID
))
540 if (hpet_setup_msi_irq(hdev
->irq
))
544 per_cpu(cpu_hpet_dev
, cpu
) = hdev
;
545 evt
->name
= hdev
->name
;
546 hpet_setup_irq(hdev
);
547 evt
->irq
= hdev
->irq
;
550 evt
->features
= CLOCK_EVT_FEAT_ONESHOT
;
551 if (hdev
->flags
& HPET_DEV_PERI_CAP
)
552 evt
->features
|= CLOCK_EVT_FEAT_PERIODIC
;
554 evt
->set_mode
= hpet_msi_set_mode
;
555 evt
->set_next_event
= hpet_msi_next_event
;
556 evt
->cpumask
= cpumask_of(hdev
->cpu
);
558 clockevents_config_and_register(evt
, hpet_freq
, HPET_MIN_PROG_DELTA
,
563 /* Reserve at least one timer for userspace (/dev/hpet) */
564 #define RESERVE_TIMERS 1
566 #define RESERVE_TIMERS 0
569 static void hpet_msi_capability_lookup(unsigned int start_timer
)
572 unsigned int num_timers
;
573 unsigned int num_timers_used
= 0;
576 if (hpet_msi_disable
)
579 if (boot_cpu_has(X86_FEATURE_ARAT
))
581 id
= hpet_readl(HPET_ID
);
583 num_timers
= ((id
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
);
584 num_timers
++; /* Value read out starts from 0 */
587 hpet_devs
= kzalloc(sizeof(struct hpet_dev
) * num_timers
, GFP_KERNEL
);
591 hpet_num_timers
= num_timers
;
593 for (i
= start_timer
; i
< num_timers
- RESERVE_TIMERS
; i
++) {
594 struct hpet_dev
*hdev
= &hpet_devs
[num_timers_used
];
595 unsigned int cfg
= hpet_readl(HPET_Tn_CFG(i
));
597 /* Only consider HPET timer with MSI support */
598 if (!(cfg
& HPET_TN_FSB_CAP
))
602 if (cfg
& HPET_TN_PERIODIC_CAP
)
603 hdev
->flags
|= HPET_DEV_PERI_CAP
;
606 sprintf(hdev
->name
, "hpet%d", i
);
607 if (hpet_assign_irq(hdev
))
610 hdev
->flags
|= HPET_DEV_FSB_CAP
;
611 hdev
->flags
|= HPET_DEV_VALID
;
613 if (num_timers_used
== num_possible_cpus())
617 printk(KERN_INFO
"HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
618 num_timers
, num_timers_used
);
622 static void hpet_reserve_msi_timers(struct hpet_data
*hd
)
629 for (i
= 0; i
< hpet_num_timers
; i
++) {
630 struct hpet_dev
*hdev
= &hpet_devs
[i
];
632 if (!(hdev
->flags
& HPET_DEV_VALID
))
635 hd
->hd_irq
[hdev
->num
] = hdev
->irq
;
636 hpet_reserve_timer(hd
, hdev
->num
);
641 static struct hpet_dev
*hpet_get_unused_timer(void)
648 for (i
= 0; i
< hpet_num_timers
; i
++) {
649 struct hpet_dev
*hdev
= &hpet_devs
[i
];
651 if (!(hdev
->flags
& HPET_DEV_VALID
))
653 if (test_and_set_bit(HPET_DEV_USED_BIT
,
654 (unsigned long *)&hdev
->flags
))
661 struct hpet_work_struct
{
662 struct delayed_work work
;
663 struct completion complete
;
666 static void hpet_work(struct work_struct
*w
)
668 struct hpet_dev
*hdev
;
669 int cpu
= smp_processor_id();
670 struct hpet_work_struct
*hpet_work
;
672 hpet_work
= container_of(w
, struct hpet_work_struct
, work
.work
);
674 hdev
= hpet_get_unused_timer();
676 init_one_hpet_msi_clockevent(hdev
, cpu
);
678 complete(&hpet_work
->complete
);
681 static int hpet_cpuhp_notify(struct notifier_block
*n
,
682 unsigned long action
, void *hcpu
)
684 unsigned long cpu
= (unsigned long)hcpu
;
685 struct hpet_work_struct work
;
686 struct hpet_dev
*hdev
= per_cpu(cpu_hpet_dev
, cpu
);
688 switch (action
& 0xf) {
690 INIT_DELAYED_WORK_ONSTACK(&work
.work
, hpet_work
);
691 init_completion(&work
.complete
);
692 /* FIXME: add schedule_work_on() */
693 schedule_delayed_work_on(cpu
, &work
.work
, 0);
694 wait_for_completion(&work
.complete
);
695 destroy_timer_on_stack(&work
.work
.timer
);
699 free_irq(hdev
->irq
, hdev
);
700 hdev
->flags
&= ~HPET_DEV_USED
;
701 per_cpu(cpu_hpet_dev
, cpu
) = NULL
;
709 static int hpet_setup_msi_irq(unsigned int irq
)
713 static void hpet_msi_capability_lookup(unsigned int start_timer
)
719 static void hpet_reserve_msi_timers(struct hpet_data
*hd
)
725 static int hpet_cpuhp_notify(struct notifier_block
*n
,
726 unsigned long action
, void *hcpu
)
734 * Clock source related code
736 static cycle_t
read_hpet(struct clocksource
*cs
)
738 return (cycle_t
)hpet_readl(HPET_COUNTER
);
742 static cycle_t __vsyscall_fn
vread_hpet(void)
744 return readl((const void __iomem
*)fix_to_virt(VSYSCALL_HPET
) + 0xf0);
748 static struct clocksource clocksource_hpet
= {
753 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
754 .resume
= hpet_resume_counter
,
756 .archdata
= { .vread
= vread_hpet
},
760 static int hpet_clocksource_register(void)
765 /* Start the counter */
766 hpet_restart_counter();
768 /* Verify whether hpet counter works */
769 t1
= hpet_readl(HPET_COUNTER
);
773 * We don't know the TSC frequency yet, but waiting for
774 * 200000 TSC cycles is safe:
781 } while ((now
- start
) < 200000UL);
783 if (t1
== hpet_readl(HPET_COUNTER
)) {
785 "HPET counter not counting. HPET disabled\n");
789 clocksource_register_hz(&clocksource_hpet
, (u32
)hpet_freq
);
794 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
796 int __init
hpet_enable(void)
798 unsigned long hpet_period
;
803 if (!is_hpet_capable())
809 * Read the period and check for a sane value:
811 hpet_period
= hpet_readl(HPET_PERIOD
);
814 * AMD SB700 based systems with spread spectrum enabled use a
815 * SMM based HPET emulation to provide proper frequency
816 * setting. The SMM code is initialized with the first HPET
817 * register access and takes some time to complete. During
818 * this time the config register reads 0xffffffff. We check
819 * for max. 1000 loops whether the config register reads a non
820 * 0xffffffff value to make sure that HPET is up and running
821 * before we go further. A counting loop is safe, as the HPET
822 * access takes thousands of CPU cycles. On non SB700 based
823 * machines this check is only done once and has no side
826 for (i
= 0; hpet_readl(HPET_CFG
) == 0xFFFFFFFF; i
++) {
829 "HPET config register value = 0xFFFFFFFF. "
835 if (hpet_period
< HPET_MIN_PERIOD
|| hpet_period
> HPET_MAX_PERIOD
)
839 * The period is a femto seconds value. Convert it to a
843 do_div(freq
, hpet_period
);
847 * Read the HPET ID register to retrieve the IRQ routing
848 * information and the number of channels
850 id
= hpet_readl(HPET_ID
);
853 #ifdef CONFIG_HPET_EMULATE_RTC
855 * The legacy routing mode needs at least two channels, tick timer
856 * and the rtc emulation channel.
858 if (!(id
& HPET_ID_NUMBER
))
862 if (hpet_clocksource_register())
865 if (id
& HPET_ID_LEGSUP
) {
866 hpet_legacy_clockevent_register();
872 hpet_clear_mapping();
878 * Needs to be late, as the reserve_timer code calls kalloc !
880 * Not a problem on i386 as hpet_enable is called from late_time_init,
881 * but on x86_64 it is necessary !
883 static __init
int hpet_late_init(void)
887 if (boot_hpet_disable
)
891 if (!force_hpet_address
)
894 hpet_address
= force_hpet_address
;
898 if (!hpet_virt_address
)
901 if (hpet_readl(HPET_ID
) & HPET_ID_LEGSUP
)
902 hpet_msi_capability_lookup(2);
904 hpet_msi_capability_lookup(0);
906 hpet_reserve_platform_timers(hpet_readl(HPET_ID
));
909 if (hpet_msi_disable
)
912 if (boot_cpu_has(X86_FEATURE_ARAT
))
915 for_each_online_cpu(cpu
) {
916 hpet_cpuhp_notify(NULL
, CPU_ONLINE
, (void *)(long)cpu
);
919 /* This notifier should be called after workqueue is ready */
920 hotcpu_notifier(hpet_cpuhp_notify
, -20);
924 fs_initcall(hpet_late_init
);
926 void hpet_disable(void)
928 if (is_hpet_capable() && hpet_virt_address
) {
929 unsigned int cfg
= hpet_readl(HPET_CFG
);
931 if (hpet_legacy_int_enabled
) {
932 cfg
&= ~HPET_CFG_LEGACY
;
933 hpet_legacy_int_enabled
= 0;
935 cfg
&= ~HPET_CFG_ENABLE
;
936 hpet_writel(cfg
, HPET_CFG
);
940 #ifdef CONFIG_HPET_EMULATE_RTC
942 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
943 * is enabled, we support RTC interrupt functionality in software.
944 * RTC has 3 kinds of interrupts:
945 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
947 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
948 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
949 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
950 * (1) and (2) above are implemented using polling at a frequency of
951 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
952 * overhead. (DEFAULT_RTC_INT_FREQ)
953 * For (3), we use interrupts at 64Hz or user specified periodic
954 * frequency, whichever is higher.
956 #include <linux/mc146818rtc.h>
957 #include <linux/rtc.h>
960 #define DEFAULT_RTC_INT_FREQ 64
961 #define DEFAULT_RTC_SHIFT 6
962 #define RTC_NUM_INTS 1
964 static unsigned long hpet_rtc_flags
;
965 static int hpet_prev_update_sec
;
966 static struct rtc_time hpet_alarm_time
;
967 static unsigned long hpet_pie_count
;
968 static u32 hpet_t1_cmp
;
969 static u32 hpet_default_delta
;
970 static u32 hpet_pie_delta
;
971 static unsigned long hpet_pie_limit
;
973 static rtc_irq_handler irq_handler
;
976 * Check that the hpet counter c1 is ahead of the c2
978 static inline int hpet_cnt_ahead(u32 c1
, u32 c2
)
980 return (s32
)(c2
- c1
) < 0;
984 * Registers a IRQ handler.
986 int hpet_register_irq_handler(rtc_irq_handler handler
)
988 if (!is_hpet_enabled())
993 irq_handler
= handler
;
997 EXPORT_SYMBOL_GPL(hpet_register_irq_handler
);
1000 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1003 void hpet_unregister_irq_handler(rtc_irq_handler handler
)
1005 if (!is_hpet_enabled())
1011 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler
);
1014 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1015 * is not supported by all HPET implementations for timer 1.
1017 * hpet_rtc_timer_init() is called when the rtc is initialized.
1019 int hpet_rtc_timer_init(void)
1021 unsigned int cfg
, cnt
, delta
;
1022 unsigned long flags
;
1024 if (!is_hpet_enabled())
1027 if (!hpet_default_delta
) {
1030 clc
= (uint64_t) hpet_clockevent
.mult
* NSEC_PER_SEC
;
1031 clc
>>= hpet_clockevent
.shift
+ DEFAULT_RTC_SHIFT
;
1032 hpet_default_delta
= clc
;
1035 if (!(hpet_rtc_flags
& RTC_PIE
) || hpet_pie_limit
)
1036 delta
= hpet_default_delta
;
1038 delta
= hpet_pie_delta
;
1040 local_irq_save(flags
);
1042 cnt
= delta
+ hpet_readl(HPET_COUNTER
);
1043 hpet_writel(cnt
, HPET_T1_CMP
);
1046 cfg
= hpet_readl(HPET_T1_CFG
);
1047 cfg
&= ~HPET_TN_PERIODIC
;
1048 cfg
|= HPET_TN_ENABLE
| HPET_TN_32BIT
;
1049 hpet_writel(cfg
, HPET_T1_CFG
);
1051 local_irq_restore(flags
);
1055 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init
);
1058 * The functions below are called from rtc driver.
1059 * Return 0 if HPET is not being used.
1060 * Otherwise do the necessary changes and return 1.
1062 int hpet_mask_rtc_irq_bit(unsigned long bit_mask
)
1064 if (!is_hpet_enabled())
1067 hpet_rtc_flags
&= ~bit_mask
;
1070 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit
);
1072 int hpet_set_rtc_irq_bit(unsigned long bit_mask
)
1074 unsigned long oldbits
= hpet_rtc_flags
;
1076 if (!is_hpet_enabled())
1079 hpet_rtc_flags
|= bit_mask
;
1081 if ((bit_mask
& RTC_UIE
) && !(oldbits
& RTC_UIE
))
1082 hpet_prev_update_sec
= -1;
1085 hpet_rtc_timer_init();
1089 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit
);
1091 int hpet_set_alarm_time(unsigned char hrs
, unsigned char min
,
1094 if (!is_hpet_enabled())
1097 hpet_alarm_time
.tm_hour
= hrs
;
1098 hpet_alarm_time
.tm_min
= min
;
1099 hpet_alarm_time
.tm_sec
= sec
;
1103 EXPORT_SYMBOL_GPL(hpet_set_alarm_time
);
1105 int hpet_set_periodic_freq(unsigned long freq
)
1109 if (!is_hpet_enabled())
1112 if (freq
<= DEFAULT_RTC_INT_FREQ
)
1113 hpet_pie_limit
= DEFAULT_RTC_INT_FREQ
/ freq
;
1115 clc
= (uint64_t) hpet_clockevent
.mult
* NSEC_PER_SEC
;
1117 clc
>>= hpet_clockevent
.shift
;
1118 hpet_pie_delta
= clc
;
1123 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq
);
1125 int hpet_rtc_dropped_irq(void)
1127 return is_hpet_enabled();
1129 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq
);
1131 static void hpet_rtc_timer_reinit(void)
1133 unsigned int cfg
, delta
;
1136 if (unlikely(!hpet_rtc_flags
)) {
1137 cfg
= hpet_readl(HPET_T1_CFG
);
1138 cfg
&= ~HPET_TN_ENABLE
;
1139 hpet_writel(cfg
, HPET_T1_CFG
);
1143 if (!(hpet_rtc_flags
& RTC_PIE
) || hpet_pie_limit
)
1144 delta
= hpet_default_delta
;
1146 delta
= hpet_pie_delta
;
1149 * Increment the comparator value until we are ahead of the
1153 hpet_t1_cmp
+= delta
;
1154 hpet_writel(hpet_t1_cmp
, HPET_T1_CMP
);
1156 } while (!hpet_cnt_ahead(hpet_t1_cmp
, hpet_readl(HPET_COUNTER
)));
1159 if (hpet_rtc_flags
& RTC_PIE
)
1160 hpet_pie_count
+= lost_ints
;
1161 if (printk_ratelimit())
1162 printk(KERN_WARNING
"hpet1: lost %d rtc interrupts\n",
1167 irqreturn_t
hpet_rtc_interrupt(int irq
, void *dev_id
)
1169 struct rtc_time curr_time
;
1170 unsigned long rtc_int_flag
= 0;
1172 hpet_rtc_timer_reinit();
1173 memset(&curr_time
, 0, sizeof(struct rtc_time
));
1175 if (hpet_rtc_flags
& (RTC_UIE
| RTC_AIE
))
1176 get_rtc_time(&curr_time
);
1178 if (hpet_rtc_flags
& RTC_UIE
&&
1179 curr_time
.tm_sec
!= hpet_prev_update_sec
) {
1180 if (hpet_prev_update_sec
>= 0)
1181 rtc_int_flag
= RTC_UF
;
1182 hpet_prev_update_sec
= curr_time
.tm_sec
;
1185 if (hpet_rtc_flags
& RTC_PIE
&&
1186 ++hpet_pie_count
>= hpet_pie_limit
) {
1187 rtc_int_flag
|= RTC_PF
;
1191 if (hpet_rtc_flags
& RTC_AIE
&&
1192 (curr_time
.tm_sec
== hpet_alarm_time
.tm_sec
) &&
1193 (curr_time
.tm_min
== hpet_alarm_time
.tm_min
) &&
1194 (curr_time
.tm_hour
== hpet_alarm_time
.tm_hour
))
1195 rtc_int_flag
|= RTC_AF
;
1198 rtc_int_flag
|= (RTC_IRQF
| (RTC_NUM_INTS
<< 8));
1200 irq_handler(rtc_int_flag
, dev_id
);
1204 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt
);