arch/x86/kernel/head_64.S

   1 /*
   2  *  linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
   3  *
   4  *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
   5  *  Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
   6  *  Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
   7  *  Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
   8  *  Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
   9  */
  10
  11
  12 #include <linux/linkage.h>
  13 #include <linux/threads.h>
  14 #include <linux/init.h>
  15 #include <asm/segment.h>
  16 #include <asm/pgtable.h>
  17 #include <asm/page.h>
  18 #include <asm/msr.h>
  19 #include <asm/cache.h>
  20 #include <asm/processor-flags.h>
  21 #include <asm/percpu.h>
  22 #include <asm/nops.h>
  23
  24 #ifdef CONFIG_PARAVIRT
  25 #include <asm/asm-offsets.h>
  26 #include <asm/paravirt.h>
  27 #define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
  28 #else
  29 #define GET_CR2_INTO(reg) movq %cr2, reg
  30 #define INTERRUPT_RETURN iretq
  31 #endif
  32
  33 /* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
  34  * because we need identity-mapped pages.
  35  *
  36  */
  37
  38 #define pud_index(x)    (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
  39
  40 L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
  41 L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
  42 L4_START_KERNEL = pgd_index(__START_KERNEL_map)
  43 L3_START_KERNEL = pud_index(__START_KERNEL_map)
  44
  45         .text
  46         __HEAD
  47         .code64
  48         .globl startup_64
  49 startup_64:
  50
  51         /*
  52          * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
  53          * and someone has loaded an identity mapped page table
  54          * for us.  These identity mapped page tables map all of the
  55          * kernel pages and possibly all of memory.
  56          *
  57          * %esi holds a physical pointer to real_mode_data.
  58          *
  59          * We come here either directly from a 64bit bootloader, or from
  60          * arch/x86_64/boot/compressed/head.S.
  61          *
  62          * We only come here initially at boot nothing else comes here.
  63          *
  64          * Since we may be loaded at an address different from what we were
  65          * compiled to run at we first fixup the physical addresses in our page
  66          * tables and then reload them.
  67          */
  68
  69         /* Compute the delta between the address I am compiled to run at and the
  70          * address I am actually running at.
  71          */
  72         leaq    _text(%rip), %rbp
  73         subq    $_text - __START_KERNEL_map, %rbp
  74
  75         /* Is the address not 2M aligned? */
  76         movq    %rbp, %rax
  77         andl    $~PMD_PAGE_MASK, %eax
  78         testl   %eax, %eax
  79         jnz     bad_address
  80
  81         /* Is the address too large? */
  82         leaq    _text(%rip), %rdx
  83         movq    $PGDIR_SIZE, %rax
  84         cmpq    %rax, %rdx
  85         jae     bad_address
  86
  87         /* Fixup the physical addresses in the page table
  88          */
  89         addq    %rbp, init_level4_pgt + 0(%rip)
  90         addq    %rbp, init_level4_pgt + (L4_PAGE_OFFSET*8)(%rip)
  91         addq    %rbp, init_level4_pgt + (L4_START_KERNEL*8)(%rip)
  92
  93         addq    %rbp, level3_ident_pgt + 0(%rip)
  94
  95         addq    %rbp, level3_kernel_pgt + (510*8)(%rip)
  96         addq    %rbp, level3_kernel_pgt + (511*8)(%rip)
  97
  98         addq    %rbp, level2_fixmap_pgt + (506*8)(%rip)
  99
 100         /* Add an Identity mapping if I am above 1G */
 101         leaq    _text(%rip), %rdi
 102         andq    $PMD_PAGE_MASK, %rdi
 103
 104         movq    %rdi, %rax
 105         shrq    $PUD_SHIFT, %rax
 106         andq    $(PTRS_PER_PUD - 1), %rax
 107         jz      ident_complete
 108
 109         leaq    (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
 110         leaq    level3_ident_pgt(%rip), %rbx
 111         movq    %rdx, 0(%rbx, %rax, 8)
 112
 113         movq    %rdi, %rax
 114         shrq    $PMD_SHIFT, %rax
 115         andq    $(PTRS_PER_PMD - 1), %rax
 116         leaq    __PAGE_KERNEL_IDENT_LARGE_EXEC(%rdi), %rdx
 117         leaq    level2_spare_pgt(%rip), %rbx
 118         movq    %rdx, 0(%rbx, %rax, 8)
 119 ident_complete:
 120
 121         /*
 122          * Fixup the kernel text+data virtual addresses. Note that
 123          * we might write invalid pmds, when the kernel is relocated
 124          * cleanup_highmap() fixes this up along with the mappings
 125          * beyond _end.
 126          */
 127
 128         leaq    level2_kernel_pgt(%rip), %rdi
 129         leaq    4096(%rdi), %r8
 130         /* See if it is a valid page table entry */
 131 1:      testq   $1, 0(%rdi)
 132         jz      2f
 133         addq    %rbp, 0(%rdi)
 134         /* Go to the next page */
 135 2:      addq    $8, %rdi
 136         cmp     %r8, %rdi
 137         jne     1b
 138
 139         /* Fixup phys_base */
 140         addq    %rbp, phys_base(%rip)
 141
 142         /* Due to ENTRY(), sometimes the empty space gets filled with
 143          * zeros. Better take a jmp than relying on empty space being
 144          * filled with 0x90 (nop)
 145          */
 146         jmp secondary_startup_64
 147 ENTRY(secondary_startup_64)
 148         /*
 149          * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
 150          * and someone has loaded a mapped page table.
 151          *
 152          * %esi holds a physical pointer to real_mode_data.
 153          *
 154          * We come here either from startup_64 (using physical addresses)
 155          * or from trampoline.S (using virtual addresses).
 156          *
 157          * Using virtual addresses from trampoline.S removes the need
 158          * to have any identity mapped pages in the kernel page table
 159          * after the boot processor executes this code.
 160          */
 161
 162         /* Enable PAE mode and PGE */
 163         movl    $(X86_CR4_PAE | X86_CR4_PGE), %eax
 164         movq    %rax, %cr4
 165
 166         /* Setup early boot stage 4 level pagetables. */
 167         movq    $(init_level4_pgt - __START_KERNEL_map), %rax
 168         addq    phys_base(%rip), %rax
 169         movq    %rax, %cr3
 170
 171         /* Ensure I am executing from virtual addresses */
 172         movq    $1f, %rax
 173         jmp     *%rax
 174 1:
 175
 176         /* Check if nx is implemented */
 177         movl    $0x80000001, %eax
 178         cpuid
 179         movl    %edx,%edi
 180
 181         /* Setup EFER (Extended Feature Enable Register) */
 182         movl    $MSR_EFER, %ecx
 183         rdmsr
 184         btsl    $_EFER_SCE, %eax        /* Enable System Call */
 185         btl     $20,%edi                /* No Execute supported? */
 186         jnc     1f
 187         btsl    $_EFER_NX, %eax
 188 1:      wrmsr                           /* Make changes effective */
 189
 190         /* Setup cr0 */
 191 #define CR0_STATE       (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
 192                          X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
 193                          X86_CR0_PG)
 194         movl    $CR0_STATE, %eax
 195         /* Make changes effective */
 196         movq    %rax, %cr0
 197
 198         /* Setup a boot time stack */
 199         movq stack_start(%rip),%rsp
 200
 201         /* zero EFLAGS after setting rsp */
 202         pushq $0
 203         popfq
 204
 205         /*
 206          * We must switch to a new descriptor in kernel space for the GDT
 207          * because soon the kernel won't have access anymore to the userspace
 208          * addresses where we're currently running on. We have to do that here
 209          * because in 32bit we couldn't load a 64bit linear address.
 210          */
 211         lgdt    early_gdt_descr(%rip)
 212
 213         /* set up data segments */
 214         xorl %eax,%eax
 215         movl %eax,%ds
 216         movl %eax,%ss
 217         movl %eax,%es
 218
 219         /*
 220          * We don't really need to load %fs or %gs, but load them anyway
 221          * to kill any stale realmode selectors.  This allows execution
 222          * under VT hardware.
 223          */
 224         movl %eax,%fs
 225         movl %eax,%gs
 226
 227         /* Set up %gs.
 228          *
 229          * The base of %gs always points to the bottom of the irqstack
 230          * union.  If the stack protector canary is enabled, it is
 231          * located at %gs:40.  Note that, on SMP, the boot cpu uses
 232          * init data section till per cpu areas are set up.
 233          */
 234         movl    $MSR_GS_BASE,%ecx
 235         movl    initial_gs(%rip),%eax
 236         movl    initial_gs+4(%rip),%edx
 237         wrmsr
 238
 239         /* esi is pointer to real mode structure with interesting info.
 240            pass it to C */
 241         movl    %esi, %edi
 242
 243         /* Finally jump to run C code and to be on real kernel address
 244          * Since we are running on identity-mapped space we have to jump
 245          * to the full 64bit address, this is only possible as indirect
 246          * jump.  In addition we need to ensure %cs is set so we make this
 247          * a far return.
 248          */
 249         movq    initial_code(%rip),%rax
 250         pushq   $0              # fake return address to stop unwinder
 251         pushq   $__KERNEL_CS    # set correct cs
 252         pushq   %rax            # target address in negative space
 253         lretq
 254
 255         /* SMP bootup changes these two */
 256         __REFDATA
 257         .align  8
 258         ENTRY(initial_code)
 259         .quad   x86_64_start_kernel
 260         ENTRY(initial_gs)
 261         .quad   INIT_PER_CPU_VAR(irq_stack_union)
 262
 263         ENTRY(stack_start)
 264         .quad  init_thread_union+THREAD_SIZE-8
 265         .word  0
 266         __FINITDATA
 267
 268 bad_address:
 269         jmp bad_address
 270
 271         .section ".init.text","ax"
 272         .globl early_idt_handlers
 273 early_idt_handlers:
 274         # 104(%rsp) %rflags
 275         #  96(%rsp) %cs
 276         #  88(%rsp) %rip
 277         #  80(%rsp) error code
 278         i = 0
 279         .rept NUM_EXCEPTION_VECTORS
 280         .if (EXCEPTION_ERRCODE_MASK >> i) & 1
 281         ASM_NOP2
 282         .else
 283         pushq $0                # Dummy error code, to make stack frame uniform
 284         .endif
 285         pushq $i                # 72(%rsp) Vector number
 286         jmp early_idt_handler
 287         i = i + 1
 288         .endr
 289
 290 ENTRY(early_idt_handler)
 291         cld
 292
 293         cmpl $2,early_recursion_flag(%rip)
 294         jz  1f
 295         incl early_recursion_flag(%rip)
 296
 297         pushq %rax              # 64(%rsp)
 298         pushq %rcx              # 56(%rsp)
 299         pushq %rdx              # 48(%rsp)
 300         pushq %rsi              # 40(%rsp)
 301         pushq %rdi              # 32(%rsp)
 302         pushq %r8               # 24(%rsp)
 303         pushq %r9               # 16(%rsp)
 304         pushq %r10              #  8(%rsp)
 305         pushq %r11              #  0(%rsp)
 306
 307         cmpl $__KERNEL_CS,96(%rsp)
 308         jne 10f
 309
 310         leaq 88(%rsp),%rdi      # Pointer to %rip
 311         call early_fixup_exception
 312         andl %eax,%eax
 313         jnz 20f                 # Found an exception entry
 314
 315 10:
 316 #ifdef CONFIG_EARLY_PRINTK
 317         GET_CR2_INTO(%r9)       # can clobber any volatile register if pv
 318         movl 80(%rsp),%r8d      # error code
 319         movl 72(%rsp),%esi      # vector number
 320         movl 96(%rsp),%edx      # %cs
 321         movq 88(%rsp),%rcx      # %rip
 322         xorl %eax,%eax
 323         leaq early_idt_msg(%rip),%rdi
 324         call early_printk
 325         cmpl $2,early_recursion_flag(%rip)
 326         jz  1f
 327         call dump_stack
 328 #ifdef CONFIG_KALLSYMS
 329         leaq early_idt_ripmsg(%rip),%rdi
 330         movq 40(%rsp),%rsi      # %rip again
 331         call __print_symbol
 332 #endif
 333 #endif /* EARLY_PRINTK */
 334 1:      hlt
 335         jmp 1b
 336
 337 20:     # Exception table entry found
 338         popq %r11
 339         popq %r10
 340         popq %r9
 341         popq %r8
 342         popq %rdi
 343         popq %rsi
 344         popq %rdx
 345         popq %rcx
 346         popq %rax
 347         addq $16,%rsp           # drop vector number and error code
 348         decl early_recursion_flag(%rip)
 349         INTERRUPT_RETURN
 350
 351         .balign 4
 352 early_recursion_flag:
 353         .long 0
 354
 355 #ifdef CONFIG_EARLY_PRINTK
 356 early_idt_msg:
 357         .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
 358 early_idt_ripmsg:
 359         .asciz "RIP %s\n"
 360 #endif /* CONFIG_EARLY_PRINTK */
 361         .previous
 362
 363 #define NEXT_PAGE(name) \
 364         .balign PAGE_SIZE; \
 365 ENTRY(name)
 366
 367 /* Automate the creation of 1 to 1 mapping pmd entries */
 368 #define PMDS(START, PERM, COUNT)                        \
 369         i = 0 ;                                         \
 370         .rept (COUNT) ;                                 \
 371         .quad   (START) + (i << PMD_SHIFT) + (PERM) ;   \
 372         i = i + 1 ;                                     \
 373         .endr
 374
 375         .data
 376         /*
 377          * This default setting generates an ident mapping at address 0x100000
 378          * and a mapping for the kernel that precisely maps virtual address
 379          * 0xffffffff80000000 to physical address 0x000000. (always using
 380          * 2Mbyte large pages provided by PAE mode)
 381          */
 382 NEXT_PAGE(init_level4_pgt)
 383         .quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
 384         .org    init_level4_pgt + L4_PAGE_OFFSET*8, 0
 385         .quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
 386         .org    init_level4_pgt + L4_START_KERNEL*8, 0
 387         /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
 388         .quad   level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
 389
 390 NEXT_PAGE(level3_ident_pgt)
 391         .quad   level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
 392         .fill   511,8,0
 393
 394 NEXT_PAGE(level3_kernel_pgt)
 395         .fill   L3_START_KERNEL,8,0
 396         /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
 397         .quad   level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
 398         .quad   level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
 399
 400 NEXT_PAGE(level2_fixmap_pgt)
 401         .fill   506,8,0
 402         .quad   level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
 403         /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
 404         .fill   5,8,0
 405
 406 NEXT_PAGE(level1_fixmap_pgt)
 407         .fill   512,8,0
 408
 409 NEXT_PAGE(level2_ident_pgt)
 410         /* Since I easily can, map the first 1G.
 411          * Don't set NX because code runs from these pages.
 412          */
 413         PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
 414
 415 NEXT_PAGE(level2_kernel_pgt)
 416         /*
 417          * 512 MB kernel mapping. We spend a full page on this pagetable
 418          * anyway.
 419          *
 420          * The kernel code+data+bss must not be bigger than that.
 421          *
 422          * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
 423          *  If you want to increase this then increase MODULES_VADDR
 424          *  too.)
 425          */
 426         PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
 427                 KERNEL_IMAGE_SIZE/PMD_SIZE)
 428
 429 NEXT_PAGE(level2_spare_pgt)
 430         .fill   512, 8, 0
 431
 432 #undef PMDS
 433 #undef NEXT_PAGE
 434
 435         .data
 436         .align 16
 437         .globl early_gdt_descr
 438 early_gdt_descr:
 439         .word   GDT_ENTRIES*8-1
 440 early_gdt_descr_base:
 441         .quad   INIT_PER_CPU_VAR(gdt_page)
 442
 443 ENTRY(phys_base)
 444         /* This must match the first entry in level2_kernel_pgt */
 445         .quad   0x0000000000000000
 446
 447 #include "../../x86/xen/xen-head.S"
 448
 449         .section .bss, "aw", @nobits
 450         .align L1_CACHE_BYTES
 451 ENTRY(idt_table)
 452         .skip IDT_ENTRIES * 16
 453
 454         .align L1_CACHE_BYTES
 455 ENTRY(nmi_idt_table)
 456         .skip IDT_ENTRIES * 16
 457
 458         __PAGE_ALIGNED_BSS
 459         .align PAGE_SIZE
 460 ENTRY(empty_zero_page)
 461         .skip PAGE_SIZE