arch/x86/kernel/genx2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/threads.h>
  13 #include <linux/cpumask.h>
  14 #include <linux/string.h>
  15 #include <linux/ctype.h>
  16 #include <linux/init.h>
  17 #include <linux/sched.h>
  18 #include <linux/bootmem.h>
  19 #include <linux/module.h>
  20 #include <linux/hardirq.h>
  21 #include <asm/smp.h>
  22 #include <asm/ipi.h>
  23 #include <asm/genapic.h>
  24 #include <asm/pgtable.h>
  25 #include <asm/uv/uv_mmrs.h>
  26 #include <asm/uv/uv_hub.h>
  27 #include <asm/uv/bios.h>
  28
  29 DEFINE_PER_CPU(int, x2apic_extra_bits);
  30
  31 static enum uv_system_type uv_system_type;
  32
  33 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  34 {
  35         if (!strcmp(oem_id, "SGI")) {
  36                 if (!strcmp(oem_table_id, "UVL"))
  37                         uv_system_type = UV_LEGACY_APIC;
  38                 else if (!strcmp(oem_table_id, "UVX"))
  39                         uv_system_type = UV_X2APIC;
  40                 else if (!strcmp(oem_table_id, "UVH")) {
  41                         uv_system_type = UV_NON_UNIQUE_APIC;
  42                         return 1;
  43                 }
  44         }
  45         return 0;
  46 }
  47
  48 enum uv_system_type get_uv_system_type(void)
  49 {
  50         return uv_system_type;
  51 }
  52
  53 int is_uv_system(void)
  54 {
  55         return uv_system_type != UV_NONE;
  56 }
  57 EXPORT_SYMBOL_GPL(is_uv_system);
  58
  59 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  60 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  61
  62 struct uv_blade_info *uv_blade_info;
  63 EXPORT_SYMBOL_GPL(uv_blade_info);
  64
  65 short *uv_node_to_blade;
  66 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  67
  68 short *uv_cpu_to_blade;
  69 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
  70
  71 short uv_possible_blades;
  72 EXPORT_SYMBOL_GPL(uv_possible_blades);
  73
  74 unsigned long sn_rtc_cycles_per_second;
  75 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
  76
  77 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  78
  79 static cpumask_t uv_target_cpus(void)
  80 {
  81         return cpumask_of_cpu(0);
  82 }
  83
  84 static cpumask_t uv_vector_allocation_domain(int cpu)
  85 {
  86         cpumask_t domain = CPU_MASK_NONE;
  87         cpu_set(cpu, domain);
  88         return domain;
  89 }
  90
  91 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
  92 {
  93         unsigned long val;
  94         int pnode;
  95
  96         pnode = uv_apicid_to_pnode(phys_apicid);
  97         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
  98             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
  99             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 100             APIC_DM_INIT;
 101         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 102         mdelay(10);
 103
 104         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 105             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 106             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 107             APIC_DM_STARTUP;
 108         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 109         return 0;
 110 }
 111
 112 static void uv_send_IPI_one(int cpu, int vector)
 113 {
 114         unsigned long val, apicid, lapicid;
 115         int pnode;
 116
 117         apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
 118         lapicid = apicid & 0x3f;                /* ZZZ macro needed */
 119         pnode = uv_apicid_to_pnode(apicid);
 120         val =
 121             (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
 122                                               UVH_IPI_INT_APIC_ID_SHFT) |
 123             (vector << UVH_IPI_INT_VECTOR_SHFT);
 124         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 125 }
 126
 127 static void uv_send_IPI_mask(cpumask_t mask, int vector)
 128 {
 129         unsigned int cpu;
 130
 131         for_each_possible_cpu(cpu)
 132                 if (cpu_isset(cpu, mask))
 133                         uv_send_IPI_one(cpu, vector);
 134 }
 135
 136 static void uv_send_IPI_allbutself(int vector)
 137 {
 138         cpumask_t mask = cpu_online_map;
 139
 140         cpu_clear(smp_processor_id(), mask);
 141
 142         if (!cpus_empty(mask))
 143                 uv_send_IPI_mask(mask, vector);
 144 }
 145
 146 static void uv_send_IPI_all(int vector)
 147 {
 148         uv_send_IPI_mask(cpu_online_map, vector);
 149 }
 150
 151 static int uv_apic_id_registered(void)
 152 {
 153         return 1;
 154 }
 155
 156 static void uv_init_apic_ldr(void)
 157 {
 158 }
 159
 160 static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
 161 {
 162         int cpu;
 163
 164         /*
 165          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 166          * May as well be the first.
 167          */
 168         cpu = first_cpu(cpumask);
 169         if ((unsigned)cpu < nr_cpu_ids)
 170                 return per_cpu(x86_cpu_to_apicid, cpu);
 171         else
 172                 return BAD_APICID;
 173 }
 174
 175 static unsigned int get_apic_id(unsigned long x)
 176 {
 177         unsigned int id;
 178
 179         WARN_ON(preemptible() && num_online_cpus() > 1);
 180         id = x | __get_cpu_var(x2apic_extra_bits);
 181
 182         return id;
 183 }
 184
 185 static unsigned long set_apic_id(unsigned int id)
 186 {
 187         unsigned long x;
 188
 189         /* maskout x2apic_extra_bits ? */
 190         x = id;
 191         return x;
 192 }
 193
 194 static unsigned int uv_read_apic_id(void)
 195 {
 196
 197         return get_apic_id(apic_read(APIC_ID));
 198 }
 199
 200 static unsigned int phys_pkg_id(int index_msb)
 201 {
 202         return uv_read_apic_id() >> index_msb;
 203 }
 204
 205 #ifdef ZZZ              /* Needs x2apic patch */
 206 static void uv_send_IPI_self(int vector)
 207 {
 208         apic_write(APIC_SELF_IPI, vector);
 209 }
 210 #endif
 211
 212 struct genapic apic_x2apic_uv_x = {
 213         .name = "UV large system",
 214         .acpi_madt_oem_check = uv_acpi_madt_oem_check,
 215         .int_delivery_mode = dest_Fixed,
 216         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
 217         .target_cpus = uv_target_cpus,
 218         .vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
 219         .apic_id_registered = uv_apic_id_registered,
 220         .init_apic_ldr = uv_init_apic_ldr,
 221         .send_IPI_all = uv_send_IPI_all,
 222         .send_IPI_allbutself = uv_send_IPI_allbutself,
 223         .send_IPI_mask = uv_send_IPI_mask,
 224         /* ZZZ.send_IPI_self = uv_send_IPI_self, */
 225         .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
 226         .phys_pkg_id = phys_pkg_id,     /* Fixme ZZZ */
 227         .get_apic_id = get_apic_id,
 228         .set_apic_id = set_apic_id,
 229         .apic_id_mask = (0xFFFFFFFFu),
 230 };
 231
 232 static __cpuinit void set_x2apic_extra_bits(int pnode)
 233 {
 234         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 235 }
 236
 237 /*
 238  * Called on boot cpu.
 239  */
 240 static __init int boot_pnode_to_blade(int pnode)
 241 {
 242         int blade;
 243
 244         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 245                 if (pnode == uv_blade_info[blade].pnode)
 246                         return blade;
 247         BUG();
 248 }
 249
 250 struct redir_addr {
 251         unsigned long redirect;
 252         unsigned long alias;
 253 };
 254
 255 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 256
 257 static __initdata struct redir_addr redir_addrs[] = {
 258         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 259         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 260         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 261 };
 262
 263 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 264 {
 265         union uvh_si_alias0_overlay_config_u alias;
 266         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 267         int i;
 268
 269         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 270                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 271                 if (alias.s.base == 0) {
 272                         *size = (1UL << alias.s.m_alias);
 273                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 274                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 275                         return;
 276                 }
 277         }
 278         BUG();
 279 }
 280
 281 static __init void map_low_mmrs(void)
 282 {
 283         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 284         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 285 }
 286
 287 enum map_type {map_wb, map_uc};
 288
 289 static __init void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
 290 {
 291         unsigned long bytes, paddr;
 292
 293         paddr = base << shift;
 294         bytes = (1UL << shift);
 295         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 296                                                 paddr + bytes);
 297         if (map_type == map_uc)
 298                 init_extra_mapping_uc(paddr, bytes);
 299         else
 300                 init_extra_mapping_wb(paddr, bytes);
 301
 302 }
 303 static __init void map_gru_high(int max_pnode)
 304 {
 305         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 306         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 307
 308         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 309         if (gru.s.enable)
 310                 map_high("GRU", gru.s.base, shift, map_wb);
 311 }
 312
 313 static __init void map_config_high(int max_pnode)
 314 {
 315         union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
 316         int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
 317
 318         cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
 319         if (cfg.s.enable)
 320                 map_high("CONFIG", cfg.s.base, shift, map_uc);
 321 }
 322
 323 static __init void map_mmr_high(int max_pnode)
 324 {
 325         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 326         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 327
 328         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 329         if (mmr.s.enable)
 330                 map_high("MMR", mmr.s.base, shift, map_uc);
 331 }
 332
 333 static __init void map_mmioh_high(int max_pnode)
 334 {
 335         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 336         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 337
 338         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 339         if (mmioh.s.enable)
 340                 map_high("MMIOH", mmioh.s.base, shift, map_uc);
 341 }
 342
 343 static __init void uv_rtc_init(void)
 344 {
 345         long status, ticks_per_sec, drift;
 346
 347         status =
 348             x86_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec,
 349                                         &drift);
 350         if (status != 0 || ticks_per_sec < 100000) {
 351                 printk(KERN_WARNING
 352                         "unable to determine platform RTC clock frequency, "
 353                         "guessing.\n");
 354                 /* BIOS gives wrong value for clock freq. so guess */
 355                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 356         } else
 357                 sn_rtc_cycles_per_second = ticks_per_sec;
 358 }
 359
 360 static bool uv_system_inited;
 361
 362 void __init uv_system_init(void)
 363 {
 364         union uvh_si_addr_map_config_u m_n_config;
 365         union uvh_node_id_u node_id;
 366         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 367         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 368         int max_pnode = 0;
 369         unsigned long mmr_base, present;
 370
 371         map_low_mmrs();
 372
 373         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 374         m_val = m_n_config.s.m_skt;
 375         n_val = m_n_config.s.n_skt;
 376         mmr_base =
 377             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 378             ~UV_MMR_ENABLE;
 379         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 380
 381         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 382                 uv_possible_blades +=
 383                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 384         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 385
 386         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 387         uv_blade_info = alloc_bootmem_pages(bytes);
 388
 389         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 390
 391         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 392         uv_node_to_blade = alloc_bootmem_pages(bytes);
 393         memset(uv_node_to_blade, 255, bytes);
 394
 395         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 396         uv_cpu_to_blade = alloc_bootmem_pages(bytes);
 397         memset(uv_cpu_to_blade, 255, bytes);
 398
 399         blade = 0;
 400         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 401                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 402                 for (j = 0; j < 64; j++) {
 403                         if (!test_bit(j, &present))
 404                                 continue;
 405                         uv_blade_info[blade].pnode = (i * 64 + j);
 406                         uv_blade_info[blade].nr_possible_cpus = 0;
 407                         uv_blade_info[blade].nr_online_cpus = 0;
 408                         blade++;
 409                 }
 410         }
 411
 412         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 413         gnode_upper = (((unsigned long)node_id.s.node_id) &
 414                        ~((1 << n_val) - 1)) << m_val;
 415
 416         uv_rtc_init();
 417
 418         for_each_present_cpu(cpu) {
 419                 nid = cpu_to_node(cpu);
 420                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
 421                 blade = boot_pnode_to_blade(pnode);
 422                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 423                 uv_blade_info[blade].nr_possible_cpus++;
 424
 425                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 426                 uv_cpu_hub_info(cpu)->lowmem_remap_top =
 427                                         lowmem_redir_base + lowmem_redir_size;
 428                 uv_cpu_hub_info(cpu)->m_val = m_val;
 429                 uv_cpu_hub_info(cpu)->n_val = m_val;
 430                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 431                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 432                 uv_cpu_hub_info(cpu)->pnode = pnode;
 433                 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
 434                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
 435                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 436                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 437                 uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
 438                 uv_node_to_blade[nid] = blade;
 439                 uv_cpu_to_blade[cpu] = blade;
 440                 max_pnode = max(pnode, max_pnode);
 441
 442                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
 443                         "lcpu %d, blade %d\n",
 444                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
 445                         lcpu, blade);
 446         }
 447
 448         map_gru_high(max_pnode);
 449         map_mmr_high(max_pnode);
 450         map_config_high(max_pnode);
 451         map_mmioh_high(max_pnode);
 452         uv_system_inited = true;
 453 }
 454
 455 /*
 456  * Called on each cpu to initialize the per_cpu UV data area.
 457  *      ZZZ hotplug not supported yet
 458  */
 459 void __cpuinit uv_cpu_init(void)
 460 {
 461         BUG_ON(!uv_system_inited);
 462
 463         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 464
 465         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 466                 set_x2apic_extra_bits(uv_hub_info->pnode);
 467 }
 468
 469