Merge branches 'x86/urgent', 'x86/amd-iommu', 'x86/apic', 'x86/cleanups', 'x86/core...
[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / arch / x86 / kernel / early-quirks.c
1 /* Various workarounds for chipset bugs.
2 This code runs very early and can't use the regular PCI subsystem
3 The entries are keyed to PCI bridges which usually identify chipsets
4 uniquely.
5 This is only for whole classes of chipsets with specific problems which
6 need early invasive action (e.g. before the timers are initialized).
7 Most PCI device specific workarounds can be done later and should be
8 in standard PCI quirks
9 Mainboard specific bugs should be handled by DMI entries.
10 CPU specific bugs in setup.c */
11
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/pci_ids.h>
15 #include <asm/pci-direct.h>
16 #include <asm/dma.h>
17 #include <asm/io_apic.h>
18 #include <asm/apic.h>
19 #include <asm/iommu.h>
20
21 static void __init fix_hypertransport_config(int num, int slot, int func)
22 {
23 u32 htcfg;
24 /*
25 * we found a hypertransport bus
26 * make sure that we are broadcasting
27 * interrupts to all cpus on the ht bus
28 * if we're using extended apic ids
29 */
30 htcfg = read_pci_config(num, slot, func, 0x68);
31 if (htcfg & (1 << 18)) {
32 printk(KERN_INFO "Detected use of extended apic ids "
33 "on hypertransport bus\n");
34 if ((htcfg & (1 << 17)) == 0) {
35 printk(KERN_INFO "Enabling hypertransport extended "
36 "apic interrupt broadcast\n");
37 printk(KERN_INFO "Note this is a bios bug, "
38 "please contact your hw vendor\n");
39 htcfg |= (1 << 17);
40 write_pci_config(num, slot, func, 0x68, htcfg);
41 }
42 }
43
44
45 }
46
47 static void __init via_bugs(int num, int slot, int func)
48 {
49 #ifdef CONFIG_GART_IOMMU
50 if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
51 !gart_iommu_aperture_allowed) {
52 printk(KERN_INFO
53 "Looks like a VIA chipset. Disabling IOMMU."
54 " Override with iommu=allowed\n");
55 gart_iommu_aperture_disabled = 1;
56 }
57 #endif
58 }
59
60 #ifdef CONFIG_ACPI
61 #ifdef CONFIG_X86_IO_APIC
62
63 static int __init nvidia_hpet_check(struct acpi_table_header *header)
64 {
65 return 0;
66 }
67 #endif /* CONFIG_X86_IO_APIC */
68 #endif /* CONFIG_ACPI */
69
70 static void __init nvidia_bugs(int num, int slot, int func)
71 {
72 #ifdef CONFIG_ACPI
73 #ifdef CONFIG_X86_IO_APIC
74 /*
75 * All timer overrides on Nvidia are
76 * wrong unless HPET is enabled.
77 * Unfortunately that's not true on many Asus boards.
78 * We don't know yet how to detect this automatically, but
79 * at least allow a command line override.
80 */
81 if (acpi_use_timer_override)
82 return;
83
84 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
85 acpi_skip_timer_override = 1;
86 printk(KERN_INFO "Nvidia board "
87 "detected. Ignoring ACPI "
88 "timer override.\n");
89 printk(KERN_INFO "If you got timer trouble "
90 "try acpi_use_timer_override\n");
91 }
92 #endif
93 #endif
94 /* RED-PEN skip them on mptables too? */
95
96 }
97
98 #define QFLAG_APPLY_ONCE 0x1
99 #define QFLAG_APPLIED 0x2
100 #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
101 struct chipset {
102 u32 vendor;
103 u32 device;
104 u32 class;
105 u32 class_mask;
106 u32 flags;
107 void (*f)(int num, int slot, int func);
108 };
109
110 static struct chipset early_qrk[] __initdata = {
111 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
112 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
113 { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
114 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
115 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
116 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
117 {}
118 };
119
120 /**
121 * check_dev_quirk - apply early quirks to a given PCI device
122 * @num: bus number
123 * @slot: slot number
124 * @func: PCI function
125 *
126 * Check the vendor & device ID against the early quirks table.
127 *
128 * If the device is single function, let early_quirks() know so we don't
129 * poke at this device again.
130 */
131 static int __init check_dev_quirk(int num, int slot, int func)
132 {
133 u16 class;
134 u16 vendor;
135 u16 device;
136 u8 type;
137 int i;
138
139 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
140
141 if (class == 0xffff)
142 return -1; /* no class, treat as single function */
143
144 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
145
146 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
147
148 for (i = 0; early_qrk[i].f != NULL; i++) {
149 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
150 (early_qrk[i].vendor == vendor)) &&
151 ((early_qrk[i].device == PCI_ANY_ID) ||
152 (early_qrk[i].device == device)) &&
153 (!((early_qrk[i].class ^ class) &
154 early_qrk[i].class_mask))) {
155 if ((early_qrk[i].flags &
156 QFLAG_DONE) != QFLAG_DONE)
157 early_qrk[i].f(num, slot, func);
158 early_qrk[i].flags |= QFLAG_APPLIED;
159 }
160 }
161
162 type = read_pci_config_byte(num, slot, func,
163 PCI_HEADER_TYPE);
164 if (!(type & 0x80))
165 return -1;
166
167 return 0;
168 }
169
170 void __init early_quirks(void)
171 {
172 int num, slot, func;
173
174 if (!early_pci_allowed())
175 return;
176
177 /* Poor man's PCI discovery */
178 for (num = 0; num < 32; num++)
179 for (slot = 0; slot < 32; slot++)
180 for (func = 0; func < 8; func++) {
181 /* Only probe function 0 on single fn devices */
182 if (check_dev_quirk(num, slot, func))
183 break;
184 }
185 }