arch/x86/kernel/cpu/common_64.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3 #include <linux/sched.h>
   4 #include <linux/string.h>
   5 #include <linux/bootmem.h>
   6 #include <linux/bitops.h>
   7 #include <linux/module.h>
   8 #include <linux/kgdb.h>
   9 #include <linux/topology.h>
  10 #include <linux/string.h>
  11 #include <linux/delay.h>
  12 #include <linux/smp.h>
  13 #include <linux/module.h>
  14 #include <linux/percpu.h>
  15 #include <asm/processor.h>
  16 #include <asm/i387.h>
  17 #include <asm/msr.h>
  18 #include <asm/io.h>
  19 #include <asm/mmu_context.h>
  20 #include <asm/mtrr.h>
  21 #include <asm/mce.h>
  22 #include <asm/pat.h>
  23 #include <asm/numa.h>
  24 #ifdef CONFIG_X86_LOCAL_APIC
  25 #include <asm/mpspec.h>
  26 #include <asm/apic.h>
  27 #include <mach_apic.h>
  28 #endif
  29 #include <asm/pda.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/processor.h>
  32 #include <asm/desc.h>
  33 #include <asm/atomic.h>
  34 #include <asm/proto.h>
  35 #include <asm/sections.h>
  36 #include <asm/setup.h>
  37 #include <asm/genapic.h>
  38
  39 #include "cpu.h"
  40
  41 /* We need valid kernel segments for data and code in long mode too
  42  * IRET will check the segment types  kkeil 2000/10/28
  43  * Also sysret mandates a special GDT layout
  44  */
  45 /* The TLS descriptors are currently at a different place compared to i386.
  46    Hopefully nobody expects them at a fixed place (Wine?) */
  47 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
  48         [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
  49         [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
  50         [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
  51         [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
  52         [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
  53         [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
  54 } };
  55 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
  56
  57 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
  58
  59 /* Current gdt points %fs at the "master" per-cpu area: after this,
  60  * it's on the real one. */
  61 void switch_to_new_gdt(void)
  62 {
  63         struct desc_ptr gdt_descr;
  64
  65         gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
  66         gdt_descr.size = GDT_SIZE - 1;
  67         load_gdt(&gdt_descr);
  68 }
  69
  70 struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
  71
  72 static void __cpuinit default_init(struct cpuinfo_x86 *c)
  73 {
  74         display_cacheinfo(c);
  75 }
  76
  77 static struct cpu_dev __cpuinitdata default_cpu = {
  78         .c_init = default_init,
  79         .c_vendor = "Unknown",
  80 };
  81 static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
  82
  83 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
  84 {
  85         unsigned int *v;
  86
  87         if (c->extended_cpuid_level < 0x80000004)
  88                 return 0;
  89
  90         v = (unsigned int *) c->x86_model_id;
  91         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
  92         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
  93         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
  94         c->x86_model_id[48] = 0;
  95         return 1;
  96 }
  97
  98
  99 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 100 {
 101         unsigned int n, dummy, eax, ebx, ecx, edx;
 102
 103         n = c->extended_cpuid_level;
 104
 105         if (n >= 0x80000005) {
 106                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
 107                 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
 108                        "D cache %dK (%d bytes/line)\n",
 109                        edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
 110                 c->x86_cache_size = (ecx>>24) + (edx>>24);
 111                 /* On K8 L1 TLB is inclusive, so don't count it */
 112                 c->x86_tlbsize = 0;
 113         }
 114
 115         if (n >= 0x80000006) {
 116                 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
 117                 ecx = cpuid_ecx(0x80000006);
 118                 c->x86_cache_size = ecx >> 16;
 119                 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
 120
 121                 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
 122                 c->x86_cache_size, ecx & 0xFF);
 123         }
 124         if (n >= 0x80000008) {
 125                 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
 126                 c->x86_virt_bits = (eax >> 8) & 0xff;
 127                 c->x86_phys_bits = eax & 0xff;
 128         }
 129 }
 130
 131 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 132 {
 133 #ifdef CONFIG_SMP
 134         u32 eax, ebx, ecx, edx;
 135         int index_msb, core_bits;
 136
 137         cpuid(1, &eax, &ebx, &ecx, &edx);
 138
 139
 140         if (!cpu_has(c, X86_FEATURE_HT))
 141                 return;
 142         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
 143                 goto out;
 144
 145         smp_num_siblings = (ebx & 0xff0000) >> 16;
 146
 147         if (smp_num_siblings == 1) {
 148                 printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
 149         } else if (smp_num_siblings > 1) {
 150
 151                 if (smp_num_siblings > NR_CPUS) {
 152                         printk(KERN_WARNING "CPU: Unsupported number of "
 153                                "siblings %d", smp_num_siblings);
 154                         smp_num_siblings = 1;
 155                         return;
 156                 }
 157
 158                 index_msb = get_count_order(smp_num_siblings);
 159                 c->phys_proc_id = phys_pkg_id(index_msb);
 160
 161                 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
 162
 163                 index_msb = get_count_order(smp_num_siblings);
 164
 165                 core_bits = get_count_order(c->x86_max_cores);
 166
 167                 c->cpu_core_id = phys_pkg_id(index_msb) &
 168                                                ((1 << core_bits) - 1);
 169         }
 170 out:
 171         if ((c->x86_max_cores * smp_num_siblings) > 1) {
 172                 printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
 173                        c->phys_proc_id);
 174                 printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
 175                        c->cpu_core_id);
 176         }
 177
 178 #endif
 179 }
 180
 181 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
 182 {
 183         char *v = c->x86_vendor_id;
 184         int i;
 185         static int printed;
 186
 187         for (i = 0; i < X86_VENDOR_NUM; i++) {
 188                 if (cpu_devs[i]) {
 189                         if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
 190                             (cpu_devs[i]->c_ident[1] &&
 191                             !strcmp(v, cpu_devs[i]->c_ident[1]))) {
 192                                 c->x86_vendor = i;
 193                                 this_cpu = cpu_devs[i];
 194                                 return;
 195                         }
 196                 }
 197         }
 198         if (!printed) {
 199                 printed++;
 200                 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
 201                 printk(KERN_ERR "CPU: Your system may be unstable.\n");
 202         }
 203         c->x86_vendor = X86_VENDOR_UNKNOWN;
 204 }
 205
 206 static void __init early_cpu_support_print(void)
 207 {
 208         int i,j;
 209         struct cpu_dev *cpu_devx;
 210
 211         printk("KERNEL supported cpus:\n");
 212         for (i = 0; i < X86_VENDOR_NUM; i++) {
 213                 cpu_devx = cpu_devs[i];
 214                 if (!cpu_devx)
 215                         continue;
 216                 for (j = 0; j < 2; j++) {
 217                         if (!cpu_devx->c_ident[j])
 218                                 continue;
 219                         printk("  %s %s\n", cpu_devx->c_vendor,
 220                                 cpu_devx->c_ident[j]);
 221                 }
 222         }
 223 }
 224
 225 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
 226
 227 void __init early_cpu_init(void)
 228 {
 229         struct cpu_vendor_dev *cvdev;
 230
 231         for (cvdev = __x86cpuvendor_start ;
 232              cvdev < __x86cpuvendor_end   ;
 233              cvdev++)
 234                 cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
 235         early_cpu_support_print();
 236         early_identify_cpu(&boot_cpu_data);
 237 }
 238
 239 /* Do some early cpuid on the boot CPU to get some parameter that are
 240    needed before check_bugs. Everything advanced is in identify_cpu
 241    below. */
 242 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
 243 {
 244         u32 tfms, xlvl;
 245
 246         c->loops_per_jiffy = loops_per_jiffy;
 247         c->x86_cache_size = -1;
 248         c->x86_vendor = X86_VENDOR_UNKNOWN;
 249         c->x86_model = c->x86_mask = 0; /* So far unknown... */
 250         c->x86_vendor_id[0] = '\0'; /* Unset */
 251         c->x86_model_id[0] = '\0';  /* Unset */
 252         c->x86_clflush_size = 64;
 253         c->x86_cache_alignment = c->x86_clflush_size;
 254         c->x86_max_cores = 1;
 255         c->x86_coreid_bits = 0;
 256         c->extended_cpuid_level = 0;
 257         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 258
 259         /* Get vendor name */
 260         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
 261               (unsigned int *)&c->x86_vendor_id[0],
 262               (unsigned int *)&c->x86_vendor_id[8],
 263               (unsigned int *)&c->x86_vendor_id[4]);
 264
 265         get_cpu_vendor(c);
 266
 267         /* Initialize the standard set of capabilities */
 268         /* Note that the vendor-specific code below might override */
 269
 270         /* Intel-defined flags: level 0x00000001 */
 271         if (c->cpuid_level >= 0x00000001) {
 272                 __u32 misc;
 273                 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
 274                       &c->x86_capability[0]);
 275                 c->x86 = (tfms >> 8) & 0xf;
 276                 c->x86_model = (tfms >> 4) & 0xf;
 277                 c->x86_mask = tfms & 0xf;
 278                 if (c->x86 == 0xf)
 279                         c->x86 += (tfms >> 20) & 0xff;
 280                 if (c->x86 >= 0x6)
 281                         c->x86_model += ((tfms >> 16) & 0xF) << 4;
 282                 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
 283                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
 284         } else {
 285                 /* Have CPUID level 0 only - unheard of */
 286                 c->x86 = 4;
 287         }
 288
 289         c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
 290 #ifdef CONFIG_SMP
 291         c->phys_proc_id = c->initial_apicid;
 292 #endif
 293         /* AMD-defined flags: level 0x80000001 */
 294         xlvl = cpuid_eax(0x80000000);
 295         c->extended_cpuid_level = xlvl;
 296         if ((xlvl & 0xffff0000) == 0x80000000) {
 297                 if (xlvl >= 0x80000001) {
 298                         c->x86_capability[1] = cpuid_edx(0x80000001);
 299                         c->x86_capability[6] = cpuid_ecx(0x80000001);
 300                 }
 301                 if (xlvl >= 0x80000004)
 302                         get_model_name(c); /* Default name */
 303         }
 304
 305         /* Transmeta-defined flags: level 0x80860001 */
 306         xlvl = cpuid_eax(0x80860000);
 307         if ((xlvl & 0xffff0000) == 0x80860000) {
 308                 /* Don't set x86_cpuid_level here for now to not confuse. */
 309                 if (xlvl >= 0x80860001)
 310                         c->x86_capability[2] = cpuid_edx(0x80860001);
 311         }
 312
 313         c->extended_cpuid_level = cpuid_eax(0x80000000);
 314         if (c->extended_cpuid_level >= 0x80000007)
 315                 c->x86_power = cpuid_edx(0x80000007);
 316
 317         if (c->x86_vendor != X86_VENDOR_UNKNOWN &&
 318             cpu_devs[c->x86_vendor]->c_early_init)
 319                 cpu_devs[c->x86_vendor]->c_early_init(c);
 320
 321         validate_pat_support(c);
 322
 323         /* early_param could clear that, but recall get it set again */
 324         if (disable_apic)
 325                 clear_cpu_cap(c, X86_FEATURE_APIC);
 326 }
 327
 328 /*
 329  * This does the hard work of actually picking apart the CPU stuff...
 330  */
 331 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
 332 {
 333         int i;
 334
 335         early_identify_cpu(c);
 336
 337         init_scattered_cpuid_features(c);
 338
 339         c->apicid = phys_pkg_id(0);
 340
 341         /*
 342          * Vendor-specific initialization.  In this section we
 343          * canonicalize the feature flags, meaning if there are
 344          * features a certain CPU supports which CPUID doesn't
 345          * tell us, CPUID claiming incorrect flags, or other bugs,
 346          * we handle them here.
 347          *
 348          * At the end of this section, c->x86_capability better
 349          * indicate the features this CPU genuinely supports!
 350          */
 351         if (this_cpu->c_init)
 352                 this_cpu->c_init(c);
 353
 354         detect_ht(c);
 355
 356         /*
 357          * On SMP, boot_cpu_data holds the common feature set between
 358          * all CPUs; so make sure that we indicate which features are
 359          * common between the CPUs.  The first time this routine gets
 360          * executed, c == &boot_cpu_data.
 361          */
 362         if (c != &boot_cpu_data) {
 363                 /* AND the already accumulated flags with these */
 364                 for (i = 0; i < NCAPINTS; i++)
 365                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
 366         }
 367
 368         /* Clear all flags overriden by options */
 369         for (i = 0; i < NCAPINTS; i++)
 370                 c->x86_capability[i] &= ~cleared_cpu_caps[i];
 371
 372 #ifdef CONFIG_X86_MCE
 373         mcheck_init(c);
 374 #endif
 375         select_idle_routine(c);
 376
 377 #ifdef CONFIG_NUMA
 378         numa_add_cpu(smp_processor_id());
 379 #endif
 380
 381 }
 382
 383 void __cpuinit identify_boot_cpu(void)
 384 {
 385         identify_cpu(&boot_cpu_data);
 386 }
 387
 388 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
 389 {
 390         BUG_ON(c == &boot_cpu_data);
 391         identify_cpu(c);
 392         mtrr_ap_init();
 393 }
 394
 395 static __init int setup_noclflush(char *arg)
 396 {
 397         setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
 398         return 1;
 399 }
 400 __setup("noclflush", setup_noclflush);
 401
 402 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
 403 {
 404         if (c->x86_model_id[0])
 405                 printk(KERN_CONT "%s", c->x86_model_id);
 406
 407         if (c->x86_mask || c->cpuid_level >= 0)
 408                 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
 409         else
 410                 printk(KERN_CONT "\n");
 411 }
 412
 413 static __init int setup_disablecpuid(char *arg)
 414 {
 415         int bit;
 416         if (get_option(&arg, &bit) && bit < NCAPINTS*32)
 417                 setup_clear_cpu_cap(bit);
 418         else
 419                 return 0;
 420         return 1;
 421 }
 422 __setup("clearcpuid=", setup_disablecpuid);
 423
 424 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
 425
 426 struct x8664_pda **_cpu_pda __read_mostly;
 427 EXPORT_SYMBOL(_cpu_pda);
 428
 429 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
 430
 431 char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
 432
 433 unsigned long __supported_pte_mask __read_mostly = ~0UL;
 434 EXPORT_SYMBOL_GPL(__supported_pte_mask);
 435
 436 static int do_not_nx __cpuinitdata;
 437
 438 /* noexec=on|off
 439 Control non executable mappings for 64bit processes.
 440
 441 on      Enable(default)
 442 off     Disable
 443 */
 444 static int __init nonx_setup(char *str)
 445 {
 446         if (!str)
 447                 return -EINVAL;
 448         if (!strncmp(str, "on", 2)) {
 449                 __supported_pte_mask |= _PAGE_NX;
 450                 do_not_nx = 0;
 451         } else if (!strncmp(str, "off", 3)) {
 452                 do_not_nx = 1;
 453                 __supported_pte_mask &= ~_PAGE_NX;
 454         }
 455         return 0;
 456 }
 457 early_param("noexec", nonx_setup);
 458
 459 int force_personality32;
 460
 461 /* noexec32=on|off
 462 Control non executable heap for 32bit processes.
 463 To control the stack too use noexec=off
 464
 465 on      PROT_READ does not imply PROT_EXEC for 32bit processes (default)
 466 off     PROT_READ implies PROT_EXEC
 467 */
 468 static int __init nonx32_setup(char *str)
 469 {
 470         if (!strcmp(str, "on"))
 471                 force_personality32 &= ~READ_IMPLIES_EXEC;
 472         else if (!strcmp(str, "off"))
 473                 force_personality32 |= READ_IMPLIES_EXEC;
 474         return 1;
 475 }
 476 __setup("noexec32=", nonx32_setup);
 477
 478 void pda_init(int cpu)
 479 {
 480         struct x8664_pda *pda = cpu_pda(cpu);
 481
 482         /* Setup up data that may be needed in __get_free_pages early */
 483         loadsegment(fs, 0);
 484         loadsegment(gs, 0);
 485         /* Memory clobbers used to order PDA accessed */
 486         mb();
 487         wrmsrl(MSR_GS_BASE, pda);
 488         mb();
 489
 490         pda->cpunumber = cpu;
 491         pda->irqcount = -1;
 492         pda->kernelstack = (unsigned long)stack_thread_info() -
 493                                  PDA_STACKOFFSET + THREAD_SIZE;
 494         pda->active_mm = &init_mm;
 495         pda->mmu_state = 0;
 496
 497         if (cpu == 0) {
 498                 /* others are initialized in smpboot.c */
 499                 pda->pcurrent = &init_task;
 500                 pda->irqstackptr = boot_cpu_stack;
 501         } else {
 502                 pda->irqstackptr = (char *)
 503                         __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
 504                 if (!pda->irqstackptr)
 505                         panic("cannot allocate irqstack for cpu %d", cpu);
 506
 507                 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
 508                         pda->nodenumber = cpu_to_node(cpu);
 509         }
 510
 511         pda->irqstackptr += IRQSTACKSIZE-64;
 512 }
 513
 514 char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
 515                            DEBUG_STKSZ]
 516 __attribute__((section(".bss.page_aligned")));
 517
 518 extern asmlinkage void ignore_sysret(void);
 519
 520 /* May not be marked __init: used by software suspend */
 521 void syscall_init(void)
 522 {
 523         /*
 524          * LSTAR and STAR live in a bit strange symbiosis.
 525          * They both write to the same internal register. STAR allows to
 526          * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
 527          */
 528         wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32);
 529         wrmsrl(MSR_LSTAR, system_call);
 530         wrmsrl(MSR_CSTAR, ignore_sysret);
 531
 532 #ifdef CONFIG_IA32_EMULATION
 533         syscall32_cpu_init();
 534 #endif
 535
 536         /* Flags to clear on syscall */
 537         wrmsrl(MSR_SYSCALL_MASK,
 538                X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
 539 }
 540
 541 void __cpuinit check_efer(void)
 542 {
 543         unsigned long efer;
 544
 545         rdmsrl(MSR_EFER, efer);
 546         if (!(efer & EFER_NX) || do_not_nx)
 547                 __supported_pte_mask &= ~_PAGE_NX;
 548 }
 549
 550 unsigned long kernel_eflags;
 551
 552 /*
 553  * Copies of the original ist values from the tss are only accessed during
 554  * debugging, no special alignment required.
 555  */
 556 DEFINE_PER_CPU(struct orig_ist, orig_ist);
 557
 558 /*
 559  * cpu_init() initializes state that is per-CPU. Some data is already
 560  * initialized (naturally) in the bootstrap process, such as the GDT
 561  * and IDT. We reload them nevertheless, this function acts as a
 562  * 'CPU state barrier', nothing should get across.
 563  * A lot of state is already set up in PDA init.
 564  */
 565 void __cpuinit cpu_init(void)
 566 {
 567         int cpu = stack_smp_processor_id();
 568         struct tss_struct *t = &per_cpu(init_tss, cpu);
 569         struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
 570         unsigned long v;
 571         char *estacks = NULL;
 572         struct task_struct *me;
 573         int i;
 574
 575         /* CPU 0 is initialised in head64.c */
 576         if (cpu != 0)
 577                 pda_init(cpu);
 578         else
 579                 estacks = boot_exception_stacks;
 580
 581         me = current;
 582
 583         if (cpu_test_and_set(cpu, cpu_initialized))
 584                 panic("CPU#%d already initialized!\n", cpu);
 585
 586         printk(KERN_INFO "Initializing CPU#%d\n", cpu);
 587
 588         clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
 589
 590         /*
 591          * Initialize the per-CPU GDT with the boot GDT,
 592          * and set up the GDT descriptor:
 593          */
 594
 595         switch_to_new_gdt();
 596         load_idt((const struct desc_ptr *)&idt_descr);
 597
 598         memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
 599         syscall_init();
 600
 601         wrmsrl(MSR_FS_BASE, 0);
 602         wrmsrl(MSR_KERNEL_GS_BASE, 0);
 603         barrier();
 604
 605         check_efer();
 606
 607         /*
 608          * set up and load the per-CPU TSS
 609          */
 610         for (v = 0; v < N_EXCEPTION_STACKS; v++) {
 611                 static const unsigned int order[N_EXCEPTION_STACKS] = {
 612                         [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
 613                         [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
 614                 };
 615                 if (cpu) {
 616                         estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
 617                         if (!estacks)
 618                                 panic("Cannot allocate exception stack %ld %d\n",
 619                                       v, cpu);
 620                 }
 621                 estacks += PAGE_SIZE << order[v];
 622                 orig_ist->ist[v] = t->x86_tss.ist[v] = (unsigned long)estacks;
 623         }
 624
 625         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
 626         /*
 627          * <= is required because the CPU will access up to
 628          * 8 bits beyond the end of the IO permission bitmap.
 629          */
 630         for (i = 0; i <= IO_BITMAP_LONGS; i++)
 631                 t->io_bitmap[i] = ~0UL;
 632
 633         atomic_inc(&init_mm.mm_count);
 634         me->active_mm = &init_mm;
 635         if (me->mm)
 636                 BUG();
 637         enter_lazy_tlb(&init_mm, me);
 638
 639         load_sp0(t, &current->thread);
 640         set_tss_desc(cpu, t);
 641         load_TR_desc();
 642         load_LDT(&init_mm.context);
 643
 644 #ifdef CONFIG_KGDB
 645         /*
 646          * If the kgdb is connected no debug regs should be altered.  This
 647          * is only applicable when KGDB and a KGDB I/O module are built
 648          * into the kernel and you are using early debugging with
 649          * kgdbwait. KGDB will control the kernel HW breakpoint registers.
 650          */
 651         if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
 652                 arch_kgdb_ops.correct_hw_break();
 653         else {
 654 #endif
 655         /*
 656          * Clear all 6 debug registers:
 657          */
 658
 659         set_debugreg(0UL, 0);
 660         set_debugreg(0UL, 1);
 661         set_debugreg(0UL, 2);
 662         set_debugreg(0UL, 3);
 663         set_debugreg(0UL, 6);
 664         set_debugreg(0UL, 7);
 665 #ifdef CONFIG_KGDB
 666         /* If the kgdb is connected no debug regs should be altered. */
 667         }
 668 #endif
 669
 670         fpu_init();
 671
 672         raw_local_save_flags(kernel_eflags);
 673
 674         if (is_uv_system())
 675                 uv_cpu_init();
 676 }