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Merge tag 'v3.10.107' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / cpu / amd.c
1 #include <linux/export.h>
2 #include <linux/init.h>
3 #include <linux/bitops.h>
4 #include <linux/elf.h>
5 #include <linux/mm.h>
6
7 #include <linux/io.h>
8 #include <linux/sched.h>
9 #include <asm/processor.h>
10 #include <asm/apic.h>
11 #include <asm/cpu.h>
12 #include <asm/pci-direct.h>
13
14 #ifdef CONFIG_X86_64
15 # include <asm/mmconfig.h>
16 # include <asm/cacheflush.h>
17 #endif
18
19 #include "cpu.h"
20
21 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
22 {
23 u32 gprs[8] = { 0 };
24 int err;
25
26 WARN_ONCE((boot_cpu_data.x86 != 0xf),
27 "%s should only be used on K8!\n", __func__);
28
29 gprs[1] = msr;
30 gprs[7] = 0x9c5a203a;
31
32 err = rdmsr_safe_regs(gprs);
33
34 *p = gprs[0] | ((u64)gprs[2] << 32);
35
36 return err;
37 }
38
39 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
40 {
41 u32 gprs[8] = { 0 };
42
43 WARN_ONCE((boot_cpu_data.x86 != 0xf),
44 "%s should only be used on K8!\n", __func__);
45
46 gprs[0] = (u32)val;
47 gprs[1] = msr;
48 gprs[2] = val >> 32;
49 gprs[7] = 0x9c5a203a;
50
51 return wrmsr_safe_regs(gprs);
52 }
53
54 #ifdef CONFIG_X86_32
55 /*
56 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
57 * misexecution of code under Linux. Owners of such processors should
58 * contact AMD for precise details and a CPU swap.
59 *
60 * See http://www.multimania.com/poulot/k6bug.html
61 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
62 * (Publication # 21266 Issue Date: August 1998)
63 *
64 * The following test is erm.. interesting. AMD neglected to up
65 * the chip setting when fixing the bug but they also tweaked some
66 * performance at the same time..
67 */
68
69 extern void vide(void);
70 __asm__(".align 4\nvide: ret");
71
72 static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
73 {
74 /*
75 * General Systems BIOSen alias the cpu frequency registers
76 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
77 * drivers subsequently pokes it, and changes the CPU speed.
78 * Workaround : Remove the unneeded alias.
79 */
80 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
81 #define CBAR_ENB (0x80000000)
82 #define CBAR_KEY (0X000000CB)
83 if (c->x86_model == 9 || c->x86_model == 10) {
84 if (inl(CBAR) & CBAR_ENB)
85 outl(0 | CBAR_KEY, CBAR);
86 }
87 }
88
89
90 static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
91 {
92 u32 l, h;
93 int mbytes = num_physpages >> (20-PAGE_SHIFT);
94
95 if (c->x86_model < 6) {
96 /* Based on AMD doc 20734R - June 2000 */
97 if (c->x86_model == 0) {
98 clear_cpu_cap(c, X86_FEATURE_APIC);
99 set_cpu_cap(c, X86_FEATURE_PGE);
100 }
101 return;
102 }
103
104 if (c->x86_model == 6 && c->x86_mask == 1) {
105 const int K6_BUG_LOOP = 1000000;
106 int n;
107 void (*f_vide)(void);
108 unsigned long d, d2;
109
110 printk(KERN_INFO "AMD K6 stepping B detected - ");
111
112 /*
113 * It looks like AMD fixed the 2.6.2 bug and improved indirect
114 * calls at the same time.
115 */
116
117 n = K6_BUG_LOOP;
118 f_vide = vide;
119 rdtscl(d);
120 while (n--)
121 f_vide();
122 rdtscl(d2);
123 d = d2-d;
124
125 if (d > 20*K6_BUG_LOOP)
126 printk(KERN_CONT
127 "system stability may be impaired when more than 32 MB are used.\n");
128 else
129 printk(KERN_CONT "probably OK (after B9730xxxx).\n");
130 }
131
132 /* K6 with old style WHCR */
133 if (c->x86_model < 8 ||
134 (c->x86_model == 8 && c->x86_mask < 8)) {
135 /* We can only write allocate on the low 508Mb */
136 if (mbytes > 508)
137 mbytes = 508;
138
139 rdmsr(MSR_K6_WHCR, l, h);
140 if ((l&0x0000FFFF) == 0) {
141 unsigned long flags;
142 l = (1<<0)|((mbytes/4)<<1);
143 local_irq_save(flags);
144 wbinvd();
145 wrmsr(MSR_K6_WHCR, l, h);
146 local_irq_restore(flags);
147 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
148 mbytes);
149 }
150 return;
151 }
152
153 if ((c->x86_model == 8 && c->x86_mask > 7) ||
154 c->x86_model == 9 || c->x86_model == 13) {
155 /* The more serious chips .. */
156
157 if (mbytes > 4092)
158 mbytes = 4092;
159
160 rdmsr(MSR_K6_WHCR, l, h);
161 if ((l&0xFFFF0000) == 0) {
162 unsigned long flags;
163 l = ((mbytes>>2)<<22)|(1<<16);
164 local_irq_save(flags);
165 wbinvd();
166 wrmsr(MSR_K6_WHCR, l, h);
167 local_irq_restore(flags);
168 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
169 mbytes);
170 }
171
172 return;
173 }
174
175 if (c->x86_model == 10) {
176 /* AMD Geode LX is model 10 */
177 /* placeholder for any needed mods */
178 return;
179 }
180 }
181
182 static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c)
183 {
184 /* calling is from identify_secondary_cpu() ? */
185 if (!c->cpu_index)
186 return;
187
188 /*
189 * Certain Athlons might work (for various values of 'work') in SMP
190 * but they are not certified as MP capable.
191 */
192 /* Athlon 660/661 is valid. */
193 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
194 (c->x86_mask == 1)))
195 return;
196
197 /* Duron 670 is valid */
198 if ((c->x86_model == 7) && (c->x86_mask == 0))
199 return;
200
201 /*
202 * Athlon 662, Duron 671, and Athlon >model 7 have capability
203 * bit. It's worth noting that the A5 stepping (662) of some
204 * Athlon XP's have the MP bit set.
205 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
206 * more.
207 */
208 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
209 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
210 (c->x86_model > 7))
211 if (cpu_has_mp)
212 return;
213
214 /* If we get here, not a certified SMP capable AMD system. */
215
216 /*
217 * Don't taint if we are running SMP kernel on a single non-MP
218 * approved Athlon
219 */
220 WARN_ONCE(1, "WARNING: This combination of AMD"
221 " processors is not suitable for SMP.\n");
222 add_taint(TAINT_UNSAFE_SMP, LOCKDEP_NOW_UNRELIABLE);
223 }
224
225 static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
226 {
227 u32 l, h;
228
229 /*
230 * Bit 15 of Athlon specific MSR 15, needs to be 0
231 * to enable SSE on Palomino/Morgan/Barton CPU's.
232 * If the BIOS didn't enable it already, enable it here.
233 */
234 if (c->x86_model >= 6 && c->x86_model <= 10) {
235 if (!cpu_has(c, X86_FEATURE_XMM)) {
236 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
237 rdmsr(MSR_K7_HWCR, l, h);
238 l &= ~0x00008000;
239 wrmsr(MSR_K7_HWCR, l, h);
240 set_cpu_cap(c, X86_FEATURE_XMM);
241 }
242 }
243
244 /*
245 * It's been determined by AMD that Athlons since model 8 stepping 1
246 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
247 * As per AMD technical note 27212 0.2
248 */
249 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
250 rdmsr(MSR_K7_CLK_CTL, l, h);
251 if ((l & 0xfff00000) != 0x20000000) {
252 printk(KERN_INFO
253 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
254 l, ((l & 0x000fffff)|0x20000000));
255 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
256 }
257 }
258
259 set_cpu_cap(c, X86_FEATURE_K7);
260
261 amd_k7_smp_check(c);
262 }
263 #endif
264
265 #ifdef CONFIG_NUMA
266 /*
267 * To workaround broken NUMA config. Read the comment in
268 * srat_detect_node().
269 */
270 static int __cpuinit nearby_node(int apicid)
271 {
272 int i, node;
273
274 for (i = apicid - 1; i >= 0; i--) {
275 node = __apicid_to_node[i];
276 if (node != NUMA_NO_NODE && node_online(node))
277 return node;
278 }
279 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
280 node = __apicid_to_node[i];
281 if (node != NUMA_NO_NODE && node_online(node))
282 return node;
283 }
284 return first_node(node_online_map); /* Shouldn't happen */
285 }
286 #endif
287
288 /*
289 * Fixup core topology information for
290 * (1) AMD multi-node processors
291 * Assumption: Number of cores in each internal node is the same.
292 * (2) AMD processors supporting compute units
293 */
294 #ifdef CONFIG_X86_HT
295 static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)
296 {
297 u32 nodes, cores_per_cu = 1;
298 u8 node_id;
299 int cpu = smp_processor_id();
300
301 /* get information required for multi-node processors */
302 if (cpu_has_topoext) {
303 u32 eax, ebx, ecx, edx;
304
305 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
306 nodes = ((ecx >> 8) & 7) + 1;
307 node_id = ecx & 7;
308
309 /* get compute unit information */
310 smp_num_siblings = ((ebx >> 8) & 3) + 1;
311 c->compute_unit_id = ebx & 0xff;
312 cores_per_cu += ((ebx >> 8) & 3);
313 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
314 u64 value;
315
316 rdmsrl(MSR_FAM10H_NODE_ID, value);
317 nodes = ((value >> 3) & 7) + 1;
318 node_id = value & 7;
319 } else
320 return;
321
322 /* fixup multi-node processor information */
323 if (nodes > 1) {
324 u32 cores_per_node;
325 u32 cus_per_node;
326
327 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
328 cores_per_node = c->x86_max_cores / nodes;
329 cus_per_node = cores_per_node / cores_per_cu;
330
331 /* store NodeID, use llc_shared_map to store sibling info */
332 per_cpu(cpu_llc_id, cpu) = node_id;
333
334 /* core id has to be in the [0 .. cores_per_node - 1] range */
335 c->cpu_core_id %= cores_per_node;
336 c->compute_unit_id %= cus_per_node;
337 }
338 }
339 #endif
340
341 /*
342 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
343 * Assumes number of cores is a power of two.
344 */
345 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
346 {
347 #ifdef CONFIG_X86_HT
348 unsigned bits;
349 int cpu = smp_processor_id();
350
351 bits = c->x86_coreid_bits;
352 /* Low order bits define the core id (index of core in socket) */
353 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
354 /* Convert the initial APIC ID into the socket ID */
355 c->phys_proc_id = c->initial_apicid >> bits;
356 /* use socket ID also for last level cache */
357 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
358 amd_get_topology(c);
359 #endif
360 }
361
362 u16 amd_get_nb_id(int cpu)
363 {
364 u16 id = 0;
365 #ifdef CONFIG_SMP
366 id = per_cpu(cpu_llc_id, cpu);
367 #endif
368 return id;
369 }
370 EXPORT_SYMBOL_GPL(amd_get_nb_id);
371
372 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
373 {
374 #ifdef CONFIG_NUMA
375 int cpu = smp_processor_id();
376 int node;
377 unsigned apicid = c->apicid;
378
379 node = numa_cpu_node(cpu);
380 if (node == NUMA_NO_NODE)
381 node = per_cpu(cpu_llc_id, cpu);
382
383 /*
384 * On multi-fabric platform (e.g. Numascale NumaChip) a
385 * platform-specific handler needs to be called to fixup some
386 * IDs of the CPU.
387 */
388 if (x86_cpuinit.fixup_cpu_id)
389 x86_cpuinit.fixup_cpu_id(c, node);
390
391 if (!node_online(node)) {
392 /*
393 * Two possibilities here:
394 *
395 * - The CPU is missing memory and no node was created. In
396 * that case try picking one from a nearby CPU.
397 *
398 * - The APIC IDs differ from the HyperTransport node IDs
399 * which the K8 northbridge parsing fills in. Assume
400 * they are all increased by a constant offset, but in
401 * the same order as the HT nodeids. If that doesn't
402 * result in a usable node fall back to the path for the
403 * previous case.
404 *
405 * This workaround operates directly on the mapping between
406 * APIC ID and NUMA node, assuming certain relationship
407 * between APIC ID, HT node ID and NUMA topology. As going
408 * through CPU mapping may alter the outcome, directly
409 * access __apicid_to_node[].
410 */
411 int ht_nodeid = c->initial_apicid;
412
413 if (ht_nodeid >= 0 &&
414 __apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
415 node = __apicid_to_node[ht_nodeid];
416 /* Pick a nearby node */
417 if (!node_online(node))
418 node = nearby_node(apicid);
419 }
420 numa_set_node(cpu, node);
421 #endif
422 }
423
424 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
425 {
426 #ifdef CONFIG_X86_HT
427 unsigned bits, ecx;
428
429 /* Multi core CPU? */
430 if (c->extended_cpuid_level < 0x80000008)
431 return;
432
433 ecx = cpuid_ecx(0x80000008);
434
435 c->x86_max_cores = (ecx & 0xff) + 1;
436
437 /* CPU telling us the core id bits shift? */
438 bits = (ecx >> 12) & 0xF;
439
440 /* Otherwise recompute */
441 if (bits == 0) {
442 while ((1 << bits) < c->x86_max_cores)
443 bits++;
444 }
445
446 c->x86_coreid_bits = bits;
447 #endif
448 }
449
450 static void __cpuinit bsp_init_amd(struct cpuinfo_x86 *c)
451 {
452 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
453
454 if (c->x86 > 0x10 ||
455 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
456 u64 val;
457
458 rdmsrl(MSR_K7_HWCR, val);
459 if (!(val & BIT(24)))
460 printk(KERN_WARNING FW_BUG "TSC doesn't count "
461 "with P0 frequency!\n");
462 }
463 }
464
465 if (c->x86 == 0x15) {
466 unsigned long upperbit;
467 u32 cpuid, assoc;
468
469 cpuid = cpuid_edx(0x80000005);
470 assoc = cpuid >> 16 & 0xff;
471 upperbit = ((cpuid >> 24) << 10) / assoc;
472
473 va_align.mask = (upperbit - 1) & PAGE_MASK;
474 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
475 }
476 }
477
478 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
479 {
480 early_init_amd_mc(c);
481
482 /*
483 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
484 * with P/T states and does not stop in deep C-states
485 */
486 if (c->x86_power & (1 << 8)) {
487 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
488 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
489 if (!check_tsc_unstable())
490 sched_clock_stable = 1;
491 }
492
493 #ifdef CONFIG_X86_64
494 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
495 #else
496 /* Set MTRR capability flag if appropriate */
497 if (c->x86 == 5)
498 if (c->x86_model == 13 || c->x86_model == 9 ||
499 (c->x86_model == 8 && c->x86_mask >= 8))
500 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
501 #endif
502 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
503 /* check CPU config space for extended APIC ID */
504 if (cpu_has_apic && c->x86 >= 0xf) {
505 unsigned int val;
506 val = read_pci_config(0, 24, 0, 0x68);
507 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))
508 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
509 }
510 #endif
511
512 /* F16h erratum 793, CVE-2013-6885 */
513 if (c->x86 == 0x16 && c->x86_model <= 0xf) {
514 u64 val;
515
516 rdmsrl(MSR_AMD64_LS_CFG, val);
517 if (!(val & BIT(15)))
518 wrmsrl(MSR_AMD64_LS_CFG, val | BIT(15));
519 }
520
521 }
522
523 static const int amd_erratum_383[];
524 static const int amd_erratum_400[];
525 static bool cpu_has_amd_erratum(const int *erratum);
526
527 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
528 {
529 u32 dummy;
530 unsigned long long value;
531
532 #ifdef CONFIG_SMP
533 /*
534 * Disable TLB flush filter by setting HWCR.FFDIS on K8
535 * bit 6 of msr C001_0015
536 *
537 * Errata 63 for SH-B3 steppings
538 * Errata 122 for all steppings (F+ have it disabled by default)
539 */
540 if (c->x86 == 0xf) {
541 rdmsrl(MSR_K7_HWCR, value);
542 value |= 1 << 6;
543 wrmsrl(MSR_K7_HWCR, value);
544 }
545 #endif
546
547 early_init_amd(c);
548
549 /*
550 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
551 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
552 */
553 clear_cpu_cap(c, 0*32+31);
554
555 #ifdef CONFIG_X86_64
556 /* On C+ stepping K8 rep microcode works well for copy/memset */
557 if (c->x86 == 0xf) {
558 u32 level;
559
560 level = cpuid_eax(1);
561 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
562 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
563
564 /*
565 * Some BIOSes incorrectly force this feature, but only K8
566 * revision D (model = 0x14) and later actually support it.
567 * (AMD Erratum #110, docId: 25759).
568 */
569 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
570 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
571 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
572 value &= ~(1ULL << 32);
573 wrmsrl_amd_safe(0xc001100d, value);
574 }
575 }
576
577 }
578 if (c->x86 >= 0x10)
579 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
580
581 /* get apicid instead of initial apic id from cpuid */
582 c->apicid = hard_smp_processor_id();
583 #else
584
585 /*
586 * FIXME: We should handle the K5 here. Set up the write
587 * range and also turn on MSR 83 bits 4 and 31 (write alloc,
588 * no bus pipeline)
589 */
590
591 switch (c->x86) {
592 case 4:
593 init_amd_k5(c);
594 break;
595 case 5:
596 init_amd_k6(c);
597 break;
598 case 6: /* An Athlon/Duron */
599 init_amd_k7(c);
600 break;
601 }
602
603 /* K6s reports MCEs but don't actually have all the MSRs */
604 if (c->x86 < 6)
605 clear_cpu_cap(c, X86_FEATURE_MCE);
606 #endif
607
608 /* Enable workaround for FXSAVE leak */
609 if (c->x86 >= 6)
610 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
611
612 if (!c->x86_model_id[0]) {
613 switch (c->x86) {
614 case 0xf:
615 /* Should distinguish Models here, but this is only
616 a fallback anyways. */
617 strcpy(c->x86_model_id, "Hammer");
618 break;
619 }
620 }
621
622 /* re-enable TopologyExtensions if switched off by BIOS */
623 if ((c->x86 == 0x15) &&
624 (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
625 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
626
627 if (!rdmsrl_safe(0xc0011005, &value)) {
628 value |= 1ULL << 54;
629 wrmsrl_safe(0xc0011005, value);
630 rdmsrl(0xc0011005, value);
631 if (value & (1ULL << 54)) {
632 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
633 printk(KERN_INFO FW_INFO "CPU: Re-enabling "
634 "disabled Topology Extensions Support\n");
635 }
636 }
637 }
638
639 /*
640 * The way access filter has a performance penalty on some workloads.
641 * Disable it on the affected CPUs.
642 */
643 if ((c->x86 == 0x15) &&
644 (c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
645
646 if (!rdmsrl_safe(0xc0011021, &value) && !(value & 0x1E)) {
647 value |= 0x1E;
648 wrmsrl_safe(0xc0011021, value);
649 }
650 }
651
652 cpu_detect_cache_sizes(c);
653
654 /* Multi core CPU? */
655 if (c->extended_cpuid_level >= 0x80000008) {
656 amd_detect_cmp(c);
657 srat_detect_node(c);
658 }
659
660 #ifdef CONFIG_X86_32
661 detect_ht(c);
662 #endif
663
664 init_amd_cacheinfo(c);
665
666 if (c->x86 >= 0xf)
667 set_cpu_cap(c, X86_FEATURE_K8);
668
669 if (cpu_has_xmm2) {
670 /* MFENCE stops RDTSC speculation */
671 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
672 }
673
674 #ifdef CONFIG_X86_64
675 if (c->x86 == 0x10) {
676 /* do this for boot cpu */
677 if (c == &boot_cpu_data)
678 check_enable_amd_mmconf_dmi();
679
680 fam10h_check_enable_mmcfg();
681 }
682
683 if (c == &boot_cpu_data && c->x86 >= 0xf) {
684 unsigned long long tseg;
685
686 /*
687 * Split up direct mapping around the TSEG SMM area.
688 * Don't do it for gbpages because there seems very little
689 * benefit in doing so.
690 */
691 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
692 unsigned long pfn = tseg >> PAGE_SHIFT;
693
694 printk(KERN_DEBUG "tseg: %010llx\n", tseg);
695 if (pfn_range_is_mapped(pfn, pfn + 1))
696 set_memory_4k((unsigned long)__va(tseg), 1);
697 }
698 }
699 #endif
700
701 /*
702 * Family 0x12 and above processors have APIC timer
703 * running in deep C states.
704 */
705 if (c->x86 > 0x11)
706 set_cpu_cap(c, X86_FEATURE_ARAT);
707
708 if (c->x86 == 0x10) {
709 /*
710 * Disable GART TLB Walk Errors on Fam10h. We do this here
711 * because this is always needed when GART is enabled, even in a
712 * kernel which has no MCE support built in.
713 * BIOS should disable GartTlbWlk Errors themself. If
714 * it doesn't do it here as suggested by the BKDG.
715 *
716 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
717 */
718 u64 mask;
719 int err;
720
721 err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask);
722 if (err == 0) {
723 mask |= (1 << 10);
724 wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);
725 }
726
727 /*
728 * On family 10h BIOS may not have properly enabled WC+ support,
729 * causing it to be converted to CD memtype. This may result in
730 * performance degradation for certain nested-paging guests.
731 * Prevent this conversion by clearing bit 24 in
732 * MSR_AMD64_BU_CFG2.
733 *
734 * NOTE: we want to use the _safe accessors so as not to #GP kvm
735 * guests on older kvm hosts.
736 */
737
738 rdmsrl_safe(MSR_AMD64_BU_CFG2, &value);
739 value &= ~(1ULL << 24);
740 wrmsrl_safe(MSR_AMD64_BU_CFG2, value);
741
742 if (cpu_has_amd_erratum(amd_erratum_383))
743 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
744 }
745
746 if (cpu_has_amd_erratum(amd_erratum_400))
747 set_cpu_bug(c, X86_BUG_AMD_APIC_C1E);
748
749 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
750 }
751
752 #ifdef CONFIG_X86_32
753 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c,
754 unsigned int size)
755 {
756 /* AMD errata T13 (order #21922) */
757 if ((c->x86 == 6)) {
758 /* Duron Rev A0 */
759 if (c->x86_model == 3 && c->x86_mask == 0)
760 size = 64;
761 /* Tbird rev A1/A2 */
762 if (c->x86_model == 4 &&
763 (c->x86_mask == 0 || c->x86_mask == 1))
764 size = 256;
765 }
766 return size;
767 }
768 #endif
769
770 static void __cpuinit cpu_set_tlb_flushall_shift(struct cpuinfo_x86 *c)
771 {
772 tlb_flushall_shift = 5;
773
774 if (c->x86 <= 0x11)
775 tlb_flushall_shift = 4;
776 }
777
778 static void __cpuinit cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
779 {
780 u32 ebx, eax, ecx, edx;
781 u16 mask = 0xfff;
782
783 if (c->x86 < 0xf)
784 return;
785
786 if (c->extended_cpuid_level < 0x80000006)
787 return;
788
789 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
790
791 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
792 tlb_lli_4k[ENTRIES] = ebx & mask;
793
794 /*
795 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
796 * characteristics from the CPUID function 0x80000005 instead.
797 */
798 if (c->x86 == 0xf) {
799 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
800 mask = 0xff;
801 }
802
803 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
804 if (!((eax >> 16) & mask)) {
805 u32 a, b, c, d;
806
807 cpuid(0x80000005, &a, &b, &c, &d);
808 tlb_lld_2m[ENTRIES] = (a >> 16) & 0xff;
809 } else {
810 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
811 }
812
813 /* a 4M entry uses two 2M entries */
814 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
815
816 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
817 if (!(eax & mask)) {
818 /* Erratum 658 */
819 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
820 tlb_lli_2m[ENTRIES] = 1024;
821 } else {
822 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
823 tlb_lli_2m[ENTRIES] = eax & 0xff;
824 }
825 } else
826 tlb_lli_2m[ENTRIES] = eax & mask;
827
828 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
829
830 cpu_set_tlb_flushall_shift(c);
831 }
832
833 static const struct cpu_dev __cpuinitconst amd_cpu_dev = {
834 .c_vendor = "AMD",
835 .c_ident = { "AuthenticAMD" },
836 #ifdef CONFIG_X86_32
837 .c_models = {
838 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
839 {
840 [3] = "486 DX/2",
841 [7] = "486 DX/2-WB",
842 [8] = "486 DX/4",
843 [9] = "486 DX/4-WB",
844 [14] = "Am5x86-WT",
845 [15] = "Am5x86-WB"
846 }
847 },
848 },
849 .c_size_cache = amd_size_cache,
850 #endif
851 .c_early_init = early_init_amd,
852 .c_detect_tlb = cpu_detect_tlb_amd,
853 .c_bsp_init = bsp_init_amd,
854 .c_init = init_amd,
855 .c_x86_vendor = X86_VENDOR_AMD,
856 };
857
858 cpu_dev_register(amd_cpu_dev);
859
860 /*
861 * AMD errata checking
862 *
863 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
864 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
865 * have an OSVW id assigned, which it takes as first argument. Both take a
866 * variable number of family-specific model-stepping ranges created by
867 * AMD_MODEL_RANGE().
868 *
869 * Example:
870 *
871 * const int amd_erratum_319[] =
872 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
873 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
874 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
875 */
876
877 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
878 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
879 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
880 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
881 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
882 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
883 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
884
885 static const int amd_erratum_400[] =
886 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
887 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
888
889 static const int amd_erratum_383[] =
890 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
891
892 static bool cpu_has_amd_erratum(const int *erratum)
893 {
894 struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info);
895 int osvw_id = *erratum++;
896 u32 range;
897 u32 ms;
898
899 /*
900 * If called early enough that current_cpu_data hasn't been initialized
901 * yet, fall back to boot_cpu_data.
902 */
903 if (cpu->x86 == 0)
904 cpu = &boot_cpu_data;
905
906 if (cpu->x86_vendor != X86_VENDOR_AMD)
907 return false;
908
909 if (osvw_id >= 0 && osvw_id < 65536 &&
910 cpu_has(cpu, X86_FEATURE_OSVW)) {
911 u64 osvw_len;
912
913 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
914 if (osvw_id < osvw_len) {
915 u64 osvw_bits;
916
917 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
918 osvw_bits);
919 return osvw_bits & (1ULL << (osvw_id & 0x3f));
920 }
921 }
922
923 /* OSVW unavailable or ID unknown, match family-model-stepping range */
924 ms = (cpu->x86_model << 4) | cpu->x86_mask;
925 while ((range = *erratum++))
926 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
927 (ms >= AMD_MODEL_RANGE_START(range)) &&
928 (ms <= AMD_MODEL_RANGE_END(range)))
929 return true;
930
931 return false;
932 }
kernel source for telekom puls (alcatel/mediatek)