2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/pgalloc.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
43 #include <asm/i8259.h>
46 #include <mach_apic.h>
48 static int disable_apic_timer __cpuinitdata
;
49 static int apic_calibrate_pmtmr __initdata
;
54 /* x2apic enabled before OS handover */
55 int x2apic_preenabled
;
57 /* Local APIC timer works in C2 */
58 int local_apic_timer_c2_ok
;
59 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
62 * Debug level, exported for io_apic.c
64 unsigned int apic_verbosity
;
66 /* Have we found an MP table */
69 static struct resource lapic_resource
= {
71 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
74 static unsigned int calibration_result
;
76 static int lapic_next_event(unsigned long delta
,
77 struct clock_event_device
*evt
);
78 static void lapic_timer_setup(enum clock_event_mode mode
,
79 struct clock_event_device
*evt
);
80 static void lapic_timer_broadcast(cpumask_t mask
);
81 static void apic_pm_activate(void);
83 static struct clock_event_device lapic_clockevent
= {
85 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
86 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
88 .set_mode
= lapic_timer_setup
,
89 .set_next_event
= lapic_next_event
,
90 .broadcast
= lapic_timer_broadcast
,
94 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
96 static unsigned long apic_phys
;
98 unsigned long mp_lapic_addr
;
100 unsigned int __cpuinitdata maxcpus
= NR_CPUS
;
102 * Get the LAPIC version
104 static inline int lapic_get_version(void)
106 return GET_APIC_VERSION(apic_read(APIC_LVR
));
110 * Check, if the APIC is integrated or a seperate chip
112 static inline int lapic_is_integrated(void)
118 * Check, whether this is a modern or a first generation APIC
120 static int modern_apic(void)
122 /* AMD systems use old APIC versions, so check the CPU */
123 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
124 boot_cpu_data
.x86
>= 0xf)
126 return lapic_get_version() >= 0x14;
129 void xapic_wait_icr_idle(void)
131 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
135 u32
safe_xapic_wait_icr_idle(void)
142 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
146 } while (timeout
++ < 1000);
151 void xapic_icr_write(u32 low
, u32 id
)
153 apic_write(APIC_ICR2
, id
<< 24);
154 apic_write(APIC_ICR
, low
);
157 u64
xapic_icr_read(void)
161 icr2
= apic_read(APIC_ICR2
);
162 icr1
= apic_read(APIC_ICR
);
164 return (icr1
| ((u64
)icr2
<< 32));
167 static struct apic_ops xapic_ops
= {
168 .read
= native_apic_mem_read
,
169 .write
= native_apic_mem_write
,
170 .icr_read
= xapic_icr_read
,
171 .icr_write
= xapic_icr_write
,
172 .wait_icr_idle
= xapic_wait_icr_idle
,
173 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
176 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
178 EXPORT_SYMBOL_GPL(apic_ops
);
180 static void x2apic_wait_icr_idle(void)
182 /* no need to wait for icr idle in x2apic */
186 static u32
safe_x2apic_wait_icr_idle(void)
188 /* no need to wait for icr idle in x2apic */
192 void x2apic_icr_write(u32 low
, u32 id
)
194 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
197 u64
x2apic_icr_read(void)
201 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
205 static struct apic_ops x2apic_ops
= {
206 .read
= native_apic_msr_read
,
207 .write
= native_apic_msr_write
,
208 .icr_read
= x2apic_icr_read
,
209 .icr_write
= x2apic_icr_write
,
210 .wait_icr_idle
= x2apic_wait_icr_idle
,
211 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
215 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
217 void __cpuinit
enable_NMI_through_LVT0(void)
221 /* unmask and set to NMI */
224 /* Level triggered for 82489DX (32bit mode) */
225 if (!lapic_is_integrated())
226 v
|= APIC_LVT_LEVEL_TRIGGER
;
228 apic_write(APIC_LVT0
, v
);
232 * lapic_get_maxlvt - get the maximum number of local vector table entries
234 int lapic_get_maxlvt(void)
238 v
= apic_read(APIC_LVR
);
240 * - we always have APIC integrated on 64bit mode
241 * - 82489DXs do not report # of LVT entries
243 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
247 * This function sets up the local APIC timer, with a timeout of
248 * 'clocks' APIC bus clock. During calibration we actually call
249 * this function twice on the boot CPU, once with a bogus timeout
250 * value, second time for real. The other (noncalibrating) CPUs
251 * call this function only once, with the real, calibrated value.
253 * We do reads before writes even if unnecessary, to get around the
254 * P5 APIC double write bug.
257 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
259 unsigned int lvtt_value
, tmp_value
;
261 lvtt_value
= LOCAL_TIMER_VECTOR
;
263 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
265 lvtt_value
|= APIC_LVT_MASKED
;
267 apic_write(APIC_LVTT
, lvtt_value
);
272 tmp_value
= apic_read(APIC_TDCR
);
273 apic_write(APIC_TDCR
, (tmp_value
274 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
278 apic_write(APIC_TMICT
, clocks
);
282 * Setup extended LVT, AMD specific (K8, family 10h)
284 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
285 * MCE interrupts are supported. Thus MCE offset must be set to 0.
288 #define APIC_EILVT_LVTOFF_MCE 0
289 #define APIC_EILVT_LVTOFF_IBS 1
291 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
293 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
294 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
299 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
301 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
302 return APIC_EILVT_LVTOFF_MCE
;
305 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
307 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
308 return APIC_EILVT_LVTOFF_IBS
;
312 * Program the next event, relative to now
314 static int lapic_next_event(unsigned long delta
,
315 struct clock_event_device
*evt
)
317 apic_write(APIC_TMICT
, delta
);
322 * Setup the lapic timer in periodic or oneshot mode
324 static void lapic_timer_setup(enum clock_event_mode mode
,
325 struct clock_event_device
*evt
)
330 /* Lapic used as dummy for broadcast ? */
331 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
334 local_irq_save(flags
);
337 case CLOCK_EVT_MODE_PERIODIC
:
338 case CLOCK_EVT_MODE_ONESHOT
:
339 __setup_APIC_LVTT(calibration_result
,
340 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
342 case CLOCK_EVT_MODE_UNUSED
:
343 case CLOCK_EVT_MODE_SHUTDOWN
:
344 v
= apic_read(APIC_LVTT
);
345 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
346 apic_write(APIC_LVTT
, v
);
348 case CLOCK_EVT_MODE_RESUME
:
349 /* Nothing to do here */
353 local_irq_restore(flags
);
357 * Local APIC timer broadcast function
359 static void lapic_timer_broadcast(cpumask_t mask
)
362 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
367 * Setup the local APIC timer for this CPU. Copy the initilized values
368 * of the boot CPU and register the clock event in the framework.
370 static void setup_APIC_timer(void)
372 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
374 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
375 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
377 clockevents_register_device(levt
);
381 * In this function we calibrate APIC bus clocks to the external
382 * timer. Unfortunately we cannot use jiffies and the timer irq
383 * to calibrate, since some later bootup code depends on getting
384 * the first irq? Ugh.
386 * We want to do the calibration only once since we
387 * want to have local timer irqs syncron. CPUs connected
388 * by the same APIC bus have the very same bus frequency.
389 * And we want to have irqs off anyways, no accidental
393 #define TICK_COUNT 100000000
395 static int __init
calibrate_APIC_clock(void)
397 unsigned apic
, apic_start
;
398 unsigned long tsc
, tsc_start
;
404 * Put whatever arbitrary (but long enough) timeout
405 * value into the APIC clock, we just want to get the
406 * counter running for calibration.
408 * No interrupt enable !
410 __setup_APIC_LVTT(250000000, 0, 0);
412 apic_start
= apic_read(APIC_TMCCT
);
413 #ifdef CONFIG_X86_PM_TIMER
414 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
415 pmtimer_wait(5000); /* 5ms wait */
416 apic
= apic_read(APIC_TMCCT
);
417 result
= (apic_start
- apic
) * 1000L / 5;
424 apic
= apic_read(APIC_TMCCT
);
426 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
427 (apic_start
- apic
) < TICK_COUNT
);
429 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
435 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
437 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
438 result
/ 1000 / 1000, result
/ 1000 % 1000);
440 /* Calculate the scaled math multiplication factor */
441 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
442 lapic_clockevent
.shift
);
443 lapic_clockevent
.max_delta_ns
=
444 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
445 lapic_clockevent
.min_delta_ns
=
446 clockevent_delta2ns(0xF, &lapic_clockevent
);
448 calibration_result
= result
/ HZ
;
451 * Do a sanity check on the APIC calibration result
453 if (calibration_result
< (1000000 / HZ
)) {
455 "APIC frequency too slow, disabling apic timer\n");
463 * Setup the boot APIC
465 * Calibrate and verify the result.
467 void __init
setup_boot_APIC_clock(void)
470 * The local apic timer can be disabled via the kernel commandline.
471 * Register the lapic timer as a dummy clock event source on SMP
472 * systems, so the broadcast mechanism is used. On UP systems simply
475 if (disable_apic_timer
) {
476 printk(KERN_INFO
"Disabling APIC timer\n");
477 /* No broadcast on UP ! */
478 if (num_possible_cpus() > 1) {
479 lapic_clockevent
.mult
= 1;
485 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
486 if (calibrate_APIC_clock()) {
487 /* No broadcast on UP ! */
488 if (num_possible_cpus() > 1)
494 * If nmi_watchdog is set to IO_APIC, we need the
495 * PIT/HPET going. Otherwise register lapic as a dummy
498 if (nmi_watchdog
!= NMI_IO_APIC
)
499 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
501 printk(KERN_WARNING
"APIC timer registered as dummy,"
502 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
507 void __cpuinit
setup_secondary_APIC_clock(void)
513 * The guts of the apic timer interrupt
515 static void local_apic_timer_interrupt(void)
517 int cpu
= smp_processor_id();
518 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
521 * Normally we should not be here till LAPIC has been initialized but
522 * in some cases like kdump, its possible that there is a pending LAPIC
523 * timer interrupt from previous kernel's context and is delivered in
524 * new kernel the moment interrupts are enabled.
526 * Interrupts are enabled early and LAPIC is setup much later, hence
527 * its possible that when we get here evt->event_handler is NULL.
528 * Check for event_handler being NULL and discard the interrupt as
531 if (!evt
->event_handler
) {
533 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
535 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
540 * the NMI deadlock-detector uses this.
542 add_pda(apic_timer_irqs
, 1);
544 evt
->event_handler(evt
);
548 * Local APIC timer interrupt. This is the most natural way for doing
549 * local interrupts, but local timer interrupts can be emulated by
550 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
552 * [ if a single-CPU system runs an SMP kernel then we call the local
553 * interrupt as well. Thus we cannot inline the local irq ... ]
555 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
557 struct pt_regs
*old_regs
= set_irq_regs(regs
);
560 * NOTE! We'd better ACK the irq immediately,
561 * because timer handling can be slow.
565 * update_process_times() expects us to have done irq_enter().
566 * Besides, if we don't timer interrupts ignore the global
567 * interrupt lock, which is the WrongThing (tm) to do.
571 local_apic_timer_interrupt();
573 set_irq_regs(old_regs
);
576 int setup_profiling_timer(unsigned int multiplier
)
583 * Local APIC start and shutdown
587 * clear_local_APIC - shutdown the local APIC
589 * This is called, when a CPU is disabled and before rebooting, so the state of
590 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
591 * leftovers during boot.
593 void clear_local_APIC(void)
598 /* APIC hasn't been mapped yet */
602 maxlvt
= lapic_get_maxlvt();
604 * Masking an LVT entry can trigger a local APIC error
605 * if the vector is zero. Mask LVTERR first to prevent this.
608 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
609 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
612 * Careful: we have to set masks only first to deassert
613 * any level-triggered sources.
615 v
= apic_read(APIC_LVTT
);
616 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
617 v
= apic_read(APIC_LVT0
);
618 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
619 v
= apic_read(APIC_LVT1
);
620 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
622 v
= apic_read(APIC_LVTPC
);
623 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
627 * Clean APIC state for other OSs:
629 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
630 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
631 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
633 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
635 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
636 apic_write(APIC_ESR
, 0);
641 * disable_local_APIC - clear and disable the local APIC
643 void disable_local_APIC(void)
650 * Disable APIC (implies clearing of registers
653 value
= apic_read(APIC_SPIV
);
654 value
&= ~APIC_SPIV_APIC_ENABLED
;
655 apic_write(APIC_SPIV
, value
);
658 void lapic_shutdown(void)
665 local_irq_save(flags
);
667 disable_local_APIC();
669 local_irq_restore(flags
);
673 * This is to verify that we're looking at a real local APIC.
674 * Check these against your board if the CPUs aren't getting
675 * started for no apparent reason.
677 int __init
verify_local_APIC(void)
679 unsigned int reg0
, reg1
;
682 * The version register is read-only in a real APIC.
684 reg0
= apic_read(APIC_LVR
);
685 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
686 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
687 reg1
= apic_read(APIC_LVR
);
688 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
691 * The two version reads above should print the same
692 * numbers. If the second one is different, then we
693 * poke at a non-APIC.
699 * Check if the version looks reasonably.
701 reg1
= GET_APIC_VERSION(reg0
);
702 if (reg1
== 0x00 || reg1
== 0xff)
704 reg1
= lapic_get_maxlvt();
705 if (reg1
< 0x02 || reg1
== 0xff)
709 * The ID register is read/write in a real APIC.
711 reg0
= apic_read(APIC_ID
);
712 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
713 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
714 reg1
= apic_read(APIC_ID
);
715 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
716 apic_write(APIC_ID
, reg0
);
717 if (reg1
!= (reg0
^ APIC_ID_MASK
))
721 * The next two are just to see if we have sane values.
722 * They're only really relevant if we're in Virtual Wire
723 * compatibility mode, but most boxes are anymore.
725 reg0
= apic_read(APIC_LVT0
);
726 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
727 reg1
= apic_read(APIC_LVT1
);
728 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
734 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
736 void __init
sync_Arb_IDs(void)
738 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
745 apic_wait_icr_idle();
747 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
748 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
753 * An initial setup of the virtual wire mode.
755 void __init
init_bsp_APIC(void)
760 * Don't do the setup now if we have a SMP BIOS as the
761 * through-I/O-APIC virtual wire mode might be active.
763 if (smp_found_config
|| !cpu_has_apic
)
766 value
= apic_read(APIC_LVR
);
769 * Do not trust the local APIC being empty at bootup.
776 value
= apic_read(APIC_SPIV
);
777 value
&= ~APIC_VECTOR_MASK
;
778 value
|= APIC_SPIV_APIC_ENABLED
;
779 value
|= APIC_SPIV_FOCUS_DISABLED
;
780 value
|= SPURIOUS_APIC_VECTOR
;
781 apic_write(APIC_SPIV
, value
);
784 * Set up the virtual wire mode.
786 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
788 apic_write(APIC_LVT1
, value
);
792 * setup_local_APIC - setup the local APIC
794 void __cpuinit
setup_local_APIC(void)
800 value
= apic_read(APIC_LVR
);
802 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
805 * Double-check whether this APIC is really registered.
806 * This is meaningless in clustered apic mode, so we skip it.
808 if (!apic_id_registered())
812 * Intel recommends to set DFR, LDR and TPR before enabling
813 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
814 * document number 292116). So here it goes...
819 * Set Task Priority to 'accept all'. We never change this
822 value
= apic_read(APIC_TASKPRI
);
823 value
&= ~APIC_TPRI_MASK
;
824 apic_write(APIC_TASKPRI
, value
);
827 * After a crash, we no longer service the interrupts and a pending
828 * interrupt from previous kernel might still have ISR bit set.
830 * Most probably by now CPU has serviced that pending interrupt and
831 * it might not have done the ack_APIC_irq() because it thought,
832 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
833 * does not clear the ISR bit and cpu thinks it has already serivced
834 * the interrupt. Hence a vector might get locked. It was noticed
835 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
837 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
838 value
= apic_read(APIC_ISR
+ i
*0x10);
839 for (j
= 31; j
>= 0; j
--) {
846 * Now that we are all set up, enable the APIC
848 value
= apic_read(APIC_SPIV
);
849 value
&= ~APIC_VECTOR_MASK
;
853 value
|= APIC_SPIV_APIC_ENABLED
;
855 /* We always use processor focus */
858 * Set spurious IRQ vector
860 value
|= SPURIOUS_APIC_VECTOR
;
861 apic_write(APIC_SPIV
, value
);
866 * set up through-local-APIC on the BP's LINT0. This is not
867 * strictly necessary in pure symmetric-IO mode, but sometimes
868 * we delegate interrupts to the 8259A.
871 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
873 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
874 if (!smp_processor_id() && !value
) {
875 value
= APIC_DM_EXTINT
;
876 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
879 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
880 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
883 apic_write(APIC_LVT0
, value
);
886 * only the BP should see the LINT1 NMI signal, obviously.
888 if (!smp_processor_id())
891 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
892 apic_write(APIC_LVT1
, value
);
896 static void __cpuinit
lapic_setup_esr(void)
898 unsigned maxlvt
= lapic_get_maxlvt();
900 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
);
902 * spec says clear errors after enabling vector.
905 apic_write(APIC_ESR
, 0);
908 void __cpuinit
end_local_APIC_setup(void)
911 setup_apic_nmi_watchdog(NULL
);
915 void check_x2apic(void)
919 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
921 if (msr
& X2APIC_ENABLE
) {
922 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
923 x2apic_preenabled
= x2apic
= 1;
924 apic_ops
= &x2apic_ops
;
928 void enable_x2apic(void)
932 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
933 if (!(msr
& X2APIC_ENABLE
)) {
934 printk("Enabling x2apic\n");
935 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
939 void enable_IR_x2apic(void)
941 #ifdef CONFIG_INTR_REMAP
948 if (!x2apic_preenabled
&& disable_x2apic
) {
950 "Skipped enabling x2apic and Interrupt-remapping "
951 "because of nox2apic\n");
955 if (x2apic_preenabled
&& disable_x2apic
)
956 panic("Bios already enabled x2apic, can't enforce nox2apic");
958 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
960 "Skipped enabling x2apic and Interrupt-remapping "
961 "because of skipping io-apic setup\n");
965 ret
= dmar_table_init();
968 "dmar_table_init() failed with %d:\n", ret
);
970 if (x2apic_preenabled
)
971 panic("x2apic enabled by bios. But IR enabling failed");
974 "Not enabling x2apic,Intr-remapping\n");
978 local_irq_save(flags
);
980 save_mask_IO_APIC_setup();
982 ret
= enable_intr_remapping(1);
984 if (ret
&& x2apic_preenabled
) {
985 local_irq_restore(flags
);
986 panic("x2apic enabled by bios. But IR enabling failed");
994 apic_ops
= &x2apic_ops
;
1000 * IR enabling failed
1002 restore_IO_APIC_setup();
1004 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1007 local_irq_restore(flags
);
1010 if (!x2apic_preenabled
)
1012 "Enabled x2apic and interrupt-remapping\n");
1015 "Enabled Interrupt-remapping\n");
1018 "Failed to enable Interrupt-remapping and x2apic\n");
1020 if (!cpu_has_x2apic
)
1023 if (x2apic_preenabled
)
1024 panic("x2apic enabled prior OS handover,"
1025 " enable CONFIG_INTR_REMAP");
1027 printk(KERN_INFO
"Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1035 * Detect and enable local APICs on non-SMP boards.
1036 * Original code written by Keir Fraser.
1037 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1038 * not correctly set up (usually the APIC timer won't work etc.)
1040 static int __init
detect_init_APIC(void)
1042 if (!cpu_has_apic
) {
1043 printk(KERN_INFO
"No local APIC present\n");
1047 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1048 boot_cpu_physical_apicid
= 0;
1052 void __init
early_init_lapic_mapping(void)
1054 unsigned long phys_addr
;
1057 * If no local APIC can be found then go out
1058 * : it means there is no mpatable and MADT
1060 if (!smp_found_config
)
1063 phys_addr
= mp_lapic_addr
;
1065 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1066 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1067 APIC_BASE
, phys_addr
);
1070 * Fetch the APIC ID of the BSP in case we have a
1071 * default configuration (or the MP table is broken).
1073 boot_cpu_physical_apicid
= read_apic_id();
1077 * init_apic_mappings - initialize APIC mappings
1079 void __init
init_apic_mappings(void)
1082 boot_cpu_physical_apicid
= read_apic_id();
1087 * If no local APIC can be found then set up a fake all
1088 * zeroes page to simulate the local APIC and another
1089 * one for the IO-APIC.
1091 if (!smp_found_config
&& detect_init_APIC()) {
1092 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1093 apic_phys
= __pa(apic_phys
);
1095 apic_phys
= mp_lapic_addr
;
1097 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1098 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1099 APIC_BASE
, apic_phys
);
1102 * Fetch the APIC ID of the BSP in case we have a
1103 * default configuration (or the MP table is broken).
1105 boot_cpu_physical_apicid
= read_apic_id();
1109 * This initializes the IO-APIC and APIC hardware if this is
1112 int __init
APIC_init_uniprocessor(void)
1115 printk(KERN_INFO
"Apic disabled\n");
1118 if (!cpu_has_apic
) {
1120 printk(KERN_INFO
"Apic disabled by BIOS\n");
1125 setup_apic_routing();
1127 verify_local_APIC();
1131 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1132 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1137 * Now enable IO-APICs, actually call clear_IO_APIC
1138 * We need clear_IO_APIC before enabling vector on BP
1140 if (!skip_ioapic_setup
&& nr_ioapics
)
1143 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1144 localise_nmi_watchdog();
1145 end_local_APIC_setup();
1147 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1151 setup_boot_APIC_clock();
1152 check_nmi_watchdog();
1157 * Local APIC interrupts
1161 * This interrupt should _never_ happen with our APIC/SMP architecture
1163 asmlinkage
void smp_spurious_interrupt(void)
1169 * Check if this really is a spurious interrupt and ACK it
1170 * if it is a vectored one. Just in case...
1171 * Spurious interrupts should not be ACKed.
1173 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1174 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1177 add_pda(irq_spurious_count
, 1);
1182 * This interrupt should never happen with our APIC/SMP architecture
1184 asmlinkage
void smp_error_interrupt(void)
1190 /* First tickle the hardware, only then report what went on. -- REW */
1191 v
= apic_read(APIC_ESR
);
1192 apic_write(APIC_ESR
, 0);
1193 v1
= apic_read(APIC_ESR
);
1195 atomic_inc(&irq_err_count
);
1197 /* Here is what the APIC error bits mean:
1200 2: Send accept error
1201 3: Receive accept error
1203 5: Send illegal vector
1204 6: Received illegal vector
1205 7: Illegal register address
1207 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1208 smp_processor_id(), v
, v1
);
1213 * * connect_bsp_APIC - attach the APIC to the interrupt system
1215 void __init
connect_bsp_APIC(void)
1220 void disconnect_bsp_APIC(int virt_wire_setup
)
1222 /* Go back to Virtual Wire compatibility mode */
1223 unsigned long value
;
1225 /* For the spurious interrupt use vector F, and enable it */
1226 value
= apic_read(APIC_SPIV
);
1227 value
&= ~APIC_VECTOR_MASK
;
1228 value
|= APIC_SPIV_APIC_ENABLED
;
1230 apic_write(APIC_SPIV
, value
);
1232 if (!virt_wire_setup
) {
1234 * For LVT0 make it edge triggered, active high,
1235 * external and enabled
1237 value
= apic_read(APIC_LVT0
);
1238 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1239 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1240 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1241 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1242 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1243 apic_write(APIC_LVT0
, value
);
1246 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1249 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1250 value
= apic_read(APIC_LVT1
);
1251 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1252 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1253 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1254 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1255 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1256 apic_write(APIC_LVT1
, value
);
1259 void __cpuinit
generic_processor_info(int apicid
, int version
)
1264 if (num_processors
>= NR_CPUS
) {
1265 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1266 " Processor ignored.\n", NR_CPUS
);
1270 if (num_processors
>= maxcpus
) {
1271 printk(KERN_WARNING
"WARNING: maxcpus limit of %i reached."
1272 " Processor ignored.\n", maxcpus
);
1277 cpus_complement(tmp_map
, cpu_present_map
);
1278 cpu
= first_cpu(tmp_map
);
1280 physid_set(apicid
, phys_cpu_present_map
);
1281 if (apicid
== boot_cpu_physical_apicid
) {
1283 * x86_bios_cpu_apicid is required to have processors listed
1284 * in same order as logical cpu numbers. Hence the first
1285 * entry is BSP, and so on.
1289 if (apicid
> max_physical_apicid
)
1290 max_physical_apicid
= apicid
;
1292 /* are we being called early in kernel startup? */
1293 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1294 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1295 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1297 cpu_to_apicid
[cpu
] = apicid
;
1298 bios_cpu_apicid
[cpu
] = apicid
;
1300 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1301 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1304 cpu_set(cpu
, cpu_possible_map
);
1305 cpu_set(cpu
, cpu_present_map
);
1308 int hard_smp_processor_id(void)
1310 return read_apic_id();
1319 /* 'active' is true if the local APIC was enabled by us and
1320 not the BIOS; this signifies that we are also responsible
1321 for disabling it before entering apm/acpi suspend */
1323 /* r/w apic fields */
1324 unsigned int apic_id
;
1325 unsigned int apic_taskpri
;
1326 unsigned int apic_ldr
;
1327 unsigned int apic_dfr
;
1328 unsigned int apic_spiv
;
1329 unsigned int apic_lvtt
;
1330 unsigned int apic_lvtpc
;
1331 unsigned int apic_lvt0
;
1332 unsigned int apic_lvt1
;
1333 unsigned int apic_lvterr
;
1334 unsigned int apic_tmict
;
1335 unsigned int apic_tdcr
;
1336 unsigned int apic_thmr
;
1339 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1341 unsigned long flags
;
1344 if (!apic_pm_state
.active
)
1347 maxlvt
= lapic_get_maxlvt();
1349 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1350 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1351 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1352 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1353 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1354 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1356 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1357 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1358 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1359 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1360 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1361 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1362 #ifdef CONFIG_X86_MCE_INTEL
1364 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1366 local_irq_save(flags
);
1367 disable_local_APIC();
1368 local_irq_restore(flags
);
1372 static int lapic_resume(struct sys_device
*dev
)
1375 unsigned long flags
;
1378 if (!apic_pm_state
.active
)
1381 maxlvt
= lapic_get_maxlvt();
1383 local_irq_save(flags
);
1385 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1386 l
&= ~MSR_IA32_APICBASE_BASE
;
1387 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1388 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1392 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1393 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1394 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1395 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1396 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1397 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1398 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1399 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1400 #ifdef CONFIG_X86_MCE_INTEL
1402 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1405 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1406 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1407 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1408 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1409 apic_write(APIC_ESR
, 0);
1410 apic_read(APIC_ESR
);
1411 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1412 apic_write(APIC_ESR
, 0);
1413 apic_read(APIC_ESR
);
1414 local_irq_restore(flags
);
1418 static struct sysdev_class lapic_sysclass
= {
1420 .resume
= lapic_resume
,
1421 .suspend
= lapic_suspend
,
1424 static struct sys_device device_lapic
= {
1426 .cls
= &lapic_sysclass
,
1429 static void __cpuinit
apic_pm_activate(void)
1431 apic_pm_state
.active
= 1;
1434 static int __init
init_lapic_sysfs(void)
1440 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1442 error
= sysdev_class_register(&lapic_sysclass
);
1444 error
= sysdev_register(&device_lapic
);
1447 device_initcall(init_lapic_sysfs
);
1449 #else /* CONFIG_PM */
1451 static void apic_pm_activate(void) { }
1453 #endif /* CONFIG_PM */
1456 * apic_is_clustered_box() -- Check if we can expect good TSC
1458 * Thus far, the major user of this is IBM's Summit2 series:
1460 * Clustered boxes may have unsynced TSC problems if they are
1461 * multi-chassis. Use available data to take a good guess.
1462 * If in doubt, go HPET.
1464 __cpuinit
int apic_is_clustered_box(void)
1466 int i
, clusters
, zeros
;
1468 u16
*bios_cpu_apicid
;
1469 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1472 * there is not this kind of box with AMD CPU yet.
1473 * Some AMD box with quadcore cpu and 8 sockets apicid
1474 * will be [4, 0x23] or [8, 0x27] could be thought to
1475 * vsmp box still need checking...
1477 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1480 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1481 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1483 for (i
= 0; i
< NR_CPUS
; i
++) {
1484 /* are we being called early in kernel startup? */
1485 if (bios_cpu_apicid
) {
1486 id
= bios_cpu_apicid
[i
];
1488 else if (i
< nr_cpu_ids
) {
1490 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1497 if (id
!= BAD_APICID
)
1498 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1501 /* Problem: Partially populated chassis may not have CPUs in some of
1502 * the APIC clusters they have been allocated. Only present CPUs have
1503 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1504 * Since clusters are allocated sequentially, count zeros only if
1505 * they are bounded by ones.
1509 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1510 if (test_bit(i
, clustermap
)) {
1511 clusters
+= 1 + zeros
;
1517 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1518 * not guaranteed to be synced between boards
1520 if (is_vsmp_box() && clusters
> 1)
1524 * If clusters > 2, then should be multi-chassis.
1525 * May have to revisit this when multi-core + hyperthreaded CPUs come
1526 * out, but AFAIK this will work even for them.
1528 return (clusters
> 2);
1531 static __init
int setup_nox2apic(char *str
)
1534 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_X2APIC
);
1537 early_param("nox2apic", setup_nox2apic
);
1541 * APIC command line parameters
1543 static int __init
apic_set_verbosity(char *str
)
1546 skip_ioapic_setup
= 0;
1550 if (strcmp("debug", str
) == 0)
1551 apic_verbosity
= APIC_DEBUG
;
1552 else if (strcmp("verbose", str
) == 0)
1553 apic_verbosity
= APIC_VERBOSE
;
1555 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1556 " use apic=verbose or apic=debug\n", str
);
1562 early_param("apic", apic_set_verbosity
);
1564 static __init
int setup_disableapic(char *str
)
1567 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1570 early_param("disableapic", setup_disableapic
);
1572 /* same as disableapic, for compatibility */
1573 static __init
int setup_nolapic(char *str
)
1575 return setup_disableapic(str
);
1577 early_param("nolapic", setup_nolapic
);
1579 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1581 local_apic_timer_c2_ok
= 1;
1584 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1586 static __init
int setup_noapictimer(char *str
)
1588 if (str
[0] != ' ' && str
[0] != 0)
1590 disable_apic_timer
= 1;
1593 __setup("noapictimer", setup_noapictimer
);
1595 static __init
int setup_apicpmtimer(char *s
)
1597 apic_calibrate_pmtmr
= 1;
1601 __setup("apicpmtimer", setup_apicpmtimer
);
1603 static int __init
lapic_insert_resource(void)
1608 /* Put local APIC into the resource map. */
1609 lapic_resource
.start
= apic_phys
;
1610 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1611 insert_resource(&iomem_resource
, &lapic_resource
);
1617 * need call insert after e820_reserve_resources()
1618 * that is using request_resource
1620 late_initcall(lapic_insert_resource
);