2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/bootmem.h>
23 #include <linux/ftrace.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/sysdev.h>
27 #include <linux/delay.h>
28 #include <linux/timex.h>
29 #include <linux/dmar.h>
30 #include <linux/init.h>
31 #include <linux/cpu.h>
32 #include <linux/dmi.h>
33 #include <linux/nmi.h>
34 #include <linux/smp.h>
37 #include <asm/arch_hooks.h>
38 #include <asm/pgalloc.h>
40 #include <asm/atomic.h>
41 #include <asm/mpspec.h>
42 #include <asm/i8253.h>
43 #include <asm/i8259.h>
44 #include <asm/proto.h>
52 unsigned int num_processors
;
54 unsigned disabled_cpus __cpuinitdata
;
56 /* Processor that is doing the boot up */
57 unsigned int boot_cpu_physical_apicid
= -1U;
60 * The highest APIC ID seen during enumeration.
62 * This determines the messaging protocol we can use: if all APIC IDs
63 * are in the 0 ... 7 range, then we can use logical addressing which
64 * has some performance advantages (better broadcasting).
66 * If there's an APIC ID above 8, we use physical addressing.
68 unsigned int max_physical_apicid
;
71 * Bitmask of physically existing CPUs:
73 physid_mask_t phys_cpu_present_map
;
76 * Map cpu index to physical APIC ID
78 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
79 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
81 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
85 * Knob to control our willingness to enable the local APIC.
89 static int force_enable_local_apic
;
91 * APIC command line parameters
93 static int __init
parse_lapic(char *arg
)
95 force_enable_local_apic
= 1;
98 early_param("lapic", parse_lapic
);
99 /* Local APIC was disabled by the BIOS and enabled by the kernel */
100 static int enabled_via_apicbase
;
105 static int apic_calibrate_pmtmr __initdata
;
106 static __init
int setup_apicpmtimer(char *s
)
108 apic_calibrate_pmtmr
= 1;
112 __setup("apicpmtimer", setup_apicpmtimer
);
115 #ifdef CONFIG_X86_X2APIC
117 /* x2apic enabled before OS handover */
118 static int x2apic_preenabled
;
119 static int disable_x2apic
;
120 static __init
int setup_nox2apic(char *str
)
123 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
126 early_param("nox2apic", setup_nox2apic
);
129 unsigned long mp_lapic_addr
;
131 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
132 static int disable_apic_timer __cpuinitdata
;
133 /* Local APIC timer works in C2 */
134 int local_apic_timer_c2_ok
;
135 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
137 int first_system_vector
= 0xfe;
140 * Debug level, exported for io_apic.c
142 unsigned int apic_verbosity
;
146 /* Have we found an MP table */
147 int smp_found_config
;
149 static struct resource lapic_resource
= {
150 .name
= "Local APIC",
151 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
154 static unsigned int calibration_result
;
156 static int lapic_next_event(unsigned long delta
,
157 struct clock_event_device
*evt
);
158 static void lapic_timer_setup(enum clock_event_mode mode
,
159 struct clock_event_device
*evt
);
160 static void lapic_timer_broadcast(const struct cpumask
*mask
);
161 static void apic_pm_activate(void);
164 * The local apic timer can be used for any function which is CPU local.
166 static struct clock_event_device lapic_clockevent
= {
168 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
169 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
171 .set_mode
= lapic_timer_setup
,
172 .set_next_event
= lapic_next_event
,
173 .broadcast
= lapic_timer_broadcast
,
177 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
179 static unsigned long apic_phys
;
182 * Get the LAPIC version
184 static inline int lapic_get_version(void)
186 return GET_APIC_VERSION(apic_read(APIC_LVR
));
190 * Check, if the APIC is integrated or a separate chip
192 static inline int lapic_is_integrated(void)
197 return APIC_INTEGRATED(lapic_get_version());
202 * Check, whether this is a modern or a first generation APIC
204 static int modern_apic(void)
206 /* AMD systems use old APIC versions, so check the CPU */
207 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
208 boot_cpu_data
.x86
>= 0xf)
210 return lapic_get_version() >= 0x14;
213 void native_apic_wait_icr_idle(void)
215 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
219 u32
native_safe_apic_wait_icr_idle(void)
226 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
230 } while (timeout
++ < 1000);
235 void native_apic_icr_write(u32 low
, u32 id
)
237 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
238 apic_write(APIC_ICR
, low
);
241 u64
native_apic_icr_read(void)
245 icr2
= apic_read(APIC_ICR2
);
246 icr1
= apic_read(APIC_ICR
);
248 return icr1
| ((u64
)icr2
<< 32);
252 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
254 void __cpuinit
enable_NMI_through_LVT0(void)
258 /* unmask and set to NMI */
261 /* Level triggered for 82489DX (32bit mode) */
262 if (!lapic_is_integrated())
263 v
|= APIC_LVT_LEVEL_TRIGGER
;
265 apic_write(APIC_LVT0
, v
);
270 * get_physical_broadcast - Get number of physical broadcast IDs
272 int get_physical_broadcast(void)
274 return modern_apic() ? 0xff : 0xf;
279 * lapic_get_maxlvt - get the maximum number of local vector table entries
281 int lapic_get_maxlvt(void)
285 v
= apic_read(APIC_LVR
);
287 * - we always have APIC integrated on 64bit mode
288 * - 82489DXs do not report # of LVT entries
290 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
298 #define APIC_DIVISOR 16
301 * This function sets up the local APIC timer, with a timeout of
302 * 'clocks' APIC bus clock. During calibration we actually call
303 * this function twice on the boot CPU, once with a bogus timeout
304 * value, second time for real. The other (noncalibrating) CPUs
305 * call this function only once, with the real, calibrated value.
307 * We do reads before writes even if unnecessary, to get around the
308 * P5 APIC double write bug.
310 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
312 unsigned int lvtt_value
, tmp_value
;
314 lvtt_value
= LOCAL_TIMER_VECTOR
;
316 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
317 if (!lapic_is_integrated())
318 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
321 lvtt_value
|= APIC_LVT_MASKED
;
323 apic_write(APIC_LVTT
, lvtt_value
);
328 tmp_value
= apic_read(APIC_TDCR
);
329 apic_write(APIC_TDCR
,
330 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
334 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
338 * Setup extended LVT, AMD specific (K8, family 10h)
340 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
341 * MCE interrupts are supported. Thus MCE offset must be set to 0.
343 * If mask=1, the LVT entry does not generate interrupts while mask=0
344 * enables the vector. See also the BKDGs.
347 #define APIC_EILVT_LVTOFF_MCE 0
348 #define APIC_EILVT_LVTOFF_IBS 1
350 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
352 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
353 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
358 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
360 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
361 return APIC_EILVT_LVTOFF_MCE
;
364 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
366 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
367 return APIC_EILVT_LVTOFF_IBS
;
369 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
372 * Program the next event, relative to now
374 static int lapic_next_event(unsigned long delta
,
375 struct clock_event_device
*evt
)
377 apic_write(APIC_TMICT
, delta
);
382 * Setup the lapic timer in periodic or oneshot mode
384 static void lapic_timer_setup(enum clock_event_mode mode
,
385 struct clock_event_device
*evt
)
390 /* Lapic used as dummy for broadcast ? */
391 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
394 local_irq_save(flags
);
397 case CLOCK_EVT_MODE_PERIODIC
:
398 case CLOCK_EVT_MODE_ONESHOT
:
399 __setup_APIC_LVTT(calibration_result
,
400 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
402 case CLOCK_EVT_MODE_UNUSED
:
403 case CLOCK_EVT_MODE_SHUTDOWN
:
404 v
= apic_read(APIC_LVTT
);
405 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
406 apic_write(APIC_LVTT
, v
);
407 apic_write(APIC_TMICT
, 0xffffffff);
409 case CLOCK_EVT_MODE_RESUME
:
410 /* Nothing to do here */
414 local_irq_restore(flags
);
418 * Local APIC timer broadcast function
420 static void lapic_timer_broadcast(const struct cpumask
*mask
)
423 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
428 * Setup the local APIC timer for this CPU. Copy the initilized values
429 * of the boot CPU and register the clock event in the framework.
431 static void __cpuinit
setup_APIC_timer(void)
433 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
435 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
436 levt
->cpumask
= cpumask_of(smp_processor_id());
438 clockevents_register_device(levt
);
442 * In this functions we calibrate APIC bus clocks to the external timer.
444 * We want to do the calibration only once since we want to have local timer
445 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
448 * This was previously done by reading the PIT/HPET and waiting for a wrap
449 * around to find out, that a tick has elapsed. I have a box, where the PIT
450 * readout is broken, so it never gets out of the wait loop again. This was
451 * also reported by others.
453 * Monitoring the jiffies value is inaccurate and the clockevents
454 * infrastructure allows us to do a simple substitution of the interrupt
457 * The calibration routine also uses the pm_timer when possible, as the PIT
458 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
459 * back to normal later in the boot process).
462 #define LAPIC_CAL_LOOPS (HZ/10)
464 static __initdata
int lapic_cal_loops
= -1;
465 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
466 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
467 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
468 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
471 * Temporary interrupt handler.
473 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
475 unsigned long long tsc
= 0;
476 long tapic
= apic_read(APIC_TMCCT
);
477 unsigned long pm
= acpi_pm_read_early();
482 switch (lapic_cal_loops
++) {
484 lapic_cal_t1
= tapic
;
485 lapic_cal_tsc1
= tsc
;
487 lapic_cal_j1
= jiffies
;
490 case LAPIC_CAL_LOOPS
:
491 lapic_cal_t2
= tapic
;
492 lapic_cal_tsc2
= tsc
;
493 if (pm
< lapic_cal_pm1
)
494 pm
+= ACPI_PM_OVRRUN
;
496 lapic_cal_j2
= jiffies
;
502 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
504 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
505 const long pm_thresh
= pm_100ms
/ 100;
509 #ifndef CONFIG_X86_PM_TIMER
513 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
515 /* Check, if the PM timer is available */
519 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
521 if (deltapm
> (pm_100ms
- pm_thresh
) &&
522 deltapm
< (pm_100ms
+ pm_thresh
)) {
523 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
527 res
= (((u64
)deltapm
) * mult
) >> 22;
528 do_div(res
, 1000000);
529 pr_warning("APIC calibration not consistent "
530 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
532 /* Correct the lapic counter value */
533 res
= (((u64
)(*delta
)) * pm_100ms
);
534 do_div(res
, deltapm
);
535 pr_info("APIC delta adjusted to PM-Timer: "
536 "%lu (%ld)\n", (unsigned long)res
, *delta
);
539 /* Correct the tsc counter value */
541 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
542 do_div(res
, deltapm
);
543 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
544 "PM-Timer: %lu (%ld) \n",
545 (unsigned long)res
, *deltatsc
);
546 *deltatsc
= (long)res
;
552 static int __init
calibrate_APIC_clock(void)
554 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
555 void (*real_handler
)(struct clock_event_device
*dev
);
556 unsigned long deltaj
;
557 long delta
, deltatsc
;
558 int pm_referenced
= 0;
562 /* Replace the global interrupt handler */
563 real_handler
= global_clock_event
->event_handler
;
564 global_clock_event
->event_handler
= lapic_cal_handler
;
567 * Setup the APIC counter to maximum. There is no way the lapic
568 * can underflow in the 100ms detection time frame
570 __setup_APIC_LVTT(0xffffffff, 0, 0);
572 /* Let the interrupts run */
575 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
580 /* Restore the real event handler */
581 global_clock_event
->event_handler
= real_handler
;
583 /* Build delta t1-t2 as apic timer counts down */
584 delta
= lapic_cal_t1
- lapic_cal_t2
;
585 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
587 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
589 /* we trust the PM based calibration if possible */
590 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
593 /* Calculate the scaled math multiplication factor */
594 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
595 lapic_clockevent
.shift
);
596 lapic_clockevent
.max_delta_ns
=
597 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
598 lapic_clockevent
.min_delta_ns
=
599 clockevent_delta2ns(0xF, &lapic_clockevent
);
601 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
603 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
604 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
605 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
609 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
611 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
612 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
615 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
617 calibration_result
/ (1000000 / HZ
),
618 calibration_result
% (1000000 / HZ
));
621 * Do a sanity check on the APIC calibration result
623 if (calibration_result
< (1000000 / HZ
)) {
625 pr_warning("APIC frequency too slow, disabling apic timer\n");
629 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
632 * PM timer calibration failed or not turned on
633 * so lets try APIC timer based calibration
635 if (!pm_referenced
) {
636 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
639 * Setup the apic timer manually
641 levt
->event_handler
= lapic_cal_handler
;
642 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
643 lapic_cal_loops
= -1;
645 /* Let the interrupts run */
648 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
651 /* Stop the lapic timer */
652 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
655 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
656 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
658 /* Check, if the jiffies result is consistent */
659 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
660 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
662 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
666 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
667 pr_warning("APIC timer disabled due to verification failure\n");
675 * Setup the boot APIC
677 * Calibrate and verify the result.
679 void __init
setup_boot_APIC_clock(void)
682 * The local apic timer can be disabled via the kernel
683 * commandline or from the CPU detection code. Register the lapic
684 * timer as a dummy clock event source on SMP systems, so the
685 * broadcast mechanism is used. On UP systems simply ignore it.
687 if (disable_apic_timer
) {
688 pr_info("Disabling APIC timer\n");
689 /* No broadcast on UP ! */
690 if (num_possible_cpus() > 1) {
691 lapic_clockevent
.mult
= 1;
697 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
698 "calibrating APIC timer ...\n");
700 if (calibrate_APIC_clock()) {
701 /* No broadcast on UP ! */
702 if (num_possible_cpus() > 1)
708 * If nmi_watchdog is set to IO_APIC, we need the
709 * PIT/HPET going. Otherwise register lapic as a dummy
712 if (nmi_watchdog
!= NMI_IO_APIC
)
713 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
715 pr_warning("APIC timer registered as dummy,"
716 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
718 /* Setup the lapic or request the broadcast */
722 void __cpuinit
setup_secondary_APIC_clock(void)
728 * The guts of the apic timer interrupt
730 static void local_apic_timer_interrupt(void)
732 int cpu
= smp_processor_id();
733 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
736 * Normally we should not be here till LAPIC has been initialized but
737 * in some cases like kdump, its possible that there is a pending LAPIC
738 * timer interrupt from previous kernel's context and is delivered in
739 * new kernel the moment interrupts are enabled.
741 * Interrupts are enabled early and LAPIC is setup much later, hence
742 * its possible that when we get here evt->event_handler is NULL.
743 * Check for event_handler being NULL and discard the interrupt as
746 if (!evt
->event_handler
) {
747 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
749 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
754 * the NMI deadlock-detector uses this.
756 inc_irq_stat(apic_timer_irqs
);
758 evt
->event_handler(evt
);
762 * Local APIC timer interrupt. This is the most natural way for doing
763 * local interrupts, but local timer interrupts can be emulated by
764 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
766 * [ if a single-CPU system runs an SMP kernel then we call the local
767 * interrupt as well. Thus we cannot inline the local irq ... ]
769 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
771 struct pt_regs
*old_regs
= set_irq_regs(regs
);
774 * NOTE! We'd better ACK the irq immediately,
775 * because timer handling can be slow.
779 * update_process_times() expects us to have done irq_enter().
780 * Besides, if we don't timer interrupts ignore the global
781 * interrupt lock, which is the WrongThing (tm) to do.
785 local_apic_timer_interrupt();
788 set_irq_regs(old_regs
);
791 int setup_profiling_timer(unsigned int multiplier
)
797 * Local APIC start and shutdown
801 * clear_local_APIC - shutdown the local APIC
803 * This is called, when a CPU is disabled and before rebooting, so the state of
804 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
805 * leftovers during boot.
807 void clear_local_APIC(void)
812 /* APIC hasn't been mapped yet */
816 maxlvt
= lapic_get_maxlvt();
818 * Masking an LVT entry can trigger a local APIC error
819 * if the vector is zero. Mask LVTERR first to prevent this.
822 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
823 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
826 * Careful: we have to set masks only first to deassert
827 * any level-triggered sources.
829 v
= apic_read(APIC_LVTT
);
830 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
831 v
= apic_read(APIC_LVT0
);
832 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
833 v
= apic_read(APIC_LVT1
);
834 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
836 v
= apic_read(APIC_LVTPC
);
837 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
840 /* lets not touch this if we didn't frob it */
841 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
843 v
= apic_read(APIC_LVTTHMR
);
844 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
848 * Clean APIC state for other OSs:
850 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
851 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
852 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
854 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
856 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
858 /* Integrated APIC (!82489DX) ? */
859 if (lapic_is_integrated()) {
861 /* Clear ESR due to Pentium errata 3AP and 11AP */
862 apic_write(APIC_ESR
, 0);
868 * disable_local_APIC - clear and disable the local APIC
870 void disable_local_APIC(void)
874 /* APIC hasn't been mapped yet */
881 * Disable APIC (implies clearing of registers
884 value
= apic_read(APIC_SPIV
);
885 value
&= ~APIC_SPIV_APIC_ENABLED
;
886 apic_write(APIC_SPIV
, value
);
890 * When LAPIC was disabled by the BIOS and enabled by the kernel,
891 * restore the disabled state.
893 if (enabled_via_apicbase
) {
896 rdmsr(MSR_IA32_APICBASE
, l
, h
);
897 l
&= ~MSR_IA32_APICBASE_ENABLE
;
898 wrmsr(MSR_IA32_APICBASE
, l
, h
);
904 * If Linux enabled the LAPIC against the BIOS default disable it down before
905 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
906 * not power-off. Additionally clear all LVT entries before disable_local_APIC
907 * for the case where Linux didn't enable the LAPIC.
909 void lapic_shutdown(void)
916 local_irq_save(flags
);
919 if (!enabled_via_apicbase
)
923 disable_local_APIC();
926 local_irq_restore(flags
);
930 * This is to verify that we're looking at a real local APIC.
931 * Check these against your board if the CPUs aren't getting
932 * started for no apparent reason.
934 int __init
verify_local_APIC(void)
936 unsigned int reg0
, reg1
;
939 * The version register is read-only in a real APIC.
941 reg0
= apic_read(APIC_LVR
);
942 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
943 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
944 reg1
= apic_read(APIC_LVR
);
945 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
948 * The two version reads above should print the same
949 * numbers. If the second one is different, then we
950 * poke at a non-APIC.
956 * Check if the version looks reasonably.
958 reg1
= GET_APIC_VERSION(reg0
);
959 if (reg1
== 0x00 || reg1
== 0xff)
961 reg1
= lapic_get_maxlvt();
962 if (reg1
< 0x02 || reg1
== 0xff)
966 * The ID register is read/write in a real APIC.
968 reg0
= apic_read(APIC_ID
);
969 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
970 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
971 reg1
= apic_read(APIC_ID
);
972 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
973 apic_write(APIC_ID
, reg0
);
974 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
978 * The next two are just to see if we have sane values.
979 * They're only really relevant if we're in Virtual Wire
980 * compatibility mode, but most boxes are anymore.
982 reg0
= apic_read(APIC_LVT0
);
983 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
984 reg1
= apic_read(APIC_LVT1
);
985 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
991 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
993 void __init
sync_Arb_IDs(void)
996 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
999 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1005 apic_wait_icr_idle();
1007 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1008 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1009 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1013 * An initial setup of the virtual wire mode.
1015 void __init
init_bsp_APIC(void)
1020 * Don't do the setup now if we have a SMP BIOS as the
1021 * through-I/O-APIC virtual wire mode might be active.
1023 if (smp_found_config
|| !cpu_has_apic
)
1027 * Do not trust the local APIC being empty at bootup.
1034 value
= apic_read(APIC_SPIV
);
1035 value
&= ~APIC_VECTOR_MASK
;
1036 value
|= APIC_SPIV_APIC_ENABLED
;
1038 #ifdef CONFIG_X86_32
1039 /* This bit is reserved on P4/Xeon and should be cleared */
1040 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1041 (boot_cpu_data
.x86
== 15))
1042 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1045 value
|= APIC_SPIV_FOCUS_DISABLED
;
1046 value
|= SPURIOUS_APIC_VECTOR
;
1047 apic_write(APIC_SPIV
, value
);
1050 * Set up the virtual wire mode.
1052 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1053 value
= APIC_DM_NMI
;
1054 if (!lapic_is_integrated()) /* 82489DX */
1055 value
|= APIC_LVT_LEVEL_TRIGGER
;
1056 apic_write(APIC_LVT1
, value
);
1059 static void __cpuinit
lapic_setup_esr(void)
1061 unsigned int oldvalue
, value
, maxlvt
;
1063 if (!lapic_is_integrated()) {
1064 pr_info("No ESR for 82489DX.\n");
1068 if (apic
->disable_esr
) {
1070 * Something untraceable is creating bad interrupts on
1071 * secondary quads ... for the moment, just leave the
1072 * ESR disabled - we can't do anything useful with the
1073 * errors anyway - mbligh
1075 pr_info("Leaving ESR disabled.\n");
1079 maxlvt
= lapic_get_maxlvt();
1080 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1081 apic_write(APIC_ESR
, 0);
1082 oldvalue
= apic_read(APIC_ESR
);
1084 /* enables sending errors */
1085 value
= ERROR_APIC_VECTOR
;
1086 apic_write(APIC_LVTERR
, value
);
1089 * spec says clear errors after enabling vector.
1092 apic_write(APIC_ESR
, 0);
1093 value
= apic_read(APIC_ESR
);
1094 if (value
!= oldvalue
)
1095 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1096 "vector: 0x%08x after: 0x%08x\n",
1102 * setup_local_APIC - setup the local APIC
1104 void __cpuinit
setup_local_APIC(void)
1110 arch_disable_smp_support();
1114 #ifdef CONFIG_X86_32
1115 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1116 if (lapic_is_integrated() && apic
->disable_esr
) {
1117 apic_write(APIC_ESR
, 0);
1118 apic_write(APIC_ESR
, 0);
1119 apic_write(APIC_ESR
, 0);
1120 apic_write(APIC_ESR
, 0);
1127 * Double-check whether this APIC is really registered.
1128 * This is meaningless in clustered apic mode, so we skip it.
1130 if (!apic
->apic_id_registered())
1134 * Intel recommends to set DFR, LDR and TPR before enabling
1135 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1136 * document number 292116). So here it goes...
1138 apic
->init_apic_ldr();
1141 * Set Task Priority to 'accept all'. We never change this
1144 value
= apic_read(APIC_TASKPRI
);
1145 value
&= ~APIC_TPRI_MASK
;
1146 apic_write(APIC_TASKPRI
, value
);
1149 * After a crash, we no longer service the interrupts and a pending
1150 * interrupt from previous kernel might still have ISR bit set.
1152 * Most probably by now CPU has serviced that pending interrupt and
1153 * it might not have done the ack_APIC_irq() because it thought,
1154 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1155 * does not clear the ISR bit and cpu thinks it has already serivced
1156 * the interrupt. Hence a vector might get locked. It was noticed
1157 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1159 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1160 value
= apic_read(APIC_ISR
+ i
*0x10);
1161 for (j
= 31; j
>= 0; j
--) {
1168 * Now that we are all set up, enable the APIC
1170 value
= apic_read(APIC_SPIV
);
1171 value
&= ~APIC_VECTOR_MASK
;
1175 value
|= APIC_SPIV_APIC_ENABLED
;
1177 #ifdef CONFIG_X86_32
1179 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1180 * certain networking cards. If high frequency interrupts are
1181 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1182 * entry is masked/unmasked at a high rate as well then sooner or
1183 * later IOAPIC line gets 'stuck', no more interrupts are received
1184 * from the device. If focus CPU is disabled then the hang goes
1187 * [ This bug can be reproduced easily with a level-triggered
1188 * PCI Ne2000 networking cards and PII/PIII processors, dual
1192 * Actually disabling the focus CPU check just makes the hang less
1193 * frequent as it makes the interrupt distributon model be more
1194 * like LRU than MRU (the short-term load is more even across CPUs).
1195 * See also the comment in end_level_ioapic_irq(). --macro
1199 * - enable focus processor (bit==0)
1200 * - 64bit mode always use processor focus
1201 * so no need to set it
1203 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1207 * Set spurious IRQ vector
1209 value
|= SPURIOUS_APIC_VECTOR
;
1210 apic_write(APIC_SPIV
, value
);
1213 * Set up LVT0, LVT1:
1215 * set up through-local-APIC on the BP's LINT0. This is not
1216 * strictly necessary in pure symmetric-IO mode, but sometimes
1217 * we delegate interrupts to the 8259A.
1220 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1222 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1223 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1224 value
= APIC_DM_EXTINT
;
1225 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1226 smp_processor_id());
1228 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1229 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1230 smp_processor_id());
1232 apic_write(APIC_LVT0
, value
);
1235 * only the BP should see the LINT1 NMI signal, obviously.
1237 if (!smp_processor_id())
1238 value
= APIC_DM_NMI
;
1240 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1241 if (!lapic_is_integrated()) /* 82489DX */
1242 value
|= APIC_LVT_LEVEL_TRIGGER
;
1243 apic_write(APIC_LVT1
, value
);
1248 void __cpuinit
end_local_APIC_setup(void)
1252 #ifdef CONFIG_X86_32
1255 /* Disable the local apic timer */
1256 value
= apic_read(APIC_LVTT
);
1257 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1258 apic_write(APIC_LVTT
, value
);
1262 setup_apic_nmi_watchdog(NULL
);
1266 #ifdef CONFIG_X86_X2APIC
1267 void check_x2apic(void)
1271 if (!cpu_has_x2apic
)
1274 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1276 if (msr
& X2APIC_ENABLE
) {
1277 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1278 x2apic_preenabled
= x2apic
= 1;
1282 void enable_x2apic(void)
1289 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1290 if (!(msr
& X2APIC_ENABLE
)) {
1291 pr_info("Enabling x2apic\n");
1292 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1296 void __init
enable_IR_x2apic(void)
1298 #ifdef CONFIG_INTR_REMAP
1300 unsigned long flags
;
1302 if (!cpu_has_x2apic
)
1305 if (!x2apic_preenabled
&& disable_x2apic
) {
1306 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1307 "because of nox2apic\n");
1311 if (x2apic_preenabled
&& disable_x2apic
)
1312 panic("Bios already enabled x2apic, can't enforce nox2apic");
1314 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1315 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1316 "because of skipping io-apic setup\n");
1320 ret
= dmar_table_init();
1322 pr_info("dmar_table_init() failed with %d:\n", ret
);
1324 if (x2apic_preenabled
)
1325 panic("x2apic enabled by bios. But IR enabling failed");
1327 pr_info("Not enabling x2apic,Intr-remapping\n");
1331 local_irq_save(flags
);
1334 ret
= save_mask_IO_APIC_setup();
1336 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1340 ret
= enable_intr_remapping(1);
1342 if (ret
&& x2apic_preenabled
) {
1343 local_irq_restore(flags
);
1344 panic("x2apic enabled by bios. But IR enabling failed");
1358 * IR enabling failed
1360 restore_IO_APIC_setup();
1362 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1366 local_irq_restore(flags
);
1369 if (!x2apic_preenabled
)
1370 pr_info("Enabled x2apic and interrupt-remapping\n");
1372 pr_info("Enabled Interrupt-remapping\n");
1374 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1376 if (!cpu_has_x2apic
)
1379 if (x2apic_preenabled
)
1380 panic("x2apic enabled prior OS handover,"
1381 " enable CONFIG_INTR_REMAP");
1383 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1389 #endif /* CONFIG_X86_X2APIC */
1391 #ifdef CONFIG_X86_64
1393 * Detect and enable local APICs on non-SMP boards.
1394 * Original code written by Keir Fraser.
1395 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1396 * not correctly set up (usually the APIC timer won't work etc.)
1398 static int __init
detect_init_APIC(void)
1400 if (!cpu_has_apic
) {
1401 pr_info("No local APIC present\n");
1405 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1406 boot_cpu_physical_apicid
= 0;
1411 * Detect and initialize APIC
1413 static int __init
detect_init_APIC(void)
1417 /* Disabled by kernel option? */
1421 switch (boot_cpu_data
.x86_vendor
) {
1422 case X86_VENDOR_AMD
:
1423 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1424 (boot_cpu_data
.x86
>= 15))
1427 case X86_VENDOR_INTEL
:
1428 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1429 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1436 if (!cpu_has_apic
) {
1438 * Over-ride BIOS and try to enable the local APIC only if
1439 * "lapic" specified.
1441 if (!force_enable_local_apic
) {
1442 pr_info("Local APIC disabled by BIOS -- "
1443 "you can enable it with \"lapic\"\n");
1447 * Some BIOSes disable the local APIC in the APIC_BASE
1448 * MSR. This can only be done in software for Intel P6 or later
1449 * and AMD K7 (Model > 1) or later.
1451 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1452 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1453 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1454 l
&= ~MSR_IA32_APICBASE_BASE
;
1455 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1456 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1457 enabled_via_apicbase
= 1;
1461 * The APIC feature bit should now be enabled
1464 features
= cpuid_edx(1);
1465 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1466 pr_warning("Could not enable APIC!\n");
1469 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1470 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1472 /* The BIOS may have set up the APIC at some other address */
1473 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1474 if (l
& MSR_IA32_APICBASE_ENABLE
)
1475 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1477 pr_info("Found and enabled local APIC!\n");
1484 pr_info("No local APIC present or hardware disabled\n");
1489 #ifdef CONFIG_X86_64
1490 void __init
early_init_lapic_mapping(void)
1492 unsigned long phys_addr
;
1495 * If no local APIC can be found then go out
1496 * : it means there is no mpatable and MADT
1498 if (!smp_found_config
)
1501 phys_addr
= mp_lapic_addr
;
1503 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1504 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1505 APIC_BASE
, phys_addr
);
1508 * Fetch the APIC ID of the BSP in case we have a
1509 * default configuration (or the MP table is broken).
1511 boot_cpu_physical_apicid
= read_apic_id();
1516 * init_apic_mappings - initialize APIC mappings
1518 void __init
init_apic_mappings(void)
1520 #ifdef CONFIG_X86_X2APIC
1522 boot_cpu_physical_apicid
= read_apic_id();
1528 * If no local APIC can be found then set up a fake all
1529 * zeroes page to simulate the local APIC and another
1530 * one for the IO-APIC.
1532 if (!smp_found_config
&& detect_init_APIC()) {
1533 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1534 apic_phys
= __pa(apic_phys
);
1536 apic_phys
= mp_lapic_addr
;
1538 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1539 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1540 APIC_BASE
, apic_phys
);
1543 * Fetch the APIC ID of the BSP in case we have a
1544 * default configuration (or the MP table is broken).
1546 if (boot_cpu_physical_apicid
== -1U)
1547 boot_cpu_physical_apicid
= read_apic_id();
1551 * This initializes the IO-APIC and APIC hardware if this is
1554 int apic_version
[MAX_APICS
];
1556 int __init
APIC_init_uniprocessor(void)
1559 pr_info("Apic disabled\n");
1562 #ifdef CONFIG_X86_64
1563 if (!cpu_has_apic
) {
1565 pr_info("Apic disabled by BIOS\n");
1569 if (!smp_found_config
&& !cpu_has_apic
)
1573 * Complain if the BIOS pretends there is one.
1575 if (!cpu_has_apic
&&
1576 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1577 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1578 boot_cpu_physical_apicid
);
1579 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1585 #ifdef CONFIG_X86_64
1586 default_setup_apic_routing();
1589 verify_local_APIC();
1592 #ifdef CONFIG_X86_64
1593 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1596 * Hack: In case of kdump, after a crash, kernel might be booting
1597 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1598 * might be zero if read from MP tables. Get it from LAPIC.
1600 # ifdef CONFIG_CRASH_DUMP
1601 boot_cpu_physical_apicid
= read_apic_id();
1604 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1607 #ifdef CONFIG_X86_IO_APIC
1609 * Now enable IO-APICs, actually call clear_IO_APIC
1610 * We need clear_IO_APIC before enabling error vector
1612 if (!skip_ioapic_setup
&& nr_ioapics
)
1616 end_local_APIC_setup();
1618 #ifdef CONFIG_X86_IO_APIC
1619 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1623 localise_nmi_watchdog();
1626 localise_nmi_watchdog();
1630 #ifdef CONFIG_X86_64
1631 check_nmi_watchdog();
1638 * Local APIC interrupts
1642 * This interrupt should _never_ happen with our APIC/SMP architecture
1644 void smp_spurious_interrupt(struct pt_regs
*regs
)
1651 * Check if this really is a spurious interrupt and ACK it
1652 * if it is a vectored one. Just in case...
1653 * Spurious interrupts should not be ACKed.
1655 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1656 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1659 inc_irq_stat(irq_spurious_count
);
1661 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1662 pr_info("spurious APIC interrupt on CPU#%d, "
1663 "should never happen.\n", smp_processor_id());
1668 * This interrupt should never happen with our APIC/SMP architecture
1670 void smp_error_interrupt(struct pt_regs
*regs
)
1676 /* First tickle the hardware, only then report what went on. -- REW */
1677 v
= apic_read(APIC_ESR
);
1678 apic_write(APIC_ESR
, 0);
1679 v1
= apic_read(APIC_ESR
);
1681 atomic_inc(&irq_err_count
);
1684 * Here is what the APIC error bits mean:
1686 * 1: Receive CS error
1687 * 2: Send accept error
1688 * 3: Receive accept error
1690 * 5: Send illegal vector
1691 * 6: Received illegal vector
1692 * 7: Illegal register address
1694 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1695 smp_processor_id(), v
, v1
);
1700 * connect_bsp_APIC - attach the APIC to the interrupt system
1702 void __init
connect_bsp_APIC(void)
1704 #ifdef CONFIG_X86_32
1707 * Do not trust the local APIC being empty at bootup.
1711 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1712 * local APIC to INT and NMI lines.
1714 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1715 "enabling APIC mode.\n");
1720 if (apic
->enable_apic_mode
)
1721 apic
->enable_apic_mode();
1725 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1726 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1728 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1731 void disconnect_bsp_APIC(int virt_wire_setup
)
1735 #ifdef CONFIG_X86_32
1738 * Put the board back into PIC mode (has an effect only on
1739 * certain older boards). Note that APIC interrupts, including
1740 * IPIs, won't work beyond this point! The only exception are
1743 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1744 "entering PIC mode.\n");
1751 /* Go back to Virtual Wire compatibility mode */
1753 /* For the spurious interrupt use vector F, and enable it */
1754 value
= apic_read(APIC_SPIV
);
1755 value
&= ~APIC_VECTOR_MASK
;
1756 value
|= APIC_SPIV_APIC_ENABLED
;
1758 apic_write(APIC_SPIV
, value
);
1760 if (!virt_wire_setup
) {
1762 * For LVT0 make it edge triggered, active high,
1763 * external and enabled
1765 value
= apic_read(APIC_LVT0
);
1766 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1767 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1768 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1769 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1770 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1771 apic_write(APIC_LVT0
, value
);
1774 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1778 * For LVT1 make it edge triggered, active high,
1781 value
= apic_read(APIC_LVT1
);
1782 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1783 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1784 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1785 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1786 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1787 apic_write(APIC_LVT1
, value
);
1790 void __cpuinit
generic_processor_info(int apicid
, int version
)
1797 if (version
== 0x0) {
1798 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1799 "fixing up to 0x10. (tell your hw vendor)\n",
1803 apic_version
[apicid
] = version
;
1805 if (num_processors
>= nr_cpu_ids
) {
1806 int max
= nr_cpu_ids
;
1807 int thiscpu
= max
+ disabled_cpus
;
1810 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1811 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1818 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1820 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1822 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1823 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1825 physid_set(apicid
, phys_cpu_present_map
);
1826 if (apicid
== boot_cpu_physical_apicid
) {
1828 * x86_bios_cpu_apicid is required to have processors listed
1829 * in same order as logical cpu numbers. Hence the first
1830 * entry is BSP, and so on.
1834 if (apicid
> max_physical_apicid
)
1835 max_physical_apicid
= apicid
;
1837 #ifdef CONFIG_X86_32
1839 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1840 * but we need to work other dependencies like SMP_SUSPEND etc
1841 * before this can be done without some confusion.
1842 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1843 * - Ashok Raj <ashok.raj@intel.com>
1845 if (max_physical_apicid
>= 8) {
1846 switch (boot_cpu_data
.x86_vendor
) {
1847 case X86_VENDOR_INTEL
:
1848 if (!APIC_XAPIC(version
)) {
1852 /* If P4 and above fall through */
1853 case X86_VENDOR_AMD
:
1859 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1860 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1861 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1864 set_cpu_possible(cpu
, true);
1865 set_cpu_present(cpu
, true);
1868 int hard_smp_processor_id(void)
1870 return read_apic_id();
1873 void default_init_apic_ldr(void)
1877 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1878 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1879 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1880 apic_write(APIC_LDR
, val
);
1883 #ifdef CONFIG_X86_32
1884 int default_apicid_to_node(int logical_apicid
)
1887 return apicid_2_node
[hard_smp_processor_id()];
1901 * 'active' is true if the local APIC was enabled by us and
1902 * not the BIOS; this signifies that we are also responsible
1903 * for disabling it before entering apm/acpi suspend
1906 /* r/w apic fields */
1907 unsigned int apic_id
;
1908 unsigned int apic_taskpri
;
1909 unsigned int apic_ldr
;
1910 unsigned int apic_dfr
;
1911 unsigned int apic_spiv
;
1912 unsigned int apic_lvtt
;
1913 unsigned int apic_lvtpc
;
1914 unsigned int apic_lvt0
;
1915 unsigned int apic_lvt1
;
1916 unsigned int apic_lvterr
;
1917 unsigned int apic_tmict
;
1918 unsigned int apic_tdcr
;
1919 unsigned int apic_thmr
;
1922 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1924 unsigned long flags
;
1927 if (!apic_pm_state
.active
)
1930 maxlvt
= lapic_get_maxlvt();
1932 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1933 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1934 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1935 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1936 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1937 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1939 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1940 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1941 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1942 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1943 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1944 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1945 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1947 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1950 local_irq_save(flags
);
1951 disable_local_APIC();
1952 local_irq_restore(flags
);
1956 static int lapic_resume(struct sys_device
*dev
)
1959 unsigned long flags
;
1962 if (!apic_pm_state
.active
)
1965 maxlvt
= lapic_get_maxlvt();
1967 local_irq_save(flags
);
1969 #ifdef CONFIG_X86_X2APIC
1976 * Make sure the APICBASE points to the right address
1978 * FIXME! This will be wrong if we ever support suspend on
1979 * SMP! We'll need to do this as part of the CPU restore!
1981 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1982 l
&= ~MSR_IA32_APICBASE_BASE
;
1983 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1984 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1987 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1988 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1989 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1990 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1991 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1992 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1993 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1994 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1995 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1997 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2000 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2001 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2002 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2003 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2004 apic_write(APIC_ESR
, 0);
2005 apic_read(APIC_ESR
);
2006 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2007 apic_write(APIC_ESR
, 0);
2008 apic_read(APIC_ESR
);
2010 local_irq_restore(flags
);
2016 * This device has no shutdown method - fully functioning local APICs
2017 * are needed on every CPU up until machine_halt/restart/poweroff.
2020 static struct sysdev_class lapic_sysclass
= {
2022 .resume
= lapic_resume
,
2023 .suspend
= lapic_suspend
,
2026 static struct sys_device device_lapic
= {
2028 .cls
= &lapic_sysclass
,
2031 static void __cpuinit
apic_pm_activate(void)
2033 apic_pm_state
.active
= 1;
2036 static int __init
init_lapic_sysfs(void)
2042 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2044 error
= sysdev_class_register(&lapic_sysclass
);
2046 error
= sysdev_register(&device_lapic
);
2049 device_initcall(init_lapic_sysfs
);
2051 #else /* CONFIG_PM */
2053 static void apic_pm_activate(void) { }
2055 #endif /* CONFIG_PM */
2057 #ifdef CONFIG_X86_64
2059 * apic_is_clustered_box() -- Check if we can expect good TSC
2061 * Thus far, the major user of this is IBM's Summit2 series:
2063 * Clustered boxes may have unsynced TSC problems if they are
2064 * multi-chassis. Use available data to take a good guess.
2065 * If in doubt, go HPET.
2067 __cpuinit
int apic_is_clustered_box(void)
2069 int i
, clusters
, zeros
;
2071 u16
*bios_cpu_apicid
;
2072 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2075 * there is not this kind of box with AMD CPU yet.
2076 * Some AMD box with quadcore cpu and 8 sockets apicid
2077 * will be [4, 0x23] or [8, 0x27] could be thought to
2078 * vsmp box still need checking...
2080 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2083 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2084 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2086 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2087 /* are we being called early in kernel startup? */
2088 if (bios_cpu_apicid
) {
2089 id
= bios_cpu_apicid
[i
];
2090 } else if (i
< nr_cpu_ids
) {
2092 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2098 if (id
!= BAD_APICID
)
2099 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2102 /* Problem: Partially populated chassis may not have CPUs in some of
2103 * the APIC clusters they have been allocated. Only present CPUs have
2104 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2105 * Since clusters are allocated sequentially, count zeros only if
2106 * they are bounded by ones.
2110 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2111 if (test_bit(i
, clustermap
)) {
2112 clusters
+= 1 + zeros
;
2118 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2119 * not guaranteed to be synced between boards
2121 if (is_vsmp_box() && clusters
> 1)
2125 * If clusters > 2, then should be multi-chassis.
2126 * May have to revisit this when multi-core + hyperthreaded CPUs come
2127 * out, but AFAIK this will work even for them.
2129 return (clusters
> 2);
2134 * APIC command line parameters
2136 static int __init
setup_disableapic(char *arg
)
2139 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2142 early_param("disableapic", setup_disableapic
);
2144 /* same as disableapic, for compatibility */
2145 static int __init
setup_nolapic(char *arg
)
2147 return setup_disableapic(arg
);
2149 early_param("nolapic", setup_nolapic
);
2151 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2153 local_apic_timer_c2_ok
= 1;
2156 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2158 static int __init
parse_disable_apic_timer(char *arg
)
2160 disable_apic_timer
= 1;
2163 early_param("noapictimer", parse_disable_apic_timer
);
2165 static int __init
parse_nolapic_timer(char *arg
)
2167 disable_apic_timer
= 1;
2170 early_param("nolapic_timer", parse_nolapic_timer
);
2172 static int __init
apic_set_verbosity(char *arg
)
2175 #ifdef CONFIG_X86_64
2176 skip_ioapic_setup
= 0;
2182 if (strcmp("debug", arg
) == 0)
2183 apic_verbosity
= APIC_DEBUG
;
2184 else if (strcmp("verbose", arg
) == 0)
2185 apic_verbosity
= APIC_VERBOSE
;
2187 pr_warning("APIC Verbosity level %s not recognised"
2188 " use apic=verbose or apic=debug\n", arg
);
2194 early_param("apic", apic_set_verbosity
);
2196 static int __init
lapic_insert_resource(void)
2201 /* Put local APIC into the resource map. */
2202 lapic_resource
.start
= apic_phys
;
2203 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2204 insert_resource(&iomem_resource
, &lapic_resource
);
2210 * need call insert after e820_reserve_resources()
2211 * that is using request_resource
2213 late_initcall(lapic_insert_resource
);