2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
58 #include <asm/msidef.h>
59 #include <asm/hypertransport.h>
60 #include <asm/setup.h>
61 #include <asm/irq_remapping.h>
63 #include <asm/hw_irq.h>
67 #define __apicdebuginit(type) static type __init
68 #define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
72 * Is the SiS APIC rmw bug present ?
73 * -1 = don't know, 0 = no, 1 = yes
75 int sis_apic_bug
= -1;
77 static DEFINE_RAW_SPINLOCK(ioapic_lock
);
78 static DEFINE_RAW_SPINLOCK(vector_lock
);
81 * # of IRQ routing registers
83 int nr_ioapic_registers
[MAX_IO_APICS
];
85 /* I/O APIC entries */
86 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
89 /* IO APIC gsi routing info */
90 struct mp_ioapic_gsi mp_gsi_routing
[MAX_IO_APICS
];
92 /* The one past the highest gsi number used */
95 /* MP IRQ source entries */
96 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
98 /* # of MP IRQ source entries */
102 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
104 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
105 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
108 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
110 int skip_ioapic_setup
;
112 void arch_disable_smp_support(void)
116 noioapicreroute
= -1;
118 skip_ioapic_setup
= 1;
121 static int __init
parse_noapic(char *str
)
123 /* disable IO-APIC */
124 arch_disable_smp_support();
127 early_param("noapic", parse_noapic
);
129 struct irq_pin_list
{
131 struct irq_pin_list
*next
;
134 static struct irq_pin_list
*get_one_free_irq_2_pin(int node
)
136 struct irq_pin_list
*pin
;
138 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
143 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
144 #ifdef CONFIG_SPARSE_IRQ
145 static struct irq_cfg irq_cfgx
[NR_IRQS_LEGACY
];
147 static struct irq_cfg irq_cfgx
[NR_IRQS
];
150 int __init
arch_early_irq_init(void)
153 struct irq_desc
*desc
;
158 if (!legacy_pic
->nr_legacy_irqs
) {
164 count
= ARRAY_SIZE(irq_cfgx
);
165 node
= cpu_to_node(0);
167 for (i
= 0; i
< count
; i
++) {
168 desc
= irq_to_desc(i
);
169 desc
->chip_data
= &cfg
[i
];
170 zalloc_cpumask_var_node(&cfg
[i
].domain
, GFP_NOWAIT
, node
);
171 zalloc_cpumask_var_node(&cfg
[i
].old_domain
, GFP_NOWAIT
, node
);
173 * For legacy IRQ's, start with assigning irq0 to irq15 to
174 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
176 if (i
< legacy_pic
->nr_legacy_irqs
) {
177 cfg
[i
].vector
= IRQ0_VECTOR
+ i
;
178 cpumask_set_cpu(0, cfg
[i
].domain
);
185 #ifdef CONFIG_SPARSE_IRQ
186 struct irq_cfg
*irq_cfg(unsigned int irq
)
188 struct irq_cfg
*cfg
= NULL
;
189 struct irq_desc
*desc
;
191 desc
= irq_to_desc(irq
);
193 cfg
= desc
->chip_data
;
198 static struct irq_cfg
*get_one_free_irq_cfg(int node
)
202 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
204 if (!zalloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
207 } else if (!zalloc_cpumask_var_node(&cfg
->old_domain
,
209 free_cpumask_var(cfg
->domain
);
218 int arch_init_chip_data(struct irq_desc
*desc
, int node
)
222 cfg
= desc
->chip_data
;
224 desc
->chip_data
= get_one_free_irq_cfg(node
);
225 if (!desc
->chip_data
) {
226 printk(KERN_ERR
"can not alloc irq_cfg\n");
234 /* for move_irq_desc */
236 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int node
)
238 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
240 cfg
->irq_2_pin
= NULL
;
241 old_entry
= old_cfg
->irq_2_pin
;
245 entry
= get_one_free_irq_2_pin(node
);
249 entry
->apic
= old_entry
->apic
;
250 entry
->pin
= old_entry
->pin
;
253 old_entry
= old_entry
->next
;
255 entry
= get_one_free_irq_2_pin(node
);
263 /* still use the old one */
266 entry
->apic
= old_entry
->apic
;
267 entry
->pin
= old_entry
->pin
;
270 old_entry
= old_entry
->next
;
274 cfg
->irq_2_pin
= head
;
277 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
279 struct irq_pin_list
*entry
, *next
;
281 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
284 entry
= old_cfg
->irq_2_pin
;
291 old_cfg
->irq_2_pin
= NULL
;
294 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
295 struct irq_desc
*desc
, int node
)
298 struct irq_cfg
*old_cfg
;
300 cfg
= get_one_free_irq_cfg(node
);
305 desc
->chip_data
= cfg
;
307 old_cfg
= old_desc
->chip_data
;
309 cfg
->vector
= old_cfg
->vector
;
310 cfg
->move_in_progress
= old_cfg
->move_in_progress
;
311 cpumask_copy(cfg
->domain
, old_cfg
->domain
);
312 cpumask_copy(cfg
->old_domain
, old_cfg
->old_domain
);
314 init_copy_irq_2_pin(old_cfg
, cfg
, node
);
317 static void free_irq_cfg(struct irq_cfg
*cfg
)
319 free_cpumask_var(cfg
->domain
);
320 free_cpumask_var(cfg
->old_domain
);
324 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
326 struct irq_cfg
*old_cfg
, *cfg
;
328 old_cfg
= old_desc
->chip_data
;
329 cfg
= desc
->chip_data
;
335 free_irq_2_pin(old_cfg
, cfg
);
336 free_irq_cfg(old_cfg
);
337 old_desc
->chip_data
= NULL
;
340 /* end for move_irq_desc */
343 struct irq_cfg
*irq_cfg(unsigned int irq
)
345 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
352 unsigned int unused
[3];
354 unsigned int unused2
[11];
358 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
360 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
361 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
364 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
366 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
367 writel(vector
, &io_apic
->eoi
);
370 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
372 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
373 writel(reg
, &io_apic
->index
);
374 return readl(&io_apic
->data
);
377 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
379 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
380 writel(reg
, &io_apic
->index
);
381 writel(value
, &io_apic
->data
);
385 * Re-write a value: to be used for read-modify-write
386 * cycles where the read already set up the index register.
388 * Older SiS APIC requires we rewrite the index register
390 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
392 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
395 writel(reg
, &io_apic
->index
);
396 writel(value
, &io_apic
->data
);
399 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
401 struct irq_pin_list
*entry
;
404 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
405 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
410 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
411 /* Is the remote IRR bit set? */
412 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
413 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
417 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
423 struct { u32 w1
, w2
; };
424 struct IO_APIC_route_entry entry
;
427 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
429 union entry_union eu
;
431 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
432 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
433 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
434 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
439 * When we write a new IO APIC routing entry, we need to write the high
440 * word first! If the mask bit in the low word is clear, we will enable
441 * the interrupt, and we need to make sure the entry is fully populated
442 * before that happens.
445 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
447 union entry_union eu
= {{0, 0}};
450 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
451 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
454 void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
457 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
458 __ioapic_write_entry(apic
, pin
, e
);
459 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
463 * When we mask an IO APIC routing entry, we need to write the low
464 * word first, in order to set the mask bit before we change the
467 static void ioapic_mask_entry(int apic
, int pin
)
470 union entry_union eu
= { .entry
.mask
= 1 };
472 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
473 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
474 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
475 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
479 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
480 * shared ISA-space IRQs, so we have to support them. We are super
481 * fast in the common case, and fast for shared ISA-space IRQs.
484 add_pin_to_irq_node_nopanic(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
486 struct irq_pin_list
**last
, *entry
;
488 /* don't allow duplicates */
489 last
= &cfg
->irq_2_pin
;
490 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
491 if (entry
->apic
== apic
&& entry
->pin
== pin
)
496 entry
= get_one_free_irq_2_pin(node
);
498 printk(KERN_ERR
"can not alloc irq_pin_list (%d,%d,%d)\n",
509 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
511 if (add_pin_to_irq_node_nopanic(cfg
, node
, apic
, pin
))
512 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
516 * Reroute an IRQ to a different pin.
518 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
519 int oldapic
, int oldpin
,
520 int newapic
, int newpin
)
522 struct irq_pin_list
*entry
;
524 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
525 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
526 entry
->apic
= newapic
;
528 /* every one is different, right? */
533 /* old apic/pin didn't exist, so just add new ones */
534 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
537 static void __io_apic_modify_irq(struct irq_pin_list
*entry
,
538 int mask_and
, int mask_or
,
539 void (*final
)(struct irq_pin_list
*entry
))
541 unsigned int reg
, pin
;
544 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
547 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
552 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
553 int mask_and
, int mask_or
,
554 void (*final
)(struct irq_pin_list
*entry
))
556 struct irq_pin_list
*entry
;
558 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
559 __io_apic_modify_irq(entry
, mask_and
, mask_or
, final
);
562 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list
*entry
)
564 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
565 IO_APIC_REDIR_MASKED
, NULL
);
568 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list
*entry
)
570 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_MASKED
,
571 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
574 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
576 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
579 static void io_apic_sync(struct irq_pin_list
*entry
)
582 * Synchronize the IO-APIC and the CPU by doing
583 * a dummy read from the IO-APIC
585 struct io_apic __iomem
*io_apic
;
586 io_apic
= io_apic_base(entry
->apic
);
587 readl(&io_apic
->data
);
590 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
592 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
595 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
597 struct irq_cfg
*cfg
= desc
->chip_data
;
602 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
603 __mask_IO_APIC_irq(cfg
);
604 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
607 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
609 struct irq_cfg
*cfg
= desc
->chip_data
;
612 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
613 __unmask_IO_APIC_irq(cfg
);
614 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
617 static void mask_IO_APIC_irq(unsigned int irq
)
619 struct irq_desc
*desc
= irq_to_desc(irq
);
621 mask_IO_APIC_irq_desc(desc
);
623 static void unmask_IO_APIC_irq(unsigned int irq
)
625 struct irq_desc
*desc
= irq_to_desc(irq
);
627 unmask_IO_APIC_irq_desc(desc
);
630 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
632 struct IO_APIC_route_entry entry
;
634 /* Check delivery_mode to be sure we're not clearing an SMI pin */
635 entry
= ioapic_read_entry(apic
, pin
);
636 if (entry
.delivery_mode
== dest_SMI
)
639 * Disable it in the IO-APIC irq-routing table:
641 ioapic_mask_entry(apic
, pin
);
644 static void clear_IO_APIC (void)
648 for (apic
= 0; apic
< nr_ioapics
; apic
++)
649 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
650 clear_IO_APIC_pin(apic
, pin
);
655 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
656 * specific CPU-side IRQs.
660 static int pirq_entries
[MAX_PIRQS
] = {
661 [0 ... MAX_PIRQS
- 1] = -1
664 static int __init
ioapic_pirq_setup(char *str
)
667 int ints
[MAX_PIRQS
+1];
669 get_options(str
, ARRAY_SIZE(ints
), ints
);
671 apic_printk(APIC_VERBOSE
, KERN_INFO
672 "PIRQ redirection, working around broken MP-BIOS.\n");
674 if (ints
[0] < MAX_PIRQS
)
677 for (i
= 0; i
< max
; i
++) {
678 apic_printk(APIC_VERBOSE
, KERN_DEBUG
679 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
681 * PIRQs are mapped upside down, usually.
683 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
688 __setup("pirq=", ioapic_pirq_setup
);
689 #endif /* CONFIG_X86_32 */
691 struct IO_APIC_route_entry
**alloc_ioapic_entries(void)
694 struct IO_APIC_route_entry
**ioapic_entries
;
696 ioapic_entries
= kzalloc(sizeof(*ioapic_entries
) * nr_ioapics
,
701 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
702 ioapic_entries
[apic
] =
703 kzalloc(sizeof(struct IO_APIC_route_entry
) *
704 nr_ioapic_registers
[apic
], GFP_ATOMIC
);
705 if (!ioapic_entries
[apic
])
709 return ioapic_entries
;
713 kfree(ioapic_entries
[apic
]);
714 kfree(ioapic_entries
);
720 * Saves all the IO-APIC RTE's
722 int save_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
729 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
730 if (!ioapic_entries
[apic
])
733 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
734 ioapic_entries
[apic
][pin
] =
735 ioapic_read_entry(apic
, pin
);
742 * Mask all IO APIC entries.
744 void mask_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
751 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
752 if (!ioapic_entries
[apic
])
755 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
756 struct IO_APIC_route_entry entry
;
758 entry
= ioapic_entries
[apic
][pin
];
761 ioapic_write_entry(apic
, pin
, entry
);
768 * Restore IO APIC entries which was saved in ioapic_entries.
770 int restore_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
777 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
778 if (!ioapic_entries
[apic
])
781 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
782 ioapic_write_entry(apic
, pin
,
783 ioapic_entries
[apic
][pin
]);
788 void free_ioapic_entries(struct IO_APIC_route_entry
**ioapic_entries
)
792 for (apic
= 0; apic
< nr_ioapics
; apic
++)
793 kfree(ioapic_entries
[apic
]);
795 kfree(ioapic_entries
);
799 * Find the IRQ entry number of a certain pin.
801 static int find_irq_entry(int apic
, int pin
, int type
)
805 for (i
= 0; i
< mp_irq_entries
; i
++)
806 if (mp_irqs
[i
].irqtype
== type
&&
807 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
808 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
809 mp_irqs
[i
].dstirq
== pin
)
816 * Find the pin to which IRQ[irq] (ISA) is connected
818 static int __init
find_isa_irq_pin(int irq
, int type
)
822 for (i
= 0; i
< mp_irq_entries
; i
++) {
823 int lbus
= mp_irqs
[i
].srcbus
;
825 if (test_bit(lbus
, mp_bus_not_pci
) &&
826 (mp_irqs
[i
].irqtype
== type
) &&
827 (mp_irqs
[i
].srcbusirq
== irq
))
829 return mp_irqs
[i
].dstirq
;
834 static int __init
find_isa_irq_apic(int irq
, int type
)
838 for (i
= 0; i
< mp_irq_entries
; i
++) {
839 int lbus
= mp_irqs
[i
].srcbus
;
841 if (test_bit(lbus
, mp_bus_not_pci
) &&
842 (mp_irqs
[i
].irqtype
== type
) &&
843 (mp_irqs
[i
].srcbusirq
== irq
))
846 if (i
< mp_irq_entries
) {
848 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
849 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
857 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
859 * EISA Edge/Level control register, ELCR
861 static int EISA_ELCR(unsigned int irq
)
863 if (irq
< legacy_pic
->nr_legacy_irqs
) {
864 unsigned int port
= 0x4d0 + (irq
>> 3);
865 return (inb(port
) >> (irq
& 7)) & 1;
867 apic_printk(APIC_VERBOSE
, KERN_INFO
868 "Broken MPtable reports ISA irq %d\n", irq
);
874 /* ISA interrupts are always polarity zero edge triggered,
875 * when listed as conforming in the MP table. */
877 #define default_ISA_trigger(idx) (0)
878 #define default_ISA_polarity(idx) (0)
880 /* EISA interrupts are always polarity zero and can be edge or level
881 * trigger depending on the ELCR value. If an interrupt is listed as
882 * EISA conforming in the MP table, that means its trigger type must
883 * be read in from the ELCR */
885 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
886 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
888 /* PCI interrupts are always polarity one level triggered,
889 * when listed as conforming in the MP table. */
891 #define default_PCI_trigger(idx) (1)
892 #define default_PCI_polarity(idx) (1)
894 /* MCA interrupts are always polarity zero level triggered,
895 * when listed as conforming in the MP table. */
897 #define default_MCA_trigger(idx) (1)
898 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
900 static int MPBIOS_polarity(int idx
)
902 int bus
= mp_irqs
[idx
].srcbus
;
906 * Determine IRQ line polarity (high active or low active):
908 switch (mp_irqs
[idx
].irqflag
& 3)
910 case 0: /* conforms, ie. bus-type dependent polarity */
911 if (test_bit(bus
, mp_bus_not_pci
))
912 polarity
= default_ISA_polarity(idx
);
914 polarity
= default_PCI_polarity(idx
);
916 case 1: /* high active */
921 case 2: /* reserved */
923 printk(KERN_WARNING
"broken BIOS!!\n");
927 case 3: /* low active */
932 default: /* invalid */
934 printk(KERN_WARNING
"broken BIOS!!\n");
942 static int MPBIOS_trigger(int idx
)
944 int bus
= mp_irqs
[idx
].srcbus
;
948 * Determine IRQ trigger mode (edge or level sensitive):
950 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
952 case 0: /* conforms, ie. bus-type dependent */
953 if (test_bit(bus
, mp_bus_not_pci
))
954 trigger
= default_ISA_trigger(idx
);
956 trigger
= default_PCI_trigger(idx
);
957 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
958 switch (mp_bus_id_to_type
[bus
]) {
959 case MP_BUS_ISA
: /* ISA pin */
961 /* set before the switch */
964 case MP_BUS_EISA
: /* EISA pin */
966 trigger
= default_EISA_trigger(idx
);
969 case MP_BUS_PCI
: /* PCI pin */
971 /* set before the switch */
974 case MP_BUS_MCA
: /* MCA pin */
976 trigger
= default_MCA_trigger(idx
);
981 printk(KERN_WARNING
"broken BIOS!!\n");
993 case 2: /* reserved */
995 printk(KERN_WARNING
"broken BIOS!!\n");
1004 default: /* invalid */
1006 printk(KERN_WARNING
"broken BIOS!!\n");
1014 static inline int irq_polarity(int idx
)
1016 return MPBIOS_polarity(idx
);
1019 static inline int irq_trigger(int idx
)
1021 return MPBIOS_trigger(idx
);
1024 static int pin_2_irq(int idx
, int apic
, int pin
)
1027 int bus
= mp_irqs
[idx
].srcbus
;
1030 * Debugging check, we are in big trouble if this message pops up!
1032 if (mp_irqs
[idx
].dstirq
!= pin
)
1033 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1035 if (test_bit(bus
, mp_bus_not_pci
)) {
1036 irq
= mp_irqs
[idx
].srcbusirq
;
1038 u32 gsi
= mp_gsi_routing
[apic
].gsi_base
+ pin
;
1040 if (gsi
>= NR_IRQS_LEGACY
)
1043 irq
= gsi_top
+ gsi
;
1046 #ifdef CONFIG_X86_32
1048 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1050 if ((pin
>= 16) && (pin
<= 23)) {
1051 if (pirq_entries
[pin
-16] != -1) {
1052 if (!pirq_entries
[pin
-16]) {
1053 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1054 "disabling PIRQ%d\n", pin
-16);
1056 irq
= pirq_entries
[pin
-16];
1057 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1058 "using PIRQ%d -> IRQ %d\n",
1069 * Find a specific PCI IRQ entry.
1070 * Not an __init, possibly needed by modules
1072 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
1073 struct io_apic_irq_attr
*irq_attr
)
1075 int apic
, i
, best_guess
= -1;
1077 apic_printk(APIC_DEBUG
,
1078 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1080 if (test_bit(bus
, mp_bus_not_pci
)) {
1081 apic_printk(APIC_VERBOSE
,
1082 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1085 for (i
= 0; i
< mp_irq_entries
; i
++) {
1086 int lbus
= mp_irqs
[i
].srcbus
;
1088 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1089 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1090 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1093 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1094 !mp_irqs
[i
].irqtype
&&
1096 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1097 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1099 if (!(apic
|| IO_APIC_IRQ(irq
)))
1102 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1103 set_io_apic_irq_attr(irq_attr
, apic
,
1110 * Use the first all-but-pin matching entry as a
1111 * best-guess fuzzy result for broken mptables.
1113 if (best_guess
< 0) {
1114 set_io_apic_irq_attr(irq_attr
, apic
,
1124 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1126 void lock_vector_lock(void)
1128 /* Used to the online set of cpus does not change
1129 * during assign_irq_vector.
1131 raw_spin_lock(&vector_lock
);
1134 void unlock_vector_lock(void)
1136 raw_spin_unlock(&vector_lock
);
1140 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1143 * NOTE! The local APIC isn't very good at handling
1144 * multiple interrupts at the same interrupt level.
1145 * As the interrupt level is determined by taking the
1146 * vector number and shifting that right by 4, we
1147 * want to spread these out a bit so that they don't
1148 * all fall in the same interrupt level.
1150 * Also, we've got to be careful not to trash gate
1151 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1153 static int current_vector
= FIRST_EXTERNAL_VECTOR
+ VECTOR_OFFSET_START
;
1154 static int current_offset
= VECTOR_OFFSET_START
% 8;
1155 unsigned int old_vector
;
1157 cpumask_var_t tmp_mask
;
1159 if (cfg
->move_in_progress
)
1162 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1165 old_vector
= cfg
->vector
;
1167 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1168 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1169 if (!cpumask_empty(tmp_mask
)) {
1170 free_cpumask_var(tmp_mask
);
1175 /* Only try and allocate irqs on cpus that are present */
1177 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1181 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1183 vector
= current_vector
;
1184 offset
= current_offset
;
1187 if (vector
>= first_system_vector
) {
1188 /* If out of vectors on large boxen, must share them. */
1189 offset
= (offset
+ 1) % 8;
1190 vector
= FIRST_EXTERNAL_VECTOR
+ offset
;
1192 if (unlikely(current_vector
== vector
))
1195 if (test_bit(vector
, used_vectors
))
1198 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1199 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1202 current_vector
= vector
;
1203 current_offset
= offset
;
1205 cfg
->move_in_progress
= 1;
1206 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1208 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1209 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1210 cfg
->vector
= vector
;
1211 cpumask_copy(cfg
->domain
, tmp_mask
);
1215 free_cpumask_var(tmp_mask
);
1219 int assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1222 unsigned long flags
;
1224 raw_spin_lock_irqsave(&vector_lock
, flags
);
1225 err
= __assign_irq_vector(irq
, cfg
, mask
);
1226 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
1230 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1234 BUG_ON(!cfg
->vector
);
1236 vector
= cfg
->vector
;
1237 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1238 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1241 cpumask_clear(cfg
->domain
);
1243 if (likely(!cfg
->move_in_progress
))
1245 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1246 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1248 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1250 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1254 cfg
->move_in_progress
= 0;
1257 void __setup_vector_irq(int cpu
)
1259 /* Initialize vector_irq on a new cpu */
1261 struct irq_cfg
*cfg
;
1262 struct irq_desc
*desc
;
1265 * vector_lock will make sure that we don't run into irq vector
1266 * assignments that might be happening on another cpu in parallel,
1267 * while we setup our initial vector to irq mappings.
1269 raw_spin_lock(&vector_lock
);
1270 /* Mark the inuse vectors */
1271 for_each_irq_desc(irq
, desc
) {
1272 cfg
= desc
->chip_data
;
1275 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1276 * will be part of the irq_cfg's domain.
1278 if (irq
< legacy_pic
->nr_legacy_irqs
&& !IO_APIC_IRQ(irq
))
1279 cpumask_set_cpu(cpu
, cfg
->domain
);
1281 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1283 vector
= cfg
->vector
;
1284 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1286 /* Mark the free vectors */
1287 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1288 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1293 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1294 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1296 raw_spin_unlock(&vector_lock
);
1299 static struct irq_chip ioapic_chip
;
1300 static struct irq_chip ir_ioapic_chip
;
1302 #define IOAPIC_AUTO -1
1303 #define IOAPIC_EDGE 0
1304 #define IOAPIC_LEVEL 1
1306 #ifdef CONFIG_X86_32
1307 static inline int IO_APIC_irq_trigger(int irq
)
1311 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1312 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1313 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1314 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1315 return irq_trigger(idx
);
1319 * nonexistent IRQs are edge default
1324 static inline int IO_APIC_irq_trigger(int irq
)
1330 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1333 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1334 trigger
== IOAPIC_LEVEL
)
1335 desc
->status
|= IRQ_LEVEL
;
1337 desc
->status
&= ~IRQ_LEVEL
;
1339 if (irq_remapped(irq
)) {
1340 desc
->status
|= IRQ_MOVE_PCNTXT
;
1342 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1346 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1347 handle_edge_irq
, "edge");
1351 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1352 trigger
== IOAPIC_LEVEL
)
1353 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1357 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1358 handle_edge_irq
, "edge");
1361 int setup_ioapic_entry(int apic_id
, int irq
,
1362 struct IO_APIC_route_entry
*entry
,
1363 unsigned int destination
, int trigger
,
1364 int polarity
, int vector
, int pin
)
1367 * add it to the IO-APIC irq-routing table:
1369 memset(entry
,0,sizeof(*entry
));
1371 if (intr_remapping_enabled
) {
1372 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1374 struct IR_IO_APIC_route_entry
*ir_entry
=
1375 (struct IR_IO_APIC_route_entry
*) entry
;
1379 panic("No mapping iommu for ioapic %d\n", apic_id
);
1381 index
= alloc_irte(iommu
, irq
, 1);
1383 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1385 prepare_irte(&irte
, vector
, destination
);
1387 /* Set source-id of interrupt request */
1388 set_ioapic_sid(&irte
, apic_id
);
1390 modify_irte(irq
, &irte
);
1392 ir_entry
->index2
= (index
>> 15) & 0x1;
1394 ir_entry
->format
= 1;
1395 ir_entry
->index
= (index
& 0x7fff);
1397 * IO-APIC RTE will be configured with virtual vector.
1398 * irq handler will do the explicit EOI to the io-apic.
1400 ir_entry
->vector
= pin
;
1402 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1403 entry
->dest_mode
= apic
->irq_dest_mode
;
1404 entry
->dest
= destination
;
1405 entry
->vector
= vector
;
1408 entry
->mask
= 0; /* enable IRQ */
1409 entry
->trigger
= trigger
;
1410 entry
->polarity
= polarity
;
1412 /* Mask level triggered irqs.
1413 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1420 static void setup_IO_APIC_irq(int apic_id
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1421 int trigger
, int polarity
)
1423 struct irq_cfg
*cfg
;
1424 struct IO_APIC_route_entry entry
;
1427 if (!IO_APIC_IRQ(irq
))
1430 cfg
= desc
->chip_data
;
1433 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1434 * controllers like 8259. Now that IO-APIC can handle this irq, update
1437 if (irq
< legacy_pic
->nr_legacy_irqs
&& cpumask_test_cpu(0, cfg
->domain
))
1438 apic
->vector_allocation_domain(0, cfg
->domain
);
1440 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1443 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1445 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1446 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1447 "IRQ %d Mode:%i Active:%i)\n",
1448 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1449 irq
, trigger
, polarity
);
1452 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1453 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1454 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1455 mp_ioapics
[apic_id
].apicid
, pin
);
1456 __clear_irq_vector(irq
, cfg
);
1460 ioapic_register_intr(irq
, desc
, trigger
);
1461 if (irq
< legacy_pic
->nr_legacy_irqs
)
1462 legacy_pic
->chip
->mask(irq
);
1464 ioapic_write_entry(apic_id
, pin
, entry
);
1468 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
1469 } mp_ioapic_routing
[MAX_IO_APICS
];
1471 static void __init
setup_IO_APIC_irqs(void)
1473 int apic_id
, pin
, idx
, irq
;
1475 struct irq_desc
*desc
;
1476 struct irq_cfg
*cfg
;
1477 int node
= cpu_to_node(0);
1479 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1481 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++)
1482 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1483 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1487 apic_printk(APIC_VERBOSE
,
1488 KERN_DEBUG
" %d-%d",
1489 mp_ioapics
[apic_id
].apicid
, pin
);
1491 apic_printk(APIC_VERBOSE
, " %d-%d",
1492 mp_ioapics
[apic_id
].apicid
, pin
);
1496 apic_printk(APIC_VERBOSE
,
1497 " (apicid-pin) not connected\n");
1501 irq
= pin_2_irq(idx
, apic_id
, pin
);
1503 if ((apic_id
> 0) && (irq
> 16))
1507 * Skip the timer IRQ if there's a quirk handler
1508 * installed and if it returns 1:
1510 if (apic
->multi_timer_check
&&
1511 apic
->multi_timer_check(apic_id
, irq
))
1514 desc
= irq_to_desc_alloc_node(irq
, node
);
1516 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1519 cfg
= desc
->chip_data
;
1520 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1522 * don't mark it in pin_programmed, so later acpi could
1523 * set it correctly when irq < 16
1525 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1526 irq_trigger(idx
), irq_polarity(idx
));
1530 apic_printk(APIC_VERBOSE
,
1531 " (apicid-pin) not connected\n");
1535 * for the gsit that is not in first ioapic
1536 * but could not use acpi_register_gsi()
1537 * like some special sci in IBM x3330
1539 void setup_IO_APIC_irq_extra(u32 gsi
)
1541 int apic_id
= 0, pin
, idx
, irq
;
1542 int node
= cpu_to_node(0);
1543 struct irq_desc
*desc
;
1544 struct irq_cfg
*cfg
;
1547 * Convert 'gsi' to 'ioapic.pin'.
1549 apic_id
= mp_find_ioapic(gsi
);
1553 pin
= mp_find_ioapic_pin(apic_id
, gsi
);
1554 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1558 irq
= pin_2_irq(idx
, apic_id
, pin
);
1559 #ifdef CONFIG_SPARSE_IRQ
1560 desc
= irq_to_desc(irq
);
1564 desc
= irq_to_desc_alloc_node(irq
, node
);
1566 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1570 cfg
= desc
->chip_data
;
1571 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1573 if (test_bit(pin
, mp_ioapic_routing
[apic_id
].pin_programmed
)) {
1574 pr_debug("Pin %d-%d already programmed\n",
1575 mp_ioapics
[apic_id
].apicid
, pin
);
1578 set_bit(pin
, mp_ioapic_routing
[apic_id
].pin_programmed
);
1580 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1581 irq_trigger(idx
), irq_polarity(idx
));
1585 * Set up the timer pin, possibly with the 8259A-master behind.
1587 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1590 struct IO_APIC_route_entry entry
;
1592 if (intr_remapping_enabled
)
1595 memset(&entry
, 0, sizeof(entry
));
1598 * We use logical delivery to get the timer IRQ
1601 entry
.dest_mode
= apic
->irq_dest_mode
;
1602 entry
.mask
= 0; /* don't mask IRQ for edge */
1603 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1604 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1607 entry
.vector
= vector
;
1610 * The timer IRQ doesn't have to know that behind the
1611 * scene we may have a 8259A-master in AEOI mode ...
1613 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1616 * Add it to the IO-APIC irq-routing table:
1618 ioapic_write_entry(apic_id
, pin
, entry
);
1622 __apicdebuginit(void) print_IO_APIC(void)
1625 union IO_APIC_reg_00 reg_00
;
1626 union IO_APIC_reg_01 reg_01
;
1627 union IO_APIC_reg_02 reg_02
;
1628 union IO_APIC_reg_03 reg_03
;
1629 unsigned long flags
;
1630 struct irq_cfg
*cfg
;
1631 struct irq_desc
*desc
;
1634 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1635 for (i
= 0; i
< nr_ioapics
; i
++)
1636 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1637 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1640 * We are a bit conservative about what we expect. We have to
1641 * know about every hardware change ASAP.
1643 printk(KERN_INFO
"testing the IO APIC.......................\n");
1645 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1647 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1648 reg_00
.raw
= io_apic_read(apic
, 0);
1649 reg_01
.raw
= io_apic_read(apic
, 1);
1650 if (reg_01
.bits
.version
>= 0x10)
1651 reg_02
.raw
= io_apic_read(apic
, 2);
1652 if (reg_01
.bits
.version
>= 0x20)
1653 reg_03
.raw
= io_apic_read(apic
, 3);
1654 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1657 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1658 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1659 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1660 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1661 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1663 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1664 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1666 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1667 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1670 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1671 * but the value of reg_02 is read as the previous read register
1672 * value, so ignore it if reg_02 == reg_01.
1674 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1675 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1676 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1680 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1681 * or reg_03, but the value of reg_0[23] is read as the previous read
1682 * register value, so ignore it if reg_03 == reg_0[12].
1684 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1685 reg_03
.raw
!= reg_01
.raw
) {
1686 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1687 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1690 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1692 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1693 " Stat Dmod Deli Vect:\n");
1695 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1696 struct IO_APIC_route_entry entry
;
1698 entry
= ioapic_read_entry(apic
, i
);
1700 printk(KERN_DEBUG
" %02x %03X ",
1705 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1710 entry
.delivery_status
,
1712 entry
.delivery_mode
,
1717 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1718 for_each_irq_desc(irq
, desc
) {
1719 struct irq_pin_list
*entry
;
1721 cfg
= desc
->chip_data
;
1724 entry
= cfg
->irq_2_pin
;
1727 printk(KERN_DEBUG
"IRQ%d ", irq
);
1728 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
1729 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1733 printk(KERN_INFO
".................................... done.\n");
1738 __apicdebuginit(void) print_APIC_field(int base
)
1744 for (i
= 0; i
< 8; i
++)
1745 printk(KERN_CONT
"%08x", apic_read(base
+ i
*0x10));
1747 printk(KERN_CONT
"\n");
1750 __apicdebuginit(void) print_local_APIC(void *dummy
)
1752 unsigned int i
, v
, ver
, maxlvt
;
1755 printk(KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1756 smp_processor_id(), hard_smp_processor_id());
1757 v
= apic_read(APIC_ID
);
1758 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1759 v
= apic_read(APIC_LVR
);
1760 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1761 ver
= GET_APIC_VERSION(v
);
1762 maxlvt
= lapic_get_maxlvt();
1764 v
= apic_read(APIC_TASKPRI
);
1765 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1767 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1768 if (!APIC_XAPIC(ver
)) {
1769 v
= apic_read(APIC_ARBPRI
);
1770 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1771 v
& APIC_ARBPRI_MASK
);
1773 v
= apic_read(APIC_PROCPRI
);
1774 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1778 * Remote read supported only in the 82489DX and local APIC for
1779 * Pentium processors.
1781 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1782 v
= apic_read(APIC_RRR
);
1783 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1786 v
= apic_read(APIC_LDR
);
1787 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1788 if (!x2apic_enabled()) {
1789 v
= apic_read(APIC_DFR
);
1790 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1792 v
= apic_read(APIC_SPIV
);
1793 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1795 printk(KERN_DEBUG
"... APIC ISR field:\n");
1796 print_APIC_field(APIC_ISR
);
1797 printk(KERN_DEBUG
"... APIC TMR field:\n");
1798 print_APIC_field(APIC_TMR
);
1799 printk(KERN_DEBUG
"... APIC IRR field:\n");
1800 print_APIC_field(APIC_IRR
);
1802 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1803 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1804 apic_write(APIC_ESR
, 0);
1806 v
= apic_read(APIC_ESR
);
1807 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1810 icr
= apic_icr_read();
1811 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1812 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1814 v
= apic_read(APIC_LVTT
);
1815 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1817 if (maxlvt
> 3) { /* PC is LVT#4. */
1818 v
= apic_read(APIC_LVTPC
);
1819 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1821 v
= apic_read(APIC_LVT0
);
1822 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1823 v
= apic_read(APIC_LVT1
);
1824 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1826 if (maxlvt
> 2) { /* ERR is LVT#3. */
1827 v
= apic_read(APIC_LVTERR
);
1828 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1831 v
= apic_read(APIC_TMICT
);
1832 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1833 v
= apic_read(APIC_TMCCT
);
1834 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1835 v
= apic_read(APIC_TDCR
);
1836 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1838 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1839 v
= apic_read(APIC_EFEAT
);
1840 maxlvt
= (v
>> 16) & 0xff;
1841 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1842 v
= apic_read(APIC_ECTRL
);
1843 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1844 for (i
= 0; i
< maxlvt
; i
++) {
1845 v
= apic_read(APIC_EILVTn(i
));
1846 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1852 __apicdebuginit(void) print_local_APICs(int maxcpu
)
1860 for_each_online_cpu(cpu
) {
1863 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1868 __apicdebuginit(void) print_PIC(void)
1871 unsigned long flags
;
1873 if (!legacy_pic
->nr_legacy_irqs
)
1876 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1878 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
1880 v
= inb(0xa1) << 8 | inb(0x21);
1881 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1883 v
= inb(0xa0) << 8 | inb(0x20);
1884 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1888 v
= inb(0xa0) << 8 | inb(0x20);
1892 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
1894 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1896 v
= inb(0x4d1) << 8 | inb(0x4d0);
1897 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1900 static int __initdata show_lapic
= 1;
1901 static __init
int setup_show_lapic(char *arg
)
1905 if (strcmp(arg
, "all") == 0) {
1906 show_lapic
= CONFIG_NR_CPUS
;
1908 get_option(&arg
, &num
);
1915 __setup("show_lapic=", setup_show_lapic
);
1917 __apicdebuginit(int) print_ICs(void)
1919 if (apic_verbosity
== APIC_QUIET
)
1924 /* don't print out if apic is not there */
1925 if (!cpu_has_apic
&& !apic_from_smp_config())
1928 print_local_APICs(show_lapic
);
1934 fs_initcall(print_ICs
);
1937 /* Where if anywhere is the i8259 connect in external int mode */
1938 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1940 void __init
enable_IO_APIC(void)
1942 int i8259_apic
, i8259_pin
;
1945 if (!legacy_pic
->nr_legacy_irqs
)
1948 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1950 /* See if any of the pins is in ExtINT mode */
1951 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1952 struct IO_APIC_route_entry entry
;
1953 entry
= ioapic_read_entry(apic
, pin
);
1955 /* If the interrupt line is enabled and in ExtInt mode
1956 * I have found the pin where the i8259 is connected.
1958 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1959 ioapic_i8259
.apic
= apic
;
1960 ioapic_i8259
.pin
= pin
;
1966 /* Look to see what if the MP table has reported the ExtINT */
1967 /* If we could not find the appropriate pin by looking at the ioapic
1968 * the i8259 probably is not connected the ioapic but give the
1969 * mptable a chance anyway.
1971 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1972 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1973 /* Trust the MP table if nothing is setup in the hardware */
1974 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1975 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1976 ioapic_i8259
.pin
= i8259_pin
;
1977 ioapic_i8259
.apic
= i8259_apic
;
1979 /* Complain if the MP table and the hardware disagree */
1980 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1981 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1983 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1987 * Do not trust the IO-APIC being empty at bootup
1993 * Not an __init, needed by the reboot code
1995 void disable_IO_APIC(void)
1998 * Clear the IO-APIC before rebooting:
2002 if (!legacy_pic
->nr_legacy_irqs
)
2006 * If the i8259 is routed through an IOAPIC
2007 * Put that IOAPIC in virtual wire mode
2008 * so legacy interrupts can be delivered.
2010 * With interrupt-remapping, for now we will use virtual wire A mode,
2011 * as virtual wire B is little complex (need to configure both
2012 * IOAPIC RTE aswell as interrupt-remapping table entry).
2013 * As this gets called during crash dump, keep this simple for now.
2015 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
2016 struct IO_APIC_route_entry entry
;
2018 memset(&entry
, 0, sizeof(entry
));
2019 entry
.mask
= 0; /* Enabled */
2020 entry
.trigger
= 0; /* Edge */
2022 entry
.polarity
= 0; /* High */
2023 entry
.delivery_status
= 0;
2024 entry
.dest_mode
= 0; /* Physical */
2025 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
2027 entry
.dest
= read_apic_id();
2030 * Add it to the IO-APIC irq-routing table:
2032 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
2036 * Use virtual wire A mode when interrupt remapping is enabled.
2038 if (cpu_has_apic
|| apic_from_smp_config())
2039 disconnect_bsp_APIC(!intr_remapping_enabled
&&
2040 ioapic_i8259
.pin
!= -1);
2043 #ifdef CONFIG_X86_32
2045 * function to set the IO-APIC physical IDs based on the
2046 * values stored in the MPC table.
2048 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2051 void __init
setup_ioapic_ids_from_mpc(void)
2053 union IO_APIC_reg_00 reg_00
;
2054 physid_mask_t phys_id_present_map
;
2057 unsigned char old_id
;
2058 unsigned long flags
;
2063 * Don't check I/O APIC IDs for xAPIC systems. They have
2064 * no meaning without the serial APIC bus.
2066 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2067 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2070 * This is broken; anything with a real cpu count has to
2071 * circumvent this idiocy regardless.
2073 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &phys_id_present_map
);
2076 * Set the IOAPIC ID to the value stored in the MPC table.
2078 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
2080 /* Read the register 0 value */
2081 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2082 reg_00
.raw
= io_apic_read(apic_id
, 0);
2083 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2085 old_id
= mp_ioapics
[apic_id
].apicid
;
2087 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
2088 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2089 apic_id
, mp_ioapics
[apic_id
].apicid
);
2090 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2092 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
2096 * Sanity check, is the ID really free? Every APIC in a
2097 * system must have a unique ID or we get lots of nice
2098 * 'stuck on smp_invalidate_needed IPI wait' messages.
2100 if (apic
->check_apicid_used(&phys_id_present_map
,
2101 mp_ioapics
[apic_id
].apicid
)) {
2102 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2103 apic_id
, mp_ioapics
[apic_id
].apicid
);
2104 for (i
= 0; i
< get_physical_broadcast(); i
++)
2105 if (!physid_isset(i
, phys_id_present_map
))
2107 if (i
>= get_physical_broadcast())
2108 panic("Max APIC ID exceeded!\n");
2109 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2111 physid_set(i
, phys_id_present_map
);
2112 mp_ioapics
[apic_id
].apicid
= i
;
2115 apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
, &tmp
);
2116 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2117 "phys_id_present_map\n",
2118 mp_ioapics
[apic_id
].apicid
);
2119 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2124 * We need to adjust the IRQ routing table
2125 * if the ID changed.
2127 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
2128 for (i
= 0; i
< mp_irq_entries
; i
++)
2129 if (mp_irqs
[i
].dstapic
== old_id
)
2131 = mp_ioapics
[apic_id
].apicid
;
2134 * Read the right value from the MPC table and
2135 * write it into the ID register.
2137 apic_printk(APIC_VERBOSE
, KERN_INFO
2138 "...changing IO-APIC physical APIC ID to %d ...",
2139 mp_ioapics
[apic_id
].apicid
);
2141 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2142 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2143 io_apic_write(apic_id
, 0, reg_00
.raw
);
2144 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2149 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2150 reg_00
.raw
= io_apic_read(apic_id
, 0);
2151 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2152 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2153 printk("could not set ID!\n");
2155 apic_printk(APIC_VERBOSE
, " ok.\n");
2160 int no_timer_check __initdata
;
2162 static int __init
notimercheck(char *s
)
2167 __setup("no_timer_check", notimercheck
);
2170 * There is a nasty bug in some older SMP boards, their mptable lies
2171 * about the timer IRQ. We do the following to work around the situation:
2173 * - timer IRQ defaults to IO-APIC IRQ
2174 * - if this function detects that timer IRQs are defunct, then we fall
2175 * back to ISA timer IRQs
2177 static int __init
timer_irq_works(void)
2179 unsigned long t1
= jiffies
;
2180 unsigned long flags
;
2185 local_save_flags(flags
);
2187 /* Let ten ticks pass... */
2188 mdelay((10 * 1000) / HZ
);
2189 local_irq_restore(flags
);
2192 * Expect a few ticks at least, to be sure some possible
2193 * glue logic does not lock up after one or two first
2194 * ticks in a non-ExtINT mode. Also the local APIC
2195 * might have cached one ExtINT interrupt. Finally, at
2196 * least one tick may be lost due to delays.
2200 if (time_after(jiffies
, t1
+ 4))
2206 * In the SMP+IOAPIC case it might happen that there are an unspecified
2207 * number of pending IRQ events unhandled. These cases are very rare,
2208 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2209 * better to do it this way as thus we do not have to be aware of
2210 * 'pending' interrupts in the IRQ path, except at this point.
2213 * Edge triggered needs to resend any interrupt
2214 * that was delayed but this is now handled in the device
2219 * Starting up a edge-triggered IO-APIC interrupt is
2220 * nasty - we need to make sure that we get the edge.
2221 * If it is already asserted for some reason, we need
2222 * return 1 to indicate that is was pending.
2224 * This is not complete - we should be able to fake
2225 * an edge even if it isn't on the 8259A...
2228 static unsigned int startup_ioapic_irq(unsigned int irq
)
2230 int was_pending
= 0;
2231 unsigned long flags
;
2232 struct irq_cfg
*cfg
;
2234 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2235 if (irq
< legacy_pic
->nr_legacy_irqs
) {
2236 legacy_pic
->chip
->mask(irq
);
2237 if (legacy_pic
->irq_pending(irq
))
2241 __unmask_IO_APIC_irq(cfg
);
2242 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2247 static int ioapic_retrigger_irq(unsigned int irq
)
2250 struct irq_cfg
*cfg
= irq_cfg(irq
);
2251 unsigned long flags
;
2253 raw_spin_lock_irqsave(&vector_lock
, flags
);
2254 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2255 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2261 * Level and edge triggered IO-APIC interrupts need different handling,
2262 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2263 * handled with the level-triggered descriptor, but that one has slightly
2264 * more overhead. Level-triggered interrupts cannot be handled with the
2265 * edge-triggered handler, without risking IRQ storms and other ugly
2270 void send_cleanup_vector(struct irq_cfg
*cfg
)
2272 cpumask_var_t cleanup_mask
;
2274 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2276 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2277 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2279 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2280 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2281 free_cpumask_var(cleanup_mask
);
2283 cfg
->move_in_progress
= 0;
2286 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2289 struct irq_pin_list
*entry
;
2290 u8 vector
= cfg
->vector
;
2292 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2298 * With interrupt-remapping, destination information comes
2299 * from interrupt-remapping table entry.
2301 if (!irq_remapped(irq
))
2302 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2303 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2304 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2306 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2311 * Either sets desc->affinity to a valid value, and returns
2312 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2313 * leaves desc->affinity untouched.
2316 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
,
2317 unsigned int *dest_id
)
2319 struct irq_cfg
*cfg
;
2322 if (!cpumask_intersects(mask
, cpu_online_mask
))
2326 cfg
= desc
->chip_data
;
2327 if (assign_irq_vector(irq
, cfg
, mask
))
2330 cpumask_copy(desc
->affinity
, mask
);
2332 *dest_id
= apic
->cpu_mask_to_apicid_and(desc
->affinity
, cfg
->domain
);
2337 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2339 struct irq_cfg
*cfg
;
2340 unsigned long flags
;
2346 cfg
= desc
->chip_data
;
2348 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2349 ret
= set_desc_affinity(desc
, mask
, &dest
);
2351 /* Only the high 8 bits are valid. */
2352 dest
= SET_APIC_LOGICAL_ID(dest
);
2353 __target_IO_APIC_irq(irq
, dest
, cfg
);
2355 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2361 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
2363 struct irq_desc
*desc
;
2365 desc
= irq_to_desc(irq
);
2367 return set_ioapic_affinity_irq_desc(desc
, mask
);
2370 #ifdef CONFIG_INTR_REMAP
2373 * Migrate the IO-APIC irq in the presence of intr-remapping.
2375 * For both level and edge triggered, irq migration is a simple atomic
2376 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2378 * For level triggered, we eliminate the io-apic RTE modification (with the
2379 * updated vector information), by using a virtual vector (io-apic pin number).
2380 * Real vector that is used for interrupting cpu will be coming from
2381 * the interrupt-remapping table entry.
2384 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2386 struct irq_cfg
*cfg
;
2392 if (!cpumask_intersects(mask
, cpu_online_mask
))
2396 if (get_irte(irq
, &irte
))
2399 cfg
= desc
->chip_data
;
2400 if (assign_irq_vector(irq
, cfg
, mask
))
2403 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2405 irte
.vector
= cfg
->vector
;
2406 irte
.dest_id
= IRTE_DEST(dest
);
2409 * Modified the IRTE and flushes the Interrupt entry cache.
2411 modify_irte(irq
, &irte
);
2413 if (cfg
->move_in_progress
)
2414 send_cleanup_vector(cfg
);
2416 cpumask_copy(desc
->affinity
, mask
);
2422 * Migrates the IRQ destination in the process context.
2424 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2425 const struct cpumask
*mask
)
2427 return migrate_ioapic_irq_desc(desc
, mask
);
2429 static int set_ir_ioapic_affinity_irq(unsigned int irq
,
2430 const struct cpumask
*mask
)
2432 struct irq_desc
*desc
= irq_to_desc(irq
);
2434 return set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2437 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2438 const struct cpumask
*mask
)
2444 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2446 unsigned vector
, me
;
2452 me
= smp_processor_id();
2453 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2456 struct irq_desc
*desc
;
2457 struct irq_cfg
*cfg
;
2458 irq
= __get_cpu_var(vector_irq
)[vector
];
2463 desc
= irq_to_desc(irq
);
2468 raw_spin_lock(&desc
->lock
);
2471 * Check if the irq migration is in progress. If so, we
2472 * haven't received the cleanup request yet for this irq.
2474 if (cfg
->move_in_progress
)
2477 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2480 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2482 * Check if the vector that needs to be cleanedup is
2483 * registered at the cpu's IRR. If so, then this is not
2484 * the best time to clean it up. Lets clean it up in the
2485 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2488 if (irr
& (1 << (vector
% 32))) {
2489 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2492 __get_cpu_var(vector_irq
)[vector
] = -1;
2494 raw_spin_unlock(&desc
->lock
);
2500 static void __irq_complete_move(struct irq_desc
**descp
, unsigned vector
)
2502 struct irq_desc
*desc
= *descp
;
2503 struct irq_cfg
*cfg
= desc
->chip_data
;
2506 if (likely(!cfg
->move_in_progress
))
2509 me
= smp_processor_id();
2511 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2512 send_cleanup_vector(cfg
);
2515 static void irq_complete_move(struct irq_desc
**descp
)
2517 __irq_complete_move(descp
, ~get_irq_regs()->orig_ax
);
2520 void irq_force_complete_move(int irq
)
2522 struct irq_desc
*desc
= irq_to_desc(irq
);
2523 struct irq_cfg
*cfg
= desc
->chip_data
;
2528 __irq_complete_move(&desc
, cfg
->vector
);
2531 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2534 static void ack_apic_edge(unsigned int irq
)
2536 struct irq_desc
*desc
= irq_to_desc(irq
);
2538 irq_complete_move(&desc
);
2539 move_native_irq(irq
);
2543 atomic_t irq_mis_count
;
2546 * IO-APIC versions below 0x20 don't support EOI register.
2547 * For the record, here is the information about various versions:
2549 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2550 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2553 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2554 * version as 0x2. This is an error with documentation and these ICH chips
2555 * use io-apic's of version 0x20.
2557 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2558 * Otherwise, we simulate the EOI message manually by changing the trigger
2559 * mode to edge and then back to level, with RTE being masked during this.
2561 static void __eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2563 struct irq_pin_list
*entry
;
2565 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2566 if (mp_ioapics
[entry
->apic
].apicver
>= 0x20) {
2568 * Intr-remapping uses pin number as the virtual vector
2569 * in the RTE. Actual vector is programmed in
2570 * intr-remapping table entry. Hence for the io-apic
2571 * EOI we use the pin number.
2573 if (irq_remapped(irq
))
2574 io_apic_eoi(entry
->apic
, entry
->pin
);
2576 io_apic_eoi(entry
->apic
, cfg
->vector
);
2578 __mask_and_edge_IO_APIC_irq(entry
);
2579 __unmask_and_level_IO_APIC_irq(entry
);
2584 static void eoi_ioapic_irq(struct irq_desc
*desc
)
2586 struct irq_cfg
*cfg
;
2587 unsigned long flags
;
2591 cfg
= desc
->chip_data
;
2593 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2594 __eoi_ioapic_irq(irq
, cfg
);
2595 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2598 static void ack_apic_level(unsigned int irq
)
2600 struct irq_desc
*desc
= irq_to_desc(irq
);
2603 struct irq_cfg
*cfg
;
2604 int do_unmask_irq
= 0;
2606 irq_complete_move(&desc
);
2607 #ifdef CONFIG_GENERIC_PENDING_IRQ
2608 /* If we are moving the irq we need to mask it */
2609 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2611 mask_IO_APIC_irq_desc(desc
);
2616 * It appears there is an erratum which affects at least version 0x11
2617 * of I/O APIC (that's the 82093AA and cores integrated into various
2618 * chipsets). Under certain conditions a level-triggered interrupt is
2619 * erroneously delivered as edge-triggered one but the respective IRR
2620 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2621 * message but it will never arrive and further interrupts are blocked
2622 * from the source. The exact reason is so far unknown, but the
2623 * phenomenon was observed when two consecutive interrupt requests
2624 * from a given source get delivered to the same CPU and the source is
2625 * temporarily disabled in between.
2627 * A workaround is to simulate an EOI message manually. We achieve it
2628 * by setting the trigger mode to edge and then to level when the edge
2629 * trigger mode gets detected in the TMR of a local APIC for a
2630 * level-triggered interrupt. We mask the source for the time of the
2631 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2632 * The idea is from Manfred Spraul. --macro
2634 * Also in the case when cpu goes offline, fixup_irqs() will forward
2635 * any unhandled interrupt on the offlined cpu to the new cpu
2636 * destination that is handling the corresponding interrupt. This
2637 * interrupt forwarding is done via IPI's. Hence, in this case also
2638 * level-triggered io-apic interrupt will be seen as an edge
2639 * interrupt in the IRR. And we can't rely on the cpu's EOI
2640 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2641 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2642 * supporting EOI register, we do an explicit EOI to clear the
2643 * remote IRR and on IO-APIC's which don't have an EOI register,
2644 * we use the above logic (mask+edge followed by unmask+level) from
2645 * Manfred Spraul to clear the remote IRR.
2647 cfg
= desc
->chip_data
;
2649 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2652 * We must acknowledge the irq before we move it or the acknowledge will
2653 * not propagate properly.
2658 * Tail end of clearing remote IRR bit (either by delivering the EOI
2659 * message via io-apic EOI register write or simulating it using
2660 * mask+edge followed by unnask+level logic) manually when the
2661 * level triggered interrupt is seen as the edge triggered interrupt
2664 if (!(v
& (1 << (i
& 0x1f)))) {
2665 atomic_inc(&irq_mis_count
);
2667 eoi_ioapic_irq(desc
);
2670 /* Now we can move and renable the irq */
2671 if (unlikely(do_unmask_irq
)) {
2672 /* Only migrate the irq if the ack has been received.
2674 * On rare occasions the broadcast level triggered ack gets
2675 * delayed going to ioapics, and if we reprogram the
2676 * vector while Remote IRR is still set the irq will never
2679 * To prevent this scenario we read the Remote IRR bit
2680 * of the ioapic. This has two effects.
2681 * - On any sane system the read of the ioapic will
2682 * flush writes (and acks) going to the ioapic from
2684 * - We get to see if the ACK has actually been delivered.
2686 * Based on failed experiments of reprogramming the
2687 * ioapic entry from outside of irq context starting
2688 * with masking the ioapic entry and then polling until
2689 * Remote IRR was clear before reprogramming the
2690 * ioapic I don't trust the Remote IRR bit to be
2691 * completey accurate.
2693 * However there appears to be no other way to plug
2694 * this race, so if the Remote IRR bit is not
2695 * accurate and is causing problems then it is a hardware bug
2696 * and you can go talk to the chipset vendor about it.
2698 cfg
= desc
->chip_data
;
2699 if (!io_apic_level_ack_pending(cfg
))
2700 move_masked_irq(irq
);
2701 unmask_IO_APIC_irq_desc(desc
);
2705 #ifdef CONFIG_INTR_REMAP
2706 static void ir_ack_apic_edge(unsigned int irq
)
2711 static void ir_ack_apic_level(unsigned int irq
)
2713 struct irq_desc
*desc
= irq_to_desc(irq
);
2716 eoi_ioapic_irq(desc
);
2718 #endif /* CONFIG_INTR_REMAP */
2720 static struct irq_chip ioapic_chip __read_mostly
= {
2722 .startup
= startup_ioapic_irq
,
2723 .mask
= mask_IO_APIC_irq
,
2724 .unmask
= unmask_IO_APIC_irq
,
2725 .ack
= ack_apic_edge
,
2726 .eoi
= ack_apic_level
,
2728 .set_affinity
= set_ioapic_affinity_irq
,
2730 .retrigger
= ioapic_retrigger_irq
,
2733 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2734 .name
= "IR-IO-APIC",
2735 .startup
= startup_ioapic_irq
,
2736 .mask
= mask_IO_APIC_irq
,
2737 .unmask
= unmask_IO_APIC_irq
,
2738 #ifdef CONFIG_INTR_REMAP
2739 .ack
= ir_ack_apic_edge
,
2740 .eoi
= ir_ack_apic_level
,
2742 .set_affinity
= set_ir_ioapic_affinity_irq
,
2745 .retrigger
= ioapic_retrigger_irq
,
2748 static inline void init_IO_APIC_traps(void)
2751 struct irq_desc
*desc
;
2752 struct irq_cfg
*cfg
;
2755 * NOTE! The local APIC isn't very good at handling
2756 * multiple interrupts at the same interrupt level.
2757 * As the interrupt level is determined by taking the
2758 * vector number and shifting that right by 4, we
2759 * want to spread these out a bit so that they don't
2760 * all fall in the same interrupt level.
2762 * Also, we've got to be careful not to trash gate
2763 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2765 for_each_irq_desc(irq
, desc
) {
2766 cfg
= desc
->chip_data
;
2767 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2769 * Hmm.. We don't have an entry for this,
2770 * so default to an old-fashioned 8259
2771 * interrupt if we can..
2773 if (irq
< legacy_pic
->nr_legacy_irqs
)
2774 legacy_pic
->make_irq(irq
);
2776 /* Strange. Oh, well.. */
2777 desc
->chip
= &no_irq_chip
;
2783 * The local APIC irq-chip implementation:
2786 static void mask_lapic_irq(unsigned int irq
)
2790 v
= apic_read(APIC_LVT0
);
2791 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2794 static void unmask_lapic_irq(unsigned int irq
)
2798 v
= apic_read(APIC_LVT0
);
2799 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2802 static void ack_lapic_irq(unsigned int irq
)
2807 static struct irq_chip lapic_chip __read_mostly
= {
2808 .name
= "local-APIC",
2809 .mask
= mask_lapic_irq
,
2810 .unmask
= unmask_lapic_irq
,
2811 .ack
= ack_lapic_irq
,
2814 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2816 desc
->status
&= ~IRQ_LEVEL
;
2817 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2821 static void __init
setup_nmi(void)
2824 * Dirty trick to enable the NMI watchdog ...
2825 * We put the 8259A master into AEOI mode and
2826 * unmask on all local APICs LVT0 as NMI.
2828 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2829 * is from Maciej W. Rozycki - so we do not have to EOI from
2830 * the NMI handler or the timer interrupt.
2832 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2834 enable_NMI_through_LVT0();
2836 apic_printk(APIC_VERBOSE
, " done.\n");
2840 * This looks a bit hackish but it's about the only one way of sending
2841 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2842 * not support the ExtINT mode, unfortunately. We need to send these
2843 * cycles as some i82489DX-based boards have glue logic that keeps the
2844 * 8259A interrupt line asserted until INTA. --macro
2846 static inline void __init
unlock_ExtINT_logic(void)
2849 struct IO_APIC_route_entry entry0
, entry1
;
2850 unsigned char save_control
, save_freq_select
;
2852 pin
= find_isa_irq_pin(8, mp_INT
);
2857 apic
= find_isa_irq_apic(8, mp_INT
);
2863 entry0
= ioapic_read_entry(apic
, pin
);
2864 clear_IO_APIC_pin(apic
, pin
);
2866 memset(&entry1
, 0, sizeof(entry1
));
2868 entry1
.dest_mode
= 0; /* physical delivery */
2869 entry1
.mask
= 0; /* unmask IRQ now */
2870 entry1
.dest
= hard_smp_processor_id();
2871 entry1
.delivery_mode
= dest_ExtINT
;
2872 entry1
.polarity
= entry0
.polarity
;
2876 ioapic_write_entry(apic
, pin
, entry1
);
2878 save_control
= CMOS_READ(RTC_CONTROL
);
2879 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2880 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2882 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2887 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2891 CMOS_WRITE(save_control
, RTC_CONTROL
);
2892 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2893 clear_IO_APIC_pin(apic
, pin
);
2895 ioapic_write_entry(apic
, pin
, entry0
);
2898 static int disable_timer_pin_1 __initdata
;
2899 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2900 static int __init
disable_timer_pin_setup(char *arg
)
2902 disable_timer_pin_1
= 1;
2905 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2907 int timer_through_8259 __initdata
;
2910 * This code may look a bit paranoid, but it's supposed to cooperate with
2911 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2912 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2913 * fanatically on his truly buggy board.
2915 * FIXME: really need to revamp this for all platforms.
2917 static inline void __init
check_timer(void)
2919 struct irq_desc
*desc
= irq_to_desc(0);
2920 struct irq_cfg
*cfg
= desc
->chip_data
;
2921 int node
= cpu_to_node(0);
2922 int apic1
, pin1
, apic2
, pin2
;
2923 unsigned long flags
;
2926 local_irq_save(flags
);
2929 * get/set the timer IRQ vector:
2931 legacy_pic
->chip
->mask(0);
2932 assign_irq_vector(0, cfg
, apic
->target_cpus());
2935 * As IRQ0 is to be enabled in the 8259A, the virtual
2936 * wire has to be disabled in the local APIC. Also
2937 * timer interrupts need to be acknowledged manually in
2938 * the 8259A for the i82489DX when using the NMI
2939 * watchdog as that APIC treats NMIs as level-triggered.
2940 * The AEOI mode will finish them in the 8259A
2943 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2944 legacy_pic
->init(1);
2945 #ifdef CONFIG_X86_32
2949 ver
= apic_read(APIC_LVR
);
2950 ver
= GET_APIC_VERSION(ver
);
2951 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2955 pin1
= find_isa_irq_pin(0, mp_INT
);
2956 apic1
= find_isa_irq_apic(0, mp_INT
);
2957 pin2
= ioapic_i8259
.pin
;
2958 apic2
= ioapic_i8259
.apic
;
2960 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2961 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2962 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2965 * Some BIOS writers are clueless and report the ExtINTA
2966 * I/O APIC input from the cascaded 8259A as the timer
2967 * interrupt input. So just in case, if only one pin
2968 * was found above, try it both directly and through the
2972 if (intr_remapping_enabled
)
2973 panic("BIOS bug: timer not connected to IO-APIC");
2977 } else if (pin2
== -1) {
2984 * Ok, does IRQ0 through the IOAPIC work?
2987 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2988 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2990 /* for edge trigger, setup_IO_APIC_irq already
2991 * leave it unmasked.
2992 * so only need to unmask if it is level-trigger
2993 * do we really have level trigger timer?
2996 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2997 if (idx
!= -1 && irq_trigger(idx
))
2998 unmask_IO_APIC_irq_desc(desc
);
3000 if (timer_irq_works()) {
3001 if (nmi_watchdog
== NMI_IO_APIC
) {
3003 legacy_pic
->chip
->unmask(0);
3005 if (disable_timer_pin_1
> 0)
3006 clear_IO_APIC_pin(0, pin1
);
3009 if (intr_remapping_enabled
)
3010 panic("timer doesn't work through Interrupt-remapped IO-APIC");
3011 local_irq_disable();
3012 clear_IO_APIC_pin(apic1
, pin1
);
3014 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
3015 "8254 timer not connected to IO-APIC\n");
3017 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
3018 "(IRQ0) through the 8259A ...\n");
3019 apic_printk(APIC_QUIET
, KERN_INFO
3020 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
3022 * legacy devices should be connected to IO APIC #0
3024 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
3025 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
3026 legacy_pic
->chip
->unmask(0);
3027 if (timer_irq_works()) {
3028 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
3029 timer_through_8259
= 1;
3030 if (nmi_watchdog
== NMI_IO_APIC
) {
3031 legacy_pic
->chip
->mask(0);
3033 legacy_pic
->chip
->unmask(0);
3038 * Cleanup, just in case ...
3040 local_irq_disable();
3041 legacy_pic
->chip
->mask(0);
3042 clear_IO_APIC_pin(apic2
, pin2
);
3043 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
3046 if (nmi_watchdog
== NMI_IO_APIC
) {
3047 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
3048 "through the IO-APIC - disabling NMI Watchdog!\n");
3049 nmi_watchdog
= NMI_NONE
;
3051 #ifdef CONFIG_X86_32
3055 apic_printk(APIC_QUIET
, KERN_INFO
3056 "...trying to set up timer as Virtual Wire IRQ...\n");
3058 lapic_register_intr(0, desc
);
3059 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
3060 legacy_pic
->chip
->unmask(0);
3062 if (timer_irq_works()) {
3063 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3066 local_irq_disable();
3067 legacy_pic
->chip
->mask(0);
3068 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
3069 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
3071 apic_printk(APIC_QUIET
, KERN_INFO
3072 "...trying to set up timer as ExtINT IRQ...\n");
3074 legacy_pic
->init(0);
3075 legacy_pic
->make_irq(0);
3076 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3078 unlock_ExtINT_logic();
3080 if (timer_irq_works()) {
3081 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3084 local_irq_disable();
3085 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3086 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3087 "report. Then try booting with the 'noapic' option.\n");
3089 local_irq_restore(flags
);
3093 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3094 * to devices. However there may be an I/O APIC pin available for
3095 * this interrupt regardless. The pin may be left unconnected, but
3096 * typically it will be reused as an ExtINT cascade interrupt for
3097 * the master 8259A. In the MPS case such a pin will normally be
3098 * reported as an ExtINT interrupt in the MP table. With ACPI
3099 * there is no provision for ExtINT interrupts, and in the absence
3100 * of an override it would be treated as an ordinary ISA I/O APIC
3101 * interrupt, that is edge-triggered and unmasked by default. We
3102 * used to do this, but it caused problems on some systems because
3103 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3104 * the same ExtINT cascade interrupt to drive the local APIC of the
3105 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3106 * the I/O APIC in all cases now. No actual device should request
3107 * it anyway. --macro
3109 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3111 void __init
setup_IO_APIC(void)
3115 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3117 io_apic_irqs
= legacy_pic
->nr_legacy_irqs
? ~PIC_IRQS
: ~0UL;
3119 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3121 * Set up IO-APIC IRQ routing.
3123 x86_init
.mpparse
.setup_ioapic_ids();
3126 setup_IO_APIC_irqs();
3127 init_IO_APIC_traps();
3128 if (legacy_pic
->nr_legacy_irqs
)
3133 * Called after all the initialization is done. If we didnt find any
3134 * APIC bugs then we can allow the modify fast path
3137 static int __init
io_apic_bug_finalize(void)
3139 if (sis_apic_bug
== -1)
3144 late_initcall(io_apic_bug_finalize
);
3146 struct sysfs_ioapic_data
{
3147 struct sys_device dev
;
3148 struct IO_APIC_route_entry entry
[0];
3150 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3152 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3154 struct IO_APIC_route_entry
*entry
;
3155 struct sysfs_ioapic_data
*data
;
3158 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3159 entry
= data
->entry
;
3160 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3161 *entry
= ioapic_read_entry(dev
->id
, i
);
3166 static int ioapic_resume(struct sys_device
*dev
)
3168 struct IO_APIC_route_entry
*entry
;
3169 struct sysfs_ioapic_data
*data
;
3170 unsigned long flags
;
3171 union IO_APIC_reg_00 reg_00
;
3174 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3175 entry
= data
->entry
;
3177 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3178 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3179 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
3180 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
3181 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3183 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3184 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3185 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3190 static struct sysdev_class ioapic_sysdev_class
= {
3192 .suspend
= ioapic_suspend
,
3193 .resume
= ioapic_resume
,
3196 static int __init
ioapic_init_sysfs(void)
3198 struct sys_device
* dev
;
3201 error
= sysdev_class_register(&ioapic_sysdev_class
);
3205 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3206 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3207 * sizeof(struct IO_APIC_route_entry
);
3208 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3209 if (!mp_ioapic_data
[i
]) {
3210 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3213 dev
= &mp_ioapic_data
[i
]->dev
;
3215 dev
->cls
= &ioapic_sysdev_class
;
3216 error
= sysdev_register(dev
);
3218 kfree(mp_ioapic_data
[i
]);
3219 mp_ioapic_data
[i
] = NULL
;
3220 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3228 device_initcall(ioapic_init_sysfs
);
3231 * Dynamic irq allocate and deallocation
3233 unsigned int create_irq_nr(unsigned int irq_want
, int node
)
3235 /* Allocate an unused irq */
3238 unsigned long flags
;
3239 struct irq_cfg
*cfg_new
= NULL
;
3240 struct irq_desc
*desc_new
= NULL
;
3243 if (irq_want
< nr_irqs_gsi
)
3244 irq_want
= nr_irqs_gsi
;
3246 raw_spin_lock_irqsave(&vector_lock
, flags
);
3247 for (new = irq_want
; new < nr_irqs
; new++) {
3248 desc_new
= irq_to_desc_alloc_node(new, node
);
3250 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3253 cfg_new
= desc_new
->chip_data
;
3255 if (cfg_new
->vector
!= 0)
3258 desc_new
= move_irq_desc(desc_new
, node
);
3259 cfg_new
= desc_new
->chip_data
;
3261 if (__assign_irq_vector(new, cfg_new
, apic
->target_cpus()) == 0)
3265 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3268 dynamic_irq_init_keep_chip_data(irq
);
3273 int create_irq(void)
3275 int node
= cpu_to_node(0);
3276 unsigned int irq_want
;
3279 irq_want
= nr_irqs_gsi
;
3280 irq
= create_irq_nr(irq_want
, node
);
3288 void destroy_irq(unsigned int irq
)
3290 unsigned long flags
;
3292 dynamic_irq_cleanup_keep_chip_data(irq
);
3295 raw_spin_lock_irqsave(&vector_lock
, flags
);
3296 __clear_irq_vector(irq
, get_irq_chip_data(irq
));
3297 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3301 * MSI message composition
3303 #ifdef CONFIG_PCI_MSI
3304 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
,
3305 struct msi_msg
*msg
, u8 hpet_id
)
3307 struct irq_cfg
*cfg
;
3315 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3319 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3321 if (irq_remapped(irq
)) {
3326 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3327 BUG_ON(ir_index
== -1);
3329 prepare_irte(&irte
, cfg
->vector
, dest
);
3331 /* Set source-id of interrupt request */
3333 set_msi_sid(&irte
, pdev
);
3335 set_hpet_sid(&irte
, hpet_id
);
3337 modify_irte(irq
, &irte
);
3339 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3340 msg
->data
= sub_handle
;
3341 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3343 MSI_ADDR_IR_INDEX1(ir_index
) |
3344 MSI_ADDR_IR_INDEX2(ir_index
);
3346 if (x2apic_enabled())
3347 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3348 MSI_ADDR_EXT_DEST_ID(dest
);
3350 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3354 ((apic
->irq_dest_mode
== 0) ?
3355 MSI_ADDR_DEST_MODE_PHYSICAL
:
3356 MSI_ADDR_DEST_MODE_LOGICAL
) |
3357 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3358 MSI_ADDR_REDIRECTION_CPU
:
3359 MSI_ADDR_REDIRECTION_LOWPRI
) |
3360 MSI_ADDR_DEST_ID(dest
);
3363 MSI_DATA_TRIGGER_EDGE
|
3364 MSI_DATA_LEVEL_ASSERT
|
3365 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3366 MSI_DATA_DELIVERY_FIXED
:
3367 MSI_DATA_DELIVERY_LOWPRI
) |
3368 MSI_DATA_VECTOR(cfg
->vector
);
3374 static int set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3376 struct irq_desc
*desc
= irq_to_desc(irq
);
3377 struct irq_cfg
*cfg
;
3381 if (set_desc_affinity(desc
, mask
, &dest
))
3384 cfg
= desc
->chip_data
;
3386 get_cached_msi_msg_desc(desc
, &msg
);
3388 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3389 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3390 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3391 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3393 write_msi_msg_desc(desc
, &msg
);
3397 #ifdef CONFIG_INTR_REMAP
3399 * Migrate the MSI irq to another cpumask. This migration is
3400 * done in the process context using interrupt-remapping hardware.
3403 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3405 struct irq_desc
*desc
= irq_to_desc(irq
);
3406 struct irq_cfg
*cfg
= desc
->chip_data
;
3410 if (get_irte(irq
, &irte
))
3413 if (set_desc_affinity(desc
, mask
, &dest
))
3416 irte
.vector
= cfg
->vector
;
3417 irte
.dest_id
= IRTE_DEST(dest
);
3420 * atomically update the IRTE with the new destination and vector.
3422 modify_irte(irq
, &irte
);
3425 * After this point, all the interrupts will start arriving
3426 * at the new destination. So, time to cleanup the previous
3427 * vector allocation.
3429 if (cfg
->move_in_progress
)
3430 send_cleanup_vector(cfg
);
3436 #endif /* CONFIG_SMP */
3439 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3440 * which implement the MSI or MSI-X Capability Structure.
3442 static struct irq_chip msi_chip
= {
3444 .unmask
= unmask_msi_irq
,
3445 .mask
= mask_msi_irq
,
3446 .ack
= ack_apic_edge
,
3448 .set_affinity
= set_msi_irq_affinity
,
3450 .retrigger
= ioapic_retrigger_irq
,
3453 static struct irq_chip msi_ir_chip
= {
3454 .name
= "IR-PCI-MSI",
3455 .unmask
= unmask_msi_irq
,
3456 .mask
= mask_msi_irq
,
3457 #ifdef CONFIG_INTR_REMAP
3458 .ack
= ir_ack_apic_edge
,
3460 .set_affinity
= ir_set_msi_irq_affinity
,
3463 .retrigger
= ioapic_retrigger_irq
,
3467 * Map the PCI dev to the corresponding remapping hardware unit
3468 * and allocate 'nvec' consecutive interrupt-remapping table entries
3471 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3473 struct intel_iommu
*iommu
;
3476 iommu
= map_dev_to_ir(dev
);
3479 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3483 index
= alloc_irte(iommu
, irq
, nvec
);
3486 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3493 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3498 ret
= msi_compose_msg(dev
, irq
, &msg
, -1);
3502 set_irq_msi(irq
, msidesc
);
3503 write_msi_msg(irq
, &msg
);
3505 if (irq_remapped(irq
)) {
3506 struct irq_desc
*desc
= irq_to_desc(irq
);
3508 * irq migration in process context
3510 desc
->status
|= IRQ_MOVE_PCNTXT
;
3511 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3513 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3515 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3520 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3523 int ret
, sub_handle
;
3524 struct msi_desc
*msidesc
;
3525 unsigned int irq_want
;
3526 struct intel_iommu
*iommu
= NULL
;
3530 /* x86 doesn't support multiple MSI yet */
3531 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3534 node
= dev_to_node(&dev
->dev
);
3535 irq_want
= nr_irqs_gsi
;
3537 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3538 irq
= create_irq_nr(irq_want
, node
);
3542 if (!intr_remapping_enabled
)
3547 * allocate the consecutive block of IRTE's
3550 index
= msi_alloc_irte(dev
, irq
, nvec
);
3556 iommu
= map_dev_to_ir(dev
);
3562 * setup the mapping between the irq and the IRTE
3563 * base index, the sub_handle pointing to the
3564 * appropriate interrupt remap table entry.
3566 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3569 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3581 void arch_teardown_msi_irq(unsigned int irq
)
3586 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3588 static int dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3590 struct irq_desc
*desc
= irq_to_desc(irq
);
3591 struct irq_cfg
*cfg
;
3595 if (set_desc_affinity(desc
, mask
, &dest
))
3598 cfg
= desc
->chip_data
;
3600 dmar_msi_read(irq
, &msg
);
3602 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3603 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3604 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3605 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3607 dmar_msi_write(irq
, &msg
);
3612 #endif /* CONFIG_SMP */
3614 static struct irq_chip dmar_msi_type
= {
3616 .unmask
= dmar_msi_unmask
,
3617 .mask
= dmar_msi_mask
,
3618 .ack
= ack_apic_edge
,
3620 .set_affinity
= dmar_msi_set_affinity
,
3622 .retrigger
= ioapic_retrigger_irq
,
3625 int arch_setup_dmar_msi(unsigned int irq
)
3630 ret
= msi_compose_msg(NULL
, irq
, &msg
, -1);
3633 dmar_msi_write(irq
, &msg
);
3634 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3640 #ifdef CONFIG_HPET_TIMER
3643 static int hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3645 struct irq_desc
*desc
= irq_to_desc(irq
);
3646 struct irq_cfg
*cfg
;
3650 if (set_desc_affinity(desc
, mask
, &dest
))
3653 cfg
= desc
->chip_data
;
3655 hpet_msi_read(irq
, &msg
);
3657 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3658 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3659 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3660 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3662 hpet_msi_write(irq
, &msg
);
3667 #endif /* CONFIG_SMP */
3669 static struct irq_chip ir_hpet_msi_type
= {
3670 .name
= "IR-HPET_MSI",
3671 .unmask
= hpet_msi_unmask
,
3672 .mask
= hpet_msi_mask
,
3673 #ifdef CONFIG_INTR_REMAP
3674 .ack
= ir_ack_apic_edge
,
3676 .set_affinity
= ir_set_msi_irq_affinity
,
3679 .retrigger
= ioapic_retrigger_irq
,
3682 static struct irq_chip hpet_msi_type
= {
3684 .unmask
= hpet_msi_unmask
,
3685 .mask
= hpet_msi_mask
,
3686 .ack
= ack_apic_edge
,
3688 .set_affinity
= hpet_msi_set_affinity
,
3690 .retrigger
= ioapic_retrigger_irq
,
3693 int arch_setup_hpet_msi(unsigned int irq
, unsigned int id
)
3697 struct irq_desc
*desc
= irq_to_desc(irq
);
3699 if (intr_remapping_enabled
) {
3700 struct intel_iommu
*iommu
= map_hpet_to_ir(id
);
3706 index
= alloc_irte(iommu
, irq
, 1);
3711 ret
= msi_compose_msg(NULL
, irq
, &msg
, id
);
3715 hpet_msi_write(irq
, &msg
);
3716 desc
->status
|= IRQ_MOVE_PCNTXT
;
3717 if (irq_remapped(irq
))
3718 set_irq_chip_and_handler_name(irq
, &ir_hpet_msi_type
,
3719 handle_edge_irq
, "edge");
3721 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
,
3722 handle_edge_irq
, "edge");
3728 #endif /* CONFIG_PCI_MSI */
3730 * Hypertransport interrupt support
3732 #ifdef CONFIG_HT_IRQ
3736 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3738 struct ht_irq_msg msg
;
3739 fetch_ht_irq_msg(irq
, &msg
);
3741 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3742 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3744 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3745 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3747 write_ht_irq_msg(irq
, &msg
);
3750 static int set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3752 struct irq_desc
*desc
= irq_to_desc(irq
);
3753 struct irq_cfg
*cfg
;
3756 if (set_desc_affinity(desc
, mask
, &dest
))
3759 cfg
= desc
->chip_data
;
3761 target_ht_irq(irq
, dest
, cfg
->vector
);
3768 static struct irq_chip ht_irq_chip
= {
3770 .mask
= mask_ht_irq
,
3771 .unmask
= unmask_ht_irq
,
3772 .ack
= ack_apic_edge
,
3774 .set_affinity
= set_ht_irq_affinity
,
3776 .retrigger
= ioapic_retrigger_irq
,
3779 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3781 struct irq_cfg
*cfg
;
3788 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3790 struct ht_irq_msg msg
;
3793 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3794 apic
->target_cpus());
3796 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3800 HT_IRQ_LOW_DEST_ID(dest
) |
3801 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3802 ((apic
->irq_dest_mode
== 0) ?
3803 HT_IRQ_LOW_DM_PHYSICAL
:
3804 HT_IRQ_LOW_DM_LOGICAL
) |
3805 HT_IRQ_LOW_RQEOI_EDGE
|
3806 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3807 HT_IRQ_LOW_MT_FIXED
:
3808 HT_IRQ_LOW_MT_ARBITRATED
) |
3809 HT_IRQ_LOW_IRQ_MASKED
;
3811 write_ht_irq_msg(irq
, &msg
);
3813 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3814 handle_edge_irq
, "edge");
3816 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3820 #endif /* CONFIG_HT_IRQ */
3822 int __init
io_apic_get_redir_entries (int ioapic
)
3824 union IO_APIC_reg_01 reg_01
;
3825 unsigned long flags
;
3827 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3828 reg_01
.raw
= io_apic_read(ioapic
, 1);
3829 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3831 /* The register returns the maximum index redir index
3832 * supported, which is one less than the total number of redir
3835 return reg_01
.bits
.entries
+ 1;
3838 void __init
probe_nr_irqs_gsi(void)
3842 nr
= gsi_top
+ NR_IRQS_LEGACY
;
3843 if (nr
> nr_irqs_gsi
)
3846 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3849 #ifdef CONFIG_SPARSE_IRQ
3850 int __init
arch_probe_nr_irqs(void)
3854 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3855 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3857 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3858 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3860 * for MSI and HT dyn irq
3862 nr
+= nr_irqs_gsi
* 16;
3871 static int __io_apic_set_pci_routing(struct device
*dev
, int irq
,
3872 struct io_apic_irq_attr
*irq_attr
)
3874 struct irq_desc
*desc
;
3875 struct irq_cfg
*cfg
;
3878 int trigger
, polarity
;
3880 ioapic
= irq_attr
->ioapic
;
3881 if (!IO_APIC_IRQ(irq
)) {
3882 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3888 node
= dev_to_node(dev
);
3890 node
= cpu_to_node(0);
3892 desc
= irq_to_desc_alloc_node(irq
, node
);
3894 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3898 pin
= irq_attr
->ioapic_pin
;
3899 trigger
= irq_attr
->trigger
;
3900 polarity
= irq_attr
->polarity
;
3903 * IRQs < 16 are already in the irq_2_pin[] map
3905 if (irq
>= legacy_pic
->nr_legacy_irqs
) {
3906 cfg
= desc
->chip_data
;
3907 if (add_pin_to_irq_node_nopanic(cfg
, node
, ioapic
, pin
)) {
3908 printk(KERN_INFO
"can not add pin %d for irq %d\n",
3914 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, trigger
, polarity
);
3919 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3920 struct io_apic_irq_attr
*irq_attr
)
3924 * Avoid pin reprogramming. PRTs typically include entries
3925 * with redundant pin->gsi mappings (but unique PCI devices);
3926 * we only program the IOAPIC on the first.
3928 ioapic
= irq_attr
->ioapic
;
3929 pin
= irq_attr
->ioapic_pin
;
3930 if (test_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
)) {
3931 pr_debug("Pin %d-%d already programmed\n",
3932 mp_ioapics
[ioapic
].apicid
, pin
);
3935 set_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
);
3937 return __io_apic_set_pci_routing(dev
, irq
, irq_attr
);
3940 u8 __init
io_apic_unique_id(u8 id
)
3942 #ifdef CONFIG_X86_32
3943 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
3944 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
3945 return io_apic_get_unique_id(nr_ioapics
, id
);
3950 DECLARE_BITMAP(used
, 256);
3952 bitmap_zero(used
, 256);
3953 for (i
= 0; i
< nr_ioapics
; i
++) {
3954 struct mpc_ioapic
*ia
= &mp_ioapics
[i
];
3955 __set_bit(ia
->apicid
, used
);
3957 if (!test_bit(id
, used
))
3959 return find_first_zero_bit(used
, 256);
3963 #ifdef CONFIG_X86_32
3964 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3966 union IO_APIC_reg_00 reg_00
;
3967 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3969 unsigned long flags
;
3973 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3974 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3975 * supports up to 16 on one shared APIC bus.
3977 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3978 * advantage of new APIC bus architecture.
3981 if (physids_empty(apic_id_map
))
3982 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &apic_id_map
);
3984 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3985 reg_00
.raw
= io_apic_read(ioapic
, 0);
3986 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3988 if (apic_id
>= get_physical_broadcast()) {
3989 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3990 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3991 apic_id
= reg_00
.bits
.ID
;
3995 * Every APIC in a system must have a unique ID or we get lots of nice
3996 * 'stuck on smp_invalidate_needed IPI wait' messages.
3998 if (apic
->check_apicid_used(&apic_id_map
, apic_id
)) {
4000 for (i
= 0; i
< get_physical_broadcast(); i
++) {
4001 if (!apic
->check_apicid_used(&apic_id_map
, i
))
4005 if (i
== get_physical_broadcast())
4006 panic("Max apic_id exceeded!\n");
4008 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
4009 "trying %d\n", ioapic
, apic_id
, i
);
4014 apic
->apicid_to_cpu_present(apic_id
, &tmp
);
4015 physids_or(apic_id_map
, apic_id_map
, tmp
);
4017 if (reg_00
.bits
.ID
!= apic_id
) {
4018 reg_00
.bits
.ID
= apic_id
;
4020 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
4021 io_apic_write(ioapic
, 0, reg_00
.raw
);
4022 reg_00
.raw
= io_apic_read(ioapic
, 0);
4023 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
4026 if (reg_00
.bits
.ID
!= apic_id
) {
4027 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
4032 apic_printk(APIC_VERBOSE
, KERN_INFO
4033 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
4039 int __init
io_apic_get_version(int ioapic
)
4041 union IO_APIC_reg_01 reg_01
;
4042 unsigned long flags
;
4044 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
4045 reg_01
.raw
= io_apic_read(ioapic
, 1);
4046 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
4048 return reg_01
.bits
.version
;
4051 int acpi_get_override_irq(u32 gsi
, int *trigger
, int *polarity
)
4053 int ioapic
, pin
, idx
;
4055 if (skip_ioapic_setup
)
4058 ioapic
= mp_find_ioapic(gsi
);
4062 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
4066 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
4070 *trigger
= irq_trigger(idx
);
4071 *polarity
= irq_polarity(idx
);
4076 * This function currently is only a helper for the i386 smp boot process where
4077 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4078 * so mask in all cases should simply be apic->target_cpus()
4081 void __init
setup_ioapic_dest(void)
4083 int pin
, ioapic
, irq
, irq_entry
;
4084 struct irq_desc
*desc
;
4085 const struct cpumask
*mask
;
4087 if (skip_ioapic_setup
== 1)
4090 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++)
4091 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4092 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4093 if (irq_entry
== -1)
4095 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4097 if ((ioapic
> 0) && (irq
> 16))
4100 desc
= irq_to_desc(irq
);
4103 * Honour affinities which have been set in early boot
4106 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4107 mask
= desc
->affinity
;
4109 mask
= apic
->target_cpus();
4111 if (intr_remapping_enabled
)
4112 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4114 set_ioapic_affinity_irq_desc(desc
, mask
);
4120 #define IOAPIC_RESOURCE_NAME_SIZE 11
4122 static struct resource
*ioapic_resources
;
4124 static struct resource
* __init
ioapic_setup_resources(int nr_ioapics
)
4127 struct resource
*res
;
4131 if (nr_ioapics
<= 0)
4134 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4137 mem
= alloc_bootmem(n
);
4140 mem
+= sizeof(struct resource
) * nr_ioapics
;
4142 for (i
= 0; i
< nr_ioapics
; i
++) {
4144 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4145 snprintf(mem
, IOAPIC_RESOURCE_NAME_SIZE
, "IOAPIC %u", i
);
4146 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4149 ioapic_resources
= res
;
4154 void __init
ioapic_init_mappings(void)
4156 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4157 struct resource
*ioapic_res
;
4160 ioapic_res
= ioapic_setup_resources(nr_ioapics
);
4161 for (i
= 0; i
< nr_ioapics
; i
++) {
4162 if (smp_found_config
) {
4163 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
4164 #ifdef CONFIG_X86_32
4167 "WARNING: bogus zero IO-APIC "
4168 "address found in MPTABLE, "
4169 "disabling IO/APIC support!\n");
4170 smp_found_config
= 0;
4171 skip_ioapic_setup
= 1;
4172 goto fake_ioapic_page
;
4176 #ifdef CONFIG_X86_32
4179 ioapic_phys
= (unsigned long)alloc_bootmem_pages(PAGE_SIZE
);
4180 ioapic_phys
= __pa(ioapic_phys
);
4182 set_fixmap_nocache(idx
, ioapic_phys
);
4183 apic_printk(APIC_VERBOSE
, "mapped IOAPIC to %08lx (%08lx)\n",
4184 __fix_to_virt(idx
) + (ioapic_phys
& ~PAGE_MASK
),
4188 ioapic_res
->start
= ioapic_phys
;
4189 ioapic_res
->end
= ioapic_phys
+ IO_APIC_SLOT_SIZE
- 1;
4194 void __init
ioapic_insert_resources(void)
4197 struct resource
*r
= ioapic_resources
;
4202 "IO APIC resources couldn't be allocated.\n");
4206 for (i
= 0; i
< nr_ioapics
; i
++) {
4207 insert_resource(&iomem_resource
, r
);
4212 int mp_find_ioapic(u32 gsi
)
4216 /* Find the IOAPIC that manages this GSI. */
4217 for (i
= 0; i
< nr_ioapics
; i
++) {
4218 if ((gsi
>= mp_gsi_routing
[i
].gsi_base
)
4219 && (gsi
<= mp_gsi_routing
[i
].gsi_end
))
4223 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
4227 int mp_find_ioapic_pin(int ioapic
, u32 gsi
)
4229 if (WARN_ON(ioapic
== -1))
4231 if (WARN_ON(gsi
> mp_gsi_routing
[ioapic
].gsi_end
))
4234 return gsi
- mp_gsi_routing
[ioapic
].gsi_base
;
4237 static int bad_ioapic(unsigned long address
)
4239 if (nr_ioapics
>= MAX_IO_APICS
) {
4240 printk(KERN_WARNING
"WARING: Max # of I/O APICs (%d) exceeded "
4241 "(found %d), skipping\n", MAX_IO_APICS
, nr_ioapics
);
4245 printk(KERN_WARNING
"WARNING: Bogus (zero) I/O APIC address"
4246 " found in table, skipping!\n");
4252 void __init
mp_register_ioapic(int id
, u32 address
, u32 gsi_base
)
4257 if (bad_ioapic(address
))
4262 mp_ioapics
[idx
].type
= MP_IOAPIC
;
4263 mp_ioapics
[idx
].flags
= MPC_APIC_USABLE
;
4264 mp_ioapics
[idx
].apicaddr
= address
;
4266 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
4267 mp_ioapics
[idx
].apicid
= io_apic_unique_id(id
);
4268 mp_ioapics
[idx
].apicver
= io_apic_get_version(idx
);
4271 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4272 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4274 entries
= io_apic_get_redir_entries(idx
);
4275 mp_gsi_routing
[idx
].gsi_base
= gsi_base
;
4276 mp_gsi_routing
[idx
].gsi_end
= gsi_base
+ entries
- 1;
4279 * The number of IO-APIC IRQ registers (== #pins):
4281 nr_ioapic_registers
[idx
] = entries
;
4283 if (mp_gsi_routing
[idx
].gsi_end
>= gsi_top
)
4284 gsi_top
= mp_gsi_routing
[idx
].gsi_end
+ 1;
4286 printk(KERN_INFO
"IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4287 "GSI %d-%d\n", idx
, mp_ioapics
[idx
].apicid
,
4288 mp_ioapics
[idx
].apicver
, mp_ioapics
[idx
].apicaddr
,
4289 mp_gsi_routing
[idx
].gsi_base
, mp_gsi_routing
[idx
].gsi_end
);
4294 /* Enable IOAPIC early just for system timer */
4295 void __init
pre_init_apic_IRQ0(void)
4297 struct irq_cfg
*cfg
;
4298 struct irq_desc
*desc
;
4300 printk(KERN_INFO
"Early APIC setup for system timer0\n");
4302 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
4304 desc
= irq_to_desc_alloc_node(0, 0);
4309 add_pin_to_irq_node(cfg
, 0, 0, 0);
4310 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
4312 setup_IO_APIC_irq(0, 0, 0, desc
, 0, 0);