2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
58 #include <asm/msidef.h>
59 #include <asm/hypertransport.h>
60 #include <asm/setup.h>
61 #include <asm/irq_remapping.h>
63 #include <asm/hw_irq.h>
67 #define __apicdebuginit(type) static type __init
68 #define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
72 * Is the SiS APIC rmw bug present ?
73 * -1 = don't know, 0 = no, 1 = yes
75 int sis_apic_bug
= -1;
77 static DEFINE_RAW_SPINLOCK(ioapic_lock
);
78 static DEFINE_RAW_SPINLOCK(vector_lock
);
81 * # of IRQ routing registers
83 int nr_ioapic_registers
[MAX_IO_APICS
];
85 /* I/O APIC entries */
86 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
89 /* IO APIC gsi routing info */
90 struct mp_ioapic_gsi mp_gsi_routing
[MAX_IO_APICS
];
92 /* The one past the highest gsi number used */
95 /* MP IRQ source entries */
96 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
98 /* # of MP IRQ source entries */
102 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
104 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
105 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
108 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
110 int skip_ioapic_setup
;
112 void arch_disable_smp_support(void)
116 noioapicreroute
= -1;
118 skip_ioapic_setup
= 1;
121 static int __init
parse_noapic(char *str
)
123 /* disable IO-APIC */
124 arch_disable_smp_support();
127 early_param("noapic", parse_noapic
);
129 struct irq_pin_list
{
131 struct irq_pin_list
*next
;
134 static struct irq_pin_list
*get_one_free_irq_2_pin(int node
)
136 struct irq_pin_list
*pin
;
138 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
143 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
144 #ifdef CONFIG_SPARSE_IRQ
145 static struct irq_cfg irq_cfgx
[NR_IRQS_LEGACY
];
147 static struct irq_cfg irq_cfgx
[NR_IRQS
];
150 int __init
arch_early_irq_init(void)
153 struct irq_desc
*desc
;
158 if (!legacy_pic
->nr_legacy_irqs
) {
164 count
= ARRAY_SIZE(irq_cfgx
);
165 node
= cpu_to_node(0);
167 for (i
= 0; i
< count
; i
++) {
168 desc
= irq_to_desc(i
);
169 desc
->chip_data
= &cfg
[i
];
170 zalloc_cpumask_var_node(&cfg
[i
].domain
, GFP_NOWAIT
, node
);
171 zalloc_cpumask_var_node(&cfg
[i
].old_domain
, GFP_NOWAIT
, node
);
173 * For legacy IRQ's, start with assigning irq0 to irq15 to
174 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
176 if (i
< legacy_pic
->nr_legacy_irqs
) {
177 cfg
[i
].vector
= IRQ0_VECTOR
+ i
;
178 cpumask_set_cpu(0, cfg
[i
].domain
);
185 #ifdef CONFIG_SPARSE_IRQ
186 struct irq_cfg
*irq_cfg(unsigned int irq
)
188 struct irq_cfg
*cfg
= NULL
;
189 struct irq_desc
*desc
;
191 desc
= irq_to_desc(irq
);
193 cfg
= get_irq_desc_chip_data(desc
);
198 static struct irq_cfg
*get_one_free_irq_cfg(int node
)
202 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
204 if (!zalloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
207 } else if (!zalloc_cpumask_var_node(&cfg
->old_domain
,
209 free_cpumask_var(cfg
->domain
);
218 int arch_init_chip_data(struct irq_desc
*desc
, int node
)
222 cfg
= get_irq_desc_chip_data(desc
);
224 cfg
= get_one_free_irq_cfg(node
);
225 desc
->chip_data
= cfg
;
227 printk(KERN_ERR
"can not alloc irq_cfg\n");
235 /* for move_irq_desc */
237 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int node
)
239 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
241 cfg
->irq_2_pin
= NULL
;
242 old_entry
= old_cfg
->irq_2_pin
;
246 entry
= get_one_free_irq_2_pin(node
);
250 entry
->apic
= old_entry
->apic
;
251 entry
->pin
= old_entry
->pin
;
254 old_entry
= old_entry
->next
;
256 entry
= get_one_free_irq_2_pin(node
);
264 /* still use the old one */
267 entry
->apic
= old_entry
->apic
;
268 entry
->pin
= old_entry
->pin
;
271 old_entry
= old_entry
->next
;
275 cfg
->irq_2_pin
= head
;
278 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
280 struct irq_pin_list
*entry
, *next
;
282 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
285 entry
= old_cfg
->irq_2_pin
;
292 old_cfg
->irq_2_pin
= NULL
;
295 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
296 struct irq_desc
*desc
, int node
)
299 struct irq_cfg
*old_cfg
;
301 cfg
= get_one_free_irq_cfg(node
);
306 desc
->chip_data
= cfg
;
308 old_cfg
= old_desc
->chip_data
;
310 cfg
->vector
= old_cfg
->vector
;
311 cfg
->move_in_progress
= old_cfg
->move_in_progress
;
312 cpumask_copy(cfg
->domain
, old_cfg
->domain
);
313 cpumask_copy(cfg
->old_domain
, old_cfg
->old_domain
);
315 init_copy_irq_2_pin(old_cfg
, cfg
, node
);
318 static void free_irq_cfg(struct irq_cfg
*cfg
)
320 free_cpumask_var(cfg
->domain
);
321 free_cpumask_var(cfg
->old_domain
);
325 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
327 struct irq_cfg
*old_cfg
, *cfg
;
329 old_cfg
= get_irq_desc_chip_data(old_desc
);
330 cfg
= get_irq_desc_chip_data(desc
);
336 free_irq_2_pin(old_cfg
, cfg
);
337 free_irq_cfg(old_cfg
);
338 old_desc
->chip_data
= NULL
;
341 /* end for move_irq_desc */
344 struct irq_cfg
*irq_cfg(unsigned int irq
)
346 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
353 unsigned int unused
[3];
355 unsigned int unused2
[11];
359 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
361 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
362 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
365 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
367 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
368 writel(vector
, &io_apic
->eoi
);
371 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
373 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
374 writel(reg
, &io_apic
->index
);
375 return readl(&io_apic
->data
);
378 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
380 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
381 writel(reg
, &io_apic
->index
);
382 writel(value
, &io_apic
->data
);
386 * Re-write a value: to be used for read-modify-write
387 * cycles where the read already set up the index register.
389 * Older SiS APIC requires we rewrite the index register
391 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
393 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
396 writel(reg
, &io_apic
->index
);
397 writel(value
, &io_apic
->data
);
400 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
402 struct irq_pin_list
*entry
;
405 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
406 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
411 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
412 /* Is the remote IRR bit set? */
413 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
414 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
418 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
424 struct { u32 w1
, w2
; };
425 struct IO_APIC_route_entry entry
;
428 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
430 union entry_union eu
;
432 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
433 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
434 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
435 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
440 * When we write a new IO APIC routing entry, we need to write the high
441 * word first! If the mask bit in the low word is clear, we will enable
442 * the interrupt, and we need to make sure the entry is fully populated
443 * before that happens.
446 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
448 union entry_union eu
= {{0, 0}};
451 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
452 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
455 void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
458 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
459 __ioapic_write_entry(apic
, pin
, e
);
460 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
464 * When we mask an IO APIC routing entry, we need to write the low
465 * word first, in order to set the mask bit before we change the
468 static void ioapic_mask_entry(int apic
, int pin
)
471 union entry_union eu
= { .entry
.mask
= 1 };
473 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
474 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
475 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
476 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
480 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
481 * shared ISA-space IRQs, so we have to support them. We are super
482 * fast in the common case, and fast for shared ISA-space IRQs.
485 add_pin_to_irq_node_nopanic(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
487 struct irq_pin_list
**last
, *entry
;
489 /* don't allow duplicates */
490 last
= &cfg
->irq_2_pin
;
491 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
492 if (entry
->apic
== apic
&& entry
->pin
== pin
)
497 entry
= get_one_free_irq_2_pin(node
);
499 printk(KERN_ERR
"can not alloc irq_pin_list (%d,%d,%d)\n",
510 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
512 if (add_pin_to_irq_node_nopanic(cfg
, node
, apic
, pin
))
513 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
517 * Reroute an IRQ to a different pin.
519 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
520 int oldapic
, int oldpin
,
521 int newapic
, int newpin
)
523 struct irq_pin_list
*entry
;
525 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
526 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
527 entry
->apic
= newapic
;
529 /* every one is different, right? */
534 /* old apic/pin didn't exist, so just add new ones */
535 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
538 static void __io_apic_modify_irq(struct irq_pin_list
*entry
,
539 int mask_and
, int mask_or
,
540 void (*final
)(struct irq_pin_list
*entry
))
542 unsigned int reg
, pin
;
545 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
548 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
553 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
554 int mask_and
, int mask_or
,
555 void (*final
)(struct irq_pin_list
*entry
))
557 struct irq_pin_list
*entry
;
559 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
560 __io_apic_modify_irq(entry
, mask_and
, mask_or
, final
);
563 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list
*entry
)
565 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
566 IO_APIC_REDIR_MASKED
, NULL
);
569 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list
*entry
)
571 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_MASKED
,
572 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
575 static void io_apic_sync(struct irq_pin_list
*entry
)
578 * Synchronize the IO-APIC and the CPU by doing
579 * a dummy read from the IO-APIC
581 struct io_apic __iomem
*io_apic
;
582 io_apic
= io_apic_base(entry
->apic
);
583 readl(&io_apic
->data
);
586 static void mask_ioapic(struct irq_cfg
*cfg
)
590 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
591 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
592 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
595 static void mask_ioapic_irq(struct irq_data
*data
)
597 mask_ioapic(data
->chip_data
);
600 static void __unmask_ioapic(struct irq_cfg
*cfg
)
602 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
605 static void unmask_ioapic(struct irq_cfg
*cfg
)
609 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
610 __unmask_ioapic(cfg
);
611 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
614 static void unmask_ioapic_irq(struct irq_data
*data
)
616 unmask_ioapic(data
->chip_data
);
619 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
621 struct IO_APIC_route_entry entry
;
623 /* Check delivery_mode to be sure we're not clearing an SMI pin */
624 entry
= ioapic_read_entry(apic
, pin
);
625 if (entry
.delivery_mode
== dest_SMI
)
628 * Disable it in the IO-APIC irq-routing table:
630 ioapic_mask_entry(apic
, pin
);
633 static void clear_IO_APIC (void)
637 for (apic
= 0; apic
< nr_ioapics
; apic
++)
638 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
639 clear_IO_APIC_pin(apic
, pin
);
644 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
645 * specific CPU-side IRQs.
649 static int pirq_entries
[MAX_PIRQS
] = {
650 [0 ... MAX_PIRQS
- 1] = -1
653 static int __init
ioapic_pirq_setup(char *str
)
656 int ints
[MAX_PIRQS
+1];
658 get_options(str
, ARRAY_SIZE(ints
), ints
);
660 apic_printk(APIC_VERBOSE
, KERN_INFO
661 "PIRQ redirection, working around broken MP-BIOS.\n");
663 if (ints
[0] < MAX_PIRQS
)
666 for (i
= 0; i
< max
; i
++) {
667 apic_printk(APIC_VERBOSE
, KERN_DEBUG
668 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
670 * PIRQs are mapped upside down, usually.
672 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
677 __setup("pirq=", ioapic_pirq_setup
);
678 #endif /* CONFIG_X86_32 */
680 struct IO_APIC_route_entry
**alloc_ioapic_entries(void)
683 struct IO_APIC_route_entry
**ioapic_entries
;
685 ioapic_entries
= kzalloc(sizeof(*ioapic_entries
) * nr_ioapics
,
690 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
691 ioapic_entries
[apic
] =
692 kzalloc(sizeof(struct IO_APIC_route_entry
) *
693 nr_ioapic_registers
[apic
], GFP_ATOMIC
);
694 if (!ioapic_entries
[apic
])
698 return ioapic_entries
;
702 kfree(ioapic_entries
[apic
]);
703 kfree(ioapic_entries
);
709 * Saves all the IO-APIC RTE's
711 int save_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
718 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
719 if (!ioapic_entries
[apic
])
722 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
723 ioapic_entries
[apic
][pin
] =
724 ioapic_read_entry(apic
, pin
);
731 * Mask all IO APIC entries.
733 void mask_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
740 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
741 if (!ioapic_entries
[apic
])
744 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
745 struct IO_APIC_route_entry entry
;
747 entry
= ioapic_entries
[apic
][pin
];
750 ioapic_write_entry(apic
, pin
, entry
);
757 * Restore IO APIC entries which was saved in ioapic_entries.
759 int restore_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
766 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
767 if (!ioapic_entries
[apic
])
770 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
771 ioapic_write_entry(apic
, pin
,
772 ioapic_entries
[apic
][pin
]);
777 void free_ioapic_entries(struct IO_APIC_route_entry
**ioapic_entries
)
781 for (apic
= 0; apic
< nr_ioapics
; apic
++)
782 kfree(ioapic_entries
[apic
]);
784 kfree(ioapic_entries
);
788 * Find the IRQ entry number of a certain pin.
790 static int find_irq_entry(int apic
, int pin
, int type
)
794 for (i
= 0; i
< mp_irq_entries
; i
++)
795 if (mp_irqs
[i
].irqtype
== type
&&
796 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
797 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
798 mp_irqs
[i
].dstirq
== pin
)
805 * Find the pin to which IRQ[irq] (ISA) is connected
807 static int __init
find_isa_irq_pin(int irq
, int type
)
811 for (i
= 0; i
< mp_irq_entries
; i
++) {
812 int lbus
= mp_irqs
[i
].srcbus
;
814 if (test_bit(lbus
, mp_bus_not_pci
) &&
815 (mp_irqs
[i
].irqtype
== type
) &&
816 (mp_irqs
[i
].srcbusirq
== irq
))
818 return mp_irqs
[i
].dstirq
;
823 static int __init
find_isa_irq_apic(int irq
, int type
)
827 for (i
= 0; i
< mp_irq_entries
; i
++) {
828 int lbus
= mp_irqs
[i
].srcbus
;
830 if (test_bit(lbus
, mp_bus_not_pci
) &&
831 (mp_irqs
[i
].irqtype
== type
) &&
832 (mp_irqs
[i
].srcbusirq
== irq
))
835 if (i
< mp_irq_entries
) {
837 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
838 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
846 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
848 * EISA Edge/Level control register, ELCR
850 static int EISA_ELCR(unsigned int irq
)
852 if (irq
< legacy_pic
->nr_legacy_irqs
) {
853 unsigned int port
= 0x4d0 + (irq
>> 3);
854 return (inb(port
) >> (irq
& 7)) & 1;
856 apic_printk(APIC_VERBOSE
, KERN_INFO
857 "Broken MPtable reports ISA irq %d\n", irq
);
863 /* ISA interrupts are always polarity zero edge triggered,
864 * when listed as conforming in the MP table. */
866 #define default_ISA_trigger(idx) (0)
867 #define default_ISA_polarity(idx) (0)
869 /* EISA interrupts are always polarity zero and can be edge or level
870 * trigger depending on the ELCR value. If an interrupt is listed as
871 * EISA conforming in the MP table, that means its trigger type must
872 * be read in from the ELCR */
874 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
875 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
877 /* PCI interrupts are always polarity one level triggered,
878 * when listed as conforming in the MP table. */
880 #define default_PCI_trigger(idx) (1)
881 #define default_PCI_polarity(idx) (1)
883 /* MCA interrupts are always polarity zero level triggered,
884 * when listed as conforming in the MP table. */
886 #define default_MCA_trigger(idx) (1)
887 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
889 static int MPBIOS_polarity(int idx
)
891 int bus
= mp_irqs
[idx
].srcbus
;
895 * Determine IRQ line polarity (high active or low active):
897 switch (mp_irqs
[idx
].irqflag
& 3)
899 case 0: /* conforms, ie. bus-type dependent polarity */
900 if (test_bit(bus
, mp_bus_not_pci
))
901 polarity
= default_ISA_polarity(idx
);
903 polarity
= default_PCI_polarity(idx
);
905 case 1: /* high active */
910 case 2: /* reserved */
912 printk(KERN_WARNING
"broken BIOS!!\n");
916 case 3: /* low active */
921 default: /* invalid */
923 printk(KERN_WARNING
"broken BIOS!!\n");
931 static int MPBIOS_trigger(int idx
)
933 int bus
= mp_irqs
[idx
].srcbus
;
937 * Determine IRQ trigger mode (edge or level sensitive):
939 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
941 case 0: /* conforms, ie. bus-type dependent */
942 if (test_bit(bus
, mp_bus_not_pci
))
943 trigger
= default_ISA_trigger(idx
);
945 trigger
= default_PCI_trigger(idx
);
946 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
947 switch (mp_bus_id_to_type
[bus
]) {
948 case MP_BUS_ISA
: /* ISA pin */
950 /* set before the switch */
953 case MP_BUS_EISA
: /* EISA pin */
955 trigger
= default_EISA_trigger(idx
);
958 case MP_BUS_PCI
: /* PCI pin */
960 /* set before the switch */
963 case MP_BUS_MCA
: /* MCA pin */
965 trigger
= default_MCA_trigger(idx
);
970 printk(KERN_WARNING
"broken BIOS!!\n");
982 case 2: /* reserved */
984 printk(KERN_WARNING
"broken BIOS!!\n");
993 default: /* invalid */
995 printk(KERN_WARNING
"broken BIOS!!\n");
1003 static inline int irq_polarity(int idx
)
1005 return MPBIOS_polarity(idx
);
1008 static inline int irq_trigger(int idx
)
1010 return MPBIOS_trigger(idx
);
1013 static int pin_2_irq(int idx
, int apic
, int pin
)
1016 int bus
= mp_irqs
[idx
].srcbus
;
1019 * Debugging check, we are in big trouble if this message pops up!
1021 if (mp_irqs
[idx
].dstirq
!= pin
)
1022 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1024 if (test_bit(bus
, mp_bus_not_pci
)) {
1025 irq
= mp_irqs
[idx
].srcbusirq
;
1027 u32 gsi
= mp_gsi_routing
[apic
].gsi_base
+ pin
;
1029 if (gsi
>= NR_IRQS_LEGACY
)
1032 irq
= gsi_top
+ gsi
;
1035 #ifdef CONFIG_X86_32
1037 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1039 if ((pin
>= 16) && (pin
<= 23)) {
1040 if (pirq_entries
[pin
-16] != -1) {
1041 if (!pirq_entries
[pin
-16]) {
1042 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1043 "disabling PIRQ%d\n", pin
-16);
1045 irq
= pirq_entries
[pin
-16];
1046 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1047 "using PIRQ%d -> IRQ %d\n",
1058 * Find a specific PCI IRQ entry.
1059 * Not an __init, possibly needed by modules
1061 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
1062 struct io_apic_irq_attr
*irq_attr
)
1064 int apic
, i
, best_guess
= -1;
1066 apic_printk(APIC_DEBUG
,
1067 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1069 if (test_bit(bus
, mp_bus_not_pci
)) {
1070 apic_printk(APIC_VERBOSE
,
1071 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1074 for (i
= 0; i
< mp_irq_entries
; i
++) {
1075 int lbus
= mp_irqs
[i
].srcbus
;
1077 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1078 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1079 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1082 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1083 !mp_irqs
[i
].irqtype
&&
1085 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1086 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1088 if (!(apic
|| IO_APIC_IRQ(irq
)))
1091 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1092 set_io_apic_irq_attr(irq_attr
, apic
,
1099 * Use the first all-but-pin matching entry as a
1100 * best-guess fuzzy result for broken mptables.
1102 if (best_guess
< 0) {
1103 set_io_apic_irq_attr(irq_attr
, apic
,
1113 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1115 void lock_vector_lock(void)
1117 /* Used to the online set of cpus does not change
1118 * during assign_irq_vector.
1120 raw_spin_lock(&vector_lock
);
1123 void unlock_vector_lock(void)
1125 raw_spin_unlock(&vector_lock
);
1129 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1132 * NOTE! The local APIC isn't very good at handling
1133 * multiple interrupts at the same interrupt level.
1134 * As the interrupt level is determined by taking the
1135 * vector number and shifting that right by 4, we
1136 * want to spread these out a bit so that they don't
1137 * all fall in the same interrupt level.
1139 * Also, we've got to be careful not to trash gate
1140 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1142 static int current_vector
= FIRST_EXTERNAL_VECTOR
+ VECTOR_OFFSET_START
;
1143 static int current_offset
= VECTOR_OFFSET_START
% 8;
1144 unsigned int old_vector
;
1146 cpumask_var_t tmp_mask
;
1148 if (cfg
->move_in_progress
)
1151 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1154 old_vector
= cfg
->vector
;
1156 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1157 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1158 if (!cpumask_empty(tmp_mask
)) {
1159 free_cpumask_var(tmp_mask
);
1164 /* Only try and allocate irqs on cpus that are present */
1166 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1170 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1172 vector
= current_vector
;
1173 offset
= current_offset
;
1176 if (vector
>= first_system_vector
) {
1177 /* If out of vectors on large boxen, must share them. */
1178 offset
= (offset
+ 1) % 8;
1179 vector
= FIRST_EXTERNAL_VECTOR
+ offset
;
1181 if (unlikely(current_vector
== vector
))
1184 if (test_bit(vector
, used_vectors
))
1187 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1188 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1191 current_vector
= vector
;
1192 current_offset
= offset
;
1194 cfg
->move_in_progress
= 1;
1195 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1197 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1198 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1199 cfg
->vector
= vector
;
1200 cpumask_copy(cfg
->domain
, tmp_mask
);
1204 free_cpumask_var(tmp_mask
);
1208 int assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1211 unsigned long flags
;
1213 raw_spin_lock_irqsave(&vector_lock
, flags
);
1214 err
= __assign_irq_vector(irq
, cfg
, mask
);
1215 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
1219 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1223 BUG_ON(!cfg
->vector
);
1225 vector
= cfg
->vector
;
1226 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1227 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1230 cpumask_clear(cfg
->domain
);
1232 if (likely(!cfg
->move_in_progress
))
1234 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1235 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1237 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1239 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1243 cfg
->move_in_progress
= 0;
1246 void __setup_vector_irq(int cpu
)
1248 /* Initialize vector_irq on a new cpu */
1250 struct irq_cfg
*cfg
;
1251 struct irq_desc
*desc
;
1254 * vector_lock will make sure that we don't run into irq vector
1255 * assignments that might be happening on another cpu in parallel,
1256 * while we setup our initial vector to irq mappings.
1258 raw_spin_lock(&vector_lock
);
1259 /* Mark the inuse vectors */
1260 for_each_irq_desc(irq
, desc
) {
1261 cfg
= get_irq_desc_chip_data(desc
);
1264 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1265 * will be part of the irq_cfg's domain.
1267 if (irq
< legacy_pic
->nr_legacy_irqs
&& !IO_APIC_IRQ(irq
))
1268 cpumask_set_cpu(cpu
, cfg
->domain
);
1270 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1272 vector
= cfg
->vector
;
1273 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1275 /* Mark the free vectors */
1276 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1277 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1282 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1283 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1285 raw_spin_unlock(&vector_lock
);
1288 static struct irq_chip ioapic_chip
;
1289 static struct irq_chip ir_ioapic_chip
;
1291 #define IOAPIC_AUTO -1
1292 #define IOAPIC_EDGE 0
1293 #define IOAPIC_LEVEL 1
1295 #ifdef CONFIG_X86_32
1296 static inline int IO_APIC_irq_trigger(int irq
)
1300 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1301 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1302 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1303 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1304 return irq_trigger(idx
);
1308 * nonexistent IRQs are edge default
1313 static inline int IO_APIC_irq_trigger(int irq
)
1319 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1322 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1323 trigger
== IOAPIC_LEVEL
)
1324 desc
->status
|= IRQ_LEVEL
;
1326 desc
->status
&= ~IRQ_LEVEL
;
1328 if (irq_remapped(irq
)) {
1329 desc
->status
|= IRQ_MOVE_PCNTXT
;
1331 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1335 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1336 handle_edge_irq
, "edge");
1340 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1341 trigger
== IOAPIC_LEVEL
)
1342 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1346 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1347 handle_edge_irq
, "edge");
1350 int setup_ioapic_entry(int apic_id
, int irq
,
1351 struct IO_APIC_route_entry
*entry
,
1352 unsigned int destination
, int trigger
,
1353 int polarity
, int vector
, int pin
)
1356 * add it to the IO-APIC irq-routing table:
1358 memset(entry
,0,sizeof(*entry
));
1360 if (intr_remapping_enabled
) {
1361 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1363 struct IR_IO_APIC_route_entry
*ir_entry
=
1364 (struct IR_IO_APIC_route_entry
*) entry
;
1368 panic("No mapping iommu for ioapic %d\n", apic_id
);
1370 index
= alloc_irte(iommu
, irq
, 1);
1372 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1374 prepare_irte(&irte
, vector
, destination
);
1376 /* Set source-id of interrupt request */
1377 set_ioapic_sid(&irte
, apic_id
);
1379 modify_irte(irq
, &irte
);
1381 ir_entry
->index2
= (index
>> 15) & 0x1;
1383 ir_entry
->format
= 1;
1384 ir_entry
->index
= (index
& 0x7fff);
1386 * IO-APIC RTE will be configured with virtual vector.
1387 * irq handler will do the explicit EOI to the io-apic.
1389 ir_entry
->vector
= pin
;
1391 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1392 entry
->dest_mode
= apic
->irq_dest_mode
;
1393 entry
->dest
= destination
;
1394 entry
->vector
= vector
;
1397 entry
->mask
= 0; /* enable IRQ */
1398 entry
->trigger
= trigger
;
1399 entry
->polarity
= polarity
;
1401 /* Mask level triggered irqs.
1402 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1409 static void setup_IO_APIC_irq(int apic_id
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1410 int trigger
, int polarity
)
1412 struct irq_cfg
*cfg
;
1413 struct IO_APIC_route_entry entry
;
1416 if (!IO_APIC_IRQ(irq
))
1419 cfg
= get_irq_desc_chip_data(desc
);
1422 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1423 * controllers like 8259. Now that IO-APIC can handle this irq, update
1426 if (irq
< legacy_pic
->nr_legacy_irqs
&& cpumask_test_cpu(0, cfg
->domain
))
1427 apic
->vector_allocation_domain(0, cfg
->domain
);
1429 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1432 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1434 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1435 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1436 "IRQ %d Mode:%i Active:%i)\n",
1437 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1438 irq
, trigger
, polarity
);
1441 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1442 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1443 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1444 mp_ioapics
[apic_id
].apicid
, pin
);
1445 __clear_irq_vector(irq
, cfg
);
1449 ioapic_register_intr(irq
, desc
, trigger
);
1450 if (irq
< legacy_pic
->nr_legacy_irqs
)
1451 legacy_pic
->mask(irq
);
1453 ioapic_write_entry(apic_id
, pin
, entry
);
1457 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
1458 } mp_ioapic_routing
[MAX_IO_APICS
];
1460 static void __init
setup_IO_APIC_irqs(void)
1462 int apic_id
, pin
, idx
, irq
;
1464 struct irq_desc
*desc
;
1465 struct irq_cfg
*cfg
;
1466 int node
= cpu_to_node(0);
1468 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1470 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++)
1471 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1472 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1476 apic_printk(APIC_VERBOSE
,
1477 KERN_DEBUG
" %d-%d",
1478 mp_ioapics
[apic_id
].apicid
, pin
);
1480 apic_printk(APIC_VERBOSE
, " %d-%d",
1481 mp_ioapics
[apic_id
].apicid
, pin
);
1485 apic_printk(APIC_VERBOSE
,
1486 " (apicid-pin) not connected\n");
1490 irq
= pin_2_irq(idx
, apic_id
, pin
);
1492 if ((apic_id
> 0) && (irq
> 16))
1496 * Skip the timer IRQ if there's a quirk handler
1497 * installed and if it returns 1:
1499 if (apic
->multi_timer_check
&&
1500 apic
->multi_timer_check(apic_id
, irq
))
1503 desc
= irq_to_desc_alloc_node(irq
, node
);
1505 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1508 cfg
= get_irq_desc_chip_data(desc
);
1509 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1511 * don't mark it in pin_programmed, so later acpi could
1512 * set it correctly when irq < 16
1514 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1515 irq_trigger(idx
), irq_polarity(idx
));
1519 apic_printk(APIC_VERBOSE
,
1520 " (apicid-pin) not connected\n");
1524 * for the gsit that is not in first ioapic
1525 * but could not use acpi_register_gsi()
1526 * like some special sci in IBM x3330
1528 void setup_IO_APIC_irq_extra(u32 gsi
)
1530 int apic_id
= 0, pin
, idx
, irq
;
1531 int node
= cpu_to_node(0);
1532 struct irq_desc
*desc
;
1533 struct irq_cfg
*cfg
;
1536 * Convert 'gsi' to 'ioapic.pin'.
1538 apic_id
= mp_find_ioapic(gsi
);
1542 pin
= mp_find_ioapic_pin(apic_id
, gsi
);
1543 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1547 irq
= pin_2_irq(idx
, apic_id
, pin
);
1548 #ifdef CONFIG_SPARSE_IRQ
1549 desc
= irq_to_desc(irq
);
1553 desc
= irq_to_desc_alloc_node(irq
, node
);
1555 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1559 cfg
= get_irq_desc_chip_data(desc
);
1560 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1562 if (test_bit(pin
, mp_ioapic_routing
[apic_id
].pin_programmed
)) {
1563 pr_debug("Pin %d-%d already programmed\n",
1564 mp_ioapics
[apic_id
].apicid
, pin
);
1567 set_bit(pin
, mp_ioapic_routing
[apic_id
].pin_programmed
);
1569 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1570 irq_trigger(idx
), irq_polarity(idx
));
1574 * Set up the timer pin, possibly with the 8259A-master behind.
1576 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1579 struct IO_APIC_route_entry entry
;
1581 if (intr_remapping_enabled
)
1584 memset(&entry
, 0, sizeof(entry
));
1587 * We use logical delivery to get the timer IRQ
1590 entry
.dest_mode
= apic
->irq_dest_mode
;
1591 entry
.mask
= 0; /* don't mask IRQ for edge */
1592 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1593 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1596 entry
.vector
= vector
;
1599 * The timer IRQ doesn't have to know that behind the
1600 * scene we may have a 8259A-master in AEOI mode ...
1602 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1605 * Add it to the IO-APIC irq-routing table:
1607 ioapic_write_entry(apic_id
, pin
, entry
);
1611 __apicdebuginit(void) print_IO_APIC(void)
1614 union IO_APIC_reg_00 reg_00
;
1615 union IO_APIC_reg_01 reg_01
;
1616 union IO_APIC_reg_02 reg_02
;
1617 union IO_APIC_reg_03 reg_03
;
1618 unsigned long flags
;
1619 struct irq_cfg
*cfg
;
1620 struct irq_desc
*desc
;
1623 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1624 for (i
= 0; i
< nr_ioapics
; i
++)
1625 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1626 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1629 * We are a bit conservative about what we expect. We have to
1630 * know about every hardware change ASAP.
1632 printk(KERN_INFO
"testing the IO APIC.......................\n");
1634 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1636 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1637 reg_00
.raw
= io_apic_read(apic
, 0);
1638 reg_01
.raw
= io_apic_read(apic
, 1);
1639 if (reg_01
.bits
.version
>= 0x10)
1640 reg_02
.raw
= io_apic_read(apic
, 2);
1641 if (reg_01
.bits
.version
>= 0x20)
1642 reg_03
.raw
= io_apic_read(apic
, 3);
1643 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1646 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1647 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1648 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1649 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1650 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1652 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1653 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1655 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1656 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1659 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1660 * but the value of reg_02 is read as the previous read register
1661 * value, so ignore it if reg_02 == reg_01.
1663 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1664 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1665 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1669 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1670 * or reg_03, but the value of reg_0[23] is read as the previous read
1671 * register value, so ignore it if reg_03 == reg_0[12].
1673 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1674 reg_03
.raw
!= reg_01
.raw
) {
1675 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1676 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1679 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1681 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1682 " Stat Dmod Deli Vect:\n");
1684 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1685 struct IO_APIC_route_entry entry
;
1687 entry
= ioapic_read_entry(apic
, i
);
1689 printk(KERN_DEBUG
" %02x %03X ",
1694 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1699 entry
.delivery_status
,
1701 entry
.delivery_mode
,
1706 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1707 for_each_irq_desc(irq
, desc
) {
1708 struct irq_pin_list
*entry
;
1710 cfg
= get_irq_desc_chip_data(desc
);
1713 entry
= cfg
->irq_2_pin
;
1716 printk(KERN_DEBUG
"IRQ%d ", irq
);
1717 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
1718 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1722 printk(KERN_INFO
".................................... done.\n");
1727 __apicdebuginit(void) print_APIC_field(int base
)
1733 for (i
= 0; i
< 8; i
++)
1734 printk(KERN_CONT
"%08x", apic_read(base
+ i
*0x10));
1736 printk(KERN_CONT
"\n");
1739 __apicdebuginit(void) print_local_APIC(void *dummy
)
1741 unsigned int i
, v
, ver
, maxlvt
;
1744 printk(KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1745 smp_processor_id(), hard_smp_processor_id());
1746 v
= apic_read(APIC_ID
);
1747 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1748 v
= apic_read(APIC_LVR
);
1749 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1750 ver
= GET_APIC_VERSION(v
);
1751 maxlvt
= lapic_get_maxlvt();
1753 v
= apic_read(APIC_TASKPRI
);
1754 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1756 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1757 if (!APIC_XAPIC(ver
)) {
1758 v
= apic_read(APIC_ARBPRI
);
1759 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1760 v
& APIC_ARBPRI_MASK
);
1762 v
= apic_read(APIC_PROCPRI
);
1763 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1767 * Remote read supported only in the 82489DX and local APIC for
1768 * Pentium processors.
1770 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1771 v
= apic_read(APIC_RRR
);
1772 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1775 v
= apic_read(APIC_LDR
);
1776 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1777 if (!x2apic_enabled()) {
1778 v
= apic_read(APIC_DFR
);
1779 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1781 v
= apic_read(APIC_SPIV
);
1782 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1784 printk(KERN_DEBUG
"... APIC ISR field:\n");
1785 print_APIC_field(APIC_ISR
);
1786 printk(KERN_DEBUG
"... APIC TMR field:\n");
1787 print_APIC_field(APIC_TMR
);
1788 printk(KERN_DEBUG
"... APIC IRR field:\n");
1789 print_APIC_field(APIC_IRR
);
1791 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1792 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1793 apic_write(APIC_ESR
, 0);
1795 v
= apic_read(APIC_ESR
);
1796 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1799 icr
= apic_icr_read();
1800 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1801 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1803 v
= apic_read(APIC_LVTT
);
1804 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1806 if (maxlvt
> 3) { /* PC is LVT#4. */
1807 v
= apic_read(APIC_LVTPC
);
1808 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1810 v
= apic_read(APIC_LVT0
);
1811 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1812 v
= apic_read(APIC_LVT1
);
1813 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1815 if (maxlvt
> 2) { /* ERR is LVT#3. */
1816 v
= apic_read(APIC_LVTERR
);
1817 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1820 v
= apic_read(APIC_TMICT
);
1821 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1822 v
= apic_read(APIC_TMCCT
);
1823 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1824 v
= apic_read(APIC_TDCR
);
1825 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1827 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1828 v
= apic_read(APIC_EFEAT
);
1829 maxlvt
= (v
>> 16) & 0xff;
1830 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1831 v
= apic_read(APIC_ECTRL
);
1832 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1833 for (i
= 0; i
< maxlvt
; i
++) {
1834 v
= apic_read(APIC_EILVTn(i
));
1835 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1841 __apicdebuginit(void) print_local_APICs(int maxcpu
)
1849 for_each_online_cpu(cpu
) {
1852 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1857 __apicdebuginit(void) print_PIC(void)
1860 unsigned long flags
;
1862 if (!legacy_pic
->nr_legacy_irqs
)
1865 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1867 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
1869 v
= inb(0xa1) << 8 | inb(0x21);
1870 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1872 v
= inb(0xa0) << 8 | inb(0x20);
1873 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1877 v
= inb(0xa0) << 8 | inb(0x20);
1881 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
1883 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1885 v
= inb(0x4d1) << 8 | inb(0x4d0);
1886 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1889 static int __initdata show_lapic
= 1;
1890 static __init
int setup_show_lapic(char *arg
)
1894 if (strcmp(arg
, "all") == 0) {
1895 show_lapic
= CONFIG_NR_CPUS
;
1897 get_option(&arg
, &num
);
1904 __setup("show_lapic=", setup_show_lapic
);
1906 __apicdebuginit(int) print_ICs(void)
1908 if (apic_verbosity
== APIC_QUIET
)
1913 /* don't print out if apic is not there */
1914 if (!cpu_has_apic
&& !apic_from_smp_config())
1917 print_local_APICs(show_lapic
);
1923 fs_initcall(print_ICs
);
1926 /* Where if anywhere is the i8259 connect in external int mode */
1927 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1929 void __init
enable_IO_APIC(void)
1931 int i8259_apic
, i8259_pin
;
1934 if (!legacy_pic
->nr_legacy_irqs
)
1937 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1939 /* See if any of the pins is in ExtINT mode */
1940 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1941 struct IO_APIC_route_entry entry
;
1942 entry
= ioapic_read_entry(apic
, pin
);
1944 /* If the interrupt line is enabled and in ExtInt mode
1945 * I have found the pin where the i8259 is connected.
1947 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1948 ioapic_i8259
.apic
= apic
;
1949 ioapic_i8259
.pin
= pin
;
1955 /* Look to see what if the MP table has reported the ExtINT */
1956 /* If we could not find the appropriate pin by looking at the ioapic
1957 * the i8259 probably is not connected the ioapic but give the
1958 * mptable a chance anyway.
1960 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1961 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1962 /* Trust the MP table if nothing is setup in the hardware */
1963 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1964 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1965 ioapic_i8259
.pin
= i8259_pin
;
1966 ioapic_i8259
.apic
= i8259_apic
;
1968 /* Complain if the MP table and the hardware disagree */
1969 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1970 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1972 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1976 * Do not trust the IO-APIC being empty at bootup
1982 * Not an __init, needed by the reboot code
1984 void disable_IO_APIC(void)
1987 * Clear the IO-APIC before rebooting:
1991 if (!legacy_pic
->nr_legacy_irqs
)
1995 * If the i8259 is routed through an IOAPIC
1996 * Put that IOAPIC in virtual wire mode
1997 * so legacy interrupts can be delivered.
1999 * With interrupt-remapping, for now we will use virtual wire A mode,
2000 * as virtual wire B is little complex (need to configure both
2001 * IOAPIC RTE aswell as interrupt-remapping table entry).
2002 * As this gets called during crash dump, keep this simple for now.
2004 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
2005 struct IO_APIC_route_entry entry
;
2007 memset(&entry
, 0, sizeof(entry
));
2008 entry
.mask
= 0; /* Enabled */
2009 entry
.trigger
= 0; /* Edge */
2011 entry
.polarity
= 0; /* High */
2012 entry
.delivery_status
= 0;
2013 entry
.dest_mode
= 0; /* Physical */
2014 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
2016 entry
.dest
= read_apic_id();
2019 * Add it to the IO-APIC irq-routing table:
2021 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
2025 * Use virtual wire A mode when interrupt remapping is enabled.
2027 if (cpu_has_apic
|| apic_from_smp_config())
2028 disconnect_bsp_APIC(!intr_remapping_enabled
&&
2029 ioapic_i8259
.pin
!= -1);
2032 #ifdef CONFIG_X86_32
2034 * function to set the IO-APIC physical IDs based on the
2035 * values stored in the MPC table.
2037 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2040 void __init
setup_ioapic_ids_from_mpc(void)
2042 union IO_APIC_reg_00 reg_00
;
2043 physid_mask_t phys_id_present_map
;
2046 unsigned char old_id
;
2047 unsigned long flags
;
2052 * Don't check I/O APIC IDs for xAPIC systems. They have
2053 * no meaning without the serial APIC bus.
2055 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2056 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2059 * This is broken; anything with a real cpu count has to
2060 * circumvent this idiocy regardless.
2062 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &phys_id_present_map
);
2065 * Set the IOAPIC ID to the value stored in the MPC table.
2067 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
2069 /* Read the register 0 value */
2070 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2071 reg_00
.raw
= io_apic_read(apic_id
, 0);
2072 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2074 old_id
= mp_ioapics
[apic_id
].apicid
;
2076 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
2077 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2078 apic_id
, mp_ioapics
[apic_id
].apicid
);
2079 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2081 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
2085 * Sanity check, is the ID really free? Every APIC in a
2086 * system must have a unique ID or we get lots of nice
2087 * 'stuck on smp_invalidate_needed IPI wait' messages.
2089 if (apic
->check_apicid_used(&phys_id_present_map
,
2090 mp_ioapics
[apic_id
].apicid
)) {
2091 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2092 apic_id
, mp_ioapics
[apic_id
].apicid
);
2093 for (i
= 0; i
< get_physical_broadcast(); i
++)
2094 if (!physid_isset(i
, phys_id_present_map
))
2096 if (i
>= get_physical_broadcast())
2097 panic("Max APIC ID exceeded!\n");
2098 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2100 physid_set(i
, phys_id_present_map
);
2101 mp_ioapics
[apic_id
].apicid
= i
;
2104 apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
, &tmp
);
2105 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2106 "phys_id_present_map\n",
2107 mp_ioapics
[apic_id
].apicid
);
2108 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2113 * We need to adjust the IRQ routing table
2114 * if the ID changed.
2116 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
2117 for (i
= 0; i
< mp_irq_entries
; i
++)
2118 if (mp_irqs
[i
].dstapic
== old_id
)
2120 = mp_ioapics
[apic_id
].apicid
;
2123 * Read the right value from the MPC table and
2124 * write it into the ID register.
2126 apic_printk(APIC_VERBOSE
, KERN_INFO
2127 "...changing IO-APIC physical APIC ID to %d ...",
2128 mp_ioapics
[apic_id
].apicid
);
2130 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2131 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2132 io_apic_write(apic_id
, 0, reg_00
.raw
);
2133 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2138 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2139 reg_00
.raw
= io_apic_read(apic_id
, 0);
2140 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2141 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2142 printk("could not set ID!\n");
2144 apic_printk(APIC_VERBOSE
, " ok.\n");
2149 int no_timer_check __initdata
;
2151 static int __init
notimercheck(char *s
)
2156 __setup("no_timer_check", notimercheck
);
2159 * There is a nasty bug in some older SMP boards, their mptable lies
2160 * about the timer IRQ. We do the following to work around the situation:
2162 * - timer IRQ defaults to IO-APIC IRQ
2163 * - if this function detects that timer IRQs are defunct, then we fall
2164 * back to ISA timer IRQs
2166 static int __init
timer_irq_works(void)
2168 unsigned long t1
= jiffies
;
2169 unsigned long flags
;
2174 local_save_flags(flags
);
2176 /* Let ten ticks pass... */
2177 mdelay((10 * 1000) / HZ
);
2178 local_irq_restore(flags
);
2181 * Expect a few ticks at least, to be sure some possible
2182 * glue logic does not lock up after one or two first
2183 * ticks in a non-ExtINT mode. Also the local APIC
2184 * might have cached one ExtINT interrupt. Finally, at
2185 * least one tick may be lost due to delays.
2189 if (time_after(jiffies
, t1
+ 4))
2195 * In the SMP+IOAPIC case it might happen that there are an unspecified
2196 * number of pending IRQ events unhandled. These cases are very rare,
2197 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2198 * better to do it this way as thus we do not have to be aware of
2199 * 'pending' interrupts in the IRQ path, except at this point.
2202 * Edge triggered needs to resend any interrupt
2203 * that was delayed but this is now handled in the device
2208 * Starting up a edge-triggered IO-APIC interrupt is
2209 * nasty - we need to make sure that we get the edge.
2210 * If it is already asserted for some reason, we need
2211 * return 1 to indicate that is was pending.
2213 * This is not complete - we should be able to fake
2214 * an edge even if it isn't on the 8259A...
2217 static unsigned int startup_ioapic_irq(struct irq_data
*data
)
2219 int was_pending
= 0, irq
= data
->irq
;
2220 unsigned long flags
;
2222 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2223 if (irq
< legacy_pic
->nr_legacy_irqs
) {
2224 legacy_pic
->mask(irq
);
2225 if (legacy_pic
->irq_pending(irq
))
2228 __unmask_ioapic(data
->chip_data
);
2229 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2234 static int ioapic_retrigger_irq(struct irq_data
*data
)
2236 struct irq_cfg
*cfg
= data
->chip_data
;
2237 unsigned long flags
;
2239 raw_spin_lock_irqsave(&vector_lock
, flags
);
2240 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2241 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2247 * Level and edge triggered IO-APIC interrupts need different handling,
2248 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2249 * handled with the level-triggered descriptor, but that one has slightly
2250 * more overhead. Level-triggered interrupts cannot be handled with the
2251 * edge-triggered handler, without risking IRQ storms and other ugly
2256 void send_cleanup_vector(struct irq_cfg
*cfg
)
2258 cpumask_var_t cleanup_mask
;
2260 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2262 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2263 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2265 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2266 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2267 free_cpumask_var(cleanup_mask
);
2269 cfg
->move_in_progress
= 0;
2272 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2275 struct irq_pin_list
*entry
;
2276 u8 vector
= cfg
->vector
;
2278 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2284 * With interrupt-remapping, destination information comes
2285 * from interrupt-remapping table entry.
2287 if (!irq_remapped(irq
))
2288 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2289 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2290 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2292 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2297 * Either sets desc->affinity to a valid value, and returns
2298 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2299 * leaves desc->affinity untouched.
2302 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
,
2303 unsigned int *dest_id
)
2305 struct irq_cfg
*cfg
;
2308 if (!cpumask_intersects(mask
, cpu_online_mask
))
2312 cfg
= get_irq_desc_chip_data(desc
);
2313 if (assign_irq_vector(irq
, cfg
, mask
))
2316 cpumask_copy(desc
->affinity
, mask
);
2318 *dest_id
= apic
->cpu_mask_to_apicid_and(desc
->affinity
, cfg
->domain
);
2323 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2325 struct irq_cfg
*cfg
;
2326 unsigned long flags
;
2332 cfg
= get_irq_desc_chip_data(desc
);
2334 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2335 ret
= set_desc_affinity(desc
, mask
, &dest
);
2337 /* Only the high 8 bits are valid. */
2338 dest
= SET_APIC_LOGICAL_ID(dest
);
2339 __target_IO_APIC_irq(irq
, dest
, cfg
);
2341 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2347 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
2349 struct irq_desc
*desc
;
2351 desc
= irq_to_desc(irq
);
2353 return set_ioapic_affinity_irq_desc(desc
, mask
);
2356 #ifdef CONFIG_INTR_REMAP
2359 * Migrate the IO-APIC irq in the presence of intr-remapping.
2361 * For both level and edge triggered, irq migration is a simple atomic
2362 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2364 * For level triggered, we eliminate the io-apic RTE modification (with the
2365 * updated vector information), by using a virtual vector (io-apic pin number).
2366 * Real vector that is used for interrupting cpu will be coming from
2367 * the interrupt-remapping table entry.
2370 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2372 struct irq_cfg
*cfg
;
2378 if (!cpumask_intersects(mask
, cpu_online_mask
))
2382 if (get_irte(irq
, &irte
))
2385 cfg
= get_irq_desc_chip_data(desc
);
2386 if (assign_irq_vector(irq
, cfg
, mask
))
2389 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2391 irte
.vector
= cfg
->vector
;
2392 irte
.dest_id
= IRTE_DEST(dest
);
2395 * Modified the IRTE and flushes the Interrupt entry cache.
2397 modify_irte(irq
, &irte
);
2399 if (cfg
->move_in_progress
)
2400 send_cleanup_vector(cfg
);
2402 cpumask_copy(desc
->affinity
, mask
);
2408 * Migrates the IRQ destination in the process context.
2410 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2411 const struct cpumask
*mask
)
2413 return migrate_ioapic_irq_desc(desc
, mask
);
2415 static int set_ir_ioapic_affinity_irq(unsigned int irq
,
2416 const struct cpumask
*mask
)
2418 struct irq_desc
*desc
= irq_to_desc(irq
);
2420 return set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2423 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2424 const struct cpumask
*mask
)
2430 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2432 unsigned vector
, me
;
2438 me
= smp_processor_id();
2439 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2442 struct irq_desc
*desc
;
2443 struct irq_cfg
*cfg
;
2444 irq
= __get_cpu_var(vector_irq
)[vector
];
2449 desc
= irq_to_desc(irq
);
2454 raw_spin_lock(&desc
->lock
);
2457 * Check if the irq migration is in progress. If so, we
2458 * haven't received the cleanup request yet for this irq.
2460 if (cfg
->move_in_progress
)
2463 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2466 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2468 * Check if the vector that needs to be cleanedup is
2469 * registered at the cpu's IRR. If so, then this is not
2470 * the best time to clean it up. Lets clean it up in the
2471 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2474 if (irr
& (1 << (vector
% 32))) {
2475 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2478 __get_cpu_var(vector_irq
)[vector
] = -1;
2480 raw_spin_unlock(&desc
->lock
);
2486 static void __irq_complete_move(struct irq_cfg
*cfg
, unsigned vector
)
2490 if (likely(!cfg
->move_in_progress
))
2493 me
= smp_processor_id();
2495 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2496 send_cleanup_vector(cfg
);
2499 static void irq_complete_move(struct irq_cfg
*cfg
)
2501 __irq_complete_move(cfg
, ~get_irq_regs()->orig_ax
);
2504 void irq_force_complete_move(int irq
)
2506 struct irq_cfg
*cfg
= get_irq_chip_data(irq
);
2511 __irq_complete_move(cfg
, cfg
->vector
);
2514 static inline void irq_complete_move(struct irq_cfg
*cfg
) { }
2517 static void ack_apic_edge(struct irq_data
*data
)
2519 irq_complete_move(data
->chip_data
);
2520 move_native_irq(data
->irq
);
2524 atomic_t irq_mis_count
;
2527 * IO-APIC versions below 0x20 don't support EOI register.
2528 * For the record, here is the information about various versions:
2530 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2531 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2534 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2535 * version as 0x2. This is an error with documentation and these ICH chips
2536 * use io-apic's of version 0x20.
2538 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2539 * Otherwise, we simulate the EOI message manually by changing the trigger
2540 * mode to edge and then back to level, with RTE being masked during this.
2542 static void eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2544 struct irq_pin_list
*entry
;
2545 unsigned long flags
;
2547 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2548 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2549 if (mp_ioapics
[entry
->apic
].apicver
>= 0x20) {
2551 * Intr-remapping uses pin number as the virtual vector
2552 * in the RTE. Actual vector is programmed in
2553 * intr-remapping table entry. Hence for the io-apic
2554 * EOI we use the pin number.
2556 if (irq_remapped(irq
))
2557 io_apic_eoi(entry
->apic
, entry
->pin
);
2559 io_apic_eoi(entry
->apic
, cfg
->vector
);
2561 __mask_and_edge_IO_APIC_irq(entry
);
2562 __unmask_and_level_IO_APIC_irq(entry
);
2565 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2568 static void ack_apic_level(struct irq_data
*data
)
2570 struct irq_cfg
*cfg
= data
->chip_data
;
2571 int i
, do_unmask_irq
= 0, irq
= data
->irq
;
2572 struct irq_desc
*desc
= irq_to_desc(irq
);
2575 irq_complete_move(cfg
);
2576 #ifdef CONFIG_GENERIC_PENDING_IRQ
2577 /* If we are moving the irq we need to mask it */
2578 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2585 * It appears there is an erratum which affects at least version 0x11
2586 * of I/O APIC (that's the 82093AA and cores integrated into various
2587 * chipsets). Under certain conditions a level-triggered interrupt is
2588 * erroneously delivered as edge-triggered one but the respective IRR
2589 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2590 * message but it will never arrive and further interrupts are blocked
2591 * from the source. The exact reason is so far unknown, but the
2592 * phenomenon was observed when two consecutive interrupt requests
2593 * from a given source get delivered to the same CPU and the source is
2594 * temporarily disabled in between.
2596 * A workaround is to simulate an EOI message manually. We achieve it
2597 * by setting the trigger mode to edge and then to level when the edge
2598 * trigger mode gets detected in the TMR of a local APIC for a
2599 * level-triggered interrupt. We mask the source for the time of the
2600 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2601 * The idea is from Manfred Spraul. --macro
2603 * Also in the case when cpu goes offline, fixup_irqs() will forward
2604 * any unhandled interrupt on the offlined cpu to the new cpu
2605 * destination that is handling the corresponding interrupt. This
2606 * interrupt forwarding is done via IPI's. Hence, in this case also
2607 * level-triggered io-apic interrupt will be seen as an edge
2608 * interrupt in the IRR. And we can't rely on the cpu's EOI
2609 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2610 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2611 * supporting EOI register, we do an explicit EOI to clear the
2612 * remote IRR and on IO-APIC's which don't have an EOI register,
2613 * we use the above logic (mask+edge followed by unmask+level) from
2614 * Manfred Spraul to clear the remote IRR.
2617 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2620 * We must acknowledge the irq before we move it or the acknowledge will
2621 * not propagate properly.
2626 * Tail end of clearing remote IRR bit (either by delivering the EOI
2627 * message via io-apic EOI register write or simulating it using
2628 * mask+edge followed by unnask+level logic) manually when the
2629 * level triggered interrupt is seen as the edge triggered interrupt
2632 if (!(v
& (1 << (i
& 0x1f)))) {
2633 atomic_inc(&irq_mis_count
);
2635 eoi_ioapic_irq(irq
, cfg
);
2638 /* Now we can move and renable the irq */
2639 if (unlikely(do_unmask_irq
)) {
2640 /* Only migrate the irq if the ack has been received.
2642 * On rare occasions the broadcast level triggered ack gets
2643 * delayed going to ioapics, and if we reprogram the
2644 * vector while Remote IRR is still set the irq will never
2647 * To prevent this scenario we read the Remote IRR bit
2648 * of the ioapic. This has two effects.
2649 * - On any sane system the read of the ioapic will
2650 * flush writes (and acks) going to the ioapic from
2652 * - We get to see if the ACK has actually been delivered.
2654 * Based on failed experiments of reprogramming the
2655 * ioapic entry from outside of irq context starting
2656 * with masking the ioapic entry and then polling until
2657 * Remote IRR was clear before reprogramming the
2658 * ioapic I don't trust the Remote IRR bit to be
2659 * completey accurate.
2661 * However there appears to be no other way to plug
2662 * this race, so if the Remote IRR bit is not
2663 * accurate and is causing problems then it is a hardware bug
2664 * and you can go talk to the chipset vendor about it.
2666 if (!io_apic_level_ack_pending(cfg
))
2667 move_masked_irq(irq
);
2672 #ifdef CONFIG_INTR_REMAP
2673 static void ir_ack_apic_edge(struct irq_data
*data
)
2678 static void ir_ack_apic_level(struct irq_data
*data
)
2681 eoi_ioapic_irq(data
->irq
, data
->chip_data
);
2683 #endif /* CONFIG_INTR_REMAP */
2685 static struct irq_chip ioapic_chip __read_mostly
= {
2687 .irq_startup
= startup_ioapic_irq
,
2688 .irq_mask
= mask_ioapic_irq
,
2689 .irq_unmask
= unmask_ioapic_irq
,
2690 .irq_ack
= ack_apic_edge
,
2691 .irq_eoi
= ack_apic_level
,
2693 .set_affinity
= set_ioapic_affinity_irq
,
2695 .irq_retrigger
= ioapic_retrigger_irq
,
2698 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2699 .name
= "IR-IO-APIC",
2700 .irq_startup
= startup_ioapic_irq
,
2701 .irq_mask
= mask_ioapic_irq
,
2702 .irq_unmask
= unmask_ioapic_irq
,
2703 #ifdef CONFIG_INTR_REMAP
2704 .irq_ack
= ir_ack_apic_edge
,
2705 .irq_eoi
= ir_ack_apic_level
,
2707 .set_affinity
= set_ir_ioapic_affinity_irq
,
2710 .irq_retrigger
= ioapic_retrigger_irq
,
2713 static inline void init_IO_APIC_traps(void)
2716 struct irq_desc
*desc
;
2717 struct irq_cfg
*cfg
;
2720 * NOTE! The local APIC isn't very good at handling
2721 * multiple interrupts at the same interrupt level.
2722 * As the interrupt level is determined by taking the
2723 * vector number and shifting that right by 4, we
2724 * want to spread these out a bit so that they don't
2725 * all fall in the same interrupt level.
2727 * Also, we've got to be careful not to trash gate
2728 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2730 for_each_irq_desc(irq
, desc
) {
2731 cfg
= get_irq_desc_chip_data(desc
);
2732 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2734 * Hmm.. We don't have an entry for this,
2735 * so default to an old-fashioned 8259
2736 * interrupt if we can..
2738 if (irq
< legacy_pic
->nr_legacy_irqs
)
2739 legacy_pic
->make_irq(irq
);
2741 /* Strange. Oh, well.. */
2742 desc
->chip
= &no_irq_chip
;
2748 * The local APIC irq-chip implementation:
2751 static void mask_lapic_irq(struct irq_data
*data
)
2755 v
= apic_read(APIC_LVT0
);
2756 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2759 static void unmask_lapic_irq(struct irq_data
*data
)
2763 v
= apic_read(APIC_LVT0
);
2764 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2767 static void ack_lapic_irq(struct irq_data
*data
)
2772 static struct irq_chip lapic_chip __read_mostly
= {
2773 .name
= "local-APIC",
2774 .irq_mask
= mask_lapic_irq
,
2775 .irq_unmask
= unmask_lapic_irq
,
2776 .irq_ack
= ack_lapic_irq
,
2779 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2781 desc
->status
&= ~IRQ_LEVEL
;
2782 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2786 static void __init
setup_nmi(void)
2789 * Dirty trick to enable the NMI watchdog ...
2790 * We put the 8259A master into AEOI mode and
2791 * unmask on all local APICs LVT0 as NMI.
2793 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2794 * is from Maciej W. Rozycki - so we do not have to EOI from
2795 * the NMI handler or the timer interrupt.
2797 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2799 enable_NMI_through_LVT0();
2801 apic_printk(APIC_VERBOSE
, " done.\n");
2805 * This looks a bit hackish but it's about the only one way of sending
2806 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2807 * not support the ExtINT mode, unfortunately. We need to send these
2808 * cycles as some i82489DX-based boards have glue logic that keeps the
2809 * 8259A interrupt line asserted until INTA. --macro
2811 static inline void __init
unlock_ExtINT_logic(void)
2814 struct IO_APIC_route_entry entry0
, entry1
;
2815 unsigned char save_control
, save_freq_select
;
2817 pin
= find_isa_irq_pin(8, mp_INT
);
2822 apic
= find_isa_irq_apic(8, mp_INT
);
2828 entry0
= ioapic_read_entry(apic
, pin
);
2829 clear_IO_APIC_pin(apic
, pin
);
2831 memset(&entry1
, 0, sizeof(entry1
));
2833 entry1
.dest_mode
= 0; /* physical delivery */
2834 entry1
.mask
= 0; /* unmask IRQ now */
2835 entry1
.dest
= hard_smp_processor_id();
2836 entry1
.delivery_mode
= dest_ExtINT
;
2837 entry1
.polarity
= entry0
.polarity
;
2841 ioapic_write_entry(apic
, pin
, entry1
);
2843 save_control
= CMOS_READ(RTC_CONTROL
);
2844 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2845 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2847 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2852 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2856 CMOS_WRITE(save_control
, RTC_CONTROL
);
2857 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2858 clear_IO_APIC_pin(apic
, pin
);
2860 ioapic_write_entry(apic
, pin
, entry0
);
2863 static int disable_timer_pin_1 __initdata
;
2864 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2865 static int __init
disable_timer_pin_setup(char *arg
)
2867 disable_timer_pin_1
= 1;
2870 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2872 int timer_through_8259 __initdata
;
2875 * This code may look a bit paranoid, but it's supposed to cooperate with
2876 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2877 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2878 * fanatically on his truly buggy board.
2880 * FIXME: really need to revamp this for all platforms.
2882 static inline void __init
check_timer(void)
2884 struct irq_desc
*desc
= irq_to_desc(0);
2885 struct irq_cfg
*cfg
= get_irq_desc_chip_data(desc
);
2886 int node
= cpu_to_node(0);
2887 int apic1
, pin1
, apic2
, pin2
;
2888 unsigned long flags
;
2891 local_irq_save(flags
);
2894 * get/set the timer IRQ vector:
2896 legacy_pic
->mask(0);
2897 assign_irq_vector(0, cfg
, apic
->target_cpus());
2900 * As IRQ0 is to be enabled in the 8259A, the virtual
2901 * wire has to be disabled in the local APIC. Also
2902 * timer interrupts need to be acknowledged manually in
2903 * the 8259A for the i82489DX when using the NMI
2904 * watchdog as that APIC treats NMIs as level-triggered.
2905 * The AEOI mode will finish them in the 8259A
2908 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2909 legacy_pic
->init(1);
2910 #ifdef CONFIG_X86_32
2914 ver
= apic_read(APIC_LVR
);
2915 ver
= GET_APIC_VERSION(ver
);
2916 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2920 pin1
= find_isa_irq_pin(0, mp_INT
);
2921 apic1
= find_isa_irq_apic(0, mp_INT
);
2922 pin2
= ioapic_i8259
.pin
;
2923 apic2
= ioapic_i8259
.apic
;
2925 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2926 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2927 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2930 * Some BIOS writers are clueless and report the ExtINTA
2931 * I/O APIC input from the cascaded 8259A as the timer
2932 * interrupt input. So just in case, if only one pin
2933 * was found above, try it both directly and through the
2937 if (intr_remapping_enabled
)
2938 panic("BIOS bug: timer not connected to IO-APIC");
2942 } else if (pin2
== -1) {
2949 * Ok, does IRQ0 through the IOAPIC work?
2952 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2953 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2955 /* for edge trigger, setup_IO_APIC_irq already
2956 * leave it unmasked.
2957 * so only need to unmask if it is level-trigger
2958 * do we really have level trigger timer?
2961 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2962 if (idx
!= -1 && irq_trigger(idx
))
2965 if (timer_irq_works()) {
2966 if (nmi_watchdog
== NMI_IO_APIC
) {
2968 legacy_pic
->unmask(0);
2970 if (disable_timer_pin_1
> 0)
2971 clear_IO_APIC_pin(0, pin1
);
2974 if (intr_remapping_enabled
)
2975 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2976 local_irq_disable();
2977 clear_IO_APIC_pin(apic1
, pin1
);
2979 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2980 "8254 timer not connected to IO-APIC\n");
2982 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2983 "(IRQ0) through the 8259A ...\n");
2984 apic_printk(APIC_QUIET
, KERN_INFO
2985 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2987 * legacy devices should be connected to IO APIC #0
2989 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2990 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2991 legacy_pic
->unmask(0);
2992 if (timer_irq_works()) {
2993 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2994 timer_through_8259
= 1;
2995 if (nmi_watchdog
== NMI_IO_APIC
) {
2996 legacy_pic
->mask(0);
2998 legacy_pic
->unmask(0);
3003 * Cleanup, just in case ...
3005 local_irq_disable();
3006 legacy_pic
->mask(0);
3007 clear_IO_APIC_pin(apic2
, pin2
);
3008 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
3011 if (nmi_watchdog
== NMI_IO_APIC
) {
3012 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
3013 "through the IO-APIC - disabling NMI Watchdog!\n");
3014 nmi_watchdog
= NMI_NONE
;
3016 #ifdef CONFIG_X86_32
3020 apic_printk(APIC_QUIET
, KERN_INFO
3021 "...trying to set up timer as Virtual Wire IRQ...\n");
3023 lapic_register_intr(0, desc
);
3024 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
3025 legacy_pic
->unmask(0);
3027 if (timer_irq_works()) {
3028 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3031 local_irq_disable();
3032 legacy_pic
->mask(0);
3033 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
3034 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
3036 apic_printk(APIC_QUIET
, KERN_INFO
3037 "...trying to set up timer as ExtINT IRQ...\n");
3039 legacy_pic
->init(0);
3040 legacy_pic
->make_irq(0);
3041 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3043 unlock_ExtINT_logic();
3045 if (timer_irq_works()) {
3046 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3049 local_irq_disable();
3050 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3051 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3052 "report. Then try booting with the 'noapic' option.\n");
3054 local_irq_restore(flags
);
3058 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3059 * to devices. However there may be an I/O APIC pin available for
3060 * this interrupt regardless. The pin may be left unconnected, but
3061 * typically it will be reused as an ExtINT cascade interrupt for
3062 * the master 8259A. In the MPS case such a pin will normally be
3063 * reported as an ExtINT interrupt in the MP table. With ACPI
3064 * there is no provision for ExtINT interrupts, and in the absence
3065 * of an override it would be treated as an ordinary ISA I/O APIC
3066 * interrupt, that is edge-triggered and unmasked by default. We
3067 * used to do this, but it caused problems on some systems because
3068 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3069 * the same ExtINT cascade interrupt to drive the local APIC of the
3070 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3071 * the I/O APIC in all cases now. No actual device should request
3072 * it anyway. --macro
3074 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3076 void __init
setup_IO_APIC(void)
3080 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3082 io_apic_irqs
= legacy_pic
->nr_legacy_irqs
? ~PIC_IRQS
: ~0UL;
3084 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3086 * Set up IO-APIC IRQ routing.
3088 x86_init
.mpparse
.setup_ioapic_ids();
3091 setup_IO_APIC_irqs();
3092 init_IO_APIC_traps();
3093 if (legacy_pic
->nr_legacy_irqs
)
3098 * Called after all the initialization is done. If we didnt find any
3099 * APIC bugs then we can allow the modify fast path
3102 static int __init
io_apic_bug_finalize(void)
3104 if (sis_apic_bug
== -1)
3109 late_initcall(io_apic_bug_finalize
);
3111 struct sysfs_ioapic_data
{
3112 struct sys_device dev
;
3113 struct IO_APIC_route_entry entry
[0];
3115 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3117 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3119 struct IO_APIC_route_entry
*entry
;
3120 struct sysfs_ioapic_data
*data
;
3123 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3124 entry
= data
->entry
;
3125 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3126 *entry
= ioapic_read_entry(dev
->id
, i
);
3131 static int ioapic_resume(struct sys_device
*dev
)
3133 struct IO_APIC_route_entry
*entry
;
3134 struct sysfs_ioapic_data
*data
;
3135 unsigned long flags
;
3136 union IO_APIC_reg_00 reg_00
;
3139 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3140 entry
= data
->entry
;
3142 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3143 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3144 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
3145 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
3146 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3148 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3149 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3150 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3155 static struct sysdev_class ioapic_sysdev_class
= {
3157 .suspend
= ioapic_suspend
,
3158 .resume
= ioapic_resume
,
3161 static int __init
ioapic_init_sysfs(void)
3163 struct sys_device
* dev
;
3166 error
= sysdev_class_register(&ioapic_sysdev_class
);
3170 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3171 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3172 * sizeof(struct IO_APIC_route_entry
);
3173 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3174 if (!mp_ioapic_data
[i
]) {
3175 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3178 dev
= &mp_ioapic_data
[i
]->dev
;
3180 dev
->cls
= &ioapic_sysdev_class
;
3181 error
= sysdev_register(dev
);
3183 kfree(mp_ioapic_data
[i
]);
3184 mp_ioapic_data
[i
] = NULL
;
3185 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3193 device_initcall(ioapic_init_sysfs
);
3196 * Dynamic irq allocate and deallocation
3198 unsigned int create_irq_nr(unsigned int irq_want
, int node
)
3200 /* Allocate an unused irq */
3203 unsigned long flags
;
3204 struct irq_cfg
*cfg_new
= NULL
;
3205 struct irq_desc
*desc_new
= NULL
;
3208 if (irq_want
< nr_irqs_gsi
)
3209 irq_want
= nr_irqs_gsi
;
3211 raw_spin_lock_irqsave(&vector_lock
, flags
);
3212 for (new = irq_want
; new < nr_irqs
; new++) {
3213 desc_new
= irq_to_desc_alloc_node(new, node
);
3215 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3218 cfg_new
= get_irq_desc_chip_data(desc_new
);
3220 if (cfg_new
->vector
!= 0)
3223 desc_new
= move_irq_desc(desc_new
, node
);
3224 cfg_new
= get_irq_desc_chip_data(desc_new
);
3226 if (__assign_irq_vector(new, cfg_new
, apic
->target_cpus()) == 0)
3230 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3233 dynamic_irq_init_keep_chip_data(irq
);
3238 int create_irq(void)
3240 int node
= cpu_to_node(0);
3241 unsigned int irq_want
;
3244 irq_want
= nr_irqs_gsi
;
3245 irq
= create_irq_nr(irq_want
, node
);
3253 void destroy_irq(unsigned int irq
)
3255 unsigned long flags
;
3257 dynamic_irq_cleanup_keep_chip_data(irq
);
3260 raw_spin_lock_irqsave(&vector_lock
, flags
);
3261 __clear_irq_vector(irq
, get_irq_chip_data(irq
));
3262 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3266 * MSI message composition
3268 #ifdef CONFIG_PCI_MSI
3269 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
,
3270 struct msi_msg
*msg
, u8 hpet_id
)
3272 struct irq_cfg
*cfg
;
3280 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3284 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3286 if (irq_remapped(irq
)) {
3291 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3292 BUG_ON(ir_index
== -1);
3294 prepare_irte(&irte
, cfg
->vector
, dest
);
3296 /* Set source-id of interrupt request */
3298 set_msi_sid(&irte
, pdev
);
3300 set_hpet_sid(&irte
, hpet_id
);
3302 modify_irte(irq
, &irte
);
3304 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3305 msg
->data
= sub_handle
;
3306 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3308 MSI_ADDR_IR_INDEX1(ir_index
) |
3309 MSI_ADDR_IR_INDEX2(ir_index
);
3311 if (x2apic_enabled())
3312 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3313 MSI_ADDR_EXT_DEST_ID(dest
);
3315 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3319 ((apic
->irq_dest_mode
== 0) ?
3320 MSI_ADDR_DEST_MODE_PHYSICAL
:
3321 MSI_ADDR_DEST_MODE_LOGICAL
) |
3322 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3323 MSI_ADDR_REDIRECTION_CPU
:
3324 MSI_ADDR_REDIRECTION_LOWPRI
) |
3325 MSI_ADDR_DEST_ID(dest
);
3328 MSI_DATA_TRIGGER_EDGE
|
3329 MSI_DATA_LEVEL_ASSERT
|
3330 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3331 MSI_DATA_DELIVERY_FIXED
:
3332 MSI_DATA_DELIVERY_LOWPRI
) |
3333 MSI_DATA_VECTOR(cfg
->vector
);
3339 static int set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3341 struct irq_desc
*desc
= irq_to_desc(irq
);
3342 struct irq_cfg
*cfg
;
3346 if (set_desc_affinity(desc
, mask
, &dest
))
3349 cfg
= get_irq_desc_chip_data(desc
);
3351 __get_cached_msi_msg(desc
->irq_data
.msi_desc
, &msg
);
3353 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3354 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3355 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3356 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3358 __write_msi_msg(desc
->irq_data
.msi_desc
, &msg
);
3362 #ifdef CONFIG_INTR_REMAP
3364 * Migrate the MSI irq to another cpumask. This migration is
3365 * done in the process context using interrupt-remapping hardware.
3368 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3370 struct irq_desc
*desc
= irq_to_desc(irq
);
3371 struct irq_cfg
*cfg
= get_irq_desc_chip_data(desc
);
3375 if (get_irte(irq
, &irte
))
3378 if (set_desc_affinity(desc
, mask
, &dest
))
3381 irte
.vector
= cfg
->vector
;
3382 irte
.dest_id
= IRTE_DEST(dest
);
3385 * atomically update the IRTE with the new destination and vector.
3387 modify_irte(irq
, &irte
);
3390 * After this point, all the interrupts will start arriving
3391 * at the new destination. So, time to cleanup the previous
3392 * vector allocation.
3394 if (cfg
->move_in_progress
)
3395 send_cleanup_vector(cfg
);
3401 #endif /* CONFIG_SMP */
3404 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3405 * which implement the MSI or MSI-X Capability Structure.
3407 static struct irq_chip msi_chip
= {
3409 .irq_unmask
= unmask_msi_irq
,
3410 .irq_mask
= mask_msi_irq
,
3411 .irq_ack
= ack_apic_edge
,
3413 .set_affinity
= set_msi_irq_affinity
,
3415 .irq_retrigger
= ioapic_retrigger_irq
,
3418 static struct irq_chip msi_ir_chip
= {
3419 .name
= "IR-PCI-MSI",
3420 .irq_unmask
= unmask_msi_irq
,
3421 .irq_mask
= mask_msi_irq
,
3422 #ifdef CONFIG_INTR_REMAP
3423 .irq_ack
= ir_ack_apic_edge
,
3425 .set_affinity
= ir_set_msi_irq_affinity
,
3428 .irq_retrigger
= ioapic_retrigger_irq
,
3432 * Map the PCI dev to the corresponding remapping hardware unit
3433 * and allocate 'nvec' consecutive interrupt-remapping table entries
3436 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3438 struct intel_iommu
*iommu
;
3441 iommu
= map_dev_to_ir(dev
);
3444 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3448 index
= alloc_irte(iommu
, irq
, nvec
);
3451 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3458 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3463 ret
= msi_compose_msg(dev
, irq
, &msg
, -1);
3467 set_irq_msi(irq
, msidesc
);
3468 write_msi_msg(irq
, &msg
);
3470 if (irq_remapped(irq
)) {
3471 struct irq_desc
*desc
= irq_to_desc(irq
);
3473 * irq migration in process context
3475 desc
->status
|= IRQ_MOVE_PCNTXT
;
3476 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3478 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3480 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3485 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3488 int ret
, sub_handle
;
3489 struct msi_desc
*msidesc
;
3490 unsigned int irq_want
;
3491 struct intel_iommu
*iommu
= NULL
;
3495 /* x86 doesn't support multiple MSI yet */
3496 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3499 node
= dev_to_node(&dev
->dev
);
3500 irq_want
= nr_irqs_gsi
;
3502 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3503 irq
= create_irq_nr(irq_want
, node
);
3507 if (!intr_remapping_enabled
)
3512 * allocate the consecutive block of IRTE's
3515 index
= msi_alloc_irte(dev
, irq
, nvec
);
3521 iommu
= map_dev_to_ir(dev
);
3527 * setup the mapping between the irq and the IRTE
3528 * base index, the sub_handle pointing to the
3529 * appropriate interrupt remap table entry.
3531 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3534 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3546 void arch_teardown_msi_irq(unsigned int irq
)
3551 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3553 static int dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3555 struct irq_desc
*desc
= irq_to_desc(irq
);
3556 struct irq_cfg
*cfg
;
3560 if (set_desc_affinity(desc
, mask
, &dest
))
3563 cfg
= get_irq_desc_chip_data(desc
);
3565 dmar_msi_read(irq
, &msg
);
3567 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3568 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3569 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3570 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3572 dmar_msi_write(irq
, &msg
);
3577 #endif /* CONFIG_SMP */
3579 static struct irq_chip dmar_msi_type
= {
3581 .irq_unmask
= dmar_msi_unmask
,
3582 .irq_mask
= dmar_msi_mask
,
3583 .irq_ack
= ack_apic_edge
,
3585 .set_affinity
= dmar_msi_set_affinity
,
3587 .irq_retrigger
= ioapic_retrigger_irq
,
3590 int arch_setup_dmar_msi(unsigned int irq
)
3595 ret
= msi_compose_msg(NULL
, irq
, &msg
, -1);
3598 dmar_msi_write(irq
, &msg
);
3599 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3605 #ifdef CONFIG_HPET_TIMER
3608 static int hpet_msi_set_affinity(struct irq_data
*data
,
3609 const struct cpumask
*mask
, bool force
)
3611 struct irq_desc
*desc
= irq_to_desc(data
->irq
);
3612 struct irq_cfg
*cfg
= data
->chip_data
;
3616 if (set_desc_affinity(desc
, mask
, &dest
))
3619 hpet_msi_read(data
->handler_data
, &msg
);
3621 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3622 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3623 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3624 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3626 hpet_msi_write(data
->handler_data
, &msg
);
3631 #endif /* CONFIG_SMP */
3633 static struct irq_chip ir_hpet_msi_type
= {
3634 .name
= "IR-HPET_MSI",
3635 .irq_unmask
= hpet_msi_unmask
,
3636 .irq_mask
= hpet_msi_mask
,
3637 #ifdef CONFIG_INTR_REMAP
3638 .irq_ack
= ir_ack_apic_edge
,
3640 .set_affinity
= ir_set_msi_irq_affinity
,
3643 .irq_retrigger
= ioapic_retrigger_irq
,
3646 static struct irq_chip hpet_msi_type
= {
3648 .irq_unmask
= hpet_msi_unmask
,
3649 .irq_mask
= hpet_msi_mask
,
3650 .irq_ack
= ack_apic_edge
,
3652 .irq_set_affinity
= hpet_msi_set_affinity
,
3654 .irq_retrigger
= ioapic_retrigger_irq
,
3657 int arch_setup_hpet_msi(unsigned int irq
, unsigned int id
)
3662 if (intr_remapping_enabled
) {
3663 struct intel_iommu
*iommu
= map_hpet_to_ir(id
);
3669 index
= alloc_irte(iommu
, irq
, 1);
3674 ret
= msi_compose_msg(NULL
, irq
, &msg
, id
);
3678 hpet_msi_write(get_irq_data(irq
), &msg
);
3679 irq_set_status_flags(irq
,IRQ_MOVE_PCNTXT
);
3680 if (irq_remapped(irq
))
3681 set_irq_chip_and_handler_name(irq
, &ir_hpet_msi_type
,
3682 handle_edge_irq
, "edge");
3684 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
,
3685 handle_edge_irq
, "edge");
3691 #endif /* CONFIG_PCI_MSI */
3693 * Hypertransport interrupt support
3695 #ifdef CONFIG_HT_IRQ
3699 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3701 struct ht_irq_msg msg
;
3702 fetch_ht_irq_msg(irq
, &msg
);
3704 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3705 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3707 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3708 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3710 write_ht_irq_msg(irq
, &msg
);
3713 static int set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3715 struct irq_desc
*desc
= irq_to_desc(irq
);
3716 struct irq_cfg
*cfg
;
3719 if (set_desc_affinity(desc
, mask
, &dest
))
3722 cfg
= get_irq_desc_chip_data(desc
);
3724 target_ht_irq(irq
, dest
, cfg
->vector
);
3731 static struct irq_chip ht_irq_chip
= {
3733 .mask
= mask_ht_irq
,
3734 .unmask
= unmask_ht_irq
,
3735 .irq_ack
= ack_apic_edge
,
3737 .set_affinity
= set_ht_irq_affinity
,
3739 .irq_retrigger
= ioapic_retrigger_irq
,
3742 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3744 struct irq_cfg
*cfg
;
3751 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3753 struct ht_irq_msg msg
;
3756 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3757 apic
->target_cpus());
3759 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3763 HT_IRQ_LOW_DEST_ID(dest
) |
3764 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3765 ((apic
->irq_dest_mode
== 0) ?
3766 HT_IRQ_LOW_DM_PHYSICAL
:
3767 HT_IRQ_LOW_DM_LOGICAL
) |
3768 HT_IRQ_LOW_RQEOI_EDGE
|
3769 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3770 HT_IRQ_LOW_MT_FIXED
:
3771 HT_IRQ_LOW_MT_ARBITRATED
) |
3772 HT_IRQ_LOW_IRQ_MASKED
;
3774 write_ht_irq_msg(irq
, &msg
);
3776 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3777 handle_edge_irq
, "edge");
3779 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3783 #endif /* CONFIG_HT_IRQ */
3785 int __init
io_apic_get_redir_entries (int ioapic
)
3787 union IO_APIC_reg_01 reg_01
;
3788 unsigned long flags
;
3790 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3791 reg_01
.raw
= io_apic_read(ioapic
, 1);
3792 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3794 /* The register returns the maximum index redir index
3795 * supported, which is one less than the total number of redir
3798 return reg_01
.bits
.entries
+ 1;
3801 void __init
probe_nr_irqs_gsi(void)
3805 nr
= gsi_top
+ NR_IRQS_LEGACY
;
3806 if (nr
> nr_irqs_gsi
)
3809 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3812 #ifdef CONFIG_SPARSE_IRQ
3813 int __init
arch_probe_nr_irqs(void)
3817 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3818 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3820 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3821 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3823 * for MSI and HT dyn irq
3825 nr
+= nr_irqs_gsi
* 16;
3830 return NR_IRQS_LEGACY
;
3834 static int __io_apic_set_pci_routing(struct device
*dev
, int irq
,
3835 struct io_apic_irq_attr
*irq_attr
)
3837 struct irq_desc
*desc
;
3838 struct irq_cfg
*cfg
;
3841 int trigger
, polarity
;
3843 ioapic
= irq_attr
->ioapic
;
3844 if (!IO_APIC_IRQ(irq
)) {
3845 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3851 node
= dev_to_node(dev
);
3853 node
= cpu_to_node(0);
3855 desc
= irq_to_desc_alloc_node(irq
, node
);
3857 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3861 pin
= irq_attr
->ioapic_pin
;
3862 trigger
= irq_attr
->trigger
;
3863 polarity
= irq_attr
->polarity
;
3866 * IRQs < 16 are already in the irq_2_pin[] map
3868 if (irq
>= legacy_pic
->nr_legacy_irqs
) {
3869 cfg
= get_irq_desc_chip_data(desc
);
3870 if (add_pin_to_irq_node_nopanic(cfg
, node
, ioapic
, pin
)) {
3871 printk(KERN_INFO
"can not add pin %d for irq %d\n",
3877 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, trigger
, polarity
);
3882 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3883 struct io_apic_irq_attr
*irq_attr
)
3887 * Avoid pin reprogramming. PRTs typically include entries
3888 * with redundant pin->gsi mappings (but unique PCI devices);
3889 * we only program the IOAPIC on the first.
3891 ioapic
= irq_attr
->ioapic
;
3892 pin
= irq_attr
->ioapic_pin
;
3893 if (test_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
)) {
3894 pr_debug("Pin %d-%d already programmed\n",
3895 mp_ioapics
[ioapic
].apicid
, pin
);
3898 set_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
);
3900 return __io_apic_set_pci_routing(dev
, irq
, irq_attr
);
3903 u8 __init
io_apic_unique_id(u8 id
)
3905 #ifdef CONFIG_X86_32
3906 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
3907 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
3908 return io_apic_get_unique_id(nr_ioapics
, id
);
3913 DECLARE_BITMAP(used
, 256);
3915 bitmap_zero(used
, 256);
3916 for (i
= 0; i
< nr_ioapics
; i
++) {
3917 struct mpc_ioapic
*ia
= &mp_ioapics
[i
];
3918 __set_bit(ia
->apicid
, used
);
3920 if (!test_bit(id
, used
))
3922 return find_first_zero_bit(used
, 256);
3926 #ifdef CONFIG_X86_32
3927 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3929 union IO_APIC_reg_00 reg_00
;
3930 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3932 unsigned long flags
;
3936 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3937 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3938 * supports up to 16 on one shared APIC bus.
3940 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3941 * advantage of new APIC bus architecture.
3944 if (physids_empty(apic_id_map
))
3945 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &apic_id_map
);
3947 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3948 reg_00
.raw
= io_apic_read(ioapic
, 0);
3949 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3951 if (apic_id
>= get_physical_broadcast()) {
3952 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3953 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3954 apic_id
= reg_00
.bits
.ID
;
3958 * Every APIC in a system must have a unique ID or we get lots of nice
3959 * 'stuck on smp_invalidate_needed IPI wait' messages.
3961 if (apic
->check_apicid_used(&apic_id_map
, apic_id
)) {
3963 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3964 if (!apic
->check_apicid_used(&apic_id_map
, i
))
3968 if (i
== get_physical_broadcast())
3969 panic("Max apic_id exceeded!\n");
3971 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3972 "trying %d\n", ioapic
, apic_id
, i
);
3977 apic
->apicid_to_cpu_present(apic_id
, &tmp
);
3978 physids_or(apic_id_map
, apic_id_map
, tmp
);
3980 if (reg_00
.bits
.ID
!= apic_id
) {
3981 reg_00
.bits
.ID
= apic_id
;
3983 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3984 io_apic_write(ioapic
, 0, reg_00
.raw
);
3985 reg_00
.raw
= io_apic_read(ioapic
, 0);
3986 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3989 if (reg_00
.bits
.ID
!= apic_id
) {
3990 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3995 apic_printk(APIC_VERBOSE
, KERN_INFO
3996 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
4002 int __init
io_apic_get_version(int ioapic
)
4004 union IO_APIC_reg_01 reg_01
;
4005 unsigned long flags
;
4007 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
4008 reg_01
.raw
= io_apic_read(ioapic
, 1);
4009 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
4011 return reg_01
.bits
.version
;
4014 int acpi_get_override_irq(u32 gsi
, int *trigger
, int *polarity
)
4016 int ioapic
, pin
, idx
;
4018 if (skip_ioapic_setup
)
4021 ioapic
= mp_find_ioapic(gsi
);
4025 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
4029 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
4033 *trigger
= irq_trigger(idx
);
4034 *polarity
= irq_polarity(idx
);
4039 * This function currently is only a helper for the i386 smp boot process where
4040 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4041 * so mask in all cases should simply be apic->target_cpus()
4044 void __init
setup_ioapic_dest(void)
4046 int pin
, ioapic
, irq
, irq_entry
;
4047 struct irq_desc
*desc
;
4048 const struct cpumask
*mask
;
4050 if (skip_ioapic_setup
== 1)
4053 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++)
4054 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4055 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4056 if (irq_entry
== -1)
4058 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4060 if ((ioapic
> 0) && (irq
> 16))
4063 desc
= irq_to_desc(irq
);
4066 * Honour affinities which have been set in early boot
4069 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4070 mask
= desc
->affinity
;
4072 mask
= apic
->target_cpus();
4074 if (intr_remapping_enabled
)
4075 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4077 set_ioapic_affinity_irq_desc(desc
, mask
);
4083 #define IOAPIC_RESOURCE_NAME_SIZE 11
4085 static struct resource
*ioapic_resources
;
4087 static struct resource
* __init
ioapic_setup_resources(int nr_ioapics
)
4090 struct resource
*res
;
4094 if (nr_ioapics
<= 0)
4097 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4100 mem
= alloc_bootmem(n
);
4103 mem
+= sizeof(struct resource
) * nr_ioapics
;
4105 for (i
= 0; i
< nr_ioapics
; i
++) {
4107 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4108 snprintf(mem
, IOAPIC_RESOURCE_NAME_SIZE
, "IOAPIC %u", i
);
4109 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4112 ioapic_resources
= res
;
4117 void __init
ioapic_init_mappings(void)
4119 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4120 struct resource
*ioapic_res
;
4123 ioapic_res
= ioapic_setup_resources(nr_ioapics
);
4124 for (i
= 0; i
< nr_ioapics
; i
++) {
4125 if (smp_found_config
) {
4126 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
4127 #ifdef CONFIG_X86_32
4130 "WARNING: bogus zero IO-APIC "
4131 "address found in MPTABLE, "
4132 "disabling IO/APIC support!\n");
4133 smp_found_config
= 0;
4134 skip_ioapic_setup
= 1;
4135 goto fake_ioapic_page
;
4139 #ifdef CONFIG_X86_32
4142 ioapic_phys
= (unsigned long)alloc_bootmem_pages(PAGE_SIZE
);
4143 ioapic_phys
= __pa(ioapic_phys
);
4145 set_fixmap_nocache(idx
, ioapic_phys
);
4146 apic_printk(APIC_VERBOSE
, "mapped IOAPIC to %08lx (%08lx)\n",
4147 __fix_to_virt(idx
) + (ioapic_phys
& ~PAGE_MASK
),
4151 ioapic_res
->start
= ioapic_phys
;
4152 ioapic_res
->end
= ioapic_phys
+ IO_APIC_SLOT_SIZE
- 1;
4157 void __init
ioapic_insert_resources(void)
4160 struct resource
*r
= ioapic_resources
;
4165 "IO APIC resources couldn't be allocated.\n");
4169 for (i
= 0; i
< nr_ioapics
; i
++) {
4170 insert_resource(&iomem_resource
, r
);
4175 int mp_find_ioapic(u32 gsi
)
4179 /* Find the IOAPIC that manages this GSI. */
4180 for (i
= 0; i
< nr_ioapics
; i
++) {
4181 if ((gsi
>= mp_gsi_routing
[i
].gsi_base
)
4182 && (gsi
<= mp_gsi_routing
[i
].gsi_end
))
4186 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
4190 int mp_find_ioapic_pin(int ioapic
, u32 gsi
)
4192 if (WARN_ON(ioapic
== -1))
4194 if (WARN_ON(gsi
> mp_gsi_routing
[ioapic
].gsi_end
))
4197 return gsi
- mp_gsi_routing
[ioapic
].gsi_base
;
4200 static int bad_ioapic(unsigned long address
)
4202 if (nr_ioapics
>= MAX_IO_APICS
) {
4203 printk(KERN_WARNING
"WARING: Max # of I/O APICs (%d) exceeded "
4204 "(found %d), skipping\n", MAX_IO_APICS
, nr_ioapics
);
4208 printk(KERN_WARNING
"WARNING: Bogus (zero) I/O APIC address"
4209 " found in table, skipping!\n");
4215 void __init
mp_register_ioapic(int id
, u32 address
, u32 gsi_base
)
4220 if (bad_ioapic(address
))
4225 mp_ioapics
[idx
].type
= MP_IOAPIC
;
4226 mp_ioapics
[idx
].flags
= MPC_APIC_USABLE
;
4227 mp_ioapics
[idx
].apicaddr
= address
;
4229 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
4230 mp_ioapics
[idx
].apicid
= io_apic_unique_id(id
);
4231 mp_ioapics
[idx
].apicver
= io_apic_get_version(idx
);
4234 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4235 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4237 entries
= io_apic_get_redir_entries(idx
);
4238 mp_gsi_routing
[idx
].gsi_base
= gsi_base
;
4239 mp_gsi_routing
[idx
].gsi_end
= gsi_base
+ entries
- 1;
4242 * The number of IO-APIC IRQ registers (== #pins):
4244 nr_ioapic_registers
[idx
] = entries
;
4246 if (mp_gsi_routing
[idx
].gsi_end
>= gsi_top
)
4247 gsi_top
= mp_gsi_routing
[idx
].gsi_end
+ 1;
4249 printk(KERN_INFO
"IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4250 "GSI %d-%d\n", idx
, mp_ioapics
[idx
].apicid
,
4251 mp_ioapics
[idx
].apicver
, mp_ioapics
[idx
].apicaddr
,
4252 mp_gsi_routing
[idx
].gsi_base
, mp_gsi_routing
[idx
].gsi_end
);
4257 /* Enable IOAPIC early just for system timer */
4258 void __init
pre_init_apic_IRQ0(void)
4260 struct irq_cfg
*cfg
;
4261 struct irq_desc
*desc
;
4263 printk(KERN_INFO
"Early APIC setup for system timer0\n");
4265 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
4267 desc
= irq_to_desc_alloc_node(0, 0);
4272 add_pin_to_irq_node(cfg
, 0, 0, 0);
4273 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
4275 setup_IO_APIC_irq(0, 0, 0, desc
, 0, 0);