2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/bootmem.h>
23 #include <linux/ftrace.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/sysdev.h>
27 #include <linux/delay.h>
28 #include <linux/timex.h>
29 #include <linux/dmar.h>
30 #include <linux/init.h>
31 #include <linux/cpu.h>
32 #include <linux/dmi.h>
33 #include <linux/nmi.h>
34 #include <linux/smp.h>
37 #include <asm/pgalloc.h>
38 #include <asm/atomic.h>
39 #include <asm/mpspec.h>
40 #include <asm/i8253.h>
41 #include <asm/i8259.h>
42 #include <asm/proto.h>
51 unsigned int num_processors
;
53 unsigned disabled_cpus __cpuinitdata
;
55 /* Processor that is doing the boot up */
56 unsigned int boot_cpu_physical_apicid
= -1U;
59 * The highest APIC ID seen during enumeration.
61 * This determines the messaging protocol we can use: if all APIC IDs
62 * are in the 0 ... 7 range, then we can use logical addressing which
63 * has some performance advantages (better broadcasting).
65 * If there's an APIC ID above 8, we use physical addressing.
67 unsigned int max_physical_apicid
;
70 * Bitmask of physically existing CPUs:
72 physid_mask_t phys_cpu_present_map
;
75 * Map cpu index to physical APIC ID
77 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
78 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
84 * Knob to control our willingness to enable the local APIC.
88 static int force_enable_local_apic
;
90 * APIC command line parameters
92 static int __init
parse_lapic(char *arg
)
94 force_enable_local_apic
= 1;
97 early_param("lapic", parse_lapic
);
98 /* Local APIC was disabled by the BIOS and enabled by the kernel */
99 static int enabled_via_apicbase
;
102 * Handle interrupt mode configuration register (IMCR).
103 * This register controls whether the interrupt signals
104 * that reach the BSP come from the master PIC or from the
105 * local APIC. Before entering Symmetric I/O Mode, either
106 * the BIOS or the operating system must switch out of
107 * PIC Mode by changing the IMCR.
109 static inline imcr_pic_to_apic(void)
111 /* select IMCR register */
113 /* NMI and 8259 INTR go through APIC */
117 static inline imcr_apic_to_pic(void)
119 /* select IMCR register */
121 /* NMI and 8259 INTR go directly to BSP */
127 static int apic_calibrate_pmtmr __initdata
;
128 static __init
int setup_apicpmtimer(char *s
)
130 apic_calibrate_pmtmr
= 1;
134 __setup("apicpmtimer", setup_apicpmtimer
);
137 #ifdef CONFIG_X86_X2APIC
139 /* x2apic enabled before OS handover */
140 static int x2apic_preenabled
;
141 static int disable_x2apic
;
142 static __init
int setup_nox2apic(char *str
)
145 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
148 early_param("nox2apic", setup_nox2apic
);
151 unsigned long mp_lapic_addr
;
153 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
154 static int disable_apic_timer __cpuinitdata
;
155 /* Local APIC timer works in C2 */
156 int local_apic_timer_c2_ok
;
157 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
159 int first_system_vector
= 0xfe;
162 * Debug level, exported for io_apic.c
164 unsigned int apic_verbosity
;
168 /* Have we found an MP table */
169 int smp_found_config
;
171 static struct resource lapic_resource
= {
172 .name
= "Local APIC",
173 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
176 static unsigned int calibration_result
;
178 static int lapic_next_event(unsigned long delta
,
179 struct clock_event_device
*evt
);
180 static void lapic_timer_setup(enum clock_event_mode mode
,
181 struct clock_event_device
*evt
);
182 static void lapic_timer_broadcast(const struct cpumask
*mask
);
183 static void apic_pm_activate(void);
186 * The local apic timer can be used for any function which is CPU local.
188 static struct clock_event_device lapic_clockevent
= {
190 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
191 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
193 .set_mode
= lapic_timer_setup
,
194 .set_next_event
= lapic_next_event
,
195 .broadcast
= lapic_timer_broadcast
,
199 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
201 static unsigned long apic_phys
;
204 * Get the LAPIC version
206 static inline int lapic_get_version(void)
208 return GET_APIC_VERSION(apic_read(APIC_LVR
));
212 * Check, if the APIC is integrated or a separate chip
214 static inline int lapic_is_integrated(void)
219 return APIC_INTEGRATED(lapic_get_version());
224 * Check, whether this is a modern or a first generation APIC
226 static int modern_apic(void)
228 /* AMD systems use old APIC versions, so check the CPU */
229 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
230 boot_cpu_data
.x86
>= 0xf)
232 return lapic_get_version() >= 0x14;
235 void native_apic_wait_icr_idle(void)
237 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
241 u32
native_safe_apic_wait_icr_idle(void)
248 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
252 } while (timeout
++ < 1000);
257 void native_apic_icr_write(u32 low
, u32 id
)
259 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
260 apic_write(APIC_ICR
, low
);
263 u64
native_apic_icr_read(void)
267 icr2
= apic_read(APIC_ICR2
);
268 icr1
= apic_read(APIC_ICR
);
270 return icr1
| ((u64
)icr2
<< 32);
274 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
276 void __cpuinit
enable_NMI_through_LVT0(void)
280 /* unmask and set to NMI */
283 /* Level triggered for 82489DX (32bit mode) */
284 if (!lapic_is_integrated())
285 v
|= APIC_LVT_LEVEL_TRIGGER
;
287 apic_write(APIC_LVT0
, v
);
292 * get_physical_broadcast - Get number of physical broadcast IDs
294 int get_physical_broadcast(void)
296 return modern_apic() ? 0xff : 0xf;
301 * lapic_get_maxlvt - get the maximum number of local vector table entries
303 int lapic_get_maxlvt(void)
307 v
= apic_read(APIC_LVR
);
309 * - we always have APIC integrated on 64bit mode
310 * - 82489DXs do not report # of LVT entries
312 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
320 #define APIC_DIVISOR 16
323 * This function sets up the local APIC timer, with a timeout of
324 * 'clocks' APIC bus clock. During calibration we actually call
325 * this function twice on the boot CPU, once with a bogus timeout
326 * value, second time for real. The other (noncalibrating) CPUs
327 * call this function only once, with the real, calibrated value.
329 * We do reads before writes even if unnecessary, to get around the
330 * P5 APIC double write bug.
332 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
334 unsigned int lvtt_value
, tmp_value
;
336 lvtt_value
= LOCAL_TIMER_VECTOR
;
338 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
339 if (!lapic_is_integrated())
340 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
343 lvtt_value
|= APIC_LVT_MASKED
;
345 apic_write(APIC_LVTT
, lvtt_value
);
350 tmp_value
= apic_read(APIC_TDCR
);
351 apic_write(APIC_TDCR
,
352 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
356 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
360 * Setup extended LVT, AMD specific (K8, family 10h)
362 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
363 * MCE interrupts are supported. Thus MCE offset must be set to 0.
365 * If mask=1, the LVT entry does not generate interrupts while mask=0
366 * enables the vector. See also the BKDGs.
369 #define APIC_EILVT_LVTOFF_MCE 0
370 #define APIC_EILVT_LVTOFF_IBS 1
372 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
374 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
375 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
380 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
382 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
383 return APIC_EILVT_LVTOFF_MCE
;
386 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
388 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
389 return APIC_EILVT_LVTOFF_IBS
;
391 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
394 * Program the next event, relative to now
396 static int lapic_next_event(unsigned long delta
,
397 struct clock_event_device
*evt
)
399 apic_write(APIC_TMICT
, delta
);
404 * Setup the lapic timer in periodic or oneshot mode
406 static void lapic_timer_setup(enum clock_event_mode mode
,
407 struct clock_event_device
*evt
)
412 /* Lapic used as dummy for broadcast ? */
413 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
416 local_irq_save(flags
);
419 case CLOCK_EVT_MODE_PERIODIC
:
420 case CLOCK_EVT_MODE_ONESHOT
:
421 __setup_APIC_LVTT(calibration_result
,
422 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
424 case CLOCK_EVT_MODE_UNUSED
:
425 case CLOCK_EVT_MODE_SHUTDOWN
:
426 v
= apic_read(APIC_LVTT
);
427 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
428 apic_write(APIC_LVTT
, v
);
429 apic_write(APIC_TMICT
, 0xffffffff);
431 case CLOCK_EVT_MODE_RESUME
:
432 /* Nothing to do here */
436 local_irq_restore(flags
);
440 * Local APIC timer broadcast function
442 static void lapic_timer_broadcast(const struct cpumask
*mask
)
445 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
450 * Setup the local APIC timer for this CPU. Copy the initilized values
451 * of the boot CPU and register the clock event in the framework.
453 static void __cpuinit
setup_APIC_timer(void)
455 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
457 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
458 levt
->cpumask
= cpumask_of(smp_processor_id());
460 clockevents_register_device(levt
);
464 * In this functions we calibrate APIC bus clocks to the external timer.
466 * We want to do the calibration only once since we want to have local timer
467 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
470 * This was previously done by reading the PIT/HPET and waiting for a wrap
471 * around to find out, that a tick has elapsed. I have a box, where the PIT
472 * readout is broken, so it never gets out of the wait loop again. This was
473 * also reported by others.
475 * Monitoring the jiffies value is inaccurate and the clockevents
476 * infrastructure allows us to do a simple substitution of the interrupt
479 * The calibration routine also uses the pm_timer when possible, as the PIT
480 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
481 * back to normal later in the boot process).
484 #define LAPIC_CAL_LOOPS (HZ/10)
486 static __initdata
int lapic_cal_loops
= -1;
487 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
488 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
489 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
490 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
493 * Temporary interrupt handler.
495 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
497 unsigned long long tsc
= 0;
498 long tapic
= apic_read(APIC_TMCCT
);
499 unsigned long pm
= acpi_pm_read_early();
504 switch (lapic_cal_loops
++) {
506 lapic_cal_t1
= tapic
;
507 lapic_cal_tsc1
= tsc
;
509 lapic_cal_j1
= jiffies
;
512 case LAPIC_CAL_LOOPS
:
513 lapic_cal_t2
= tapic
;
514 lapic_cal_tsc2
= tsc
;
515 if (pm
< lapic_cal_pm1
)
516 pm
+= ACPI_PM_OVRRUN
;
518 lapic_cal_j2
= jiffies
;
524 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
526 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
527 const long pm_thresh
= pm_100ms
/ 100;
531 #ifndef CONFIG_X86_PM_TIMER
535 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
537 /* Check, if the PM timer is available */
541 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
543 if (deltapm
> (pm_100ms
- pm_thresh
) &&
544 deltapm
< (pm_100ms
+ pm_thresh
)) {
545 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
549 res
= (((u64
)deltapm
) * mult
) >> 22;
550 do_div(res
, 1000000);
551 pr_warning("APIC calibration not consistent "
552 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
554 /* Correct the lapic counter value */
555 res
= (((u64
)(*delta
)) * pm_100ms
);
556 do_div(res
, deltapm
);
557 pr_info("APIC delta adjusted to PM-Timer: "
558 "%lu (%ld)\n", (unsigned long)res
, *delta
);
561 /* Correct the tsc counter value */
563 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
564 do_div(res
, deltapm
);
565 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
566 "PM-Timer: %lu (%ld) \n",
567 (unsigned long)res
, *deltatsc
);
568 *deltatsc
= (long)res
;
574 static int __init
calibrate_APIC_clock(void)
576 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
577 void (*real_handler
)(struct clock_event_device
*dev
);
578 unsigned long deltaj
;
579 long delta
, deltatsc
;
580 int pm_referenced
= 0;
584 /* Replace the global interrupt handler */
585 real_handler
= global_clock_event
->event_handler
;
586 global_clock_event
->event_handler
= lapic_cal_handler
;
589 * Setup the APIC counter to maximum. There is no way the lapic
590 * can underflow in the 100ms detection time frame
592 __setup_APIC_LVTT(0xffffffff, 0, 0);
594 /* Let the interrupts run */
597 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
602 /* Restore the real event handler */
603 global_clock_event
->event_handler
= real_handler
;
605 /* Build delta t1-t2 as apic timer counts down */
606 delta
= lapic_cal_t1
- lapic_cal_t2
;
607 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
609 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
611 /* we trust the PM based calibration if possible */
612 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
615 /* Calculate the scaled math multiplication factor */
616 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
617 lapic_clockevent
.shift
);
618 lapic_clockevent
.max_delta_ns
=
619 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
620 lapic_clockevent
.min_delta_ns
=
621 clockevent_delta2ns(0xF, &lapic_clockevent
);
623 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
625 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
626 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
627 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
631 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
633 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
634 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
637 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
639 calibration_result
/ (1000000 / HZ
),
640 calibration_result
% (1000000 / HZ
));
643 * Do a sanity check on the APIC calibration result
645 if (calibration_result
< (1000000 / HZ
)) {
647 pr_warning("APIC frequency too slow, disabling apic timer\n");
651 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
654 * PM timer calibration failed or not turned on
655 * so lets try APIC timer based calibration
657 if (!pm_referenced
) {
658 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
661 * Setup the apic timer manually
663 levt
->event_handler
= lapic_cal_handler
;
664 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
665 lapic_cal_loops
= -1;
667 /* Let the interrupts run */
670 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
673 /* Stop the lapic timer */
674 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
677 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
678 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
680 /* Check, if the jiffies result is consistent */
681 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
682 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
684 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
688 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
689 pr_warning("APIC timer disabled due to verification failure\n");
697 * Setup the boot APIC
699 * Calibrate and verify the result.
701 void __init
setup_boot_APIC_clock(void)
704 * The local apic timer can be disabled via the kernel
705 * commandline or from the CPU detection code. Register the lapic
706 * timer as a dummy clock event source on SMP systems, so the
707 * broadcast mechanism is used. On UP systems simply ignore it.
709 if (disable_apic_timer
) {
710 pr_info("Disabling APIC timer\n");
711 /* No broadcast on UP ! */
712 if (num_possible_cpus() > 1) {
713 lapic_clockevent
.mult
= 1;
719 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
720 "calibrating APIC timer ...\n");
722 if (calibrate_APIC_clock()) {
723 /* No broadcast on UP ! */
724 if (num_possible_cpus() > 1)
730 * If nmi_watchdog is set to IO_APIC, we need the
731 * PIT/HPET going. Otherwise register lapic as a dummy
734 if (nmi_watchdog
!= NMI_IO_APIC
)
735 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
737 pr_warning("APIC timer registered as dummy,"
738 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
740 /* Setup the lapic or request the broadcast */
744 void __cpuinit
setup_secondary_APIC_clock(void)
750 * The guts of the apic timer interrupt
752 static void local_apic_timer_interrupt(void)
754 int cpu
= smp_processor_id();
755 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
758 * Normally we should not be here till LAPIC has been initialized but
759 * in some cases like kdump, its possible that there is a pending LAPIC
760 * timer interrupt from previous kernel's context and is delivered in
761 * new kernel the moment interrupts are enabled.
763 * Interrupts are enabled early and LAPIC is setup much later, hence
764 * its possible that when we get here evt->event_handler is NULL.
765 * Check for event_handler being NULL and discard the interrupt as
768 if (!evt
->event_handler
) {
769 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
771 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
776 * the NMI deadlock-detector uses this.
778 inc_irq_stat(apic_timer_irqs
);
780 evt
->event_handler(evt
);
784 * Local APIC timer interrupt. This is the most natural way for doing
785 * local interrupts, but local timer interrupts can be emulated by
786 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
788 * [ if a single-CPU system runs an SMP kernel then we call the local
789 * interrupt as well. Thus we cannot inline the local irq ... ]
791 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
793 struct pt_regs
*old_regs
= set_irq_regs(regs
);
796 * NOTE! We'd better ACK the irq immediately,
797 * because timer handling can be slow.
801 * update_process_times() expects us to have done irq_enter().
802 * Besides, if we don't timer interrupts ignore the global
803 * interrupt lock, which is the WrongThing (tm) to do.
807 local_apic_timer_interrupt();
810 set_irq_regs(old_regs
);
813 int setup_profiling_timer(unsigned int multiplier
)
819 * Local APIC start and shutdown
823 * clear_local_APIC - shutdown the local APIC
825 * This is called, when a CPU is disabled and before rebooting, so the state of
826 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
827 * leftovers during boot.
829 void clear_local_APIC(void)
834 /* APIC hasn't been mapped yet */
835 if (!x2apic
&& !apic_phys
)
838 maxlvt
= lapic_get_maxlvt();
840 * Masking an LVT entry can trigger a local APIC error
841 * if the vector is zero. Mask LVTERR first to prevent this.
844 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
845 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
848 * Careful: we have to set masks only first to deassert
849 * any level-triggered sources.
851 v
= apic_read(APIC_LVTT
);
852 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
853 v
= apic_read(APIC_LVT0
);
854 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
855 v
= apic_read(APIC_LVT1
);
856 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
858 v
= apic_read(APIC_LVTPC
);
859 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
862 /* lets not touch this if we didn't frob it */
863 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
865 v
= apic_read(APIC_LVTTHMR
);
866 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
869 #ifdef CONFIG_X86_MCE_INTEL
871 v
= apic_read(APIC_LVTCMCI
);
872 if (!(v
& APIC_LVT_MASKED
))
873 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
878 * Clean APIC state for other OSs:
880 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
881 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
882 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
884 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
886 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
888 /* Integrated APIC (!82489DX) ? */
889 if (lapic_is_integrated()) {
891 /* Clear ESR due to Pentium errata 3AP and 11AP */
892 apic_write(APIC_ESR
, 0);
898 * disable_local_APIC - clear and disable the local APIC
900 void disable_local_APIC(void)
904 /* APIC hasn't been mapped yet */
911 * Disable APIC (implies clearing of registers
914 value
= apic_read(APIC_SPIV
);
915 value
&= ~APIC_SPIV_APIC_ENABLED
;
916 apic_write(APIC_SPIV
, value
);
920 * When LAPIC was disabled by the BIOS and enabled by the kernel,
921 * restore the disabled state.
923 if (enabled_via_apicbase
) {
926 rdmsr(MSR_IA32_APICBASE
, l
, h
);
927 l
&= ~MSR_IA32_APICBASE_ENABLE
;
928 wrmsr(MSR_IA32_APICBASE
, l
, h
);
934 * If Linux enabled the LAPIC against the BIOS default disable it down before
935 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
936 * not power-off. Additionally clear all LVT entries before disable_local_APIC
937 * for the case where Linux didn't enable the LAPIC.
939 void lapic_shutdown(void)
946 local_irq_save(flags
);
949 if (!enabled_via_apicbase
)
953 disable_local_APIC();
956 local_irq_restore(flags
);
960 * This is to verify that we're looking at a real local APIC.
961 * Check these against your board if the CPUs aren't getting
962 * started for no apparent reason.
964 int __init
verify_local_APIC(void)
966 unsigned int reg0
, reg1
;
969 * The version register is read-only in a real APIC.
971 reg0
= apic_read(APIC_LVR
);
972 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
973 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
974 reg1
= apic_read(APIC_LVR
);
975 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
978 * The two version reads above should print the same
979 * numbers. If the second one is different, then we
980 * poke at a non-APIC.
986 * Check if the version looks reasonably.
988 reg1
= GET_APIC_VERSION(reg0
);
989 if (reg1
== 0x00 || reg1
== 0xff)
991 reg1
= lapic_get_maxlvt();
992 if (reg1
< 0x02 || reg1
== 0xff)
996 * The ID register is read/write in a real APIC.
998 reg0
= apic_read(APIC_ID
);
999 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1000 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1001 reg1
= apic_read(APIC_ID
);
1002 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1003 apic_write(APIC_ID
, reg0
);
1004 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1008 * The next two are just to see if we have sane values.
1009 * They're only really relevant if we're in Virtual Wire
1010 * compatibility mode, but most boxes are anymore.
1012 reg0
= apic_read(APIC_LVT0
);
1013 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1014 reg1
= apic_read(APIC_LVT1
);
1015 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1021 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1023 void __init
sync_Arb_IDs(void)
1026 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1029 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1035 apic_wait_icr_idle();
1037 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1038 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1039 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1043 * An initial setup of the virtual wire mode.
1045 void __init
init_bsp_APIC(void)
1050 * Don't do the setup now if we have a SMP BIOS as the
1051 * through-I/O-APIC virtual wire mode might be active.
1053 if (smp_found_config
|| !cpu_has_apic
)
1057 * Do not trust the local APIC being empty at bootup.
1064 value
= apic_read(APIC_SPIV
);
1065 value
&= ~APIC_VECTOR_MASK
;
1066 value
|= APIC_SPIV_APIC_ENABLED
;
1068 #ifdef CONFIG_X86_32
1069 /* This bit is reserved on P4/Xeon and should be cleared */
1070 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1071 (boot_cpu_data
.x86
== 15))
1072 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1075 value
|= APIC_SPIV_FOCUS_DISABLED
;
1076 value
|= SPURIOUS_APIC_VECTOR
;
1077 apic_write(APIC_SPIV
, value
);
1080 * Set up the virtual wire mode.
1082 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1083 value
= APIC_DM_NMI
;
1084 if (!lapic_is_integrated()) /* 82489DX */
1085 value
|= APIC_LVT_LEVEL_TRIGGER
;
1086 apic_write(APIC_LVT1
, value
);
1089 static void __cpuinit
lapic_setup_esr(void)
1091 unsigned int oldvalue
, value
, maxlvt
;
1093 if (!lapic_is_integrated()) {
1094 pr_info("No ESR for 82489DX.\n");
1098 if (apic
->disable_esr
) {
1100 * Something untraceable is creating bad interrupts on
1101 * secondary quads ... for the moment, just leave the
1102 * ESR disabled - we can't do anything useful with the
1103 * errors anyway - mbligh
1105 pr_info("Leaving ESR disabled.\n");
1109 maxlvt
= lapic_get_maxlvt();
1110 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1111 apic_write(APIC_ESR
, 0);
1112 oldvalue
= apic_read(APIC_ESR
);
1114 /* enables sending errors */
1115 value
= ERROR_APIC_VECTOR
;
1116 apic_write(APIC_LVTERR
, value
);
1119 * spec says clear errors after enabling vector.
1122 apic_write(APIC_ESR
, 0);
1123 value
= apic_read(APIC_ESR
);
1124 if (value
!= oldvalue
)
1125 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1126 "vector: 0x%08x after: 0x%08x\n",
1132 * setup_local_APIC - setup the local APIC
1134 void __cpuinit
setup_local_APIC(void)
1140 arch_disable_smp_support();
1144 #ifdef CONFIG_X86_32
1145 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1146 if (lapic_is_integrated() && apic
->disable_esr
) {
1147 apic_write(APIC_ESR
, 0);
1148 apic_write(APIC_ESR
, 0);
1149 apic_write(APIC_ESR
, 0);
1150 apic_write(APIC_ESR
, 0);
1157 * Double-check whether this APIC is really registered.
1158 * This is meaningless in clustered apic mode, so we skip it.
1160 if (!apic
->apic_id_registered())
1164 * Intel recommends to set DFR, LDR and TPR before enabling
1165 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1166 * document number 292116). So here it goes...
1168 apic
->init_apic_ldr();
1171 * Set Task Priority to 'accept all'. We never change this
1174 value
= apic_read(APIC_TASKPRI
);
1175 value
&= ~APIC_TPRI_MASK
;
1176 apic_write(APIC_TASKPRI
, value
);
1179 * After a crash, we no longer service the interrupts and a pending
1180 * interrupt from previous kernel might still have ISR bit set.
1182 * Most probably by now CPU has serviced that pending interrupt and
1183 * it might not have done the ack_APIC_irq() because it thought,
1184 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1185 * does not clear the ISR bit and cpu thinks it has already serivced
1186 * the interrupt. Hence a vector might get locked. It was noticed
1187 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1189 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1190 value
= apic_read(APIC_ISR
+ i
*0x10);
1191 for (j
= 31; j
>= 0; j
--) {
1198 * Now that we are all set up, enable the APIC
1200 value
= apic_read(APIC_SPIV
);
1201 value
&= ~APIC_VECTOR_MASK
;
1205 value
|= APIC_SPIV_APIC_ENABLED
;
1207 #ifdef CONFIG_X86_32
1209 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1210 * certain networking cards. If high frequency interrupts are
1211 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1212 * entry is masked/unmasked at a high rate as well then sooner or
1213 * later IOAPIC line gets 'stuck', no more interrupts are received
1214 * from the device. If focus CPU is disabled then the hang goes
1217 * [ This bug can be reproduced easily with a level-triggered
1218 * PCI Ne2000 networking cards and PII/PIII processors, dual
1222 * Actually disabling the focus CPU check just makes the hang less
1223 * frequent as it makes the interrupt distributon model be more
1224 * like LRU than MRU (the short-term load is more even across CPUs).
1225 * See also the comment in end_level_ioapic_irq(). --macro
1229 * - enable focus processor (bit==0)
1230 * - 64bit mode always use processor focus
1231 * so no need to set it
1233 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1237 * Set spurious IRQ vector
1239 value
|= SPURIOUS_APIC_VECTOR
;
1240 apic_write(APIC_SPIV
, value
);
1243 * Set up LVT0, LVT1:
1245 * set up through-local-APIC on the BP's LINT0. This is not
1246 * strictly necessary in pure symmetric-IO mode, but sometimes
1247 * we delegate interrupts to the 8259A.
1250 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1252 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1253 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1254 value
= APIC_DM_EXTINT
;
1255 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1256 smp_processor_id());
1258 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1259 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1260 smp_processor_id());
1262 apic_write(APIC_LVT0
, value
);
1265 * only the BP should see the LINT1 NMI signal, obviously.
1267 if (!smp_processor_id())
1268 value
= APIC_DM_NMI
;
1270 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1271 if (!lapic_is_integrated()) /* 82489DX */
1272 value
|= APIC_LVT_LEVEL_TRIGGER
;
1273 apic_write(APIC_LVT1
, value
);
1277 #ifdef CONFIG_X86_MCE_INTEL
1278 /* Recheck CMCI information after local APIC is up on CPU #0 */
1279 if (smp_processor_id() == 0)
1284 void __cpuinit
end_local_APIC_setup(void)
1288 #ifdef CONFIG_X86_32
1291 /* Disable the local apic timer */
1292 value
= apic_read(APIC_LVTT
);
1293 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1294 apic_write(APIC_LVTT
, value
);
1298 setup_apic_nmi_watchdog(NULL
);
1302 #ifdef CONFIG_X86_X2APIC
1303 void check_x2apic(void)
1305 if (x2apic_enabled()) {
1306 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1307 x2apic_preenabled
= x2apic
= 1;
1311 void enable_x2apic(void)
1318 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1319 if (!(msr
& X2APIC_ENABLE
)) {
1320 pr_info("Enabling x2apic\n");
1321 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1325 void __init
enable_IR_x2apic(void)
1327 #ifdef CONFIG_INTR_REMAP
1329 unsigned long flags
;
1330 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
1332 if (!cpu_has_x2apic
)
1335 if (!x2apic_preenabled
&& disable_x2apic
) {
1336 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1337 "because of nox2apic\n");
1341 if (x2apic_preenabled
&& disable_x2apic
)
1342 panic("Bios already enabled x2apic, can't enforce nox2apic");
1344 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1345 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1346 "because of skipping io-apic setup\n");
1350 ret
= dmar_table_init();
1352 pr_info("dmar_table_init() failed with %d:\n", ret
);
1354 if (x2apic_preenabled
)
1355 panic("x2apic enabled by bios. But IR enabling failed");
1357 pr_info("Not enabling x2apic,Intr-remapping\n");
1361 ioapic_entries
= alloc_ioapic_entries();
1362 if (!ioapic_entries
) {
1363 pr_info("Allocate ioapic_entries failed: %d\n", ret
);
1367 ret
= save_IO_APIC_setup(ioapic_entries
);
1369 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1373 local_irq_save(flags
);
1374 mask_IO_APIC_setup(ioapic_entries
);
1377 ret
= enable_intr_remapping(EIM_32BIT_APIC_ID
);
1379 if (ret
&& x2apic_preenabled
) {
1380 local_irq_restore(flags
);
1381 panic("x2apic enabled by bios. But IR enabling failed");
1395 * IR enabling failed
1397 restore_IO_APIC_setup(ioapic_entries
);
1399 reinit_intr_remapped_IO_APIC(x2apic_preenabled
, ioapic_entries
);
1402 local_irq_restore(flags
);
1406 if (!x2apic_preenabled
)
1407 pr_info("Enabled x2apic and interrupt-remapping\n");
1409 pr_info("Enabled Interrupt-remapping\n");
1411 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1413 free_ioapic_entries(ioapic_entries
);
1415 if (!cpu_has_x2apic
)
1418 if (x2apic_preenabled
)
1419 panic("x2apic enabled prior OS handover,"
1420 " enable CONFIG_INTR_REMAP");
1422 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1428 #endif /* CONFIG_X86_X2APIC */
1430 #ifdef CONFIG_X86_64
1432 * Detect and enable local APICs on non-SMP boards.
1433 * Original code written by Keir Fraser.
1434 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1435 * not correctly set up (usually the APIC timer won't work etc.)
1437 static int __init
detect_init_APIC(void)
1439 if (!cpu_has_apic
) {
1440 pr_info("No local APIC present\n");
1444 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1445 boot_cpu_physical_apicid
= 0;
1450 * Detect and initialize APIC
1452 static int __init
detect_init_APIC(void)
1456 /* Disabled by kernel option? */
1460 switch (boot_cpu_data
.x86_vendor
) {
1461 case X86_VENDOR_AMD
:
1462 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1463 (boot_cpu_data
.x86
>= 15))
1466 case X86_VENDOR_INTEL
:
1467 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1468 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1475 if (!cpu_has_apic
) {
1477 * Over-ride BIOS and try to enable the local APIC only if
1478 * "lapic" specified.
1480 if (!force_enable_local_apic
) {
1481 pr_info("Local APIC disabled by BIOS -- "
1482 "you can enable it with \"lapic\"\n");
1486 * Some BIOSes disable the local APIC in the APIC_BASE
1487 * MSR. This can only be done in software for Intel P6 or later
1488 * and AMD K7 (Model > 1) or later.
1490 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1491 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1492 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1493 l
&= ~MSR_IA32_APICBASE_BASE
;
1494 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1495 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1496 enabled_via_apicbase
= 1;
1500 * The APIC feature bit should now be enabled
1503 features
= cpuid_edx(1);
1504 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1505 pr_warning("Could not enable APIC!\n");
1508 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1509 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1511 /* The BIOS may have set up the APIC at some other address */
1512 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1513 if (l
& MSR_IA32_APICBASE_ENABLE
)
1514 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1516 pr_info("Found and enabled local APIC!\n");
1523 pr_info("No local APIC present or hardware disabled\n");
1528 #ifdef CONFIG_X86_64
1529 void __init
early_init_lapic_mapping(void)
1531 unsigned long phys_addr
;
1534 * If no local APIC can be found then go out
1535 * : it means there is no mpatable and MADT
1537 if (!smp_found_config
)
1540 phys_addr
= mp_lapic_addr
;
1542 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1543 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1544 APIC_BASE
, phys_addr
);
1547 * Fetch the APIC ID of the BSP in case we have a
1548 * default configuration (or the MP table is broken).
1550 boot_cpu_physical_apicid
= read_apic_id();
1555 * init_apic_mappings - initialize APIC mappings
1557 void __init
init_apic_mappings(void)
1560 boot_cpu_physical_apicid
= read_apic_id();
1565 * If no local APIC can be found then set up a fake all
1566 * zeroes page to simulate the local APIC and another
1567 * one for the IO-APIC.
1569 if (!smp_found_config
&& detect_init_APIC()) {
1570 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1571 apic_phys
= __pa(apic_phys
);
1573 apic_phys
= mp_lapic_addr
;
1575 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1576 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1577 APIC_BASE
, apic_phys
);
1580 * Fetch the APIC ID of the BSP in case we have a
1581 * default configuration (or the MP table is broken).
1583 if (boot_cpu_physical_apicid
== -1U)
1584 boot_cpu_physical_apicid
= read_apic_id();
1588 * This initializes the IO-APIC and APIC hardware if this is
1591 int apic_version
[MAX_APICS
];
1593 int __init
APIC_init_uniprocessor(void)
1596 pr_info("Apic disabled\n");
1599 #ifdef CONFIG_X86_64
1600 if (!cpu_has_apic
) {
1602 pr_info("Apic disabled by BIOS\n");
1606 if (!smp_found_config
&& !cpu_has_apic
)
1610 * Complain if the BIOS pretends there is one.
1612 if (!cpu_has_apic
&&
1613 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1614 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1615 boot_cpu_physical_apicid
);
1616 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1622 #ifdef CONFIG_X86_64
1623 default_setup_apic_routing();
1626 verify_local_APIC();
1629 #ifdef CONFIG_X86_64
1630 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1633 * Hack: In case of kdump, after a crash, kernel might be booting
1634 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1635 * might be zero if read from MP tables. Get it from LAPIC.
1637 # ifdef CONFIG_CRASH_DUMP
1638 boot_cpu_physical_apicid
= read_apic_id();
1641 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1644 #ifdef CONFIG_X86_IO_APIC
1646 * Now enable IO-APICs, actually call clear_IO_APIC
1647 * We need clear_IO_APIC before enabling error vector
1649 if (!skip_ioapic_setup
&& nr_ioapics
)
1653 end_local_APIC_setup();
1655 #ifdef CONFIG_X86_IO_APIC
1656 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1660 localise_nmi_watchdog();
1663 localise_nmi_watchdog();
1667 #ifdef CONFIG_X86_64
1668 check_nmi_watchdog();
1675 * Local APIC interrupts
1679 * This interrupt should _never_ happen with our APIC/SMP architecture
1681 void smp_spurious_interrupt(struct pt_regs
*regs
)
1688 * Check if this really is a spurious interrupt and ACK it
1689 * if it is a vectored one. Just in case...
1690 * Spurious interrupts should not be ACKed.
1692 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1693 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1696 inc_irq_stat(irq_spurious_count
);
1698 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1699 pr_info("spurious APIC interrupt on CPU#%d, "
1700 "should never happen.\n", smp_processor_id());
1705 * This interrupt should never happen with our APIC/SMP architecture
1707 void smp_error_interrupt(struct pt_regs
*regs
)
1713 /* First tickle the hardware, only then report what went on. -- REW */
1714 v
= apic_read(APIC_ESR
);
1715 apic_write(APIC_ESR
, 0);
1716 v1
= apic_read(APIC_ESR
);
1718 atomic_inc(&irq_err_count
);
1721 * Here is what the APIC error bits mean:
1723 * 1: Receive CS error
1724 * 2: Send accept error
1725 * 3: Receive accept error
1727 * 5: Send illegal vector
1728 * 6: Received illegal vector
1729 * 7: Illegal register address
1731 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1732 smp_processor_id(), v
, v1
);
1737 * connect_bsp_APIC - attach the APIC to the interrupt system
1739 void __init
connect_bsp_APIC(void)
1741 #ifdef CONFIG_X86_32
1744 * Do not trust the local APIC being empty at bootup.
1748 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1749 * local APIC to INT and NMI lines.
1751 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1752 "enabling APIC mode.\n");
1756 if (apic
->enable_apic_mode
)
1757 apic
->enable_apic_mode();
1761 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1762 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1764 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1767 void disconnect_bsp_APIC(int virt_wire_setup
)
1771 #ifdef CONFIG_X86_32
1774 * Put the board back into PIC mode (has an effect only on
1775 * certain older boards). Note that APIC interrupts, including
1776 * IPIs, won't work beyond this point! The only exception are
1779 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1780 "entering PIC mode.\n");
1786 /* Go back to Virtual Wire compatibility mode */
1788 /* For the spurious interrupt use vector F, and enable it */
1789 value
= apic_read(APIC_SPIV
);
1790 value
&= ~APIC_VECTOR_MASK
;
1791 value
|= APIC_SPIV_APIC_ENABLED
;
1793 apic_write(APIC_SPIV
, value
);
1795 if (!virt_wire_setup
) {
1797 * For LVT0 make it edge triggered, active high,
1798 * external and enabled
1800 value
= apic_read(APIC_LVT0
);
1801 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1802 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1803 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1804 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1805 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1806 apic_write(APIC_LVT0
, value
);
1809 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1813 * For LVT1 make it edge triggered, active high,
1816 value
= apic_read(APIC_LVT1
);
1817 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1818 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1819 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1820 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1821 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1822 apic_write(APIC_LVT1
, value
);
1825 void __cpuinit
generic_processor_info(int apicid
, int version
)
1832 if (version
== 0x0) {
1833 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1834 "fixing up to 0x10. (tell your hw vendor)\n",
1838 apic_version
[apicid
] = version
;
1840 if (num_processors
>= nr_cpu_ids
) {
1841 int max
= nr_cpu_ids
;
1842 int thiscpu
= max
+ disabled_cpus
;
1845 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1846 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1853 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1855 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1857 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1858 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1860 physid_set(apicid
, phys_cpu_present_map
);
1861 if (apicid
== boot_cpu_physical_apicid
) {
1863 * x86_bios_cpu_apicid is required to have processors listed
1864 * in same order as logical cpu numbers. Hence the first
1865 * entry is BSP, and so on.
1869 if (apicid
> max_physical_apicid
)
1870 max_physical_apicid
= apicid
;
1872 #ifdef CONFIG_X86_32
1874 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1875 * but we need to work other dependencies like SMP_SUSPEND etc
1876 * before this can be done without some confusion.
1877 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1878 * - Ashok Raj <ashok.raj@intel.com>
1880 if (max_physical_apicid
>= 8) {
1881 switch (boot_cpu_data
.x86_vendor
) {
1882 case X86_VENDOR_INTEL
:
1883 if (!APIC_XAPIC(version
)) {
1887 /* If P4 and above fall through */
1888 case X86_VENDOR_AMD
:
1894 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1895 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1896 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1899 set_cpu_possible(cpu
, true);
1900 set_cpu_present(cpu
, true);
1903 int hard_smp_processor_id(void)
1905 return read_apic_id();
1908 void default_init_apic_ldr(void)
1912 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1913 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1914 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1915 apic_write(APIC_LDR
, val
);
1918 #ifdef CONFIG_X86_32
1919 int default_apicid_to_node(int logical_apicid
)
1922 return apicid_2_node
[hard_smp_processor_id()];
1936 * 'active' is true if the local APIC was enabled by us and
1937 * not the BIOS; this signifies that we are also responsible
1938 * for disabling it before entering apm/acpi suspend
1941 /* r/w apic fields */
1942 unsigned int apic_id
;
1943 unsigned int apic_taskpri
;
1944 unsigned int apic_ldr
;
1945 unsigned int apic_dfr
;
1946 unsigned int apic_spiv
;
1947 unsigned int apic_lvtt
;
1948 unsigned int apic_lvtpc
;
1949 unsigned int apic_lvt0
;
1950 unsigned int apic_lvt1
;
1951 unsigned int apic_lvterr
;
1952 unsigned int apic_tmict
;
1953 unsigned int apic_tdcr
;
1954 unsigned int apic_thmr
;
1957 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1959 unsigned long flags
;
1962 if (!apic_pm_state
.active
)
1965 maxlvt
= lapic_get_maxlvt();
1967 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1968 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1969 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1970 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1971 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1972 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1974 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1975 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1976 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1977 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1978 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1979 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1980 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1982 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1985 local_irq_save(flags
);
1986 disable_local_APIC();
1987 #ifdef CONFIG_INTR_REMAP
1988 if (intr_remapping_enabled
)
1989 disable_intr_remapping();
1991 local_irq_restore(flags
);
1995 static int lapic_resume(struct sys_device
*dev
)
1998 unsigned long flags
;
2001 #ifdef CONFIG_INTR_REMAP
2003 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
2005 if (!apic_pm_state
.active
)
2008 local_irq_save(flags
);
2010 ioapic_entries
= alloc_ioapic_entries();
2011 if (!ioapic_entries
) {
2012 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2016 ret
= save_IO_APIC_setup(ioapic_entries
);
2018 WARN(1, "Saving IO-APIC state failed: %d\n", ret
);
2019 free_ioapic_entries(ioapic_entries
);
2023 mask_IO_APIC_setup(ioapic_entries
);
2028 if (!apic_pm_state
.active
)
2031 local_irq_save(flags
);
2038 * Make sure the APICBASE points to the right address
2040 * FIXME! This will be wrong if we ever support suspend on
2041 * SMP! We'll need to do this as part of the CPU restore!
2043 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2044 l
&= ~MSR_IA32_APICBASE_BASE
;
2045 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2046 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2049 maxlvt
= lapic_get_maxlvt();
2050 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2051 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2052 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2053 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2054 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2055 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2056 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2057 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2058 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2060 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2063 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2064 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2065 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2066 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2067 apic_write(APIC_ESR
, 0);
2068 apic_read(APIC_ESR
);
2069 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2070 apic_write(APIC_ESR
, 0);
2071 apic_read(APIC_ESR
);
2073 #ifdef CONFIG_INTR_REMAP
2074 if (intr_remapping_enabled
)
2075 reenable_intr_remapping(EIM_32BIT_APIC_ID
);
2079 restore_IO_APIC_setup(ioapic_entries
);
2080 free_ioapic_entries(ioapic_entries
);
2084 local_irq_restore(flags
);
2091 * This device has no shutdown method - fully functioning local APICs
2092 * are needed on every CPU up until machine_halt/restart/poweroff.
2095 static struct sysdev_class lapic_sysclass
= {
2097 .resume
= lapic_resume
,
2098 .suspend
= lapic_suspend
,
2101 static struct sys_device device_lapic
= {
2103 .cls
= &lapic_sysclass
,
2106 static void __cpuinit
apic_pm_activate(void)
2108 apic_pm_state
.active
= 1;
2111 static int __init
init_lapic_sysfs(void)
2117 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2119 error
= sysdev_class_register(&lapic_sysclass
);
2121 error
= sysdev_register(&device_lapic
);
2125 /* local apic needs to resume before other devices access its registers. */
2126 core_initcall(init_lapic_sysfs
);
2128 #else /* CONFIG_PM */
2130 static void apic_pm_activate(void) { }
2132 #endif /* CONFIG_PM */
2134 #ifdef CONFIG_X86_64
2136 * apic_is_clustered_box() -- Check if we can expect good TSC
2138 * Thus far, the major user of this is IBM's Summit2 series:
2140 * Clustered boxes may have unsynced TSC problems if they are
2141 * multi-chassis. Use available data to take a good guess.
2142 * If in doubt, go HPET.
2144 __cpuinit
int apic_is_clustered_box(void)
2146 int i
, clusters
, zeros
;
2148 u16
*bios_cpu_apicid
;
2149 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2152 * there is not this kind of box with AMD CPU yet.
2153 * Some AMD box with quadcore cpu and 8 sockets apicid
2154 * will be [4, 0x23] or [8, 0x27] could be thought to
2155 * vsmp box still need checking...
2157 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2160 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2161 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2163 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2164 /* are we being called early in kernel startup? */
2165 if (bios_cpu_apicid
) {
2166 id
= bios_cpu_apicid
[i
];
2167 } else if (i
< nr_cpu_ids
) {
2169 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2175 if (id
!= BAD_APICID
)
2176 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2179 /* Problem: Partially populated chassis may not have CPUs in some of
2180 * the APIC clusters they have been allocated. Only present CPUs have
2181 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2182 * Since clusters are allocated sequentially, count zeros only if
2183 * they are bounded by ones.
2187 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2188 if (test_bit(i
, clustermap
)) {
2189 clusters
+= 1 + zeros
;
2195 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2196 * not guaranteed to be synced between boards
2198 if (is_vsmp_box() && clusters
> 1)
2202 * If clusters > 2, then should be multi-chassis.
2203 * May have to revisit this when multi-core + hyperthreaded CPUs come
2204 * out, but AFAIK this will work even for them.
2206 return (clusters
> 2);
2211 * APIC command line parameters
2213 static int __init
setup_disableapic(char *arg
)
2216 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2219 early_param("disableapic", setup_disableapic
);
2221 /* same as disableapic, for compatibility */
2222 static int __init
setup_nolapic(char *arg
)
2224 return setup_disableapic(arg
);
2226 early_param("nolapic", setup_nolapic
);
2228 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2230 local_apic_timer_c2_ok
= 1;
2233 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2235 static int __init
parse_disable_apic_timer(char *arg
)
2237 disable_apic_timer
= 1;
2240 early_param("noapictimer", parse_disable_apic_timer
);
2242 static int __init
parse_nolapic_timer(char *arg
)
2244 disable_apic_timer
= 1;
2247 early_param("nolapic_timer", parse_nolapic_timer
);
2249 static int __init
apic_set_verbosity(char *arg
)
2252 #ifdef CONFIG_X86_64
2253 skip_ioapic_setup
= 0;
2259 if (strcmp("debug", arg
) == 0)
2260 apic_verbosity
= APIC_DEBUG
;
2261 else if (strcmp("verbose", arg
) == 0)
2262 apic_verbosity
= APIC_VERBOSE
;
2264 pr_warning("APIC Verbosity level %s not recognised"
2265 " use apic=verbose or apic=debug\n", arg
);
2271 early_param("apic", apic_set_verbosity
);
2273 static int __init
lapic_insert_resource(void)
2278 /* Put local APIC into the resource map. */
2279 lapic_resource
.start
= apic_phys
;
2280 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2281 insert_resource(&iomem_resource
, &lapic_resource
);
2287 * need call insert after e820_reserve_resources()
2288 * that is using request_resource
2290 late_initcall(lapic_insert_resource
);