2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
33 * definitions for the ACPI scanning code
35 #define IVRS_HEADER_LENGTH 48
37 #define ACPI_IVHD_TYPE 0x10
38 #define ACPI_IVMD_TYPE_ALL 0x20
39 #define ACPI_IVMD_TYPE 0x21
40 #define ACPI_IVMD_TYPE_RANGE 0x22
42 #define IVHD_DEV_ALL 0x01
43 #define IVHD_DEV_SELECT 0x02
44 #define IVHD_DEV_SELECT_RANGE_START 0x03
45 #define IVHD_DEV_RANGE_END 0x04
46 #define IVHD_DEV_ALIAS 0x42
47 #define IVHD_DEV_ALIAS_RANGE 0x43
48 #define IVHD_DEV_EXT_SELECT 0x46
49 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
51 #define IVHD_FLAG_HT_TUN_EN 0x00
52 #define IVHD_FLAG_PASSPW_EN 0x01
53 #define IVHD_FLAG_RESPASSPW_EN 0x02
54 #define IVHD_FLAG_ISOC_EN 0x03
56 #define IVMD_FLAG_EXCL_RANGE 0x08
57 #define IVMD_FLAG_UNITY_MAP 0x01
59 #define ACPI_DEVFLAG_INITPASS 0x01
60 #define ACPI_DEVFLAG_EXTINT 0x02
61 #define ACPI_DEVFLAG_NMI 0x04
62 #define ACPI_DEVFLAG_SYSMGT1 0x10
63 #define ACPI_DEVFLAG_SYSMGT2 0x20
64 #define ACPI_DEVFLAG_LINT0 0x40
65 #define ACPI_DEVFLAG_LINT1 0x80
66 #define ACPI_DEVFLAG_ATSDIS 0x10000000
69 * ACPI table definitions
71 * These data structures are laid over the table to parse the important values
76 * structure describing one IOMMU in the ACPI table. Typically followed by one
77 * or more ivhd_entrys.
89 } __attribute__((packed
));
92 * A device entry describing which devices a specific IOMMU translates and
93 * which requestor ids they use.
100 } __attribute__((packed
));
103 * An AMD IOMMU memory definition structure. It defines things like exclusion
104 * ranges for devices and regions that should be unity mapped.
115 } __attribute__((packed
));
117 static int __initdata amd_iommu_detected
;
119 u16 amd_iommu_last_bdf
; /* largest PCI device id we have
121 LIST_HEAD(amd_iommu_unity_map
); /* a list of required unity mappings
123 unsigned amd_iommu_aperture_order
= 26; /* size of aperture in power of 2 */
124 int amd_iommu_isolate
= 1; /* if 1, device isolation is enabled */
125 bool amd_iommu_unmap_flush
; /* if true, flush on every unmap */
127 LIST_HEAD(amd_iommu_list
); /* list of all AMD IOMMUs in the
131 * Pointer to the device table which is shared by all AMD IOMMUs
132 * it is indexed by the PCI device id or the HT unit id and contains
133 * information about the domain the device belongs to as well as the
134 * page table root pointer.
136 struct dev_table_entry
*amd_iommu_dev_table
;
139 * The alias table is a driver specific data structure which contains the
140 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
141 * More than one device can share the same requestor id.
143 u16
*amd_iommu_alias_table
;
146 * The rlookup table is used to find the IOMMU which is responsible
147 * for a specific device. It is also indexed by the PCI device id.
149 struct amd_iommu
**amd_iommu_rlookup_table
;
152 * The pd table (protection domain table) is used to find the protection domain
153 * data structure a device belongs to. Indexed with the PCI device id too.
155 struct protection_domain
**amd_iommu_pd_table
;
158 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
159 * to know which ones are already in use.
161 unsigned long *amd_iommu_pd_alloc_bitmap
;
163 static u32 dev_table_size
; /* size of the device table */
164 static u32 alias_table_size
; /* size of the alias table */
165 static u32 rlookup_table_size
; /* size if the rlookup table */
167 static inline void update_last_devid(u16 devid
)
169 if (devid
> amd_iommu_last_bdf
)
170 amd_iommu_last_bdf
= devid
;
173 static inline unsigned long tbl_size(int entry_size
)
175 unsigned shift
= PAGE_SHIFT
+
176 get_order(amd_iommu_last_bdf
* entry_size
);
181 /****************************************************************************
183 * AMD IOMMU MMIO register space handling functions
185 * These functions are used to program the IOMMU device registers in
186 * MMIO space required for that driver.
188 ****************************************************************************/
191 * This function set the exclusion range in the IOMMU. DMA accesses to the
192 * exclusion range are passed through untranslated
194 static void __init
iommu_set_exclusion_range(struct amd_iommu
*iommu
)
196 u64 start
= iommu
->exclusion_start
& PAGE_MASK
;
197 u64 limit
= (start
+ iommu
->exclusion_length
) & PAGE_MASK
;
200 if (!iommu
->exclusion_start
)
203 entry
= start
| MMIO_EXCL_ENABLE_MASK
;
204 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_BASE_OFFSET
,
205 &entry
, sizeof(entry
));
208 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_LIMIT_OFFSET
,
209 &entry
, sizeof(entry
));
212 /* Programs the physical address of the device table into the IOMMU hardware */
213 static void __init
iommu_set_device_table(struct amd_iommu
*iommu
)
217 BUG_ON(iommu
->mmio_base
== NULL
);
219 entry
= virt_to_phys(amd_iommu_dev_table
);
220 entry
|= (dev_table_size
>> 12) - 1;
221 memcpy_toio(iommu
->mmio_base
+ MMIO_DEV_TABLE_OFFSET
,
222 &entry
, sizeof(entry
));
225 /* Generic functions to enable/disable certain features of the IOMMU. */
226 static void __init
iommu_feature_enable(struct amd_iommu
*iommu
, u8 bit
)
230 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
232 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
235 static void __init
iommu_feature_disable(struct amd_iommu
*iommu
, u8 bit
)
239 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
241 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
244 /* Function to enable the hardware */
245 void __init
iommu_enable(struct amd_iommu
*iommu
)
247 printk(KERN_INFO
"AMD IOMMU: Enabling IOMMU "
248 "at %02x:%02x.%x cap 0x%hx\n",
249 iommu
->dev
->bus
->number
,
250 PCI_SLOT(iommu
->dev
->devfn
),
251 PCI_FUNC(iommu
->dev
->devfn
),
254 iommu_feature_enable(iommu
, CONTROL_IOMMU_EN
);
257 /* Function to enable IOMMU event logging and event interrupts */
258 void __init
iommu_enable_event_logging(struct amd_iommu
*iommu
)
260 iommu_feature_enable(iommu
, CONTROL_EVT_LOG_EN
);
261 iommu_feature_enable(iommu
, CONTROL_EVT_INT_EN
);
265 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
266 * the system has one.
268 static u8
* __init
iommu_map_mmio_space(u64 address
)
272 if (!request_mem_region(address
, MMIO_REGION_LENGTH
, "amd_iommu"))
275 ret
= ioremap_nocache(address
, MMIO_REGION_LENGTH
);
279 release_mem_region(address
, MMIO_REGION_LENGTH
);
284 static void __init
iommu_unmap_mmio_space(struct amd_iommu
*iommu
)
286 if (iommu
->mmio_base
)
287 iounmap(iommu
->mmio_base
);
288 release_mem_region(iommu
->mmio_phys
, MMIO_REGION_LENGTH
);
291 /****************************************************************************
293 * The functions below belong to the first pass of AMD IOMMU ACPI table
294 * parsing. In this pass we try to find out the highest device id this
295 * code has to handle. Upon this information the size of the shared data
296 * structures is determined later.
298 ****************************************************************************/
301 * This function calculates the length of a given IVHD entry
303 static inline int ivhd_entry_length(u8
*ivhd
)
305 return 0x04 << (*ivhd
>> 6);
309 * This function reads the last device id the IOMMU has to handle from the PCI
310 * capability header for this IOMMU
312 static int __init
find_last_devid_on_pci(int bus
, int dev
, int fn
, int cap_ptr
)
316 cap
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_RANGE_OFFSET
);
317 update_last_devid(calc_devid(MMIO_GET_BUS(cap
), MMIO_GET_LD(cap
)));
323 * After reading the highest device id from the IOMMU PCI capability header
324 * this function looks if there is a higher device id defined in the ACPI table
326 static int __init
find_last_devid_from_ivhd(struct ivhd_header
*h
)
328 u8
*p
= (void *)h
, *end
= (void *)h
;
329 struct ivhd_entry
*dev
;
334 find_last_devid_on_pci(PCI_BUS(h
->devid
),
340 dev
= (struct ivhd_entry
*)p
;
342 case IVHD_DEV_SELECT
:
343 case IVHD_DEV_RANGE_END
:
345 case IVHD_DEV_EXT_SELECT
:
346 /* all the above subfield types refer to device ids */
347 update_last_devid(dev
->devid
);
352 p
+= ivhd_entry_length(p
);
361 * Iterate over all IVHD entries in the ACPI table and find the highest device
362 * id which we need to handle. This is the first of three functions which parse
363 * the ACPI table. So we check the checksum here.
365 static int __init
find_last_devid_acpi(struct acpi_table_header
*table
)
368 u8 checksum
= 0, *p
= (u8
*)table
, *end
= (u8
*)table
;
369 struct ivhd_header
*h
;
372 * Validate checksum here so we don't need to do it when
373 * we actually parse the table
375 for (i
= 0; i
< table
->length
; ++i
)
378 /* ACPI table corrupt */
381 p
+= IVRS_HEADER_LENGTH
;
383 end
+= table
->length
;
385 h
= (struct ivhd_header
*)p
;
388 find_last_devid_from_ivhd(h
);
400 /****************************************************************************
402 * The following functions belong the the code path which parses the ACPI table
403 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
404 * data structures, initialize the device/alias/rlookup table and also
405 * basically initialize the hardware.
407 ****************************************************************************/
410 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
411 * write commands to that buffer later and the IOMMU will execute them
414 static u8
* __init
alloc_command_buffer(struct amd_iommu
*iommu
)
416 u8
*cmd_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
417 get_order(CMD_BUFFER_SIZE
));
423 iommu
->cmd_buf_size
= CMD_BUFFER_SIZE
;
425 entry
= (u64
)virt_to_phys(cmd_buf
);
426 entry
|= MMIO_CMD_SIZE_512
;
427 memcpy_toio(iommu
->mmio_base
+ MMIO_CMD_BUF_OFFSET
,
428 &entry
, sizeof(entry
));
430 /* set head and tail to zero manually */
431 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
432 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
434 iommu_feature_enable(iommu
, CONTROL_CMDBUF_EN
);
439 static void __init
free_command_buffer(struct amd_iommu
*iommu
)
441 free_pages((unsigned long)iommu
->cmd_buf
,
442 get_order(iommu
->cmd_buf_size
));
445 /* allocates the memory where the IOMMU will log its events to */
446 static u8
* __init
alloc_event_buffer(struct amd_iommu
*iommu
)
449 iommu
->evt_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
450 get_order(EVT_BUFFER_SIZE
));
452 if (iommu
->evt_buf
== NULL
)
455 entry
= (u64
)virt_to_phys(iommu
->evt_buf
) | EVT_LEN_MASK
;
456 memcpy_toio(iommu
->mmio_base
+ MMIO_EVT_BUF_OFFSET
,
457 &entry
, sizeof(entry
));
459 iommu
->evt_buf_size
= EVT_BUFFER_SIZE
;
461 return iommu
->evt_buf
;
464 static void __init
free_event_buffer(struct amd_iommu
*iommu
)
466 free_pages((unsigned long)iommu
->evt_buf
, get_order(EVT_BUFFER_SIZE
));
469 /* sets a specific bit in the device table entry. */
470 static void set_dev_entry_bit(u16 devid
, u8 bit
)
472 int i
= (bit
>> 5) & 0x07;
473 int _bit
= bit
& 0x1f;
475 amd_iommu_dev_table
[devid
].data
[i
] |= (1 << _bit
);
478 /* Writes the specific IOMMU for a device into the rlookup table */
479 static void __init
set_iommu_for_device(struct amd_iommu
*iommu
, u16 devid
)
481 amd_iommu_rlookup_table
[devid
] = iommu
;
485 * This function takes the device specific flags read from the ACPI
486 * table and sets up the device table entry with that information
488 static void __init
set_dev_entry_from_acpi(struct amd_iommu
*iommu
,
489 u16 devid
, u32 flags
, u32 ext_flags
)
491 if (flags
& ACPI_DEVFLAG_INITPASS
)
492 set_dev_entry_bit(devid
, DEV_ENTRY_INIT_PASS
);
493 if (flags
& ACPI_DEVFLAG_EXTINT
)
494 set_dev_entry_bit(devid
, DEV_ENTRY_EINT_PASS
);
495 if (flags
& ACPI_DEVFLAG_NMI
)
496 set_dev_entry_bit(devid
, DEV_ENTRY_NMI_PASS
);
497 if (flags
& ACPI_DEVFLAG_SYSMGT1
)
498 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
);
499 if (flags
& ACPI_DEVFLAG_SYSMGT2
)
500 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
);
501 if (flags
& ACPI_DEVFLAG_LINT0
)
502 set_dev_entry_bit(devid
, DEV_ENTRY_LINT0_PASS
);
503 if (flags
& ACPI_DEVFLAG_LINT1
)
504 set_dev_entry_bit(devid
, DEV_ENTRY_LINT1_PASS
);
506 set_iommu_for_device(iommu
, devid
);
510 * Reads the device exclusion range from ACPI and initialize IOMMU with
513 static void __init
set_device_exclusion_range(u16 devid
, struct ivmd_header
*m
)
515 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
517 if (!(m
->flags
& IVMD_FLAG_EXCL_RANGE
))
522 * We only can configure exclusion ranges per IOMMU, not
523 * per device. But we can enable the exclusion range per
524 * device. This is done here
526 set_dev_entry_bit(m
->devid
, DEV_ENTRY_EX
);
527 iommu
->exclusion_start
= m
->range_start
;
528 iommu
->exclusion_length
= m
->range_length
;
533 * This function reads some important data from the IOMMU PCI space and
534 * initializes the driver data structure with it. It reads the hardware
535 * capabilities and the first/last device entries
537 static void __init
init_iommu_from_pci(struct amd_iommu
*iommu
)
539 int cap_ptr
= iommu
->cap_ptr
;
542 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_CAP_HDR_OFFSET
,
544 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_RANGE_OFFSET
,
546 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_MISC_OFFSET
,
549 iommu
->first_device
= calc_devid(MMIO_GET_BUS(range
),
551 iommu
->last_device
= calc_devid(MMIO_GET_BUS(range
),
553 iommu
->evt_msi_num
= MMIO_MSI_NUM(misc
);
557 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
558 * initializes the hardware and our data structures with it.
560 static void __init
init_iommu_from_acpi(struct amd_iommu
*iommu
,
561 struct ivhd_header
*h
)
564 u8
*end
= p
, flags
= 0;
565 u16 dev_i
, devid
= 0, devid_start
= 0, devid_to
= 0;
568 struct ivhd_entry
*e
;
571 * First set the recommended feature enable bits from ACPI
572 * into the IOMMU control registers
574 h
->flags
& IVHD_FLAG_HT_TUN_EN
?
575 iommu_feature_enable(iommu
, CONTROL_HT_TUN_EN
) :
576 iommu_feature_disable(iommu
, CONTROL_HT_TUN_EN
);
578 h
->flags
& IVHD_FLAG_PASSPW_EN
?
579 iommu_feature_enable(iommu
, CONTROL_PASSPW_EN
) :
580 iommu_feature_disable(iommu
, CONTROL_PASSPW_EN
);
582 h
->flags
& IVHD_FLAG_RESPASSPW_EN
?
583 iommu_feature_enable(iommu
, CONTROL_RESPASSPW_EN
) :
584 iommu_feature_disable(iommu
, CONTROL_RESPASSPW_EN
);
586 h
->flags
& IVHD_FLAG_ISOC_EN
?
587 iommu_feature_enable(iommu
, CONTROL_ISOC_EN
) :
588 iommu_feature_disable(iommu
, CONTROL_ISOC_EN
);
591 * make IOMMU memory accesses cache coherent
593 iommu_feature_enable(iommu
, CONTROL_COHERENT_EN
);
596 * Done. Now parse the device entries
598 p
+= sizeof(struct ivhd_header
);
602 e
= (struct ivhd_entry
*)p
;
605 for (dev_i
= iommu
->first_device
;
606 dev_i
<= iommu
->last_device
; ++dev_i
)
607 set_dev_entry_from_acpi(iommu
, dev_i
,
610 case IVHD_DEV_SELECT
:
612 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
614 case IVHD_DEV_SELECT_RANGE_START
:
615 devid_start
= e
->devid
;
622 devid_to
= e
->ext
>> 8;
623 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
624 amd_iommu_alias_table
[devid
] = devid_to
;
626 case IVHD_DEV_ALIAS_RANGE
:
627 devid_start
= e
->devid
;
629 devid_to
= e
->ext
>> 8;
633 case IVHD_DEV_EXT_SELECT
:
635 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
,
638 case IVHD_DEV_EXT_SELECT_RANGE
:
639 devid_start
= e
->devid
;
644 case IVHD_DEV_RANGE_END
:
646 for (dev_i
= devid_start
; dev_i
<= devid
; ++dev_i
) {
648 amd_iommu_alias_table
[dev_i
] = devid_to
;
649 set_dev_entry_from_acpi(iommu
,
650 amd_iommu_alias_table
[dev_i
],
658 p
+= ivhd_entry_length(p
);
662 /* Initializes the device->iommu mapping for the driver */
663 static int __init
init_iommu_devices(struct amd_iommu
*iommu
)
667 for (i
= iommu
->first_device
; i
<= iommu
->last_device
; ++i
)
668 set_iommu_for_device(iommu
, i
);
673 static void __init
free_iommu_one(struct amd_iommu
*iommu
)
675 free_command_buffer(iommu
);
676 free_event_buffer(iommu
);
677 iommu_unmap_mmio_space(iommu
);
680 static void __init
free_iommu_all(void)
682 struct amd_iommu
*iommu
, *next
;
684 list_for_each_entry_safe(iommu
, next
, &amd_iommu_list
, list
) {
685 list_del(&iommu
->list
);
686 free_iommu_one(iommu
);
692 * This function clues the initialization function for one IOMMU
693 * together and also allocates the command buffer and programs the
694 * hardware. It does NOT enable the IOMMU. This is done afterwards.
696 static int __init
init_iommu_one(struct amd_iommu
*iommu
, struct ivhd_header
*h
)
698 spin_lock_init(&iommu
->lock
);
699 list_add_tail(&iommu
->list
, &amd_iommu_list
);
702 * Copy data from ACPI table entry to the iommu struct
704 iommu
->dev
= pci_get_bus_and_slot(PCI_BUS(h
->devid
), h
->devid
& 0xff);
708 iommu
->cap_ptr
= h
->cap_ptr
;
709 iommu
->pci_seg
= h
->pci_seg
;
710 iommu
->mmio_phys
= h
->mmio_phys
;
711 iommu
->mmio_base
= iommu_map_mmio_space(h
->mmio_phys
);
712 if (!iommu
->mmio_base
)
715 iommu_set_device_table(iommu
);
716 iommu
->cmd_buf
= alloc_command_buffer(iommu
);
720 iommu
->evt_buf
= alloc_event_buffer(iommu
);
724 iommu
->int_enabled
= false;
726 init_iommu_from_pci(iommu
);
727 init_iommu_from_acpi(iommu
, h
);
728 init_iommu_devices(iommu
);
730 return pci_enable_device(iommu
->dev
);
734 * Iterates over all IOMMU entries in the ACPI table, allocates the
735 * IOMMU structure and initializes it with init_iommu_one()
737 static int __init
init_iommu_all(struct acpi_table_header
*table
)
739 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
740 struct ivhd_header
*h
;
741 struct amd_iommu
*iommu
;
744 end
+= table
->length
;
745 p
+= IVRS_HEADER_LENGTH
;
748 h
= (struct ivhd_header
*)p
;
751 iommu
= kzalloc(sizeof(struct amd_iommu
), GFP_KERNEL
);
754 ret
= init_iommu_one(iommu
, h
);
769 /****************************************************************************
771 * The following functions initialize the MSI interrupts for all IOMMUs
772 * in the system. Its a bit challenging because there could be multiple
773 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
776 ****************************************************************************/
778 static int __init
iommu_setup_msix(struct amd_iommu
*iommu
)
780 struct amd_iommu
*curr
;
781 struct msix_entry entries
[32]; /* only 32 supported by AMD IOMMU */
784 list_for_each_entry(curr
, &amd_iommu_list
, list
) {
785 if (curr
->dev
== iommu
->dev
) {
786 entries
[nvec
].entry
= curr
->evt_msi_num
;
787 entries
[nvec
].vector
= 0;
788 curr
->int_enabled
= true;
793 if (pci_enable_msix(iommu
->dev
, entries
, nvec
)) {
794 pci_disable_msix(iommu
->dev
);
798 for (i
= 0; i
< nvec
; ++i
) {
799 int r
= request_irq(entries
->vector
, amd_iommu_int_handler
,
810 for (i
-= 1; i
>= 0; --i
)
811 free_irq(entries
->vector
, NULL
);
813 pci_disable_msix(iommu
->dev
);
818 static int __init
iommu_setup_msi(struct amd_iommu
*iommu
)
821 struct amd_iommu
*curr
;
823 list_for_each_entry(curr
, &amd_iommu_list
, list
) {
824 if (curr
->dev
== iommu
->dev
)
825 curr
->int_enabled
= true;
829 if (pci_enable_msi(iommu
->dev
))
832 r
= request_irq(iommu
->dev
->irq
, amd_iommu_int_handler
,
838 pci_disable_msi(iommu
->dev
);
845 static int __init
iommu_init_msi(struct amd_iommu
*iommu
)
847 if (iommu
->int_enabled
)
850 if (pci_find_capability(iommu
->dev
, PCI_CAP_ID_MSIX
))
851 return iommu_setup_msix(iommu
);
852 else if (pci_find_capability(iommu
->dev
, PCI_CAP_ID_MSI
))
853 return iommu_setup_msi(iommu
);
858 /****************************************************************************
860 * The next functions belong to the third pass of parsing the ACPI
861 * table. In this last pass the memory mapping requirements are
862 * gathered (like exclusion and unity mapping reanges).
864 ****************************************************************************/
866 static void __init
free_unity_maps(void)
868 struct unity_map_entry
*entry
, *next
;
870 list_for_each_entry_safe(entry
, next
, &amd_iommu_unity_map
, list
) {
871 list_del(&entry
->list
);
876 /* called when we find an exclusion range definition in ACPI */
877 static int __init
init_exclusion_range(struct ivmd_header
*m
)
883 set_device_exclusion_range(m
->devid
, m
);
885 case ACPI_IVMD_TYPE_ALL
:
886 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
887 set_device_exclusion_range(i
, m
);
889 case ACPI_IVMD_TYPE_RANGE
:
890 for (i
= m
->devid
; i
<= m
->aux
; ++i
)
891 set_device_exclusion_range(i
, m
);
900 /* called for unity map ACPI definition */
901 static int __init
init_unity_map_range(struct ivmd_header
*m
)
903 struct unity_map_entry
*e
= 0;
905 e
= kzalloc(sizeof(*e
), GFP_KERNEL
);
912 e
->devid_start
= e
->devid_end
= m
->devid
;
914 case ACPI_IVMD_TYPE_ALL
:
916 e
->devid_end
= amd_iommu_last_bdf
;
918 case ACPI_IVMD_TYPE_RANGE
:
919 e
->devid_start
= m
->devid
;
920 e
->devid_end
= m
->aux
;
923 e
->address_start
= PAGE_ALIGN(m
->range_start
);
924 e
->address_end
= e
->address_start
+ PAGE_ALIGN(m
->range_length
);
925 e
->prot
= m
->flags
>> 1;
927 list_add_tail(&e
->list
, &amd_iommu_unity_map
);
932 /* iterates over all memory definitions we find in the ACPI table */
933 static int __init
init_memory_definitions(struct acpi_table_header
*table
)
935 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
936 struct ivmd_header
*m
;
938 end
+= table
->length
;
939 p
+= IVRS_HEADER_LENGTH
;
942 m
= (struct ivmd_header
*)p
;
943 if (m
->flags
& IVMD_FLAG_EXCL_RANGE
)
944 init_exclusion_range(m
);
945 else if (m
->flags
& IVMD_FLAG_UNITY_MAP
)
946 init_unity_map_range(m
);
955 * Init the device table to not allow DMA access for devices and
956 * suppress all page faults
958 static void init_device_table(void)
962 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
) {
963 set_dev_entry_bit(devid
, DEV_ENTRY_VALID
);
964 set_dev_entry_bit(devid
, DEV_ENTRY_TRANSLATION
);
969 * This function finally enables all IOMMUs found in the system after
970 * they have been initialized
972 static void __init
enable_iommus(void)
974 struct amd_iommu
*iommu
;
976 list_for_each_entry(iommu
, &amd_iommu_list
, list
) {
977 iommu_set_exclusion_range(iommu
);
978 iommu_init_msi(iommu
);
979 iommu_enable_event_logging(iommu
);
985 * Suspend/Resume support
986 * disable suspend until real resume implemented
989 static int amd_iommu_resume(struct sys_device
*dev
)
994 static int amd_iommu_suspend(struct sys_device
*dev
, pm_message_t state
)
999 static struct sysdev_class amd_iommu_sysdev_class
= {
1000 .name
= "amd_iommu",
1001 .suspend
= amd_iommu_suspend
,
1002 .resume
= amd_iommu_resume
,
1005 static struct sys_device device_amd_iommu
= {
1007 .cls
= &amd_iommu_sysdev_class
,
1011 * This is the core init function for AMD IOMMU hardware in the system.
1012 * This function is called from the generic x86 DMA layer initialization
1015 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1018 * 1 pass) Find the highest PCI device id the driver has to handle.
1019 * Upon this information the size of the data structures is
1020 * determined that needs to be allocated.
1022 * 2 pass) Initialize the data structures just allocated with the
1023 * information in the ACPI table about available AMD IOMMUs
1024 * in the system. It also maps the PCI devices in the
1025 * system to specific IOMMUs
1027 * 3 pass) After the basic data structures are allocated and
1028 * initialized we update them with information about memory
1029 * remapping requirements parsed out of the ACPI table in
1032 * After that the hardware is initialized and ready to go. In the last
1033 * step we do some Linux specific things like registering the driver in
1034 * the dma_ops interface and initializing the suspend/resume support
1035 * functions. Finally it prints some information about AMD IOMMUs and
1036 * the driver state and enables the hardware.
1038 int __init
amd_iommu_init(void)
1044 printk(KERN_INFO
"AMD IOMMU disabled by kernel command line\n");
1048 if (!amd_iommu_detected
)
1052 * First parse ACPI tables to find the largest Bus/Dev/Func
1053 * we need to handle. Upon this information the shared data
1054 * structures for the IOMMUs in the system will be allocated
1056 if (acpi_table_parse("IVRS", find_last_devid_acpi
) != 0)
1059 dev_table_size
= tbl_size(DEV_TABLE_ENTRY_SIZE
);
1060 alias_table_size
= tbl_size(ALIAS_TABLE_ENTRY_SIZE
);
1061 rlookup_table_size
= tbl_size(RLOOKUP_TABLE_ENTRY_SIZE
);
1065 /* Device table - directly used by all IOMMUs */
1066 amd_iommu_dev_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
1067 get_order(dev_table_size
));
1068 if (amd_iommu_dev_table
== NULL
)
1072 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1073 * IOMMU see for that device
1075 amd_iommu_alias_table
= (void *)__get_free_pages(GFP_KERNEL
,
1076 get_order(alias_table_size
));
1077 if (amd_iommu_alias_table
== NULL
)
1080 /* IOMMU rlookup table - find the IOMMU for a specific device */
1081 amd_iommu_rlookup_table
= (void *)__get_free_pages(
1082 GFP_KERNEL
| __GFP_ZERO
,
1083 get_order(rlookup_table_size
));
1084 if (amd_iommu_rlookup_table
== NULL
)
1088 * Protection Domain table - maps devices to protection domains
1089 * This table has the same size as the rlookup_table
1091 amd_iommu_pd_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
1092 get_order(rlookup_table_size
));
1093 if (amd_iommu_pd_table
== NULL
)
1096 amd_iommu_pd_alloc_bitmap
= (void *)__get_free_pages(
1097 GFP_KERNEL
| __GFP_ZERO
,
1098 get_order(MAX_DOMAIN_ID
/8));
1099 if (amd_iommu_pd_alloc_bitmap
== NULL
)
1102 /* init the device table */
1103 init_device_table();
1106 * let all alias entries point to itself
1108 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
1109 amd_iommu_alias_table
[i
] = i
;
1112 * never allocate domain 0 because its used as the non-allocated and
1113 * error value placeholder
1115 amd_iommu_pd_alloc_bitmap
[0] = 1;
1118 * now the data structures are allocated and basically initialized
1119 * start the real acpi table scan
1122 if (acpi_table_parse("IVRS", init_iommu_all
) != 0)
1125 if (acpi_table_parse("IVRS", init_memory_definitions
) != 0)
1128 ret
= sysdev_class_register(&amd_iommu_sysdev_class
);
1132 ret
= sysdev_register(&device_amd_iommu
);
1136 ret
= amd_iommu_init_dma_ops();
1142 printk(KERN_INFO
"AMD IOMMU: aperture size is %d MB\n",
1143 (1 << (amd_iommu_aperture_order
-20)));
1145 printk(KERN_INFO
"AMD IOMMU: device isolation ");
1146 if (amd_iommu_isolate
)
1147 printk("enabled\n");
1149 printk("disabled\n");
1151 if (amd_iommu_unmap_flush
)
1152 printk(KERN_INFO
"AMD IOMMU: IO/TLB flush on unmap enabled\n");
1154 printk(KERN_INFO
"AMD IOMMU: Lazy IO/TLB flushing enabled\n");
1160 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap
,
1161 get_order(MAX_DOMAIN_ID
/8));
1163 free_pages((unsigned long)amd_iommu_pd_table
,
1164 get_order(rlookup_table_size
));
1166 free_pages((unsigned long)amd_iommu_rlookup_table
,
1167 get_order(rlookup_table_size
));
1169 free_pages((unsigned long)amd_iommu_alias_table
,
1170 get_order(alias_table_size
));
1172 free_pages((unsigned long)amd_iommu_dev_table
,
1173 get_order(dev_table_size
));
1182 /****************************************************************************
1184 * Early detect code. This code runs at IOMMU detection time in the DMA
1185 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1188 ****************************************************************************/
1189 static int __init
early_amd_iommu_detect(struct acpi_table_header
*table
)
1194 void __init
amd_iommu_detect(void)
1196 if (swiotlb
|| no_iommu
|| (iommu_detected
&& !gart_iommu_aperture
))
1199 if (acpi_table_parse("IVRS", early_amd_iommu_detect
) == 0) {
1201 amd_iommu_detected
= 1;
1202 #ifdef CONFIG_GART_IOMMU
1203 gart_iommu_aperture_disabled
= 1;
1204 gart_iommu_aperture
= 0;
1209 /****************************************************************************
1211 * Parsing functions for the AMD IOMMU specific kernel command line
1214 ****************************************************************************/
1216 static int __init
parse_amd_iommu_options(char *str
)
1218 for (; *str
; ++str
) {
1219 if (strncmp(str
, "isolate", 7) == 0)
1220 amd_iommu_isolate
= 1;
1221 if (strncmp(str
, "share", 5) == 0)
1222 amd_iommu_isolate
= 0;
1223 if (strncmp(str
, "fullflush", 9) == 0)
1224 amd_iommu_unmap_flush
= true;
1230 static int __init
parse_amd_iommu_size_options(char *str
)
1232 unsigned order
= PAGE_SHIFT
+ get_order(memparse(str
, &str
));
1234 if ((order
> 24) && (order
< 31))
1235 amd_iommu_aperture_order
= order
;
1240 __setup("amd_iommu=", parse_amd_iommu_options
);
1241 __setup("amd_iommu_size=", parse_amd_iommu_size_options
);