arch/x86/include/asm/uv/uv_hub.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV architectural definitions
   7  *
   8  * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #ifndef _ASM_X86_UV_UV_HUB_H
  12 #define _ASM_X86_UV_UV_HUB_H
  13
  14 #ifdef CONFIG_X86_64
  15 #include <linux/numa.h>
  16 #include <linux/percpu.h>
  17 #include <linux/timer.h>
  18 #include <linux/io.h>
  19 #include <asm/types.h>
  20 #include <asm/percpu.h>
  21 #include <asm/uv/uv_mmrs.h>
  22 #include <asm/irq_vectors.h>
  23 #include <asm/io_apic.h>
  24
  25
  26 /*
  27  * Addressing Terminology
  28  *
  29  *      M       - The low M bits of a physical address represent the offset
  30  *                into the blade local memory. RAM memory on a blade is physically
  31  *                contiguous (although various IO spaces may punch holes in
  32  *                it)..
  33  *
  34  *      N       - Number of bits in the node portion of a socket physical
  35  *                address.
  36  *
  37  *      NASID   - network ID of a router, Mbrick or Cbrick. Nasid values of
  38  *                routers always have low bit of 1, C/MBricks have low bit
  39  *                equal to 0. Most addressing macros that target UV hub chips
  40  *                right shift the NASID by 1 to exclude the always-zero bit.
  41  *                NASIDs contain up to 15 bits.
  42  *
  43  *      GNODE   - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
  44  *                of nasids.
  45  *
  46  *      PNODE   - the low N bits of the GNODE. The PNODE is the most useful variant
  47  *                of the nasid for socket usage.
  48  *
  49  *
  50  *  NumaLink Global Physical Address Format:
  51  *  +--------------------------------+---------------------+
  52  *  |00..000|      GNODE             |      NodeOffset     |
  53  *  +--------------------------------+---------------------+
  54  *          |<-------53 - M bits --->|<--------M bits ----->
  55  *
  56  *      M - number of node offset bits (35 .. 40)
  57  *
  58  *
  59  *  Memory/UV-HUB Processor Socket Address Format:
  60  *  +----------------+---------------+---------------------+
  61  *  |00..000000000000|   PNODE       |      NodeOffset     |
  62  *  +----------------+---------------+---------------------+
  63  *                   <--- N bits --->|<--------M bits ----->
  64  *
  65  *      M - number of node offset bits (35 .. 40)
  66  *      N - number of PNODE bits (0 .. 10)
  67  *
  68  *              Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
  69  *              The actual values are configuration dependent and are set at
  70  *              boot time. M & N values are set by the hardware/BIOS at boot.
  71  *
  72  *
  73  * APICID format
  74  *      NOTE!!!!!! This is the current format of the APICID. However, code
  75  *      should assume that this will change in the future. Use functions
  76  *      in this file for all APICID bit manipulations and conversion.
  77  *
  78  *              1111110000000000
  79  *              5432109876543210
  80  *              pppppppppplc0cch        Nehalem-EX
  81  *              ppppppppplcc0cch        Westmere-EX
  82  *              sssssssssss
  83  *
  84  *                      p  = pnode bits
  85  *                      l =  socket number on board
  86  *                      c  = core
  87  *                      h  = hyperthread
  88  *                      s  = bits that are in the SOCKET_ID CSR
  89  *
  90  *      Note: Processor only supports 12 bits in the APICID register. The ACPI
  91  *            tables hold all 16 bits. Software needs to be aware of this.
  92  *
  93  *            Unless otherwise specified, all references to APICID refer to
  94  *            the FULL value contained in ACPI tables, not the subset in the
  95  *            processor APICID register.
  96  */
  97
  98
  99 /*
 100  * Maximum number of bricks in all partitions and in all coherency domains.
 101  * This is the total number of bricks accessible in the numalink fabric. It
 102  * includes all C & M bricks. Routers are NOT included.
 103  *
 104  * This value is also the value of the maximum number of non-router NASIDs
 105  * in the numalink fabric.
 106  *
 107  * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
 108  */
 109 #define UV_MAX_NUMALINK_BLADES  16384
 110
 111 /*
 112  * Maximum number of C/Mbricks within a software SSI (hardware may support
 113  * more).
 114  */
 115 #define UV_MAX_SSI_BLADES       256
 116
 117 /*
 118  * The largest possible NASID of a C or M brick (+ 2)
 119  */
 120 #define UV_MAX_NASID_VALUE      (UV_MAX_NUMALINK_BLADES * 2)
 121
 122 struct uv_scir_s {
 123         struct timer_list timer;
 124         unsigned long   offset;
 125         unsigned long   last;
 126         unsigned long   idle_on;
 127         unsigned long   idle_off;
 128         unsigned char   state;
 129         unsigned char   enabled;
 130 };
 131
 132 /*
 133  * The following defines attributes of the HUB chip. These attributes are
 134  * frequently referenced and are kept in the per-cpu data areas of each cpu.
 135  * They are kept together in a struct to minimize cache misses.
 136  */
 137 struct uv_hub_info_s {
 138         unsigned long           global_mmr_base;
 139         unsigned long           gpa_mask;
 140         unsigned int            gnode_extra;
 141         unsigned long           gnode_upper;
 142         unsigned long           lowmem_remap_top;
 143         unsigned long           lowmem_remap_base;
 144         unsigned short          pnode;
 145         unsigned short          pnode_mask;
 146         unsigned short          coherency_domain_number;
 147         unsigned short          numa_blade_id;
 148         unsigned char           blade_processor_id;
 149         unsigned char           m_val;
 150         unsigned char           n_val;
 151         struct uv_scir_s        scir;
 152         unsigned char           apic_pnode_shift;
 153 };
 154
 155 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 156 #define uv_hub_info             (&__get_cpu_var(__uv_hub_info))
 157 #define uv_cpu_hub_info(cpu)    (&per_cpu(__uv_hub_info, cpu))
 158
 159 union uvh_apicid {
 160     unsigned long       v;
 161     struct uvh_apicid_s {
 162         unsigned long   local_apic_mask  : 24;
 163         unsigned long   local_apic_shift :  5;
 164         unsigned long   unused1          :  3;
 165         unsigned long   pnode_mask       : 24;
 166         unsigned long   pnode_shift      :  5;
 167         unsigned long   unused2          :  3;
 168     } s;
 169 };
 170
 171 /*
 172  * Local & Global MMR space macros.
 173  *      Note: macros are intended to be used ONLY by inline functions
 174  *      in this file - not by other kernel code.
 175  *              n -  NASID (full 15-bit global nasid)
 176  *              g -  GNODE (full 15-bit global nasid, right shifted 1)
 177  *              p -  PNODE (local part of nsids, right shifted 1)
 178  */
 179 #define UV_NASID_TO_PNODE(n)            (((n) >> 1) & uv_hub_info->pnode_mask)
 180 #define UV_PNODE_TO_GNODE(p)            ((p) |uv_hub_info->gnode_extra)
 181 #define UV_PNODE_TO_NASID(p)            (UV_PNODE_TO_GNODE(p) << 1)
 182
 183 #define UV_LOCAL_MMR_BASE               0xf4000000UL
 184 #define UV_GLOBAL_MMR32_BASE            0xf8000000UL
 185 #define UV_GLOBAL_MMR64_BASE            (uv_hub_info->global_mmr_base)
 186 #define UV_LOCAL_MMR_SIZE               (64UL * 1024 * 1024)
 187 #define UV_GLOBAL_MMR32_SIZE            (64UL * 1024 * 1024)
 188
 189 #define UV_GLOBAL_GRU_MMR_BASE          0x4000000
 190
 191 #define UV_GLOBAL_MMR32_PNODE_SHIFT     15
 192 #define UV_GLOBAL_MMR64_PNODE_SHIFT     26
 193
 194 #define UV_GLOBAL_MMR32_PNODE_BITS(p)   ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
 195
 196 #define UV_GLOBAL_MMR64_PNODE_BITS(p)                                   \
 197         (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
 198
 199 #define UVH_APICID              0x002D0E00L
 200 #define UV_APIC_PNODE_SHIFT     6
 201
 202 #define UV_APICID_HIBIT_MASK    0xffff0000
 203
 204 /* Local Bus from cpu's perspective */
 205 #define LOCAL_BUS_BASE          0x1c00000
 206 #define LOCAL_BUS_SIZE          (4 * 1024 * 1024)
 207
 208 /*
 209  * System Controller Interface Reg
 210  *
 211  * Note there are NO leds on a UV system.  This register is only
 212  * used by the system controller to monitor system-wide operation.
 213  * There are 64 regs per node.  With Nahelem cpus (2 cores per node,
 214  * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
 215  * a node.
 216  *
 217  * The window is located at top of ACPI MMR space
 218  */
 219 #define SCIR_WINDOW_COUNT       64
 220 #define SCIR_LOCAL_MMR_BASE     (LOCAL_BUS_BASE + \
 221                                  LOCAL_BUS_SIZE - \
 222                                  SCIR_WINDOW_COUNT)
 223
 224 #define SCIR_CPU_HEARTBEAT      0x01    /* timer interrupt */
 225 #define SCIR_CPU_ACTIVITY       0x02    /* not idle */
 226 #define SCIR_CPU_HB_INTERVAL    (HZ)    /* once per second */
 227
 228 /* Loop through all installed blades */
 229 #define for_each_possible_blade(bid)            \
 230         for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
 231
 232 /*
 233  * Macros for converting between kernel virtual addresses, socket local physical
 234  * addresses, and UV global physical addresses.
 235  *      Note: use the standard __pa() & __va() macros for converting
 236  *            between socket virtual and socket physical addresses.
 237  */
 238
 239 /* socket phys RAM --> UV global physical address */
 240 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
 241 {
 242         if (paddr < uv_hub_info->lowmem_remap_top)
 243                 paddr |= uv_hub_info->lowmem_remap_base;
 244         return paddr | uv_hub_info->gnode_upper;
 245 }
 246
 247
 248 /* socket virtual --> UV global physical address */
 249 static inline unsigned long uv_gpa(void *v)
 250 {
 251         return uv_soc_phys_ram_to_gpa(__pa(v));
 252 }
 253
 254 /* Top two bits indicate the requested address is in MMR space.  */
 255 static inline int
 256 uv_gpa_in_mmr_space(unsigned long gpa)
 257 {
 258         return (gpa >> 62) == 0x3UL;
 259 }
 260
 261 /* UV global physical address --> socket phys RAM */
 262 static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
 263 {
 264         unsigned long paddr = gpa & uv_hub_info->gpa_mask;
 265         unsigned long remap_base = uv_hub_info->lowmem_remap_base;
 266         unsigned long remap_top =  uv_hub_info->lowmem_remap_top;
 267
 268         if (paddr >= remap_base && paddr < remap_base + remap_top)
 269                 paddr -= remap_base;
 270         return paddr;
 271 }
 272
 273
 274 /* gnode -> pnode */
 275 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
 276 {
 277         return gpa >> uv_hub_info->m_val;
 278 }
 279
 280 /* gpa -> pnode */
 281 static inline int uv_gpa_to_pnode(unsigned long gpa)
 282 {
 283         unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1;
 284
 285         return uv_gpa_to_gnode(gpa) & n_mask;
 286 }
 287
 288 /* pnode, offset --> socket virtual */
 289 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
 290 {
 291         return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
 292 }
 293
 294
 295 /*
 296  * Extract a PNODE from an APICID (full apicid, not processor subset)
 297  */
 298 static inline int uv_apicid_to_pnode(int apicid)
 299 {
 300         return (apicid >> uv_hub_info->apic_pnode_shift);
 301 }
 302
 303 /*
 304  * Access global MMRs using the low memory MMR32 space. This region supports
 305  * faster MMR access but not all MMRs are accessible in this space.
 306  */
 307 static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset)
 308 {
 309         return __va(UV_GLOBAL_MMR32_BASE |
 310                        UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
 311 }
 312
 313 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val)
 314 {
 315         writeq(val, uv_global_mmr32_address(pnode, offset));
 316 }
 317
 318 static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset)
 319 {
 320         return readq(uv_global_mmr32_address(pnode, offset));
 321 }
 322
 323 /*
 324  * Access Global MMR space using the MMR space located at the top of physical
 325  * memory.
 326  */
 327 static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset)
 328 {
 329         return __va(UV_GLOBAL_MMR64_BASE |
 330                     UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
 331 }
 332
 333 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val)
 334 {
 335         writeq(val, uv_global_mmr64_address(pnode, offset));
 336 }
 337
 338 static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset)
 339 {
 340         return readq(uv_global_mmr64_address(pnode, offset));
 341 }
 342
 343 /*
 344  * Global MMR space addresses when referenced by the GRU. (GRU does
 345  * NOT use socket addressing).
 346  */
 347 static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset)
 348 {
 349         return UV_GLOBAL_GRU_MMR_BASE | offset |
 350                 ((unsigned long)pnode << uv_hub_info->m_val);
 351 }
 352
 353 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
 354 {
 355         writeb(val, uv_global_mmr64_address(pnode, offset));
 356 }
 357
 358 static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset)
 359 {
 360         return readb(uv_global_mmr64_address(pnode, offset));
 361 }
 362
 363 /*
 364  * Access hub local MMRs. Faster than using global space but only local MMRs
 365  * are accessible.
 366  */
 367 static inline unsigned long *uv_local_mmr_address(unsigned long offset)
 368 {
 369         return __va(UV_LOCAL_MMR_BASE | offset);
 370 }
 371
 372 static inline unsigned long uv_read_local_mmr(unsigned long offset)
 373 {
 374         return readq(uv_local_mmr_address(offset));
 375 }
 376
 377 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
 378 {
 379         writeq(val, uv_local_mmr_address(offset));
 380 }
 381
 382 static inline unsigned char uv_read_local_mmr8(unsigned long offset)
 383 {
 384         return readb(uv_local_mmr_address(offset));
 385 }
 386
 387 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
 388 {
 389         writeb(val, uv_local_mmr_address(offset));
 390 }
 391
 392 /*
 393  * Structures and definitions for converting between cpu, node, pnode, and blade
 394  * numbers.
 395  */
 396 struct uv_blade_info {
 397         unsigned short  nr_possible_cpus;
 398         unsigned short  nr_online_cpus;
 399         unsigned short  pnode;
 400         short           memory_nid;
 401 };
 402 extern struct uv_blade_info *uv_blade_info;
 403 extern short *uv_node_to_blade;
 404 extern short *uv_cpu_to_blade;
 405 extern short uv_possible_blades;
 406
 407 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
 408 static inline int uv_blade_processor_id(void)
 409 {
 410         return uv_hub_info->blade_processor_id;
 411 }
 412
 413 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
 414 static inline int uv_numa_blade_id(void)
 415 {
 416         return uv_hub_info->numa_blade_id;
 417 }
 418
 419 /* Convert a cpu number to the the UV blade number */
 420 static inline int uv_cpu_to_blade_id(int cpu)
 421 {
 422         return uv_cpu_to_blade[cpu];
 423 }
 424
 425 /* Convert linux node number to the UV blade number */
 426 static inline int uv_node_to_blade_id(int nid)
 427 {
 428         return uv_node_to_blade[nid];
 429 }
 430
 431 /* Convert a blade id to the PNODE of the blade */
 432 static inline int uv_blade_to_pnode(int bid)
 433 {
 434         return uv_blade_info[bid].pnode;
 435 }
 436
 437 /* Nid of memory node on blade. -1 if no blade-local memory */
 438 static inline int uv_blade_to_memory_nid(int bid)
 439 {
 440         return uv_blade_info[bid].memory_nid;
 441 }
 442
 443 /* Determine the number of possible cpus on a blade */
 444 static inline int uv_blade_nr_possible_cpus(int bid)
 445 {
 446         return uv_blade_info[bid].nr_possible_cpus;
 447 }
 448
 449 /* Determine the number of online cpus on a blade */
 450 static inline int uv_blade_nr_online_cpus(int bid)
 451 {
 452         return uv_blade_info[bid].nr_online_cpus;
 453 }
 454
 455 /* Convert a cpu id to the PNODE of the blade containing the cpu */
 456 static inline int uv_cpu_to_pnode(int cpu)
 457 {
 458         return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
 459 }
 460
 461 /* Convert a linux node number to the PNODE of the blade */
 462 static inline int uv_node_to_pnode(int nid)
 463 {
 464         return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
 465 }
 466
 467 /* Maximum possible number of blades */
 468 static inline int uv_num_possible_blades(void)
 469 {
 470         return uv_possible_blades;
 471 }
 472
 473 /* Update SCIR state */
 474 static inline void uv_set_scir_bits(unsigned char value)
 475 {
 476         if (uv_hub_info->scir.state != value) {
 477                 uv_hub_info->scir.state = value;
 478                 uv_write_local_mmr8(uv_hub_info->scir.offset, value);
 479         }
 480 }
 481
 482 static inline unsigned long uv_scir_offset(int apicid)
 483 {
 484         return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f);
 485 }
 486
 487 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
 488 {
 489         if (uv_cpu_hub_info(cpu)->scir.state != value) {
 490                 uv_write_global_mmr8(uv_cpu_to_pnode(cpu),
 491                                 uv_cpu_hub_info(cpu)->scir.offset, value);
 492                 uv_cpu_hub_info(cpu)->scir.state = value;
 493         }
 494 }
 495
 496 extern unsigned int uv_apicid_hibits;
 497 static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode)
 498 {
 499         apicid |= uv_apicid_hibits;
 500         return (1UL << UVH_IPI_INT_SEND_SHFT) |
 501                         ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
 502                         (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
 503                         (vector << UVH_IPI_INT_VECTOR_SHFT);
 504 }
 505
 506 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
 507 {
 508         unsigned long val;
 509         unsigned long dmode = dest_Fixed;
 510
 511         if (vector == NMI_VECTOR)
 512                 dmode = dest_NMI;
 513
 514         val = uv_hub_ipi_value(apicid, vector, dmode);
 515         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 516 }
 517
 518 /*
 519  * Get the minimum revision number of the hub chips within the partition.
 520  *     1 - initial rev 1.0 silicon
 521  *     2 - rev 2.0 production silicon
 522  */
 523 static inline int uv_get_min_hub_revision_id(void)
 524 {
 525         extern int uv_min_hub_revision_id;
 526
 527         return uv_min_hub_revision_id;
 528 }
 529
 530 #endif /* CONFIG_X86_64 */
 531 #endif /* _ASM_X86_UV_UV_HUB_H */