arch/x86/include/asm/apic.h

   1 #ifndef _ASM_X86_APIC_H
   2 #define _ASM_X86_APIC_H
   3
   4 #include <linux/cpumask.h>
   5 #include <linux/delay.h>
   6 #include <linux/pm.h>
   7
   8 #include <asm/alternative.h>
   9 #include <asm/cpufeature.h>
  10 #include <asm/processor.h>
  11 #include <asm/apicdef.h>
  12 #include <asm/atomic.h>
  13 #include <asm/fixmap.h>
  14 #include <asm/mpspec.h>
  15 #include <asm/system.h>
  16 #include <asm/msr.h>
  17
  18 #define ARCH_APICTIMER_STOPS_ON_C3      1
  19
  20 /*
  21  * Debugging macros
  22  */
  23 #define APIC_QUIET   0
  24 #define APIC_VERBOSE 1
  25 #define APIC_DEBUG   2
  26
  27 /*
  28  * Define the default level of output to be very little
  29  * This can be turned up by using apic=verbose for more
  30  * information and apic=debug for _lots_ of information.
  31  * apic_verbosity is defined in apic.c
  32  */
  33 #define apic_printk(v, s, a...) do {       \
  34                 if ((v) <= apic_verbosity) \
  35                         printk(s, ##a);    \
  36         } while (0)
  37
  38
  39 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
  40 extern void generic_apic_probe(void);
  41 #else
  42 static inline void generic_apic_probe(void)
  43 {
  44 }
  45 #endif
  46
  47 #ifdef CONFIG_X86_LOCAL_APIC
  48
  49 extern unsigned int apic_verbosity;
  50 extern int local_apic_timer_c2_ok;
  51
  52 extern int disable_apic;
  53
  54 #ifdef CONFIG_SMP
  55 extern void __inquire_remote_apic(int apicid);
  56 #else /* CONFIG_SMP */
  57 static inline void __inquire_remote_apic(int apicid)
  58 {
  59 }
  60 #endif /* CONFIG_SMP */
  61
  62 static inline void default_inquire_remote_apic(int apicid)
  63 {
  64         if (apic_verbosity >= APIC_DEBUG)
  65                 __inquire_remote_apic(apicid);
  66 }
  67
  68 /*
  69  * Basic functions accessing APICs.
  70  */
  71 #ifdef CONFIG_PARAVIRT
  72 #include <asm/paravirt.h>
  73 #else
  74 #define setup_boot_clock setup_boot_APIC_clock
  75 #define setup_secondary_clock setup_secondary_APIC_clock
  76 #endif
  77
  78 #ifdef CONFIG_X86_VSMP
  79 extern int is_vsmp_box(void);
  80 #else
  81 static inline int is_vsmp_box(void)
  82 {
  83         return 0;
  84 }
  85 #endif
  86 extern void xapic_wait_icr_idle(void);
  87 extern u32 safe_xapic_wait_icr_idle(void);
  88 extern void xapic_icr_write(u32, u32);
  89 extern int setup_profiling_timer(unsigned int);
  90
  91 static inline void native_apic_mem_write(u32 reg, u32 v)
  92 {
  93         volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
  94
  95         alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
  96                        ASM_OUTPUT2("=r" (v), "=m" (*addr)),
  97                        ASM_OUTPUT2("0" (v), "m" (*addr)));
  98 }
  99
 100 static inline u32 native_apic_mem_read(u32 reg)
 101 {
 102         return *((volatile u32 *)(APIC_BASE + reg));
 103 }
 104
 105 extern void native_apic_wait_icr_idle(void);
 106 extern u32 native_safe_apic_wait_icr_idle(void);
 107 extern void native_apic_icr_write(u32 low, u32 id);
 108 extern u64 native_apic_icr_read(void);
 109
 110 #ifdef CONFIG_X86_X2APIC
 111 static inline void native_apic_msr_write(u32 reg, u32 v)
 112 {
 113         if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
 114             reg == APIC_LVR)
 115                 return;
 116
 117         wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
 118 }
 119
 120 static inline u32 native_apic_msr_read(u32 reg)
 121 {
 122         u32 low, high;
 123
 124         if (reg == APIC_DFR)
 125                 return -1;
 126
 127         rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
 128         return low;
 129 }
 130
 131 static inline void native_x2apic_wait_icr_idle(void)
 132 {
 133         /* no need to wait for icr idle in x2apic */
 134         return;
 135 }
 136
 137 static inline u32 native_safe_x2apic_wait_icr_idle(void)
 138 {
 139         /* no need to wait for icr idle in x2apic */
 140         return 0;
 141 }
 142
 143 static inline void native_x2apic_icr_write(u32 low, u32 id)
 144 {
 145         wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
 146 }
 147
 148 static inline u64 native_x2apic_icr_read(void)
 149 {
 150         unsigned long val;
 151
 152         rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
 153         return val;
 154 }
 155
 156 extern int x2apic, x2apic_phys;
 157 extern void check_x2apic(void);
 158 extern void enable_x2apic(void);
 159 extern void enable_IR_x2apic(void);
 160 extern void x2apic_icr_write(u32 low, u32 id);
 161 static inline int x2apic_enabled(void)
 162 {
 163         int msr, msr2;
 164
 165         if (!cpu_has_x2apic)
 166                 return 0;
 167
 168         rdmsr(MSR_IA32_APICBASE, msr, msr2);
 169         if (msr & X2APIC_ENABLE)
 170                 return 1;
 171         return 0;
 172 }
 173 #else
 174 static inline void check_x2apic(void)
 175 {
 176 }
 177 static inline void enable_x2apic(void)
 178 {
 179 }
 180 static inline void enable_IR_x2apic(void)
 181 {
 182 }
 183 static inline int x2apic_enabled(void)
 184 {
 185         return 0;
 186 }
 187 #endif
 188
 189 extern int get_physical_broadcast(void);
 190
 191 #ifdef CONFIG_X86_X2APIC
 192 static inline void ack_x2APIC_irq(void)
 193 {
 194         /* Docs say use 0 for future compatibility */
 195         native_apic_msr_write(APIC_EOI, 0);
 196 }
 197 #endif
 198
 199 extern int lapic_get_maxlvt(void);
 200 extern void clear_local_APIC(void);
 201 extern void connect_bsp_APIC(void);
 202 extern void disconnect_bsp_APIC(int virt_wire_setup);
 203 extern void disable_local_APIC(void);
 204 extern void lapic_shutdown(void);
 205 extern int verify_local_APIC(void);
 206 extern void cache_APIC_registers(void);
 207 extern void sync_Arb_IDs(void);
 208 extern void init_bsp_APIC(void);
 209 extern void setup_local_APIC(void);
 210 extern void end_local_APIC_setup(void);
 211 extern void init_apic_mappings(void);
 212 extern void setup_boot_APIC_clock(void);
 213 extern void setup_secondary_APIC_clock(void);
 214 extern int APIC_init_uniprocessor(void);
 215 extern void enable_NMI_through_LVT0(void);
 216
 217 /*
 218  * On 32bit this is mach-xxx local
 219  */
 220 #ifdef CONFIG_X86_64
 221 extern void early_init_lapic_mapping(void);
 222 extern int apic_is_clustered_box(void);
 223 #else
 224 static inline int apic_is_clustered_box(void)
 225 {
 226         return 0;
 227 }
 228 #endif
 229
 230 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
 231 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
 232
 233
 234 #else /* !CONFIG_X86_LOCAL_APIC */
 235 static inline void lapic_shutdown(void) { }
 236 #define local_apic_timer_c2_ok          1
 237 static inline void init_apic_mappings(void) { }
 238 static inline void disable_local_APIC(void) { }
 239
 240 #endif /* !CONFIG_X86_LOCAL_APIC */
 241
 242 #ifdef CONFIG_X86_64
 243 #define SET_APIC_ID(x)          (apic->set_apic_id(x))
 244 #else
 245
 246 #endif
 247
 248 /*
 249  * Copyright 2004 James Cleverdon, IBM.
 250  * Subject to the GNU Public License, v.2
 251  *
 252  * Generic APIC sub-arch data struct.
 253  *
 254  * Hacked for x86-64 by James Cleverdon from i386 architecture code by
 255  * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
 256  * James Cleverdon.
 257  */
 258 struct apic {
 259         char *name;
 260
 261         int (*probe)(void);
 262         int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
 263         int (*apic_id_registered)(void);
 264
 265         u32 irq_delivery_mode;
 266         u32 irq_dest_mode;
 267
 268         const struct cpumask *(*target_cpus)(void);
 269
 270         int disable_esr;
 271
 272         int dest_logical;
 273         unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid);
 274         unsigned long (*check_apicid_present)(int apicid);
 275
 276         void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
 277         void (*init_apic_ldr)(void);
 278
 279         physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map);
 280
 281         void (*setup_apic_routing)(void);
 282         int (*multi_timer_check)(int apic, int irq);
 283         int (*apicid_to_node)(int logical_apicid);
 284         int (*cpu_to_logical_apicid)(int cpu);
 285         int (*cpu_present_to_apicid)(int mps_cpu);
 286         physid_mask_t (*apicid_to_cpu_present)(int phys_apicid);
 287         void (*setup_portio_remap)(void);
 288         int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
 289         void (*enable_apic_mode)(void);
 290         int (*phys_pkg_id)(int cpuid_apic, int index_msb);
 291
 292         /*
 293          * When one of the next two hooks returns 1 the apic
 294          * is switched to this. Essentially they are additional
 295          * probe functions:
 296          */
 297         int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
 298
 299         unsigned int (*get_apic_id)(unsigned long x);
 300         unsigned long (*set_apic_id)(unsigned int id);
 301         unsigned long apic_id_mask;
 302
 303         unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
 304         unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
 305                                                const struct cpumask *andmask);
 306
 307         /* ipi */
 308         void (*send_IPI_mask)(const struct cpumask *mask, int vector);
 309         void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
 310                                          int vector);
 311         void (*send_IPI_allbutself)(int vector);
 312         void (*send_IPI_all)(int vector);
 313         void (*send_IPI_self)(int vector);
 314
 315         /* wakeup_secondary_cpu */
 316         int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
 317
 318         int trampoline_phys_low;
 319         int trampoline_phys_high;
 320
 321         void (*wait_for_init_deassert)(atomic_t *deassert);
 322         void (*smp_callin_clear_local_apic)(void);
 323         void (*inquire_remote_apic)(int apicid);
 324
 325         /* apic ops */
 326         u32 (*read)(u32 reg);
 327         void (*write)(u32 reg, u32 v);
 328         u64 (*icr_read)(void);
 329         void (*icr_write)(u32 low, u32 high);
 330         void (*wait_icr_idle)(void);
 331         u32 (*safe_wait_icr_idle)(void);
 332 };
 333
 334 /*
 335  * Pointer to the local APIC driver in use on this system (there's
 336  * always just one such driver in use - the kernel decides via an
 337  * early probing process which one it picks - and then sticks to it):
 338  */
 339 extern struct apic *apic;
 340
 341 /*
 342  * APIC functionality to boot other CPUs - only used on SMP:
 343  */
 344 #ifdef CONFIG_SMP
 345 extern atomic_t init_deasserted;
 346 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
 347 #endif
 348
 349 static inline u32 apic_read(u32 reg)
 350 {
 351         return apic->read(reg);
 352 }
 353
 354 static inline void apic_write(u32 reg, u32 val)
 355 {
 356         apic->write(reg, val);
 357 }
 358
 359 static inline u64 apic_icr_read(void)
 360 {
 361         return apic->icr_read();
 362 }
 363
 364 static inline void apic_icr_write(u32 low, u32 high)
 365 {
 366         apic->icr_write(low, high);
 367 }
 368
 369 static inline void apic_wait_icr_idle(void)
 370 {
 371         apic->wait_icr_idle();
 372 }
 373
 374 static inline u32 safe_apic_wait_icr_idle(void)
 375 {
 376         return apic->safe_wait_icr_idle();
 377 }
 378
 379
 380 static inline void ack_APIC_irq(void)
 381 {
 382 #ifdef CONFIG_X86_LOCAL_APIC
 383         /*
 384          * ack_APIC_irq() actually gets compiled as a single instruction
 385          * ... yummie.
 386          */
 387
 388         /* Docs say use 0 for future compatibility */
 389         apic_write(APIC_EOI, 0);
 390 #endif
 391 }
 392
 393 static inline unsigned default_get_apic_id(unsigned long x)
 394 {
 395         unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
 396
 397         if (APIC_XAPIC(ver))
 398                 return (x >> 24) & 0xFF;
 399         else
 400                 return (x >> 24) & 0x0F;
 401 }
 402
 403 /*
 404  * Warm reset vector default position:
 405  */
 406 #define DEFAULT_TRAMPOLINE_PHYS_LOW             0x467
 407 #define DEFAULT_TRAMPOLINE_PHYS_HIGH            0x469
 408
 409 #ifdef CONFIG_X86_64
 410 extern struct apic apic_flat;
 411 extern struct apic apic_physflat;
 412 extern struct apic apic_x2apic_cluster;
 413 extern struct apic apic_x2apic_phys;
 414 extern int default_acpi_madt_oem_check(char *, char *);
 415
 416 extern void apic_send_IPI_self(int vector);
 417
 418 extern struct apic apic_x2apic_uv_x;
 419 DECLARE_PER_CPU(int, x2apic_extra_bits);
 420
 421 extern int default_cpu_present_to_apicid(int mps_cpu);
 422 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
 423 #endif
 424
 425 static inline void default_wait_for_init_deassert(atomic_t *deassert)
 426 {
 427         while (!atomic_read(deassert))
 428                 cpu_relax();
 429         return;
 430 }
 431
 432 extern void generic_bigsmp_probe(void);
 433
 434
 435 #ifdef CONFIG_X86_LOCAL_APIC
 436
 437 #include <asm/smp.h>
 438
 439 #define APIC_DFR_VALUE  (APIC_DFR_FLAT)
 440
 441 static inline const struct cpumask *default_target_cpus(void)
 442 {
 443 #ifdef CONFIG_SMP
 444         return cpu_online_mask;
 445 #else
 446         return cpumask_of(0);
 447 #endif
 448 }
 449
 450 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
 451
 452
 453 static inline unsigned int read_apic_id(void)
 454 {
 455         unsigned int reg;
 456
 457         reg = apic_read(APIC_ID);
 458
 459         return apic->get_apic_id(reg);
 460 }
 461
 462 extern void default_setup_apic_routing(void);
 463
 464 #ifdef CONFIG_X86_32
 465 /*
 466  * Set up the logical destination ID.
 467  *
 468  * Intel recommends to set DFR, LDR and TPR before enabling
 469  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
 470  * document number 292116).  So here it goes...
 471  */
 472 extern void default_init_apic_ldr(void);
 473
 474 static inline int default_apic_id_registered(void)
 475 {
 476         return physid_isset(read_apic_id(), phys_cpu_present_map);
 477 }
 478
 479 static inline unsigned int
 480 default_cpu_mask_to_apicid(const struct cpumask *cpumask)
 481 {
 482         return cpumask_bits(cpumask)[0];
 483 }
 484
 485 static inline unsigned int
 486 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 487                                const struct cpumask *andmask)
 488 {
 489         unsigned long mask1 = cpumask_bits(cpumask)[0];
 490         unsigned long mask2 = cpumask_bits(andmask)[0];
 491         unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
 492
 493         return (unsigned int)(mask1 & mask2 & mask3);
 494 }
 495
 496 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
 497 {
 498         return cpuid_apic >> index_msb;
 499 }
 500
 501 extern int default_apicid_to_node(int logical_apicid);
 502
 503 #endif
 504
 505 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
 506 {
 507         return physid_isset(apicid, bitmap);
 508 }
 509
 510 static inline unsigned long default_check_apicid_present(int bit)
 511 {
 512         return physid_isset(bit, phys_cpu_present_map);
 513 }
 514
 515 static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
 516 {
 517         return phys_map;
 518 }
 519
 520 /* Mapping from cpu number to logical apicid */
 521 static inline int default_cpu_to_logical_apicid(int cpu)
 522 {
 523         return 1 << cpu;
 524 }
 525
 526 static inline int __default_cpu_present_to_apicid(int mps_cpu)
 527 {
 528         if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
 529                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 530         else
 531                 return BAD_APICID;
 532 }
 533
 534 static inline int
 535 __default_check_phys_apicid_present(int boot_cpu_physical_apicid)
 536 {
 537         return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
 538 }
 539
 540 #ifdef CONFIG_X86_32
 541 static inline int default_cpu_present_to_apicid(int mps_cpu)
 542 {
 543         return __default_cpu_present_to_apicid(mps_cpu);
 544 }
 545
 546 static inline int
 547 default_check_phys_apicid_present(int boot_cpu_physical_apicid)
 548 {
 549         return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
 550 }
 551 #else
 552 extern int default_cpu_present_to_apicid(int mps_cpu);
 553 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
 554 #endif
 555
 556 static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
 557 {
 558         return physid_mask_of_physid(phys_apicid);
 559 }
 560
 561 #endif /* CONFIG_X86_LOCAL_APIC */
 562
 563 #ifdef CONFIG_X86_32
 564 extern u8 cpu_2_logical_apicid[NR_CPUS];
 565 #endif
 566
 567 #endif /* _ASM_X86_APIC_H */