x86: Add optimized popcnt variants
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / include / asm / alternative.h
1 #ifndef _ASM_X86_ALTERNATIVE_H
2 #define _ASM_X86_ALTERNATIVE_H
3
4 #include <linux/types.h>
5 #include <linux/stddef.h>
6 #include <linux/stringify.h>
7 #include <asm/asm.h>
8
9 /*
10 * Alternative inline assembly for SMP.
11 *
12 * The LOCK_PREFIX macro defined here replaces the LOCK and
13 * LOCK_PREFIX macros used everywhere in the source tree.
14 *
15 * SMP alternatives use the same data structures as the other
16 * alternatives and the X86_FEATURE_UP flag to indicate the case of a
17 * UP system running a SMP kernel. The existing apply_alternatives()
18 * works fine for patching a SMP kernel for UP.
19 *
20 * The SMP alternative tables can be kept after boot and contain both
21 * UP and SMP versions of the instructions to allow switching back to
22 * SMP at runtime, when hotplugging in a new CPU, which is especially
23 * useful in virtualized environments.
24 *
25 * The very common lock prefix is handled as special case in a
26 * separate table which is a pure address list without replacement ptr
27 * and size information. That keeps the table sizes small.
28 */
29
30 #ifdef CONFIG_SMP
31 #define LOCK_PREFIX \
32 ".section .smp_locks,\"a\"\n" \
33 _ASM_ALIGN "\n" \
34 _ASM_PTR "661f\n" /* address */ \
35 ".previous\n" \
36 "661:\n\tlock; "
37
38 #else /* ! CONFIG_SMP */
39 #define LOCK_PREFIX ""
40 #endif
41
42 struct alt_instr {
43 u8 *instr; /* original instruction */
44 u8 *replacement;
45 u8 cpuid; /* cpuid bit set for replacement */
46 u8 instrlen; /* length of original instruction */
47 u8 replacementlen; /* length of new instruction, <= instrlen */
48 u8 pad1;
49 #ifdef CONFIG_X86_64
50 u32 pad2;
51 #endif
52 };
53
54 extern void alternative_instructions(void);
55 extern void apply_alternatives(struct alt_instr *start, struct alt_instr *end);
56
57 struct module;
58
59 #ifdef CONFIG_SMP
60 extern void alternatives_smp_module_add(struct module *mod, char *name,
61 void *locks, void *locks_end,
62 void *text, void *text_end);
63 extern void alternatives_smp_module_del(struct module *mod);
64 extern void alternatives_smp_switch(int smp);
65 extern int alternatives_text_reserved(void *start, void *end);
66 #else
67 static inline void alternatives_smp_module_add(struct module *mod, char *name,
68 void *locks, void *locks_end,
69 void *text, void *text_end) {}
70 static inline void alternatives_smp_module_del(struct module *mod) {}
71 static inline void alternatives_smp_switch(int smp) {}
72 static inline int alternatives_text_reserved(void *start, void *end)
73 {
74 return 0;
75 }
76 #endif /* CONFIG_SMP */
77
78 /* alternative assembly primitive: */
79 #define ALTERNATIVE(oldinstr, newinstr, feature) \
80 \
81 "661:\n\t" oldinstr "\n662:\n" \
82 ".section .altinstructions,\"a\"\n" \
83 _ASM_ALIGN "\n" \
84 _ASM_PTR "661b\n" /* label */ \
85 _ASM_PTR "663f\n" /* new instruction */ \
86 " .byte " __stringify(feature) "\n" /* feature bit */ \
87 " .byte 662b-661b\n" /* sourcelen */ \
88 " .byte 664f-663f\n" /* replacementlen */ \
89 " .byte 0xff + (664f-663f) - (662b-661b)\n" /* rlen <= slen */ \
90 ".previous\n" \
91 ".section .altinstr_replacement, \"ax\"\n" \
92 "663:\n\t" newinstr "\n664:\n" /* replacement */ \
93 ".previous"
94
95 /*
96 * This must be included *after* the definition of ALTERNATIVE due to
97 * <asm/arch_hweight.h>
98 */
99 #include <asm/cpufeature.h>
100
101 /*
102 * Alternative instructions for different CPU types or capabilities.
103 *
104 * This allows to use optimized instructions even on generic binary
105 * kernels.
106 *
107 * length of oldinstr must be longer or equal the length of newinstr
108 * It can be padded with nops as needed.
109 *
110 * For non barrier like inlines please define new variants
111 * without volatile and memory clobber.
112 */
113 #define alternative(oldinstr, newinstr, feature) \
114 asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) : : : "memory")
115
116 /*
117 * Alternative inline assembly with input.
118 *
119 * Pecularities:
120 * No memory clobber here.
121 * Argument numbers start with 1.
122 * Best is to use constraints that are fixed size (like (%1) ... "r")
123 * If you use variable sized constraints like "m" or "g" in the
124 * replacement make sure to pad to the worst case length.
125 * Leaving an unused argument 0 to keep API compatibility.
126 */
127 #define alternative_input(oldinstr, newinstr, feature, input...) \
128 asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) \
129 : : "i" (0), ## input)
130
131 /* Like alternative_input, but with a single output argument */
132 #define alternative_io(oldinstr, newinstr, feature, output, input...) \
133 asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) \
134 : output : "i" (0), ## input)
135
136 /* Like alternative_io, but for replacing a direct call with another one. */
137 #define alternative_call(oldfunc, newfunc, feature, output, input...) \
138 asm volatile (ALTERNATIVE("call %P[old]", "call %P[new]", feature) \
139 : output : [old] "i" (oldfunc), [new] "i" (newfunc), ## input)
140
141 /*
142 * use this macro(s) if you need more than one output parameter
143 * in alternative_io
144 */
145 #define ASM_OUTPUT2(a...) a
146
147 struct paravirt_patch_site;
148 #ifdef CONFIG_PARAVIRT
149 void apply_paravirt(struct paravirt_patch_site *start,
150 struct paravirt_patch_site *end);
151 #else
152 static inline void apply_paravirt(struct paravirt_patch_site *start,
153 struct paravirt_patch_site *end)
154 {}
155 #define __parainstructions NULL
156 #define __parainstructions_end NULL
157 #endif
158
159 /*
160 * Clear and restore the kernel write-protection flag on the local CPU.
161 * Allows the kernel to edit read-only pages.
162 * Side-effect: any interrupt handler running between save and restore will have
163 * the ability to write to read-only pages.
164 *
165 * Warning:
166 * Code patching in the UP case is safe if NMIs and MCE handlers are stopped and
167 * no thread can be preempted in the instructions being modified (no iret to an
168 * invalid instruction possible) or if the instructions are changed from a
169 * consistent state to another consistent state atomically.
170 * More care must be taken when modifying code in the SMP case because of
171 * Intel's errata. text_poke_smp() takes care that errata, but still
172 * doesn't support NMI/MCE handler code modifying.
173 * On the local CPU you need to be protected again NMI or MCE handlers seeing an
174 * inconsistent instruction while you patch.
175 */
176 extern void *text_poke(void *addr, const void *opcode, size_t len);
177 extern void *text_poke_smp(void *addr, const void *opcode, size_t len);
178
179 #endif /* _ASM_X86_ALTERNATIVE_H */