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Merge branches 'x86/cache', 'x86/debug' and 'x86/irq' into x86/urgent
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / arch / x86 / events / intel / core.c
1 /*
2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/stddef.h>
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/export.h>
15 #include <linux/nmi.h>
16
17 #include <asm/cpufeature.h>
18 #include <asm/hardirq.h>
19 #include <asm/intel-family.h>
20 #include <asm/apic.h>
21
22 #include "../perf_event.h"
23
24 /*
25 * Intel PerfMon, used on Core and later.
26 */
27 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
28 {
29 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
30 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
31 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
32 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
33 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
34 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
35 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
36 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
37 };
38
39 static struct event_constraint intel_core_event_constraints[] __read_mostly =
40 {
41 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
42 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
43 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
44 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
45 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
46 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
47 EVENT_CONSTRAINT_END
48 };
49
50 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
51 {
52 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
53 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
54 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
55 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
56 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
57 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
58 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
59 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
60 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
61 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
62 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
63 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
64 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
65 EVENT_CONSTRAINT_END
66 };
67
68 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
69 {
70 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
71 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
72 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
73 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
74 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
75 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
76 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
77 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
78 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
79 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
80 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
81 EVENT_CONSTRAINT_END
82 };
83
84 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
85 {
86 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
87 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
88 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
89 EVENT_EXTRA_END
90 };
91
92 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
93 {
94 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
95 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
96 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
97 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
98 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
99 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
100 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
101 EVENT_CONSTRAINT_END
102 };
103
104 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
105 {
106 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
107 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
108 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
109 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
110 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
111 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
112 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
113 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
114 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
115 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
116 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
117 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
118
119 /*
120 * When HT is off these events can only run on the bottom 4 counters
121 * When HT is on, they are impacted by the HT bug and require EXCL access
122 */
123 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
124 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
125 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
126 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
127
128 EVENT_CONSTRAINT_END
129 };
130
131 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
132 {
133 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
134 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
135 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
136 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
138 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
139 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
141 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
142 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
144 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
146
147 /*
148 * When HT is off these events can only run on the bottom 4 counters
149 * When HT is on, they are impacted by the HT bug and require EXCL access
150 */
151 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
152 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
153 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
154 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
155
156 EVENT_CONSTRAINT_END
157 };
158
159 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
160 {
161 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
162 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
163 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
164 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
165 EVENT_EXTRA_END
166 };
167
168 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
169 {
170 EVENT_CONSTRAINT_END
171 };
172
173 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
174 {
175 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
176 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
177 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
178 EVENT_CONSTRAINT_END
179 };
180
181 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
182 {
183 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
184 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
185 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
186 EVENT_CONSTRAINT_END
187 };
188
189 static struct event_constraint intel_skl_event_constraints[] = {
190 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
191 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
192 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
193 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
194
195 /*
196 * when HT is off, these can only run on the bottom 4 counters
197 */
198 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
199 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
200 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
201 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
202 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
203
204 EVENT_CONSTRAINT_END
205 };
206
207 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
208 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
209 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
210 EVENT_EXTRA_END
211 };
212
213 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
214 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
215 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
216 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
217 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
218 EVENT_EXTRA_END
219 };
220
221 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
222 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
223 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
224 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
225 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
226 EVENT_EXTRA_END
227 };
228
229 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
230 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
231 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
232 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
233 /*
234 * Note the low 8 bits eventsel code is not a continuous field, containing
235 * some #GPing bits. These are masked out.
236 */
237 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
238 EVENT_EXTRA_END
239 };
240
241 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
242 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
243 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
244
245 static struct attribute *nhm_events_attrs[] = {
246 EVENT_PTR(mem_ld_nhm),
247 NULL,
248 };
249
250 /*
251 * topdown events for Intel Core CPUs.
252 *
253 * The events are all in slots, which is a free slot in a 4 wide
254 * pipeline. Some events are already reported in slots, for cycle
255 * events we multiply by the pipeline width (4).
256 *
257 * With Hyper Threading on, topdown metrics are either summed or averaged
258 * between the threads of a core: (count_t0 + count_t1).
259 *
260 * For the average case the metric is always scaled to pipeline width,
261 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
262 */
263
264 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
265 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
266 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
267 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
268 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
269 "event=0xe,umask=0x1"); /* uops_issued.any */
270 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
271 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
272 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
273 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
274 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
275 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
276 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
277 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
278 "4", "2");
279
280 static struct attribute *snb_events_attrs[] = {
281 EVENT_PTR(mem_ld_snb),
282 EVENT_PTR(mem_st_snb),
283 EVENT_PTR(td_slots_issued),
284 EVENT_PTR(td_slots_retired),
285 EVENT_PTR(td_fetch_bubbles),
286 EVENT_PTR(td_total_slots),
287 EVENT_PTR(td_total_slots_scale),
288 EVENT_PTR(td_recovery_bubbles),
289 EVENT_PTR(td_recovery_bubbles_scale),
290 NULL,
291 };
292
293 static struct event_constraint intel_hsw_event_constraints[] = {
294 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
295 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
296 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
297 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
298 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
299 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
300 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
301 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
302 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
303 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
304 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
305 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
306
307 /*
308 * When HT is off these events can only run on the bottom 4 counters
309 * When HT is on, they are impacted by the HT bug and require EXCL access
310 */
311 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
312 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
313 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
314 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
315
316 EVENT_CONSTRAINT_END
317 };
318
319 static struct event_constraint intel_bdw_event_constraints[] = {
320 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
321 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
322 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
323 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
324 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
325 /*
326 * when HT is off, these can only run on the bottom 4 counters
327 */
328 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
329 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
330 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
331 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
332 EVENT_CONSTRAINT_END
333 };
334
335 static u64 intel_pmu_event_map(int hw_event)
336 {
337 return intel_perfmon_event_map[hw_event];
338 }
339
340 /*
341 * Notes on the events:
342 * - data reads do not include code reads (comparable to earlier tables)
343 * - data counts include speculative execution (except L1 write, dtlb, bpu)
344 * - remote node access includes remote memory, remote cache, remote mmio.
345 * - prefetches are not included in the counts.
346 * - icache miss does not include decoded icache
347 */
348
349 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
350 #define SKL_DEMAND_RFO BIT_ULL(1)
351 #define SKL_ANY_RESPONSE BIT_ULL(16)
352 #define SKL_SUPPLIER_NONE BIT_ULL(17)
353 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
354 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
355 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
356 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
357 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
358 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
359 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
360 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
361 #define SKL_SPL_HIT BIT_ULL(30)
362 #define SKL_SNOOP_NONE BIT_ULL(31)
363 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
364 #define SKL_SNOOP_MISS BIT_ULL(33)
365 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
366 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
367 #define SKL_SNOOP_HITM BIT_ULL(36)
368 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
369 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
370 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
371 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
372 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
373 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
374 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
375 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
376 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
377 SKL_SNOOP_HITM|SKL_SPL_HIT)
378 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
379 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
380 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
381 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
382 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
383
384 static __initconst const u64 skl_hw_cache_event_ids
385 [PERF_COUNT_HW_CACHE_MAX]
386 [PERF_COUNT_HW_CACHE_OP_MAX]
387 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
388 {
389 [ C(L1D ) ] = {
390 [ C(OP_READ) ] = {
391 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
392 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
393 },
394 [ C(OP_WRITE) ] = {
395 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
396 [ C(RESULT_MISS) ] = 0x0,
397 },
398 [ C(OP_PREFETCH) ] = {
399 [ C(RESULT_ACCESS) ] = 0x0,
400 [ C(RESULT_MISS) ] = 0x0,
401 },
402 },
403 [ C(L1I ) ] = {
404 [ C(OP_READ) ] = {
405 [ C(RESULT_ACCESS) ] = 0x0,
406 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
407 },
408 [ C(OP_WRITE) ] = {
409 [ C(RESULT_ACCESS) ] = -1,
410 [ C(RESULT_MISS) ] = -1,
411 },
412 [ C(OP_PREFETCH) ] = {
413 [ C(RESULT_ACCESS) ] = 0x0,
414 [ C(RESULT_MISS) ] = 0x0,
415 },
416 },
417 [ C(LL ) ] = {
418 [ C(OP_READ) ] = {
419 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
420 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
421 },
422 [ C(OP_WRITE) ] = {
423 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
424 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
425 },
426 [ C(OP_PREFETCH) ] = {
427 [ C(RESULT_ACCESS) ] = 0x0,
428 [ C(RESULT_MISS) ] = 0x0,
429 },
430 },
431 [ C(DTLB) ] = {
432 [ C(OP_READ) ] = {
433 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
434 [ C(RESULT_MISS) ] = 0x608, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
435 },
436 [ C(OP_WRITE) ] = {
437 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
438 [ C(RESULT_MISS) ] = 0x649, /* DTLB_STORE_MISSES.WALK_COMPLETED */
439 },
440 [ C(OP_PREFETCH) ] = {
441 [ C(RESULT_ACCESS) ] = 0x0,
442 [ C(RESULT_MISS) ] = 0x0,
443 },
444 },
445 [ C(ITLB) ] = {
446 [ C(OP_READ) ] = {
447 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
448 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
449 },
450 [ C(OP_WRITE) ] = {
451 [ C(RESULT_ACCESS) ] = -1,
452 [ C(RESULT_MISS) ] = -1,
453 },
454 [ C(OP_PREFETCH) ] = {
455 [ C(RESULT_ACCESS) ] = -1,
456 [ C(RESULT_MISS) ] = -1,
457 },
458 },
459 [ C(BPU ) ] = {
460 [ C(OP_READ) ] = {
461 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
462 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
463 },
464 [ C(OP_WRITE) ] = {
465 [ C(RESULT_ACCESS) ] = -1,
466 [ C(RESULT_MISS) ] = -1,
467 },
468 [ C(OP_PREFETCH) ] = {
469 [ C(RESULT_ACCESS) ] = -1,
470 [ C(RESULT_MISS) ] = -1,
471 },
472 },
473 [ C(NODE) ] = {
474 [ C(OP_READ) ] = {
475 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
476 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
477 },
478 [ C(OP_WRITE) ] = {
479 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
480 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
481 },
482 [ C(OP_PREFETCH) ] = {
483 [ C(RESULT_ACCESS) ] = 0x0,
484 [ C(RESULT_MISS) ] = 0x0,
485 },
486 },
487 };
488
489 static __initconst const u64 skl_hw_cache_extra_regs
490 [PERF_COUNT_HW_CACHE_MAX]
491 [PERF_COUNT_HW_CACHE_OP_MAX]
492 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
493 {
494 [ C(LL ) ] = {
495 [ C(OP_READ) ] = {
496 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
497 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
498 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
499 SKL_L3_MISS|SKL_ANY_SNOOP|
500 SKL_SUPPLIER_NONE,
501 },
502 [ C(OP_WRITE) ] = {
503 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
504 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
505 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
506 SKL_L3_MISS|SKL_ANY_SNOOP|
507 SKL_SUPPLIER_NONE,
508 },
509 [ C(OP_PREFETCH) ] = {
510 [ C(RESULT_ACCESS) ] = 0x0,
511 [ C(RESULT_MISS) ] = 0x0,
512 },
513 },
514 [ C(NODE) ] = {
515 [ C(OP_READ) ] = {
516 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
517 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
518 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
519 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
520 },
521 [ C(OP_WRITE) ] = {
522 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
523 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
524 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
525 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
526 },
527 [ C(OP_PREFETCH) ] = {
528 [ C(RESULT_ACCESS) ] = 0x0,
529 [ C(RESULT_MISS) ] = 0x0,
530 },
531 },
532 };
533
534 #define SNB_DMND_DATA_RD (1ULL << 0)
535 #define SNB_DMND_RFO (1ULL << 1)
536 #define SNB_DMND_IFETCH (1ULL << 2)
537 #define SNB_DMND_WB (1ULL << 3)
538 #define SNB_PF_DATA_RD (1ULL << 4)
539 #define SNB_PF_RFO (1ULL << 5)
540 #define SNB_PF_IFETCH (1ULL << 6)
541 #define SNB_LLC_DATA_RD (1ULL << 7)
542 #define SNB_LLC_RFO (1ULL << 8)
543 #define SNB_LLC_IFETCH (1ULL << 9)
544 #define SNB_BUS_LOCKS (1ULL << 10)
545 #define SNB_STRM_ST (1ULL << 11)
546 #define SNB_OTHER (1ULL << 15)
547 #define SNB_RESP_ANY (1ULL << 16)
548 #define SNB_NO_SUPP (1ULL << 17)
549 #define SNB_LLC_HITM (1ULL << 18)
550 #define SNB_LLC_HITE (1ULL << 19)
551 #define SNB_LLC_HITS (1ULL << 20)
552 #define SNB_LLC_HITF (1ULL << 21)
553 #define SNB_LOCAL (1ULL << 22)
554 #define SNB_REMOTE (0xffULL << 23)
555 #define SNB_SNP_NONE (1ULL << 31)
556 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
557 #define SNB_SNP_MISS (1ULL << 33)
558 #define SNB_NO_FWD (1ULL << 34)
559 #define SNB_SNP_FWD (1ULL << 35)
560 #define SNB_HITM (1ULL << 36)
561 #define SNB_NON_DRAM (1ULL << 37)
562
563 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
564 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
565 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
566
567 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
568 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
569 SNB_HITM)
570
571 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
572 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
573
574 #define SNB_L3_ACCESS SNB_RESP_ANY
575 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
576
577 static __initconst const u64 snb_hw_cache_extra_regs
578 [PERF_COUNT_HW_CACHE_MAX]
579 [PERF_COUNT_HW_CACHE_OP_MAX]
580 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
581 {
582 [ C(LL ) ] = {
583 [ C(OP_READ) ] = {
584 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
585 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
586 },
587 [ C(OP_WRITE) ] = {
588 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
589 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
590 },
591 [ C(OP_PREFETCH) ] = {
592 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
593 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
594 },
595 },
596 [ C(NODE) ] = {
597 [ C(OP_READ) ] = {
598 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
599 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
600 },
601 [ C(OP_WRITE) ] = {
602 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
603 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
604 },
605 [ C(OP_PREFETCH) ] = {
606 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
607 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
608 },
609 },
610 };
611
612 static __initconst const u64 snb_hw_cache_event_ids
613 [PERF_COUNT_HW_CACHE_MAX]
614 [PERF_COUNT_HW_CACHE_OP_MAX]
615 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
616 {
617 [ C(L1D) ] = {
618 [ C(OP_READ) ] = {
619 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
620 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
621 },
622 [ C(OP_WRITE) ] = {
623 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
624 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
625 },
626 [ C(OP_PREFETCH) ] = {
627 [ C(RESULT_ACCESS) ] = 0x0,
628 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
629 },
630 },
631 [ C(L1I ) ] = {
632 [ C(OP_READ) ] = {
633 [ C(RESULT_ACCESS) ] = 0x0,
634 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
635 },
636 [ C(OP_WRITE) ] = {
637 [ C(RESULT_ACCESS) ] = -1,
638 [ C(RESULT_MISS) ] = -1,
639 },
640 [ C(OP_PREFETCH) ] = {
641 [ C(RESULT_ACCESS) ] = 0x0,
642 [ C(RESULT_MISS) ] = 0x0,
643 },
644 },
645 [ C(LL ) ] = {
646 [ C(OP_READ) ] = {
647 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
648 [ C(RESULT_ACCESS) ] = 0x01b7,
649 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
650 [ C(RESULT_MISS) ] = 0x01b7,
651 },
652 [ C(OP_WRITE) ] = {
653 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
654 [ C(RESULT_ACCESS) ] = 0x01b7,
655 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
656 [ C(RESULT_MISS) ] = 0x01b7,
657 },
658 [ C(OP_PREFETCH) ] = {
659 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
660 [ C(RESULT_ACCESS) ] = 0x01b7,
661 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
662 [ C(RESULT_MISS) ] = 0x01b7,
663 },
664 },
665 [ C(DTLB) ] = {
666 [ C(OP_READ) ] = {
667 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
668 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
669 },
670 [ C(OP_WRITE) ] = {
671 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
672 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
673 },
674 [ C(OP_PREFETCH) ] = {
675 [ C(RESULT_ACCESS) ] = 0x0,
676 [ C(RESULT_MISS) ] = 0x0,
677 },
678 },
679 [ C(ITLB) ] = {
680 [ C(OP_READ) ] = {
681 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
682 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
683 },
684 [ C(OP_WRITE) ] = {
685 [ C(RESULT_ACCESS) ] = -1,
686 [ C(RESULT_MISS) ] = -1,
687 },
688 [ C(OP_PREFETCH) ] = {
689 [ C(RESULT_ACCESS) ] = -1,
690 [ C(RESULT_MISS) ] = -1,
691 },
692 },
693 [ C(BPU ) ] = {
694 [ C(OP_READ) ] = {
695 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
696 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
697 },
698 [ C(OP_WRITE) ] = {
699 [ C(RESULT_ACCESS) ] = -1,
700 [ C(RESULT_MISS) ] = -1,
701 },
702 [ C(OP_PREFETCH) ] = {
703 [ C(RESULT_ACCESS) ] = -1,
704 [ C(RESULT_MISS) ] = -1,
705 },
706 },
707 [ C(NODE) ] = {
708 [ C(OP_READ) ] = {
709 [ C(RESULT_ACCESS) ] = 0x01b7,
710 [ C(RESULT_MISS) ] = 0x01b7,
711 },
712 [ C(OP_WRITE) ] = {
713 [ C(RESULT_ACCESS) ] = 0x01b7,
714 [ C(RESULT_MISS) ] = 0x01b7,
715 },
716 [ C(OP_PREFETCH) ] = {
717 [ C(RESULT_ACCESS) ] = 0x01b7,
718 [ C(RESULT_MISS) ] = 0x01b7,
719 },
720 },
721
722 };
723
724 /*
725 * Notes on the events:
726 * - data reads do not include code reads (comparable to earlier tables)
727 * - data counts include speculative execution (except L1 write, dtlb, bpu)
728 * - remote node access includes remote memory, remote cache, remote mmio.
729 * - prefetches are not included in the counts because they are not
730 * reliably counted.
731 */
732
733 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
734 #define HSW_DEMAND_RFO BIT_ULL(1)
735 #define HSW_ANY_RESPONSE BIT_ULL(16)
736 #define HSW_SUPPLIER_NONE BIT_ULL(17)
737 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
738 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
739 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
740 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
741 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
742 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
743 HSW_L3_MISS_REMOTE_HOP2P)
744 #define HSW_SNOOP_NONE BIT_ULL(31)
745 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
746 #define HSW_SNOOP_MISS BIT_ULL(33)
747 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
748 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
749 #define HSW_SNOOP_HITM BIT_ULL(36)
750 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
751 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
752 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
753 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
754 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
755 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
756 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
757 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
758 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
759 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
760 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
761
762 #define BDW_L3_MISS_LOCAL BIT(26)
763 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
764 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
765 HSW_L3_MISS_REMOTE_HOP2P)
766
767
768 static __initconst const u64 hsw_hw_cache_event_ids
769 [PERF_COUNT_HW_CACHE_MAX]
770 [PERF_COUNT_HW_CACHE_OP_MAX]
771 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
772 {
773 [ C(L1D ) ] = {
774 [ C(OP_READ) ] = {
775 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
776 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
777 },
778 [ C(OP_WRITE) ] = {
779 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
780 [ C(RESULT_MISS) ] = 0x0,
781 },
782 [ C(OP_PREFETCH) ] = {
783 [ C(RESULT_ACCESS) ] = 0x0,
784 [ C(RESULT_MISS) ] = 0x0,
785 },
786 },
787 [ C(L1I ) ] = {
788 [ C(OP_READ) ] = {
789 [ C(RESULT_ACCESS) ] = 0x0,
790 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
791 },
792 [ C(OP_WRITE) ] = {
793 [ C(RESULT_ACCESS) ] = -1,
794 [ C(RESULT_MISS) ] = -1,
795 },
796 [ C(OP_PREFETCH) ] = {
797 [ C(RESULT_ACCESS) ] = 0x0,
798 [ C(RESULT_MISS) ] = 0x0,
799 },
800 },
801 [ C(LL ) ] = {
802 [ C(OP_READ) ] = {
803 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
804 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
805 },
806 [ C(OP_WRITE) ] = {
807 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
808 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
809 },
810 [ C(OP_PREFETCH) ] = {
811 [ C(RESULT_ACCESS) ] = 0x0,
812 [ C(RESULT_MISS) ] = 0x0,
813 },
814 },
815 [ C(DTLB) ] = {
816 [ C(OP_READ) ] = {
817 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
818 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
819 },
820 [ C(OP_WRITE) ] = {
821 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
822 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
823 },
824 [ C(OP_PREFETCH) ] = {
825 [ C(RESULT_ACCESS) ] = 0x0,
826 [ C(RESULT_MISS) ] = 0x0,
827 },
828 },
829 [ C(ITLB) ] = {
830 [ C(OP_READ) ] = {
831 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
832 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
833 },
834 [ C(OP_WRITE) ] = {
835 [ C(RESULT_ACCESS) ] = -1,
836 [ C(RESULT_MISS) ] = -1,
837 },
838 [ C(OP_PREFETCH) ] = {
839 [ C(RESULT_ACCESS) ] = -1,
840 [ C(RESULT_MISS) ] = -1,
841 },
842 },
843 [ C(BPU ) ] = {
844 [ C(OP_READ) ] = {
845 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
846 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
847 },
848 [ C(OP_WRITE) ] = {
849 [ C(RESULT_ACCESS) ] = -1,
850 [ C(RESULT_MISS) ] = -1,
851 },
852 [ C(OP_PREFETCH) ] = {
853 [ C(RESULT_ACCESS) ] = -1,
854 [ C(RESULT_MISS) ] = -1,
855 },
856 },
857 [ C(NODE) ] = {
858 [ C(OP_READ) ] = {
859 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
860 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
861 },
862 [ C(OP_WRITE) ] = {
863 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
864 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
865 },
866 [ C(OP_PREFETCH) ] = {
867 [ C(RESULT_ACCESS) ] = 0x0,
868 [ C(RESULT_MISS) ] = 0x0,
869 },
870 },
871 };
872
873 static __initconst const u64 hsw_hw_cache_extra_regs
874 [PERF_COUNT_HW_CACHE_MAX]
875 [PERF_COUNT_HW_CACHE_OP_MAX]
876 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
877 {
878 [ C(LL ) ] = {
879 [ C(OP_READ) ] = {
880 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
881 HSW_LLC_ACCESS,
882 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
883 HSW_L3_MISS|HSW_ANY_SNOOP,
884 },
885 [ C(OP_WRITE) ] = {
886 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
887 HSW_LLC_ACCESS,
888 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
889 HSW_L3_MISS|HSW_ANY_SNOOP,
890 },
891 [ C(OP_PREFETCH) ] = {
892 [ C(RESULT_ACCESS) ] = 0x0,
893 [ C(RESULT_MISS) ] = 0x0,
894 },
895 },
896 [ C(NODE) ] = {
897 [ C(OP_READ) ] = {
898 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
899 HSW_L3_MISS_LOCAL_DRAM|
900 HSW_SNOOP_DRAM,
901 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
902 HSW_L3_MISS_REMOTE|
903 HSW_SNOOP_DRAM,
904 },
905 [ C(OP_WRITE) ] = {
906 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
907 HSW_L3_MISS_LOCAL_DRAM|
908 HSW_SNOOP_DRAM,
909 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
910 HSW_L3_MISS_REMOTE|
911 HSW_SNOOP_DRAM,
912 },
913 [ C(OP_PREFETCH) ] = {
914 [ C(RESULT_ACCESS) ] = 0x0,
915 [ C(RESULT_MISS) ] = 0x0,
916 },
917 },
918 };
919
920 static __initconst const u64 westmere_hw_cache_event_ids
921 [PERF_COUNT_HW_CACHE_MAX]
922 [PERF_COUNT_HW_CACHE_OP_MAX]
923 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
924 {
925 [ C(L1D) ] = {
926 [ C(OP_READ) ] = {
927 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
928 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
929 },
930 [ C(OP_WRITE) ] = {
931 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
932 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
933 },
934 [ C(OP_PREFETCH) ] = {
935 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
936 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
937 },
938 },
939 [ C(L1I ) ] = {
940 [ C(OP_READ) ] = {
941 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
942 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
943 },
944 [ C(OP_WRITE) ] = {
945 [ C(RESULT_ACCESS) ] = -1,
946 [ C(RESULT_MISS) ] = -1,
947 },
948 [ C(OP_PREFETCH) ] = {
949 [ C(RESULT_ACCESS) ] = 0x0,
950 [ C(RESULT_MISS) ] = 0x0,
951 },
952 },
953 [ C(LL ) ] = {
954 [ C(OP_READ) ] = {
955 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
956 [ C(RESULT_ACCESS) ] = 0x01b7,
957 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
958 [ C(RESULT_MISS) ] = 0x01b7,
959 },
960 /*
961 * Use RFO, not WRITEBACK, because a write miss would typically occur
962 * on RFO.
963 */
964 [ C(OP_WRITE) ] = {
965 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
966 [ C(RESULT_ACCESS) ] = 0x01b7,
967 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
968 [ C(RESULT_MISS) ] = 0x01b7,
969 },
970 [ C(OP_PREFETCH) ] = {
971 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
972 [ C(RESULT_ACCESS) ] = 0x01b7,
973 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
974 [ C(RESULT_MISS) ] = 0x01b7,
975 },
976 },
977 [ C(DTLB) ] = {
978 [ C(OP_READ) ] = {
979 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
980 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
981 },
982 [ C(OP_WRITE) ] = {
983 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
984 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
985 },
986 [ C(OP_PREFETCH) ] = {
987 [ C(RESULT_ACCESS) ] = 0x0,
988 [ C(RESULT_MISS) ] = 0x0,
989 },
990 },
991 [ C(ITLB) ] = {
992 [ C(OP_READ) ] = {
993 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
994 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
995 },
996 [ C(OP_WRITE) ] = {
997 [ C(RESULT_ACCESS) ] = -1,
998 [ C(RESULT_MISS) ] = -1,
999 },
1000 [ C(OP_PREFETCH) ] = {
1001 [ C(RESULT_ACCESS) ] = -1,
1002 [ C(RESULT_MISS) ] = -1,
1003 },
1004 },
1005 [ C(BPU ) ] = {
1006 [ C(OP_READ) ] = {
1007 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1008 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1009 },
1010 [ C(OP_WRITE) ] = {
1011 [ C(RESULT_ACCESS) ] = -1,
1012 [ C(RESULT_MISS) ] = -1,
1013 },
1014 [ C(OP_PREFETCH) ] = {
1015 [ C(RESULT_ACCESS) ] = -1,
1016 [ C(RESULT_MISS) ] = -1,
1017 },
1018 },
1019 [ C(NODE) ] = {
1020 [ C(OP_READ) ] = {
1021 [ C(RESULT_ACCESS) ] = 0x01b7,
1022 [ C(RESULT_MISS) ] = 0x01b7,
1023 },
1024 [ C(OP_WRITE) ] = {
1025 [ C(RESULT_ACCESS) ] = 0x01b7,
1026 [ C(RESULT_MISS) ] = 0x01b7,
1027 },
1028 [ C(OP_PREFETCH) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x01b7,
1030 [ C(RESULT_MISS) ] = 0x01b7,
1031 },
1032 },
1033 };
1034
1035 /*
1036 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1037 * See IA32 SDM Vol 3B 30.6.1.3
1038 */
1039
1040 #define NHM_DMND_DATA_RD (1 << 0)
1041 #define NHM_DMND_RFO (1 << 1)
1042 #define NHM_DMND_IFETCH (1 << 2)
1043 #define NHM_DMND_WB (1 << 3)
1044 #define NHM_PF_DATA_RD (1 << 4)
1045 #define NHM_PF_DATA_RFO (1 << 5)
1046 #define NHM_PF_IFETCH (1 << 6)
1047 #define NHM_OFFCORE_OTHER (1 << 7)
1048 #define NHM_UNCORE_HIT (1 << 8)
1049 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1050 #define NHM_OTHER_CORE_HITM (1 << 10)
1051 /* reserved */
1052 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1053 #define NHM_REMOTE_DRAM (1 << 13)
1054 #define NHM_LOCAL_DRAM (1 << 14)
1055 #define NHM_NON_DRAM (1 << 15)
1056
1057 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1058 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1059
1060 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1061 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1062 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1063
1064 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1065 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1066 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1067
1068 static __initconst const u64 nehalem_hw_cache_extra_regs
1069 [PERF_COUNT_HW_CACHE_MAX]
1070 [PERF_COUNT_HW_CACHE_OP_MAX]
1071 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1072 {
1073 [ C(LL ) ] = {
1074 [ C(OP_READ) ] = {
1075 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1076 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1077 },
1078 [ C(OP_WRITE) ] = {
1079 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1080 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1081 },
1082 [ C(OP_PREFETCH) ] = {
1083 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1084 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1085 },
1086 },
1087 [ C(NODE) ] = {
1088 [ C(OP_READ) ] = {
1089 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1090 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1091 },
1092 [ C(OP_WRITE) ] = {
1093 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1094 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1095 },
1096 [ C(OP_PREFETCH) ] = {
1097 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1098 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1099 },
1100 },
1101 };
1102
1103 static __initconst const u64 nehalem_hw_cache_event_ids
1104 [PERF_COUNT_HW_CACHE_MAX]
1105 [PERF_COUNT_HW_CACHE_OP_MAX]
1106 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1107 {
1108 [ C(L1D) ] = {
1109 [ C(OP_READ) ] = {
1110 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1111 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1112 },
1113 [ C(OP_WRITE) ] = {
1114 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1115 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1116 },
1117 [ C(OP_PREFETCH) ] = {
1118 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1119 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1120 },
1121 },
1122 [ C(L1I ) ] = {
1123 [ C(OP_READ) ] = {
1124 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1125 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1126 },
1127 [ C(OP_WRITE) ] = {
1128 [ C(RESULT_ACCESS) ] = -1,
1129 [ C(RESULT_MISS) ] = -1,
1130 },
1131 [ C(OP_PREFETCH) ] = {
1132 [ C(RESULT_ACCESS) ] = 0x0,
1133 [ C(RESULT_MISS) ] = 0x0,
1134 },
1135 },
1136 [ C(LL ) ] = {
1137 [ C(OP_READ) ] = {
1138 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1139 [ C(RESULT_ACCESS) ] = 0x01b7,
1140 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1141 [ C(RESULT_MISS) ] = 0x01b7,
1142 },
1143 /*
1144 * Use RFO, not WRITEBACK, because a write miss would typically occur
1145 * on RFO.
1146 */
1147 [ C(OP_WRITE) ] = {
1148 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1149 [ C(RESULT_ACCESS) ] = 0x01b7,
1150 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1151 [ C(RESULT_MISS) ] = 0x01b7,
1152 },
1153 [ C(OP_PREFETCH) ] = {
1154 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1155 [ C(RESULT_ACCESS) ] = 0x01b7,
1156 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1157 [ C(RESULT_MISS) ] = 0x01b7,
1158 },
1159 },
1160 [ C(DTLB) ] = {
1161 [ C(OP_READ) ] = {
1162 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1163 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1164 },
1165 [ C(OP_WRITE) ] = {
1166 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1167 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1168 },
1169 [ C(OP_PREFETCH) ] = {
1170 [ C(RESULT_ACCESS) ] = 0x0,
1171 [ C(RESULT_MISS) ] = 0x0,
1172 },
1173 },
1174 [ C(ITLB) ] = {
1175 [ C(OP_READ) ] = {
1176 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1177 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1178 },
1179 [ C(OP_WRITE) ] = {
1180 [ C(RESULT_ACCESS) ] = -1,
1181 [ C(RESULT_MISS) ] = -1,
1182 },
1183 [ C(OP_PREFETCH) ] = {
1184 [ C(RESULT_ACCESS) ] = -1,
1185 [ C(RESULT_MISS) ] = -1,
1186 },
1187 },
1188 [ C(BPU ) ] = {
1189 [ C(OP_READ) ] = {
1190 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1191 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1192 },
1193 [ C(OP_WRITE) ] = {
1194 [ C(RESULT_ACCESS) ] = -1,
1195 [ C(RESULT_MISS) ] = -1,
1196 },
1197 [ C(OP_PREFETCH) ] = {
1198 [ C(RESULT_ACCESS) ] = -1,
1199 [ C(RESULT_MISS) ] = -1,
1200 },
1201 },
1202 [ C(NODE) ] = {
1203 [ C(OP_READ) ] = {
1204 [ C(RESULT_ACCESS) ] = 0x01b7,
1205 [ C(RESULT_MISS) ] = 0x01b7,
1206 },
1207 [ C(OP_WRITE) ] = {
1208 [ C(RESULT_ACCESS) ] = 0x01b7,
1209 [ C(RESULT_MISS) ] = 0x01b7,
1210 },
1211 [ C(OP_PREFETCH) ] = {
1212 [ C(RESULT_ACCESS) ] = 0x01b7,
1213 [ C(RESULT_MISS) ] = 0x01b7,
1214 },
1215 },
1216 };
1217
1218 static __initconst const u64 core2_hw_cache_event_ids
1219 [PERF_COUNT_HW_CACHE_MAX]
1220 [PERF_COUNT_HW_CACHE_OP_MAX]
1221 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1222 {
1223 [ C(L1D) ] = {
1224 [ C(OP_READ) ] = {
1225 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1226 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1227 },
1228 [ C(OP_WRITE) ] = {
1229 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1230 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1231 },
1232 [ C(OP_PREFETCH) ] = {
1233 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1234 [ C(RESULT_MISS) ] = 0,
1235 },
1236 },
1237 [ C(L1I ) ] = {
1238 [ C(OP_READ) ] = {
1239 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1240 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1241 },
1242 [ C(OP_WRITE) ] = {
1243 [ C(RESULT_ACCESS) ] = -1,
1244 [ C(RESULT_MISS) ] = -1,
1245 },
1246 [ C(OP_PREFETCH) ] = {
1247 [ C(RESULT_ACCESS) ] = 0,
1248 [ C(RESULT_MISS) ] = 0,
1249 },
1250 },
1251 [ C(LL ) ] = {
1252 [ C(OP_READ) ] = {
1253 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1254 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1255 },
1256 [ C(OP_WRITE) ] = {
1257 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1258 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1259 },
1260 [ C(OP_PREFETCH) ] = {
1261 [ C(RESULT_ACCESS) ] = 0,
1262 [ C(RESULT_MISS) ] = 0,
1263 },
1264 },
1265 [ C(DTLB) ] = {
1266 [ C(OP_READ) ] = {
1267 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1268 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1269 },
1270 [ C(OP_WRITE) ] = {
1271 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1272 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1273 },
1274 [ C(OP_PREFETCH) ] = {
1275 [ C(RESULT_ACCESS) ] = 0,
1276 [ C(RESULT_MISS) ] = 0,
1277 },
1278 },
1279 [ C(ITLB) ] = {
1280 [ C(OP_READ) ] = {
1281 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1282 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1283 },
1284 [ C(OP_WRITE) ] = {
1285 [ C(RESULT_ACCESS) ] = -1,
1286 [ C(RESULT_MISS) ] = -1,
1287 },
1288 [ C(OP_PREFETCH) ] = {
1289 [ C(RESULT_ACCESS) ] = -1,
1290 [ C(RESULT_MISS) ] = -1,
1291 },
1292 },
1293 [ C(BPU ) ] = {
1294 [ C(OP_READ) ] = {
1295 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1296 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1297 },
1298 [ C(OP_WRITE) ] = {
1299 [ C(RESULT_ACCESS) ] = -1,
1300 [ C(RESULT_MISS) ] = -1,
1301 },
1302 [ C(OP_PREFETCH) ] = {
1303 [ C(RESULT_ACCESS) ] = -1,
1304 [ C(RESULT_MISS) ] = -1,
1305 },
1306 },
1307 };
1308
1309 static __initconst const u64 atom_hw_cache_event_ids
1310 [PERF_COUNT_HW_CACHE_MAX]
1311 [PERF_COUNT_HW_CACHE_OP_MAX]
1312 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1313 {
1314 [ C(L1D) ] = {
1315 [ C(OP_READ) ] = {
1316 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1317 [ C(RESULT_MISS) ] = 0,
1318 },
1319 [ C(OP_WRITE) ] = {
1320 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1321 [ C(RESULT_MISS) ] = 0,
1322 },
1323 [ C(OP_PREFETCH) ] = {
1324 [ C(RESULT_ACCESS) ] = 0x0,
1325 [ C(RESULT_MISS) ] = 0,
1326 },
1327 },
1328 [ C(L1I ) ] = {
1329 [ C(OP_READ) ] = {
1330 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1331 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1332 },
1333 [ C(OP_WRITE) ] = {
1334 [ C(RESULT_ACCESS) ] = -1,
1335 [ C(RESULT_MISS) ] = -1,
1336 },
1337 [ C(OP_PREFETCH) ] = {
1338 [ C(RESULT_ACCESS) ] = 0,
1339 [ C(RESULT_MISS) ] = 0,
1340 },
1341 },
1342 [ C(LL ) ] = {
1343 [ C(OP_READ) ] = {
1344 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1345 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1346 },
1347 [ C(OP_WRITE) ] = {
1348 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1349 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1350 },
1351 [ C(OP_PREFETCH) ] = {
1352 [ C(RESULT_ACCESS) ] = 0,
1353 [ C(RESULT_MISS) ] = 0,
1354 },
1355 },
1356 [ C(DTLB) ] = {
1357 [ C(OP_READ) ] = {
1358 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1359 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1360 },
1361 [ C(OP_WRITE) ] = {
1362 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1363 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1364 },
1365 [ C(OP_PREFETCH) ] = {
1366 [ C(RESULT_ACCESS) ] = 0,
1367 [ C(RESULT_MISS) ] = 0,
1368 },
1369 },
1370 [ C(ITLB) ] = {
1371 [ C(OP_READ) ] = {
1372 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1373 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1374 },
1375 [ C(OP_WRITE) ] = {
1376 [ C(RESULT_ACCESS) ] = -1,
1377 [ C(RESULT_MISS) ] = -1,
1378 },
1379 [ C(OP_PREFETCH) ] = {
1380 [ C(RESULT_ACCESS) ] = -1,
1381 [ C(RESULT_MISS) ] = -1,
1382 },
1383 },
1384 [ C(BPU ) ] = {
1385 [ C(OP_READ) ] = {
1386 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1387 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1388 },
1389 [ C(OP_WRITE) ] = {
1390 [ C(RESULT_ACCESS) ] = -1,
1391 [ C(RESULT_MISS) ] = -1,
1392 },
1393 [ C(OP_PREFETCH) ] = {
1394 [ C(RESULT_ACCESS) ] = -1,
1395 [ C(RESULT_MISS) ] = -1,
1396 },
1397 },
1398 };
1399
1400 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1401 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1402 /* no_alloc_cycles.not_delivered */
1403 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1404 "event=0xca,umask=0x50");
1405 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1406 /* uops_retired.all */
1407 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1408 "event=0xc2,umask=0x10");
1409 /* uops_retired.all */
1410 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1411 "event=0xc2,umask=0x10");
1412
1413 static struct attribute *slm_events_attrs[] = {
1414 EVENT_PTR(td_total_slots_slm),
1415 EVENT_PTR(td_total_slots_scale_slm),
1416 EVENT_PTR(td_fetch_bubbles_slm),
1417 EVENT_PTR(td_fetch_bubbles_scale_slm),
1418 EVENT_PTR(td_slots_issued_slm),
1419 EVENT_PTR(td_slots_retired_slm),
1420 NULL
1421 };
1422
1423 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1424 {
1425 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1426 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1427 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1428 EVENT_EXTRA_END
1429 };
1430
1431 #define SLM_DMND_READ SNB_DMND_DATA_RD
1432 #define SLM_DMND_WRITE SNB_DMND_RFO
1433 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1434
1435 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1436 #define SLM_LLC_ACCESS SNB_RESP_ANY
1437 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1438
1439 static __initconst const u64 slm_hw_cache_extra_regs
1440 [PERF_COUNT_HW_CACHE_MAX]
1441 [PERF_COUNT_HW_CACHE_OP_MAX]
1442 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1443 {
1444 [ C(LL ) ] = {
1445 [ C(OP_READ) ] = {
1446 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1447 [ C(RESULT_MISS) ] = 0,
1448 },
1449 [ C(OP_WRITE) ] = {
1450 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1451 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1452 },
1453 [ C(OP_PREFETCH) ] = {
1454 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1455 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1456 },
1457 },
1458 };
1459
1460 static __initconst const u64 slm_hw_cache_event_ids
1461 [PERF_COUNT_HW_CACHE_MAX]
1462 [PERF_COUNT_HW_CACHE_OP_MAX]
1463 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1464 {
1465 [ C(L1D) ] = {
1466 [ C(OP_READ) ] = {
1467 [ C(RESULT_ACCESS) ] = 0,
1468 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1469 },
1470 [ C(OP_WRITE) ] = {
1471 [ C(RESULT_ACCESS) ] = 0,
1472 [ C(RESULT_MISS) ] = 0,
1473 },
1474 [ C(OP_PREFETCH) ] = {
1475 [ C(RESULT_ACCESS) ] = 0,
1476 [ C(RESULT_MISS) ] = 0,
1477 },
1478 },
1479 [ C(L1I ) ] = {
1480 [ C(OP_READ) ] = {
1481 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1482 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1483 },
1484 [ C(OP_WRITE) ] = {
1485 [ C(RESULT_ACCESS) ] = -1,
1486 [ C(RESULT_MISS) ] = -1,
1487 },
1488 [ C(OP_PREFETCH) ] = {
1489 [ C(RESULT_ACCESS) ] = 0,
1490 [ C(RESULT_MISS) ] = 0,
1491 },
1492 },
1493 [ C(LL ) ] = {
1494 [ C(OP_READ) ] = {
1495 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1496 [ C(RESULT_ACCESS) ] = 0x01b7,
1497 [ C(RESULT_MISS) ] = 0,
1498 },
1499 [ C(OP_WRITE) ] = {
1500 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1501 [ C(RESULT_ACCESS) ] = 0x01b7,
1502 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1503 [ C(RESULT_MISS) ] = 0x01b7,
1504 },
1505 [ C(OP_PREFETCH) ] = {
1506 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1507 [ C(RESULT_ACCESS) ] = 0x01b7,
1508 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1509 [ C(RESULT_MISS) ] = 0x01b7,
1510 },
1511 },
1512 [ C(DTLB) ] = {
1513 [ C(OP_READ) ] = {
1514 [ C(RESULT_ACCESS) ] = 0,
1515 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1516 },
1517 [ C(OP_WRITE) ] = {
1518 [ C(RESULT_ACCESS) ] = 0,
1519 [ C(RESULT_MISS) ] = 0,
1520 },
1521 [ C(OP_PREFETCH) ] = {
1522 [ C(RESULT_ACCESS) ] = 0,
1523 [ C(RESULT_MISS) ] = 0,
1524 },
1525 },
1526 [ C(ITLB) ] = {
1527 [ C(OP_READ) ] = {
1528 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1529 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1530 },
1531 [ C(OP_WRITE) ] = {
1532 [ C(RESULT_ACCESS) ] = -1,
1533 [ C(RESULT_MISS) ] = -1,
1534 },
1535 [ C(OP_PREFETCH) ] = {
1536 [ C(RESULT_ACCESS) ] = -1,
1537 [ C(RESULT_MISS) ] = -1,
1538 },
1539 },
1540 [ C(BPU ) ] = {
1541 [ C(OP_READ) ] = {
1542 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1543 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1544 },
1545 [ C(OP_WRITE) ] = {
1546 [ C(RESULT_ACCESS) ] = -1,
1547 [ C(RESULT_MISS) ] = -1,
1548 },
1549 [ C(OP_PREFETCH) ] = {
1550 [ C(RESULT_ACCESS) ] = -1,
1551 [ C(RESULT_MISS) ] = -1,
1552 },
1553 },
1554 };
1555
1556 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1557 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1558 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1559 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1560 EVENT_EXTRA_END
1561 };
1562
1563 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1564 #define GLM_DEMAND_RFO BIT_ULL(1)
1565 #define GLM_ANY_RESPONSE BIT_ULL(16)
1566 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1567 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1568 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1569 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1570 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1571 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1572 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1573
1574 static __initconst const u64 glm_hw_cache_event_ids
1575 [PERF_COUNT_HW_CACHE_MAX]
1576 [PERF_COUNT_HW_CACHE_OP_MAX]
1577 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1578 [C(L1D)] = {
1579 [C(OP_READ)] = {
1580 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1581 [C(RESULT_MISS)] = 0x0,
1582 },
1583 [C(OP_WRITE)] = {
1584 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1585 [C(RESULT_MISS)] = 0x0,
1586 },
1587 [C(OP_PREFETCH)] = {
1588 [C(RESULT_ACCESS)] = 0x0,
1589 [C(RESULT_MISS)] = 0x0,
1590 },
1591 },
1592 [C(L1I)] = {
1593 [C(OP_READ)] = {
1594 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1595 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1596 },
1597 [C(OP_WRITE)] = {
1598 [C(RESULT_ACCESS)] = -1,
1599 [C(RESULT_MISS)] = -1,
1600 },
1601 [C(OP_PREFETCH)] = {
1602 [C(RESULT_ACCESS)] = 0x0,
1603 [C(RESULT_MISS)] = 0x0,
1604 },
1605 },
1606 [C(LL)] = {
1607 [C(OP_READ)] = {
1608 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1609 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1610 },
1611 [C(OP_WRITE)] = {
1612 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1613 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1614 },
1615 [C(OP_PREFETCH)] = {
1616 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1617 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1618 },
1619 },
1620 [C(DTLB)] = {
1621 [C(OP_READ)] = {
1622 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1623 [C(RESULT_MISS)] = 0x0,
1624 },
1625 [C(OP_WRITE)] = {
1626 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1627 [C(RESULT_MISS)] = 0x0,
1628 },
1629 [C(OP_PREFETCH)] = {
1630 [C(RESULT_ACCESS)] = 0x0,
1631 [C(RESULT_MISS)] = 0x0,
1632 },
1633 },
1634 [C(ITLB)] = {
1635 [C(OP_READ)] = {
1636 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1637 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1638 },
1639 [C(OP_WRITE)] = {
1640 [C(RESULT_ACCESS)] = -1,
1641 [C(RESULT_MISS)] = -1,
1642 },
1643 [C(OP_PREFETCH)] = {
1644 [C(RESULT_ACCESS)] = -1,
1645 [C(RESULT_MISS)] = -1,
1646 },
1647 },
1648 [C(BPU)] = {
1649 [C(OP_READ)] = {
1650 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1651 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1652 },
1653 [C(OP_WRITE)] = {
1654 [C(RESULT_ACCESS)] = -1,
1655 [C(RESULT_MISS)] = -1,
1656 },
1657 [C(OP_PREFETCH)] = {
1658 [C(RESULT_ACCESS)] = -1,
1659 [C(RESULT_MISS)] = -1,
1660 },
1661 },
1662 };
1663
1664 static __initconst const u64 glm_hw_cache_extra_regs
1665 [PERF_COUNT_HW_CACHE_MAX]
1666 [PERF_COUNT_HW_CACHE_OP_MAX]
1667 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1668 [C(LL)] = {
1669 [C(OP_READ)] = {
1670 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1671 GLM_LLC_ACCESS,
1672 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1673 GLM_LLC_MISS,
1674 },
1675 [C(OP_WRITE)] = {
1676 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1677 GLM_LLC_ACCESS,
1678 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1679 GLM_LLC_MISS,
1680 },
1681 [C(OP_PREFETCH)] = {
1682 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1683 GLM_LLC_ACCESS,
1684 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1685 GLM_LLC_MISS,
1686 },
1687 },
1688 };
1689
1690 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
1691 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
1692 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
1693 #define KNL_MCDRAM_FAR BIT_ULL(22)
1694 #define KNL_DDR_LOCAL BIT_ULL(23)
1695 #define KNL_DDR_FAR BIT_ULL(24)
1696 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1697 KNL_DDR_LOCAL | KNL_DDR_FAR)
1698 #define KNL_L2_READ SLM_DMND_READ
1699 #define KNL_L2_WRITE SLM_DMND_WRITE
1700 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1701 #define KNL_L2_ACCESS SLM_LLC_ACCESS
1702 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1703 KNL_DRAM_ANY | SNB_SNP_ANY | \
1704 SNB_NON_DRAM)
1705
1706 static __initconst const u64 knl_hw_cache_extra_regs
1707 [PERF_COUNT_HW_CACHE_MAX]
1708 [PERF_COUNT_HW_CACHE_OP_MAX]
1709 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1710 [C(LL)] = {
1711 [C(OP_READ)] = {
1712 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1713 [C(RESULT_MISS)] = 0,
1714 },
1715 [C(OP_WRITE)] = {
1716 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1717 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1718 },
1719 [C(OP_PREFETCH)] = {
1720 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1721 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
1722 },
1723 },
1724 };
1725
1726 /*
1727 * Used from PMIs where the LBRs are already disabled.
1728 *
1729 * This function could be called consecutively. It is required to remain in
1730 * disabled state if called consecutively.
1731 *
1732 * During consecutive calls, the same disable value will be written to related
1733 * registers, so the PMU state remains unchanged.
1734 *
1735 * intel_bts events don't coexist with intel PMU's BTS events because of
1736 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
1737 * disabled around intel PMU's event batching etc, only inside the PMI handler.
1738 */
1739 static void __intel_pmu_disable_all(void)
1740 {
1741 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1742
1743 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1744
1745 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1746 intel_pmu_disable_bts();
1747
1748 intel_pmu_pebs_disable_all();
1749 }
1750
1751 static void intel_pmu_disable_all(void)
1752 {
1753 __intel_pmu_disable_all();
1754 intel_pmu_lbr_disable_all();
1755 }
1756
1757 static void __intel_pmu_enable_all(int added, bool pmi)
1758 {
1759 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1760
1761 intel_pmu_pebs_enable_all();
1762 intel_pmu_lbr_enable_all(pmi);
1763 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1764 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1765
1766 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1767 struct perf_event *event =
1768 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1769
1770 if (WARN_ON_ONCE(!event))
1771 return;
1772
1773 intel_pmu_enable_bts(event->hw.config);
1774 }
1775 }
1776
1777 static void intel_pmu_enable_all(int added)
1778 {
1779 __intel_pmu_enable_all(added, false);
1780 }
1781
1782 /*
1783 * Workaround for:
1784 * Intel Errata AAK100 (model 26)
1785 * Intel Errata AAP53 (model 30)
1786 * Intel Errata BD53 (model 44)
1787 *
1788 * The official story:
1789 * These chips need to be 'reset' when adding counters by programming the
1790 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1791 * in sequence on the same PMC or on different PMCs.
1792 *
1793 * In practise it appears some of these events do in fact count, and
1794 * we need to programm all 4 events.
1795 */
1796 static void intel_pmu_nhm_workaround(void)
1797 {
1798 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1799 static const unsigned long nhm_magic[4] = {
1800 0x4300B5,
1801 0x4300D2,
1802 0x4300B1,
1803 0x4300B1
1804 };
1805 struct perf_event *event;
1806 int i;
1807
1808 /*
1809 * The Errata requires below steps:
1810 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1811 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1812 * the corresponding PMCx;
1813 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1814 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1815 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1816 */
1817
1818 /*
1819 * The real steps we choose are a little different from above.
1820 * A) To reduce MSR operations, we don't run step 1) as they
1821 * are already cleared before this function is called;
1822 * B) Call x86_perf_event_update to save PMCx before configuring
1823 * PERFEVTSELx with magic number;
1824 * C) With step 5), we do clear only when the PERFEVTSELx is
1825 * not used currently.
1826 * D) Call x86_perf_event_set_period to restore PMCx;
1827 */
1828
1829 /* We always operate 4 pairs of PERF Counters */
1830 for (i = 0; i < 4; i++) {
1831 event = cpuc->events[i];
1832 if (event)
1833 x86_perf_event_update(event);
1834 }
1835
1836 for (i = 0; i < 4; i++) {
1837 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1838 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1839 }
1840
1841 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1842 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
1843
1844 for (i = 0; i < 4; i++) {
1845 event = cpuc->events[i];
1846
1847 if (event) {
1848 x86_perf_event_set_period(event);
1849 __x86_pmu_enable_event(&event->hw,
1850 ARCH_PERFMON_EVENTSEL_ENABLE);
1851 } else
1852 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
1853 }
1854 }
1855
1856 static void intel_pmu_nhm_enable_all(int added)
1857 {
1858 if (added)
1859 intel_pmu_nhm_workaround();
1860 intel_pmu_enable_all(added);
1861 }
1862
1863 static inline u64 intel_pmu_get_status(void)
1864 {
1865 u64 status;
1866
1867 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1868
1869 return status;
1870 }
1871
1872 static inline void intel_pmu_ack_status(u64 ack)
1873 {
1874 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1875 }
1876
1877 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
1878 {
1879 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1880 u64 ctrl_val, mask;
1881
1882 mask = 0xfULL << (idx * 4);
1883
1884 rdmsrl(hwc->config_base, ctrl_val);
1885 ctrl_val &= ~mask;
1886 wrmsrl(hwc->config_base, ctrl_val);
1887 }
1888
1889 static inline bool event_is_checkpointed(struct perf_event *event)
1890 {
1891 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1892 }
1893
1894 static void intel_pmu_disable_event(struct perf_event *event)
1895 {
1896 struct hw_perf_event *hwc = &event->hw;
1897 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1898
1899 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1900 intel_pmu_disable_bts();
1901 intel_pmu_drain_bts_buffer();
1902 return;
1903 }
1904
1905 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1906 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1907 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
1908
1909 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1910 intel_pmu_disable_fixed(hwc);
1911 return;
1912 }
1913
1914 x86_pmu_disable_event(event);
1915
1916 if (unlikely(event->attr.precise_ip))
1917 intel_pmu_pebs_disable(event);
1918 }
1919
1920 static void intel_pmu_del_event(struct perf_event *event)
1921 {
1922 if (needs_branch_stack(event))
1923 intel_pmu_lbr_del(event);
1924 if (event->attr.precise_ip)
1925 intel_pmu_pebs_del(event);
1926 }
1927
1928 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
1929 {
1930 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1931 u64 ctrl_val, bits, mask;
1932
1933 /*
1934 * Enable IRQ generation (0x8),
1935 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1936 * if requested:
1937 */
1938 bits = 0x8ULL;
1939 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1940 bits |= 0x2;
1941 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1942 bits |= 0x1;
1943
1944 /*
1945 * ANY bit is supported in v3 and up
1946 */
1947 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1948 bits |= 0x4;
1949
1950 bits <<= (idx * 4);
1951 mask = 0xfULL << (idx * 4);
1952
1953 rdmsrl(hwc->config_base, ctrl_val);
1954 ctrl_val &= ~mask;
1955 ctrl_val |= bits;
1956 wrmsrl(hwc->config_base, ctrl_val);
1957 }
1958
1959 static void intel_pmu_enable_event(struct perf_event *event)
1960 {
1961 struct hw_perf_event *hwc = &event->hw;
1962 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1963
1964 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1965 if (!__this_cpu_read(cpu_hw_events.enabled))
1966 return;
1967
1968 intel_pmu_enable_bts(hwc->config);
1969 return;
1970 }
1971
1972 if (event->attr.exclude_host)
1973 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1974 if (event->attr.exclude_guest)
1975 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1976
1977 if (unlikely(event_is_checkpointed(event)))
1978 cpuc->intel_cp_status |= (1ull << hwc->idx);
1979
1980 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1981 intel_pmu_enable_fixed(hwc);
1982 return;
1983 }
1984
1985 if (unlikely(event->attr.precise_ip))
1986 intel_pmu_pebs_enable(event);
1987
1988 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1989 }
1990
1991 static void intel_pmu_add_event(struct perf_event *event)
1992 {
1993 if (event->attr.precise_ip)
1994 intel_pmu_pebs_add(event);
1995 if (needs_branch_stack(event))
1996 intel_pmu_lbr_add(event);
1997 }
1998
1999 /*
2000 * Save and restart an expired event. Called by NMI contexts,
2001 * so it has to be careful about preempting normal event ops:
2002 */
2003 int intel_pmu_save_and_restart(struct perf_event *event)
2004 {
2005 x86_perf_event_update(event);
2006 /*
2007 * For a checkpointed counter always reset back to 0. This
2008 * avoids a situation where the counter overflows, aborts the
2009 * transaction and is then set back to shortly before the
2010 * overflow, and overflows and aborts again.
2011 */
2012 if (unlikely(event_is_checkpointed(event))) {
2013 /* No race with NMIs because the counter should not be armed */
2014 wrmsrl(event->hw.event_base, 0);
2015 local64_set(&event->hw.prev_count, 0);
2016 }
2017 return x86_perf_event_set_period(event);
2018 }
2019
2020 static void intel_pmu_reset(void)
2021 {
2022 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2023 unsigned long flags;
2024 int idx;
2025
2026 if (!x86_pmu.num_counters)
2027 return;
2028
2029 local_irq_save(flags);
2030
2031 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2032
2033 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2034 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2035 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2036 }
2037 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
2038 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2039
2040 if (ds)
2041 ds->bts_index = ds->bts_buffer_base;
2042
2043 /* Ack all overflows and disable fixed counters */
2044 if (x86_pmu.version >= 2) {
2045 intel_pmu_ack_status(intel_pmu_get_status());
2046 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2047 }
2048
2049 /* Reset LBRs and LBR freezing */
2050 if (x86_pmu.lbr_nr) {
2051 update_debugctlmsr(get_debugctlmsr() &
2052 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2053 }
2054
2055 local_irq_restore(flags);
2056 }
2057
2058 /*
2059 * This handler is triggered by the local APIC, so the APIC IRQ handling
2060 * rules apply:
2061 */
2062 static int intel_pmu_handle_irq(struct pt_regs *regs)
2063 {
2064 struct perf_sample_data data;
2065 struct cpu_hw_events *cpuc;
2066 int bit, loops;
2067 u64 status;
2068 int handled;
2069
2070 cpuc = this_cpu_ptr(&cpu_hw_events);
2071
2072 /*
2073 * No known reason to not always do late ACK,
2074 * but just in case do it opt-in.
2075 */
2076 if (!x86_pmu.late_ack)
2077 apic_write(APIC_LVTPC, APIC_DM_NMI);
2078 intel_bts_disable_local();
2079 __intel_pmu_disable_all();
2080 handled = intel_pmu_drain_bts_buffer();
2081 handled += intel_bts_interrupt();
2082 status = intel_pmu_get_status();
2083 if (!status)
2084 goto done;
2085
2086 loops = 0;
2087 again:
2088 intel_pmu_lbr_read();
2089 intel_pmu_ack_status(status);
2090 if (++loops > 100) {
2091 static bool warned = false;
2092 if (!warned) {
2093 WARN(1, "perfevents: irq loop stuck!\n");
2094 perf_event_print_debug();
2095 warned = true;
2096 }
2097 intel_pmu_reset();
2098 goto done;
2099 }
2100
2101 inc_irq_stat(apic_perf_irqs);
2102
2103
2104 /*
2105 * Ignore a range of extra bits in status that do not indicate
2106 * overflow by themselves.
2107 */
2108 status &= ~(GLOBAL_STATUS_COND_CHG |
2109 GLOBAL_STATUS_ASIF |
2110 GLOBAL_STATUS_LBRS_FROZEN);
2111 if (!status)
2112 goto done;
2113 /*
2114 * In case multiple PEBS events are sampled at the same time,
2115 * it is possible to have GLOBAL_STATUS bit 62 set indicating
2116 * PEBS buffer overflow and also seeing at most 3 PEBS counters
2117 * having their bits set in the status register. This is a sign
2118 * that there was at least one PEBS record pending at the time
2119 * of the PMU interrupt. PEBS counters must only be processed
2120 * via the drain_pebs() calls and not via the regular sample
2121 * processing loop coming after that the function, otherwise
2122 * phony regular samples may be generated in the sampling buffer
2123 * not marked with the EXACT tag. Another possibility is to have
2124 * one PEBS event and at least one non-PEBS event whic hoverflows
2125 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2126 * not be set, yet the overflow status bit for the PEBS counter will
2127 * be on Skylake.
2128 *
2129 * To avoid this problem, we systematically ignore the PEBS-enabled
2130 * counters from the GLOBAL_STATUS mask and we always process PEBS
2131 * events via drain_pebs().
2132 */
2133 status &= ~cpuc->pebs_enabled;
2134
2135 /*
2136 * PEBS overflow sets bit 62 in the global status register
2137 */
2138 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
2139 handled++;
2140 x86_pmu.drain_pebs(regs);
2141 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2142 }
2143
2144 /*
2145 * Intel PT
2146 */
2147 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
2148 handled++;
2149 intel_pt_interrupt();
2150 }
2151
2152 /*
2153 * Checkpointed counters can lead to 'spurious' PMIs because the
2154 * rollback caused by the PMI will have cleared the overflow status
2155 * bit. Therefore always force probe these counters.
2156 */
2157 status |= cpuc->intel_cp_status;
2158
2159 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2160 struct perf_event *event = cpuc->events[bit];
2161
2162 handled++;
2163
2164 if (!test_bit(bit, cpuc->active_mask))
2165 continue;
2166
2167 if (!intel_pmu_save_and_restart(event))
2168 continue;
2169
2170 perf_sample_data_init(&data, 0, event->hw.last_period);
2171
2172 if (has_branch_stack(event))
2173 data.br_stack = &cpuc->lbr_stack;
2174
2175 if (perf_event_overflow(event, &data, regs))
2176 x86_pmu_stop(event, 0);
2177 }
2178
2179 /*
2180 * Repeat if there is more work to be done:
2181 */
2182 status = intel_pmu_get_status();
2183 if (status)
2184 goto again;
2185
2186 done:
2187 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2188 if (cpuc->enabled)
2189 __intel_pmu_enable_all(0, true);
2190 intel_bts_enable_local();
2191
2192 /*
2193 * Only unmask the NMI after the overflow counters
2194 * have been reset. This avoids spurious NMIs on
2195 * Haswell CPUs.
2196 */
2197 if (x86_pmu.late_ack)
2198 apic_write(APIC_LVTPC, APIC_DM_NMI);
2199 return handled;
2200 }
2201
2202 static struct event_constraint *
2203 intel_bts_constraints(struct perf_event *event)
2204 {
2205 struct hw_perf_event *hwc = &event->hw;
2206 unsigned int hw_event, bts_event;
2207
2208 if (event->attr.freq)
2209 return NULL;
2210
2211 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
2212 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
2213
2214 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
2215 return &bts_constraint;
2216
2217 return NULL;
2218 }
2219
2220 static int intel_alt_er(int idx, u64 config)
2221 {
2222 int alt_idx = idx;
2223
2224 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
2225 return idx;
2226
2227 if (idx == EXTRA_REG_RSP_0)
2228 alt_idx = EXTRA_REG_RSP_1;
2229
2230 if (idx == EXTRA_REG_RSP_1)
2231 alt_idx = EXTRA_REG_RSP_0;
2232
2233 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
2234 return idx;
2235
2236 return alt_idx;
2237 }
2238
2239 static void intel_fixup_er(struct perf_event *event, int idx)
2240 {
2241 event->hw.extra_reg.idx = idx;
2242
2243 if (idx == EXTRA_REG_RSP_0) {
2244 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2245 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
2246 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
2247 } else if (idx == EXTRA_REG_RSP_1) {
2248 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2249 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
2250 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
2251 }
2252 }
2253
2254 /*
2255 * manage allocation of shared extra msr for certain events
2256 *
2257 * sharing can be:
2258 * per-cpu: to be shared between the various events on a single PMU
2259 * per-core: per-cpu + shared by HT threads
2260 */
2261 static struct event_constraint *
2262 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
2263 struct perf_event *event,
2264 struct hw_perf_event_extra *reg)
2265 {
2266 struct event_constraint *c = &emptyconstraint;
2267 struct er_account *era;
2268 unsigned long flags;
2269 int idx = reg->idx;
2270
2271 /*
2272 * reg->alloc can be set due to existing state, so for fake cpuc we
2273 * need to ignore this, otherwise we might fail to allocate proper fake
2274 * state for this extra reg constraint. Also see the comment below.
2275 */
2276 if (reg->alloc && !cpuc->is_fake)
2277 return NULL; /* call x86_get_event_constraint() */
2278
2279 again:
2280 era = &cpuc->shared_regs->regs[idx];
2281 /*
2282 * we use spin_lock_irqsave() to avoid lockdep issues when
2283 * passing a fake cpuc
2284 */
2285 raw_spin_lock_irqsave(&era->lock, flags);
2286
2287 if (!atomic_read(&era->ref) || era->config == reg->config) {
2288
2289 /*
2290 * If its a fake cpuc -- as per validate_{group,event}() we
2291 * shouldn't touch event state and we can avoid doing so
2292 * since both will only call get_event_constraints() once
2293 * on each event, this avoids the need for reg->alloc.
2294 *
2295 * Not doing the ER fixup will only result in era->reg being
2296 * wrong, but since we won't actually try and program hardware
2297 * this isn't a problem either.
2298 */
2299 if (!cpuc->is_fake) {
2300 if (idx != reg->idx)
2301 intel_fixup_er(event, idx);
2302
2303 /*
2304 * x86_schedule_events() can call get_event_constraints()
2305 * multiple times on events in the case of incremental
2306 * scheduling(). reg->alloc ensures we only do the ER
2307 * allocation once.
2308 */
2309 reg->alloc = 1;
2310 }
2311
2312 /* lock in msr value */
2313 era->config = reg->config;
2314 era->reg = reg->reg;
2315
2316 /* one more user */
2317 atomic_inc(&era->ref);
2318
2319 /*
2320 * need to call x86_get_event_constraint()
2321 * to check if associated event has constraints
2322 */
2323 c = NULL;
2324 } else {
2325 idx = intel_alt_er(idx, reg->config);
2326 if (idx != reg->idx) {
2327 raw_spin_unlock_irqrestore(&era->lock, flags);
2328 goto again;
2329 }
2330 }
2331 raw_spin_unlock_irqrestore(&era->lock, flags);
2332
2333 return c;
2334 }
2335
2336 static void
2337 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2338 struct hw_perf_event_extra *reg)
2339 {
2340 struct er_account *era;
2341
2342 /*
2343 * Only put constraint if extra reg was actually allocated. Also takes
2344 * care of event which do not use an extra shared reg.
2345 *
2346 * Also, if this is a fake cpuc we shouldn't touch any event state
2347 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2348 * either since it'll be thrown out.
2349 */
2350 if (!reg->alloc || cpuc->is_fake)
2351 return;
2352
2353 era = &cpuc->shared_regs->regs[reg->idx];
2354
2355 /* one fewer user */
2356 atomic_dec(&era->ref);
2357
2358 /* allocate again next time */
2359 reg->alloc = 0;
2360 }
2361
2362 static struct event_constraint *
2363 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2364 struct perf_event *event)
2365 {
2366 struct event_constraint *c = NULL, *d;
2367 struct hw_perf_event_extra *xreg, *breg;
2368
2369 xreg = &event->hw.extra_reg;
2370 if (xreg->idx != EXTRA_REG_NONE) {
2371 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2372 if (c == &emptyconstraint)
2373 return c;
2374 }
2375 breg = &event->hw.branch_reg;
2376 if (breg->idx != EXTRA_REG_NONE) {
2377 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2378 if (d == &emptyconstraint) {
2379 __intel_shared_reg_put_constraints(cpuc, xreg);
2380 c = d;
2381 }
2382 }
2383 return c;
2384 }
2385
2386 struct event_constraint *
2387 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2388 struct perf_event *event)
2389 {
2390 struct event_constraint *c;
2391
2392 if (x86_pmu.event_constraints) {
2393 for_each_event_constraint(c, x86_pmu.event_constraints) {
2394 if ((event->hw.config & c->cmask) == c->code) {
2395 event->hw.flags |= c->flags;
2396 return c;
2397 }
2398 }
2399 }
2400
2401 return &unconstrained;
2402 }
2403
2404 static struct event_constraint *
2405 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2406 struct perf_event *event)
2407 {
2408 struct event_constraint *c;
2409
2410 c = intel_bts_constraints(event);
2411 if (c)
2412 return c;
2413
2414 c = intel_shared_regs_constraints(cpuc, event);
2415 if (c)
2416 return c;
2417
2418 c = intel_pebs_constraints(event);
2419 if (c)
2420 return c;
2421
2422 return x86_get_event_constraints(cpuc, idx, event);
2423 }
2424
2425 static void
2426 intel_start_scheduling(struct cpu_hw_events *cpuc)
2427 {
2428 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2429 struct intel_excl_states *xl;
2430 int tid = cpuc->excl_thread_id;
2431
2432 /*
2433 * nothing needed if in group validation mode
2434 */
2435 if (cpuc->is_fake || !is_ht_workaround_enabled())
2436 return;
2437
2438 /*
2439 * no exclusion needed
2440 */
2441 if (WARN_ON_ONCE(!excl_cntrs))
2442 return;
2443
2444 xl = &excl_cntrs->states[tid];
2445
2446 xl->sched_started = true;
2447 /*
2448 * lock shared state until we are done scheduling
2449 * in stop_event_scheduling()
2450 * makes scheduling appear as a transaction
2451 */
2452 raw_spin_lock(&excl_cntrs->lock);
2453 }
2454
2455 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2456 {
2457 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2458 struct event_constraint *c = cpuc->event_constraint[idx];
2459 struct intel_excl_states *xl;
2460 int tid = cpuc->excl_thread_id;
2461
2462 if (cpuc->is_fake || !is_ht_workaround_enabled())
2463 return;
2464
2465 if (WARN_ON_ONCE(!excl_cntrs))
2466 return;
2467
2468 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2469 return;
2470
2471 xl = &excl_cntrs->states[tid];
2472
2473 lockdep_assert_held(&excl_cntrs->lock);
2474
2475 if (c->flags & PERF_X86_EVENT_EXCL)
2476 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
2477 else
2478 xl->state[cntr] = INTEL_EXCL_SHARED;
2479 }
2480
2481 static void
2482 intel_stop_scheduling(struct cpu_hw_events *cpuc)
2483 {
2484 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2485 struct intel_excl_states *xl;
2486 int tid = cpuc->excl_thread_id;
2487
2488 /*
2489 * nothing needed if in group validation mode
2490 */
2491 if (cpuc->is_fake || !is_ht_workaround_enabled())
2492 return;
2493 /*
2494 * no exclusion needed
2495 */
2496 if (WARN_ON_ONCE(!excl_cntrs))
2497 return;
2498
2499 xl = &excl_cntrs->states[tid];
2500
2501 xl->sched_started = false;
2502 /*
2503 * release shared state lock (acquired in intel_start_scheduling())
2504 */
2505 raw_spin_unlock(&excl_cntrs->lock);
2506 }
2507
2508 static struct event_constraint *
2509 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2510 int idx, struct event_constraint *c)
2511 {
2512 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2513 struct intel_excl_states *xlo;
2514 int tid = cpuc->excl_thread_id;
2515 int is_excl, i;
2516
2517 /*
2518 * validating a group does not require
2519 * enforcing cross-thread exclusion
2520 */
2521 if (cpuc->is_fake || !is_ht_workaround_enabled())
2522 return c;
2523
2524 /*
2525 * no exclusion needed
2526 */
2527 if (WARN_ON_ONCE(!excl_cntrs))
2528 return c;
2529
2530 /*
2531 * because we modify the constraint, we need
2532 * to make a copy. Static constraints come
2533 * from static const tables.
2534 *
2535 * only needed when constraint has not yet
2536 * been cloned (marked dynamic)
2537 */
2538 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
2539 struct event_constraint *cx;
2540
2541 /*
2542 * grab pre-allocated constraint entry
2543 */
2544 cx = &cpuc->constraint_list[idx];
2545
2546 /*
2547 * initialize dynamic constraint
2548 * with static constraint
2549 */
2550 *cx = *c;
2551
2552 /*
2553 * mark constraint as dynamic, so we
2554 * can free it later on
2555 */
2556 cx->flags |= PERF_X86_EVENT_DYNAMIC;
2557 c = cx;
2558 }
2559
2560 /*
2561 * From here on, the constraint is dynamic.
2562 * Either it was just allocated above, or it
2563 * was allocated during a earlier invocation
2564 * of this function
2565 */
2566
2567 /*
2568 * state of sibling HT
2569 */
2570 xlo = &excl_cntrs->states[tid ^ 1];
2571
2572 /*
2573 * event requires exclusive counter access
2574 * across HT threads
2575 */
2576 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2577 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2578 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2579 if (!cpuc->n_excl++)
2580 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2581 }
2582
2583 /*
2584 * Modify static constraint with current dynamic
2585 * state of thread
2586 *
2587 * EXCLUSIVE: sibling counter measuring exclusive event
2588 * SHARED : sibling counter measuring non-exclusive event
2589 * UNUSED : sibling counter unused
2590 */
2591 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
2592 /*
2593 * exclusive event in sibling counter
2594 * our corresponding counter cannot be used
2595 * regardless of our event
2596 */
2597 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
2598 __clear_bit(i, c->idxmsk);
2599 /*
2600 * if measuring an exclusive event, sibling
2601 * measuring non-exclusive, then counter cannot
2602 * be used
2603 */
2604 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED)
2605 __clear_bit(i, c->idxmsk);
2606 }
2607
2608 /*
2609 * recompute actual bit weight for scheduling algorithm
2610 */
2611 c->weight = hweight64(c->idxmsk64);
2612
2613 /*
2614 * if we return an empty mask, then switch
2615 * back to static empty constraint to avoid
2616 * the cost of freeing later on
2617 */
2618 if (c->weight == 0)
2619 c = &emptyconstraint;
2620
2621 return c;
2622 }
2623
2624 static struct event_constraint *
2625 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2626 struct perf_event *event)
2627 {
2628 struct event_constraint *c1 = NULL;
2629 struct event_constraint *c2;
2630
2631 if (idx >= 0) /* fake does < 0 */
2632 c1 = cpuc->event_constraint[idx];
2633
2634 /*
2635 * first time only
2636 * - static constraint: no change across incremental scheduling calls
2637 * - dynamic constraint: handled by intel_get_excl_constraints()
2638 */
2639 c2 = __intel_get_event_constraints(cpuc, idx, event);
2640 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2641 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2642 c1->weight = c2->weight;
2643 c2 = c1;
2644 }
2645
2646 if (cpuc->excl_cntrs)
2647 return intel_get_excl_constraints(cpuc, event, idx, c2);
2648
2649 return c2;
2650 }
2651
2652 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2653 struct perf_event *event)
2654 {
2655 struct hw_perf_event *hwc = &event->hw;
2656 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2657 int tid = cpuc->excl_thread_id;
2658 struct intel_excl_states *xl;
2659
2660 /*
2661 * nothing needed if in group validation mode
2662 */
2663 if (cpuc->is_fake)
2664 return;
2665
2666 if (WARN_ON_ONCE(!excl_cntrs))
2667 return;
2668
2669 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2670 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2671 if (!--cpuc->n_excl)
2672 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2673 }
2674
2675 /*
2676 * If event was actually assigned, then mark the counter state as
2677 * unused now.
2678 */
2679 if (hwc->idx >= 0) {
2680 xl = &excl_cntrs->states[tid];
2681
2682 /*
2683 * put_constraint may be called from x86_schedule_events()
2684 * which already has the lock held so here make locking
2685 * conditional.
2686 */
2687 if (!xl->sched_started)
2688 raw_spin_lock(&excl_cntrs->lock);
2689
2690 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
2691
2692 if (!xl->sched_started)
2693 raw_spin_unlock(&excl_cntrs->lock);
2694 }
2695 }
2696
2697 static void
2698 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
2699 struct perf_event *event)
2700 {
2701 struct hw_perf_event_extra *reg;
2702
2703 reg = &event->hw.extra_reg;
2704 if (reg->idx != EXTRA_REG_NONE)
2705 __intel_shared_reg_put_constraints(cpuc, reg);
2706
2707 reg = &event->hw.branch_reg;
2708 if (reg->idx != EXTRA_REG_NONE)
2709 __intel_shared_reg_put_constraints(cpuc, reg);
2710 }
2711
2712 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2713 struct perf_event *event)
2714 {
2715 intel_put_shared_regs_event_constraints(cpuc, event);
2716
2717 /*
2718 * is PMU has exclusive counter restrictions, then
2719 * all events are subject to and must call the
2720 * put_excl_constraints() routine
2721 */
2722 if (cpuc->excl_cntrs)
2723 intel_put_excl_constraints(cpuc, event);
2724 }
2725
2726 static void intel_pebs_aliases_core2(struct perf_event *event)
2727 {
2728 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2729 /*
2730 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2731 * (0x003c) so that we can use it with PEBS.
2732 *
2733 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2734 * PEBS capable. However we can use INST_RETIRED.ANY_P
2735 * (0x00c0), which is a PEBS capable event, to get the same
2736 * count.
2737 *
2738 * INST_RETIRED.ANY_P counts the number of cycles that retires
2739 * CNTMASK instructions. By setting CNTMASK to a value (16)
2740 * larger than the maximum number of instructions that can be
2741 * retired per cycle (4) and then inverting the condition, we
2742 * count all cycles that retire 16 or less instructions, which
2743 * is every cycle.
2744 *
2745 * Thereby we gain a PEBS capable cycle counter.
2746 */
2747 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2748
2749 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2750 event->hw.config = alt_config;
2751 }
2752 }
2753
2754 static void intel_pebs_aliases_snb(struct perf_event *event)
2755 {
2756 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2757 /*
2758 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2759 * (0x003c) so that we can use it with PEBS.
2760 *
2761 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2762 * PEBS capable. However we can use UOPS_RETIRED.ALL
2763 * (0x01c2), which is a PEBS capable event, to get the same
2764 * count.
2765 *
2766 * UOPS_RETIRED.ALL counts the number of cycles that retires
2767 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2768 * larger than the maximum number of micro-ops that can be
2769 * retired per cycle (4) and then inverting the condition, we
2770 * count all cycles that retire 16 or less micro-ops, which
2771 * is every cycle.
2772 *
2773 * Thereby we gain a PEBS capable cycle counter.
2774 */
2775 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
2776
2777 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2778 event->hw.config = alt_config;
2779 }
2780 }
2781
2782 static void intel_pebs_aliases_precdist(struct perf_event *event)
2783 {
2784 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2785 /*
2786 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2787 * (0x003c) so that we can use it with PEBS.
2788 *
2789 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2790 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
2791 * (0x01c0), which is a PEBS capable event, to get the same
2792 * count.
2793 *
2794 * The PREC_DIST event has special support to minimize sample
2795 * shadowing effects. One drawback is that it can be
2796 * only programmed on counter 1, but that seems like an
2797 * acceptable trade off.
2798 */
2799 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
2800
2801 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2802 event->hw.config = alt_config;
2803 }
2804 }
2805
2806 static void intel_pebs_aliases_ivb(struct perf_event *event)
2807 {
2808 if (event->attr.precise_ip < 3)
2809 return intel_pebs_aliases_snb(event);
2810 return intel_pebs_aliases_precdist(event);
2811 }
2812
2813 static void intel_pebs_aliases_skl(struct perf_event *event)
2814 {
2815 if (event->attr.precise_ip < 3)
2816 return intel_pebs_aliases_core2(event);
2817 return intel_pebs_aliases_precdist(event);
2818 }
2819
2820 static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
2821 {
2822 unsigned long flags = x86_pmu.free_running_flags;
2823
2824 if (event->attr.use_clockid)
2825 flags &= ~PERF_SAMPLE_TIME;
2826 return flags;
2827 }
2828
2829 static int intel_pmu_hw_config(struct perf_event *event)
2830 {
2831 int ret = x86_pmu_hw_config(event);
2832
2833 if (ret)
2834 return ret;
2835
2836 if (event->attr.precise_ip) {
2837 if (!event->attr.freq) {
2838 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
2839 if (!(event->attr.sample_type &
2840 ~intel_pmu_free_running_flags(event)))
2841 event->hw.flags |= PERF_X86_EVENT_FREERUNNING;
2842 }
2843 if (x86_pmu.pebs_aliases)
2844 x86_pmu.pebs_aliases(event);
2845 }
2846
2847 if (needs_branch_stack(event)) {
2848 ret = intel_pmu_setup_lbr_filter(event);
2849 if (ret)
2850 return ret;
2851
2852 /*
2853 * BTS is set up earlier in this path, so don't account twice
2854 */
2855 if (!intel_pmu_has_bts(event)) {
2856 /* disallow lbr if conflicting events are present */
2857 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
2858 return -EBUSY;
2859
2860 event->destroy = hw_perf_lbr_event_destroy;
2861 }
2862 }
2863
2864 if (event->attr.type != PERF_TYPE_RAW)
2865 return 0;
2866
2867 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
2868 return 0;
2869
2870 if (x86_pmu.version < 3)
2871 return -EINVAL;
2872
2873 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
2874 return -EACCES;
2875
2876 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
2877
2878 return 0;
2879 }
2880
2881 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
2882 {
2883 if (x86_pmu.guest_get_msrs)
2884 return x86_pmu.guest_get_msrs(nr);
2885 *nr = 0;
2886 return NULL;
2887 }
2888 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
2889
2890 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
2891 {
2892 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2893 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2894
2895 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
2896 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
2897 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
2898 /*
2899 * If PMU counter has PEBS enabled it is not enough to disable counter
2900 * on a guest entry since PEBS memory write can overshoot guest entry
2901 * and corrupt guest memory. Disabling PEBS solves the problem.
2902 */
2903 arr[1].msr = MSR_IA32_PEBS_ENABLE;
2904 arr[1].host = cpuc->pebs_enabled;
2905 arr[1].guest = 0;
2906
2907 *nr = 2;
2908 return arr;
2909 }
2910
2911 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2912 {
2913 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2914 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2915 int idx;
2916
2917 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2918 struct perf_event *event = cpuc->events[idx];
2919
2920 arr[idx].msr = x86_pmu_config_addr(idx);
2921 arr[idx].host = arr[idx].guest = 0;
2922
2923 if (!test_bit(idx, cpuc->active_mask))
2924 continue;
2925
2926 arr[idx].host = arr[idx].guest =
2927 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2928
2929 if (event->attr.exclude_host)
2930 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2931 else if (event->attr.exclude_guest)
2932 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2933 }
2934
2935 *nr = x86_pmu.num_counters;
2936 return arr;
2937 }
2938
2939 static void core_pmu_enable_event(struct perf_event *event)
2940 {
2941 if (!event->attr.exclude_host)
2942 x86_pmu_enable_event(event);
2943 }
2944
2945 static void core_pmu_enable_all(int added)
2946 {
2947 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2948 int idx;
2949
2950 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2951 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2952
2953 if (!test_bit(idx, cpuc->active_mask) ||
2954 cpuc->events[idx]->attr.exclude_host)
2955 continue;
2956
2957 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2958 }
2959 }
2960
2961 static int hsw_hw_config(struct perf_event *event)
2962 {
2963 int ret = intel_pmu_hw_config(event);
2964
2965 if (ret)
2966 return ret;
2967 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2968 return 0;
2969 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2970
2971 /*
2972 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2973 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2974 * this combination.
2975 */
2976 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2977 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2978 event->attr.precise_ip > 0))
2979 return -EOPNOTSUPP;
2980
2981 if (event_is_checkpointed(event)) {
2982 /*
2983 * Sampling of checkpointed events can cause situations where
2984 * the CPU constantly aborts because of a overflow, which is
2985 * then checkpointed back and ignored. Forbid checkpointing
2986 * for sampling.
2987 *
2988 * But still allow a long sampling period, so that perf stat
2989 * from KVM works.
2990 */
2991 if (event->attr.sample_period > 0 &&
2992 event->attr.sample_period < 0x7fffffff)
2993 return -EOPNOTSUPP;
2994 }
2995 return 0;
2996 }
2997
2998 static struct event_constraint counter2_constraint =
2999 EVENT_CONSTRAINT(0, 0x4, 0);
3000
3001 static struct event_constraint *
3002 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3003 struct perf_event *event)
3004 {
3005 struct event_constraint *c;
3006
3007 c = intel_get_event_constraints(cpuc, idx, event);
3008
3009 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
3010 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
3011 if (c->idxmsk64 & (1U << 2))
3012 return &counter2_constraint;
3013 return &emptyconstraint;
3014 }
3015
3016 return c;
3017 }
3018
3019 /*
3020 * Broadwell:
3021 *
3022 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
3023 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
3024 * the two to enforce a minimum period of 128 (the smallest value that has bits
3025 * 0-5 cleared and >= 100).
3026 *
3027 * Because of how the code in x86_perf_event_set_period() works, the truncation
3028 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
3029 * to make up for the 'lost' events due to carrying the 'error' in period_left.
3030 *
3031 * Therefore the effective (average) period matches the requested period,
3032 * despite coarser hardware granularity.
3033 */
3034 static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
3035 {
3036 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
3037 X86_CONFIG(.event=0xc0, .umask=0x01)) {
3038 if (left < 128)
3039 left = 128;
3040 left &= ~0x3fu;
3041 }
3042 return left;
3043 }
3044
3045 PMU_FORMAT_ATTR(event, "config:0-7" );
3046 PMU_FORMAT_ATTR(umask, "config:8-15" );
3047 PMU_FORMAT_ATTR(edge, "config:18" );
3048 PMU_FORMAT_ATTR(pc, "config:19" );
3049 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
3050 PMU_FORMAT_ATTR(inv, "config:23" );
3051 PMU_FORMAT_ATTR(cmask, "config:24-31" );
3052 PMU_FORMAT_ATTR(in_tx, "config:32");
3053 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
3054
3055 static struct attribute *intel_arch_formats_attr[] = {
3056 &format_attr_event.attr,
3057 &format_attr_umask.attr,
3058 &format_attr_edge.attr,
3059 &format_attr_pc.attr,
3060 &format_attr_inv.attr,
3061 &format_attr_cmask.attr,
3062 NULL,
3063 };
3064
3065 ssize_t intel_event_sysfs_show(char *page, u64 config)
3066 {
3067 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
3068
3069 return x86_event_sysfs_show(page, config, event);
3070 }
3071
3072 struct intel_shared_regs *allocate_shared_regs(int cpu)
3073 {
3074 struct intel_shared_regs *regs;
3075 int i;
3076
3077 regs = kzalloc_node(sizeof(struct intel_shared_regs),
3078 GFP_KERNEL, cpu_to_node(cpu));
3079 if (regs) {
3080 /*
3081 * initialize the locks to keep lockdep happy
3082 */
3083 for (i = 0; i < EXTRA_REG_MAX; i++)
3084 raw_spin_lock_init(&regs->regs[i].lock);
3085
3086 regs->core_id = -1;
3087 }
3088 return regs;
3089 }
3090
3091 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
3092 {
3093 struct intel_excl_cntrs *c;
3094
3095 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
3096 GFP_KERNEL, cpu_to_node(cpu));
3097 if (c) {
3098 raw_spin_lock_init(&c->lock);
3099 c->core_id = -1;
3100 }
3101 return c;
3102 }
3103
3104 static int intel_pmu_cpu_prepare(int cpu)
3105 {
3106 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3107
3108 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
3109 cpuc->shared_regs = allocate_shared_regs(cpu);
3110 if (!cpuc->shared_regs)
3111 goto err;
3112 }
3113
3114 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3115 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
3116
3117 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
3118 if (!cpuc->constraint_list)
3119 goto err_shared_regs;
3120
3121 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
3122 if (!cpuc->excl_cntrs)
3123 goto err_constraint_list;
3124
3125 cpuc->excl_thread_id = 0;
3126 }
3127
3128 return 0;
3129
3130 err_constraint_list:
3131 kfree(cpuc->constraint_list);
3132 cpuc->constraint_list = NULL;
3133
3134 err_shared_regs:
3135 kfree(cpuc->shared_regs);
3136 cpuc->shared_regs = NULL;
3137
3138 err:
3139 return -ENOMEM;
3140 }
3141
3142 static void intel_pmu_cpu_starting(int cpu)
3143 {
3144 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3145 int core_id = topology_core_id(cpu);
3146 int i;
3147
3148 init_debug_store_on_cpu(cpu);
3149 /*
3150 * Deal with CPUs that don't clear their LBRs on power-up.
3151 */
3152 intel_pmu_lbr_reset();
3153
3154 cpuc->lbr_sel = NULL;
3155
3156 if (!cpuc->shared_regs)
3157 return;
3158
3159 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
3160 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
3161 struct intel_shared_regs *pc;
3162
3163 pc = per_cpu(cpu_hw_events, i).shared_regs;
3164 if (pc && pc->core_id == core_id) {
3165 cpuc->kfree_on_online[0] = cpuc->shared_regs;
3166 cpuc->shared_regs = pc;
3167 break;
3168 }
3169 }
3170 cpuc->shared_regs->core_id = core_id;
3171 cpuc->shared_regs->refcnt++;
3172 }
3173
3174 if (x86_pmu.lbr_sel_map)
3175 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
3176
3177 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3178 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
3179 struct cpu_hw_events *sibling;
3180 struct intel_excl_cntrs *c;
3181
3182 sibling = &per_cpu(cpu_hw_events, i);
3183 c = sibling->excl_cntrs;
3184 if (c && c->core_id == core_id) {
3185 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
3186 cpuc->excl_cntrs = c;
3187 if (!sibling->excl_thread_id)
3188 cpuc->excl_thread_id = 1;
3189 break;
3190 }
3191 }
3192 cpuc->excl_cntrs->core_id = core_id;
3193 cpuc->excl_cntrs->refcnt++;
3194 }
3195 }
3196
3197 static void free_excl_cntrs(int cpu)
3198 {
3199 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3200 struct intel_excl_cntrs *c;
3201
3202 c = cpuc->excl_cntrs;
3203 if (c) {
3204 if (c->core_id == -1 || --c->refcnt == 0)
3205 kfree(c);
3206 cpuc->excl_cntrs = NULL;
3207 kfree(cpuc->constraint_list);
3208 cpuc->constraint_list = NULL;
3209 }
3210 }
3211
3212 static void intel_pmu_cpu_dying(int cpu)
3213 {
3214 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3215 struct intel_shared_regs *pc;
3216
3217 pc = cpuc->shared_regs;
3218 if (pc) {
3219 if (pc->core_id == -1 || --pc->refcnt == 0)
3220 kfree(pc);
3221 cpuc->shared_regs = NULL;
3222 }
3223
3224 free_excl_cntrs(cpu);
3225
3226 fini_debug_store_on_cpu(cpu);
3227 }
3228
3229 static void intel_pmu_sched_task(struct perf_event_context *ctx,
3230 bool sched_in)
3231 {
3232 if (x86_pmu.pebs_active)
3233 intel_pmu_pebs_sched_task(ctx, sched_in);
3234 if (x86_pmu.lbr_nr)
3235 intel_pmu_lbr_sched_task(ctx, sched_in);
3236 }
3237
3238 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
3239
3240 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
3241
3242 PMU_FORMAT_ATTR(frontend, "config1:0-23");
3243
3244 static struct attribute *intel_arch3_formats_attr[] = {
3245 &format_attr_event.attr,
3246 &format_attr_umask.attr,
3247 &format_attr_edge.attr,
3248 &format_attr_pc.attr,
3249 &format_attr_any.attr,
3250 &format_attr_inv.attr,
3251 &format_attr_cmask.attr,
3252 &format_attr_in_tx.attr,
3253 &format_attr_in_tx_cp.attr,
3254
3255 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
3256 &format_attr_ldlat.attr, /* PEBS load latency */
3257 NULL,
3258 };
3259
3260 static struct attribute *skl_format_attr[] = {
3261 &format_attr_frontend.attr,
3262 NULL,
3263 };
3264
3265 static __initconst const struct x86_pmu core_pmu = {
3266 .name = "core",
3267 .handle_irq = x86_pmu_handle_irq,
3268 .disable_all = x86_pmu_disable_all,
3269 .enable_all = core_pmu_enable_all,
3270 .enable = core_pmu_enable_event,
3271 .disable = x86_pmu_disable_event,
3272 .hw_config = x86_pmu_hw_config,
3273 .schedule_events = x86_schedule_events,
3274 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3275 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3276 .event_map = intel_pmu_event_map,
3277 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3278 .apic = 1,
3279 .free_running_flags = PEBS_FREERUNNING_FLAGS,
3280
3281 /*
3282 * Intel PMCs cannot be accessed sanely above 32-bit width,
3283 * so we install an artificial 1<<31 period regardless of
3284 * the generic event period:
3285 */
3286 .max_period = (1ULL<<31) - 1,
3287 .get_event_constraints = intel_get_event_constraints,
3288 .put_event_constraints = intel_put_event_constraints,
3289 .event_constraints = intel_core_event_constraints,
3290 .guest_get_msrs = core_guest_get_msrs,
3291 .format_attrs = intel_arch_formats_attr,
3292 .events_sysfs_show = intel_event_sysfs_show,
3293
3294 /*
3295 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
3296 * together with PMU version 1 and thus be using core_pmu with
3297 * shared_regs. We need following callbacks here to allocate
3298 * it properly.
3299 */
3300 .cpu_prepare = intel_pmu_cpu_prepare,
3301 .cpu_starting = intel_pmu_cpu_starting,
3302 .cpu_dying = intel_pmu_cpu_dying,
3303 };
3304
3305 static __initconst const struct x86_pmu intel_pmu = {
3306 .name = "Intel",
3307 .handle_irq = intel_pmu_handle_irq,
3308 .disable_all = intel_pmu_disable_all,
3309 .enable_all = intel_pmu_enable_all,
3310 .enable = intel_pmu_enable_event,
3311 .disable = intel_pmu_disable_event,
3312 .add = intel_pmu_add_event,
3313 .del = intel_pmu_del_event,
3314 .hw_config = intel_pmu_hw_config,
3315 .schedule_events = x86_schedule_events,
3316 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3317 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3318 .event_map = intel_pmu_event_map,
3319 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3320 .apic = 1,
3321 .free_running_flags = PEBS_FREERUNNING_FLAGS,
3322 /*
3323 * Intel PMCs cannot be accessed sanely above 32 bit width,
3324 * so we install an artificial 1<<31 period regardless of
3325 * the generic event period:
3326 */
3327 .max_period = (1ULL << 31) - 1,
3328 .get_event_constraints = intel_get_event_constraints,
3329 .put_event_constraints = intel_put_event_constraints,
3330 .pebs_aliases = intel_pebs_aliases_core2,
3331
3332 .format_attrs = intel_arch3_formats_attr,
3333 .events_sysfs_show = intel_event_sysfs_show,
3334
3335 .cpu_prepare = intel_pmu_cpu_prepare,
3336 .cpu_starting = intel_pmu_cpu_starting,
3337 .cpu_dying = intel_pmu_cpu_dying,
3338 .guest_get_msrs = intel_guest_get_msrs,
3339 .sched_task = intel_pmu_sched_task,
3340 };
3341
3342 static __init void intel_clovertown_quirk(void)
3343 {
3344 /*
3345 * PEBS is unreliable due to:
3346 *
3347 * AJ67 - PEBS may experience CPL leaks
3348 * AJ68 - PEBS PMI may be delayed by one event
3349 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
3350 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
3351 *
3352 * AJ67 could be worked around by restricting the OS/USR flags.
3353 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
3354 *
3355 * AJ106 could possibly be worked around by not allowing LBR
3356 * usage from PEBS, including the fixup.
3357 * AJ68 could possibly be worked around by always programming
3358 * a pebs_event_reset[0] value and coping with the lost events.
3359 *
3360 * But taken together it might just make sense to not enable PEBS on
3361 * these chips.
3362 */
3363 pr_warn("PEBS disabled due to CPU errata\n");
3364 x86_pmu.pebs = 0;
3365 x86_pmu.pebs_constraints = NULL;
3366 }
3367
3368 static int intel_snb_pebs_broken(int cpu)
3369 {
3370 u32 rev = UINT_MAX; /* default to broken for unknown models */
3371
3372 switch (cpu_data(cpu).x86_model) {
3373 case INTEL_FAM6_SANDYBRIDGE:
3374 rev = 0x28;
3375 break;
3376
3377 case INTEL_FAM6_SANDYBRIDGE_X:
3378 switch (cpu_data(cpu).x86_mask) {
3379 case 6: rev = 0x618; break;
3380 case 7: rev = 0x70c; break;
3381 }
3382 }
3383
3384 return (cpu_data(cpu).microcode < rev);
3385 }
3386
3387 static void intel_snb_check_microcode(void)
3388 {
3389 int pebs_broken = 0;
3390 int cpu;
3391
3392 get_online_cpus();
3393 for_each_online_cpu(cpu) {
3394 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
3395 break;
3396 }
3397 put_online_cpus();
3398
3399 if (pebs_broken == x86_pmu.pebs_broken)
3400 return;
3401
3402 /*
3403 * Serialized by the microcode lock..
3404 */
3405 if (x86_pmu.pebs_broken) {
3406 pr_info("PEBS enabled due to microcode update\n");
3407 x86_pmu.pebs_broken = 0;
3408 } else {
3409 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
3410 x86_pmu.pebs_broken = 1;
3411 }
3412 }
3413
3414 static bool is_lbr_from(unsigned long msr)
3415 {
3416 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
3417
3418 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
3419 }
3420
3421 /*
3422 * Under certain circumstances, access certain MSR may cause #GP.
3423 * The function tests if the input MSR can be safely accessed.
3424 */
3425 static bool check_msr(unsigned long msr, u64 mask)
3426 {
3427 u64 val_old, val_new, val_tmp;
3428
3429 /*
3430 * Read the current value, change it and read it back to see if it
3431 * matches, this is needed to detect certain hardware emulators
3432 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
3433 */
3434 if (rdmsrl_safe(msr, &val_old))
3435 return false;
3436
3437 /*
3438 * Only change the bits which can be updated by wrmsrl.
3439 */
3440 val_tmp = val_old ^ mask;
3441
3442 if (is_lbr_from(msr))
3443 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
3444
3445 if (wrmsrl_safe(msr, val_tmp) ||
3446 rdmsrl_safe(msr, &val_new))
3447 return false;
3448
3449 /*
3450 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
3451 * should equal rdmsrl()'s even with the quirk.
3452 */
3453 if (val_new != val_tmp)
3454 return false;
3455
3456 if (is_lbr_from(msr))
3457 val_old = lbr_from_signext_quirk_wr(val_old);
3458
3459 /* Here it's sure that the MSR can be safely accessed.
3460 * Restore the old value and return.
3461 */
3462 wrmsrl(msr, val_old);
3463
3464 return true;
3465 }
3466
3467 static __init void intel_sandybridge_quirk(void)
3468 {
3469 x86_pmu.check_microcode = intel_snb_check_microcode;
3470 intel_snb_check_microcode();
3471 }
3472
3473 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
3474 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
3475 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
3476 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
3477 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
3478 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
3479 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
3480 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
3481 };
3482
3483 static __init void intel_arch_events_quirk(void)
3484 {
3485 int bit;
3486
3487 /* disable event that reported as not presend by cpuid */
3488 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
3489 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
3490 pr_warn("CPUID marked event: \'%s\' unavailable\n",
3491 intel_arch_events_map[bit].name);
3492 }
3493 }
3494
3495 static __init void intel_nehalem_quirk(void)
3496 {
3497 union cpuid10_ebx ebx;
3498
3499 ebx.full = x86_pmu.events_maskl;
3500 if (ebx.split.no_branch_misses_retired) {
3501 /*
3502 * Erratum AAJ80 detected, we work it around by using
3503 * the BR_MISP_EXEC.ANY event. This will over-count
3504 * branch-misses, but it's still much better than the
3505 * architectural event which is often completely bogus:
3506 */
3507 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
3508 ebx.split.no_branch_misses_retired = 0;
3509 x86_pmu.events_maskl = ebx.full;
3510 pr_info("CPU erratum AAJ80 worked around\n");
3511 }
3512 }
3513
3514 /*
3515 * enable software workaround for errata:
3516 * SNB: BJ122
3517 * IVB: BV98
3518 * HSW: HSD29
3519 *
3520 * Only needed when HT is enabled. However detecting
3521 * if HT is enabled is difficult (model specific). So instead,
3522 * we enable the workaround in the early boot, and verify if
3523 * it is needed in a later initcall phase once we have valid
3524 * topology information to check if HT is actually enabled
3525 */
3526 static __init void intel_ht_bug(void)
3527 {
3528 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
3529
3530 x86_pmu.start_scheduling = intel_start_scheduling;
3531 x86_pmu.commit_scheduling = intel_commit_scheduling;
3532 x86_pmu.stop_scheduling = intel_stop_scheduling;
3533 }
3534
3535 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
3536 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
3537
3538 /* Haswell special events */
3539 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
3540 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
3541 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
3542 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
3543 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
3544 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
3545 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
3546 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
3547 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
3548 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
3549 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
3550 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
3551
3552 static struct attribute *hsw_events_attrs[] = {
3553 EVENT_PTR(tx_start),
3554 EVENT_PTR(tx_commit),
3555 EVENT_PTR(tx_abort),
3556 EVENT_PTR(tx_capacity),
3557 EVENT_PTR(tx_conflict),
3558 EVENT_PTR(el_start),
3559 EVENT_PTR(el_commit),
3560 EVENT_PTR(el_abort),
3561 EVENT_PTR(el_capacity),
3562 EVENT_PTR(el_conflict),
3563 EVENT_PTR(cycles_t),
3564 EVENT_PTR(cycles_ct),
3565 EVENT_PTR(mem_ld_hsw),
3566 EVENT_PTR(mem_st_hsw),
3567 EVENT_PTR(td_slots_issued),
3568 EVENT_PTR(td_slots_retired),
3569 EVENT_PTR(td_fetch_bubbles),
3570 EVENT_PTR(td_total_slots),
3571 EVENT_PTR(td_total_slots_scale),
3572 EVENT_PTR(td_recovery_bubbles),
3573 EVENT_PTR(td_recovery_bubbles_scale),
3574 NULL
3575 };
3576
3577 __init int intel_pmu_init(void)
3578 {
3579 union cpuid10_edx edx;
3580 union cpuid10_eax eax;
3581 union cpuid10_ebx ebx;
3582 struct event_constraint *c;
3583 unsigned int unused;
3584 struct extra_reg *er;
3585 int version, i;
3586
3587 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
3588 switch (boot_cpu_data.x86) {
3589 case 0x6:
3590 return p6_pmu_init();
3591 case 0xb:
3592 return knc_pmu_init();
3593 case 0xf:
3594 return p4_pmu_init();
3595 }
3596 return -ENODEV;
3597 }
3598
3599 /*
3600 * Check whether the Architectural PerfMon supports
3601 * Branch Misses Retired hw_event or not.
3602 */
3603 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
3604 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
3605 return -ENODEV;
3606
3607 version = eax.split.version_id;
3608 if (version < 2)
3609 x86_pmu = core_pmu;
3610 else
3611 x86_pmu = intel_pmu;
3612
3613 x86_pmu.version = version;
3614 x86_pmu.num_counters = eax.split.num_counters;
3615 x86_pmu.cntval_bits = eax.split.bit_width;
3616 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
3617
3618 x86_pmu.events_maskl = ebx.full;
3619 x86_pmu.events_mask_len = eax.split.mask_length;
3620
3621 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
3622
3623 /*
3624 * Quirk: v2 perfmon does not report fixed-purpose events, so
3625 * assume at least 3 events, when not running in a hypervisor:
3626 */
3627 if (version > 1) {
3628 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
3629
3630 x86_pmu.num_counters_fixed =
3631 max((int)edx.split.num_counters_fixed, assume);
3632 }
3633
3634 if (boot_cpu_has(X86_FEATURE_PDCM)) {
3635 u64 capabilities;
3636
3637 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
3638 x86_pmu.intel_cap.capabilities = capabilities;
3639 }
3640
3641 intel_ds_init();
3642
3643 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
3644
3645 /*
3646 * Install the hw-cache-events table:
3647 */
3648 switch (boot_cpu_data.x86_model) {
3649 case INTEL_FAM6_CORE_YONAH:
3650 pr_cont("Core events, ");
3651 break;
3652
3653 case INTEL_FAM6_CORE2_MEROM:
3654 x86_add_quirk(intel_clovertown_quirk);
3655 case INTEL_FAM6_CORE2_MEROM_L:
3656 case INTEL_FAM6_CORE2_PENRYN:
3657 case INTEL_FAM6_CORE2_DUNNINGTON:
3658 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3659 sizeof(hw_cache_event_ids));
3660
3661 intel_pmu_lbr_init_core();
3662
3663 x86_pmu.event_constraints = intel_core2_event_constraints;
3664 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
3665 pr_cont("Core2 events, ");
3666 break;
3667
3668 case INTEL_FAM6_NEHALEM:
3669 case INTEL_FAM6_NEHALEM_EP:
3670 case INTEL_FAM6_NEHALEM_EX:
3671 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3672 sizeof(hw_cache_event_ids));
3673 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3674 sizeof(hw_cache_extra_regs));
3675
3676 intel_pmu_lbr_init_nhm();
3677
3678 x86_pmu.event_constraints = intel_nehalem_event_constraints;
3679 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
3680 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3681 x86_pmu.extra_regs = intel_nehalem_extra_regs;
3682
3683 x86_pmu.cpu_events = nhm_events_attrs;
3684
3685 /* UOPS_ISSUED.STALLED_CYCLES */
3686 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3687 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3688 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3689 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3690 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3691
3692 intel_pmu_pebs_data_source_nhm();
3693 x86_add_quirk(intel_nehalem_quirk);
3694
3695 pr_cont("Nehalem events, ");
3696 break;
3697
3698 case INTEL_FAM6_ATOM_PINEVIEW:
3699 case INTEL_FAM6_ATOM_LINCROFT:
3700 case INTEL_FAM6_ATOM_PENWELL:
3701 case INTEL_FAM6_ATOM_CLOVERVIEW:
3702 case INTEL_FAM6_ATOM_CEDARVIEW:
3703 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
3704 sizeof(hw_cache_event_ids));
3705
3706 intel_pmu_lbr_init_atom();
3707
3708 x86_pmu.event_constraints = intel_gen_event_constraints;
3709 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
3710 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
3711 pr_cont("Atom events, ");
3712 break;
3713
3714 case INTEL_FAM6_ATOM_SILVERMONT1:
3715 case INTEL_FAM6_ATOM_SILVERMONT2:
3716 case INTEL_FAM6_ATOM_AIRMONT:
3717 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
3718 sizeof(hw_cache_event_ids));
3719 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
3720 sizeof(hw_cache_extra_regs));
3721
3722 intel_pmu_lbr_init_slm();
3723
3724 x86_pmu.event_constraints = intel_slm_event_constraints;
3725 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3726 x86_pmu.extra_regs = intel_slm_extra_regs;
3727 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3728 x86_pmu.cpu_events = slm_events_attrs;
3729 pr_cont("Silvermont events, ");
3730 break;
3731
3732 case INTEL_FAM6_ATOM_GOLDMONT:
3733 case INTEL_FAM6_ATOM_DENVERTON:
3734 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
3735 sizeof(hw_cache_event_ids));
3736 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
3737 sizeof(hw_cache_extra_regs));
3738
3739 intel_pmu_lbr_init_skl();
3740
3741 x86_pmu.event_constraints = intel_slm_event_constraints;
3742 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
3743 x86_pmu.extra_regs = intel_glm_extra_regs;
3744 /*
3745 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
3746 * for precise cycles.
3747 * :pp is identical to :ppp
3748 */
3749 x86_pmu.pebs_aliases = NULL;
3750 x86_pmu.pebs_prec_dist = true;
3751 x86_pmu.lbr_pt_coexist = true;
3752 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3753 pr_cont("Goldmont events, ");
3754 break;
3755
3756 case INTEL_FAM6_WESTMERE:
3757 case INTEL_FAM6_WESTMERE_EP:
3758 case INTEL_FAM6_WESTMERE_EX:
3759 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
3760 sizeof(hw_cache_event_ids));
3761 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3762 sizeof(hw_cache_extra_regs));
3763
3764 intel_pmu_lbr_init_nhm();
3765
3766 x86_pmu.event_constraints = intel_westmere_event_constraints;
3767 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3768 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
3769 x86_pmu.extra_regs = intel_westmere_extra_regs;
3770 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3771
3772 x86_pmu.cpu_events = nhm_events_attrs;
3773
3774 /* UOPS_ISSUED.STALLED_CYCLES */
3775 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3776 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3777 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3778 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3779 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3780
3781 intel_pmu_pebs_data_source_nhm();
3782 pr_cont("Westmere events, ");
3783 break;
3784
3785 case INTEL_FAM6_SANDYBRIDGE:
3786 case INTEL_FAM6_SANDYBRIDGE_X:
3787 x86_add_quirk(intel_sandybridge_quirk);
3788 x86_add_quirk(intel_ht_bug);
3789 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3790 sizeof(hw_cache_event_ids));
3791 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3792 sizeof(hw_cache_extra_regs));
3793
3794 intel_pmu_lbr_init_snb();
3795
3796 x86_pmu.event_constraints = intel_snb_event_constraints;
3797 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
3798 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3799 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
3800 x86_pmu.extra_regs = intel_snbep_extra_regs;
3801 else
3802 x86_pmu.extra_regs = intel_snb_extra_regs;
3803
3804
3805 /* all extra regs are per-cpu when HT is on */
3806 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3807 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3808
3809 x86_pmu.cpu_events = snb_events_attrs;
3810
3811 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3812 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3813 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3814 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
3815 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3816 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
3817
3818 pr_cont("SandyBridge events, ");
3819 break;
3820
3821 case INTEL_FAM6_IVYBRIDGE:
3822 case INTEL_FAM6_IVYBRIDGE_X:
3823 x86_add_quirk(intel_ht_bug);
3824 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3825 sizeof(hw_cache_event_ids));
3826 /* dTLB-load-misses on IVB is different than SNB */
3827 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3828
3829 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3830 sizeof(hw_cache_extra_regs));
3831
3832 intel_pmu_lbr_init_snb();
3833
3834 x86_pmu.event_constraints = intel_ivb_event_constraints;
3835 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
3836 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3837 x86_pmu.pebs_prec_dist = true;
3838 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
3839 x86_pmu.extra_regs = intel_snbep_extra_regs;
3840 else
3841 x86_pmu.extra_regs = intel_snb_extra_regs;
3842 /* all extra regs are per-cpu when HT is on */
3843 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3844 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3845
3846 x86_pmu.cpu_events = snb_events_attrs;
3847
3848 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3849 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3850 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3851
3852 pr_cont("IvyBridge events, ");
3853 break;
3854
3855
3856 case INTEL_FAM6_HASWELL_CORE:
3857 case INTEL_FAM6_HASWELL_X:
3858 case INTEL_FAM6_HASWELL_ULT:
3859 case INTEL_FAM6_HASWELL_GT3E:
3860 x86_add_quirk(intel_ht_bug);
3861 x86_pmu.late_ack = true;
3862 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3863 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3864
3865 intel_pmu_lbr_init_hsw();
3866
3867 x86_pmu.event_constraints = intel_hsw_event_constraints;
3868 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3869 x86_pmu.extra_regs = intel_snbep_extra_regs;
3870 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3871 x86_pmu.pebs_prec_dist = true;
3872 /* all extra regs are per-cpu when HT is on */
3873 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3874 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3875
3876 x86_pmu.hw_config = hsw_hw_config;
3877 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3878 x86_pmu.cpu_events = hsw_events_attrs;
3879 x86_pmu.lbr_double_abort = true;
3880 pr_cont("Haswell events, ");
3881 break;
3882
3883 case INTEL_FAM6_BROADWELL_CORE:
3884 case INTEL_FAM6_BROADWELL_XEON_D:
3885 case INTEL_FAM6_BROADWELL_GT3E:
3886 case INTEL_FAM6_BROADWELL_X:
3887 x86_pmu.late_ack = true;
3888 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3889 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3890
3891 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3892 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
3893 BDW_L3_MISS|HSW_SNOOP_DRAM;
3894 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
3895 HSW_SNOOP_DRAM;
3896 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
3897 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3898 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
3899 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3900
3901 intel_pmu_lbr_init_hsw();
3902
3903 x86_pmu.event_constraints = intel_bdw_event_constraints;
3904 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
3905 x86_pmu.extra_regs = intel_snbep_extra_regs;
3906 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3907 x86_pmu.pebs_prec_dist = true;
3908 /* all extra regs are per-cpu when HT is on */
3909 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3910 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3911
3912 x86_pmu.hw_config = hsw_hw_config;
3913 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3914 x86_pmu.cpu_events = hsw_events_attrs;
3915 x86_pmu.limit_period = bdw_limit_period;
3916 pr_cont("Broadwell events, ");
3917 break;
3918
3919 case INTEL_FAM6_XEON_PHI_KNL:
3920 case INTEL_FAM6_XEON_PHI_KNM:
3921 memcpy(hw_cache_event_ids,
3922 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3923 memcpy(hw_cache_extra_regs,
3924 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3925 intel_pmu_lbr_init_knl();
3926
3927 x86_pmu.event_constraints = intel_slm_event_constraints;
3928 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3929 x86_pmu.extra_regs = intel_knl_extra_regs;
3930
3931 /* all extra regs are per-cpu when HT is on */
3932 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3933 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3934
3935 pr_cont("Knights Landing/Mill events, ");
3936 break;
3937
3938 case INTEL_FAM6_SKYLAKE_MOBILE:
3939 case INTEL_FAM6_SKYLAKE_DESKTOP:
3940 case INTEL_FAM6_SKYLAKE_X:
3941 case INTEL_FAM6_KABYLAKE_MOBILE:
3942 case INTEL_FAM6_KABYLAKE_DESKTOP:
3943 x86_pmu.late_ack = true;
3944 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3945 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3946 intel_pmu_lbr_init_skl();
3947
3948 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
3949 event_attr_td_recovery_bubbles.event_str_noht =
3950 "event=0xd,umask=0x1,cmask=1";
3951 event_attr_td_recovery_bubbles.event_str_ht =
3952 "event=0xd,umask=0x1,cmask=1,any=1";
3953
3954 x86_pmu.event_constraints = intel_skl_event_constraints;
3955 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
3956 x86_pmu.extra_regs = intel_skl_extra_regs;
3957 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
3958 x86_pmu.pebs_prec_dist = true;
3959 /* all extra regs are per-cpu when HT is on */
3960 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3961 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3962
3963 x86_pmu.hw_config = hsw_hw_config;
3964 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3965 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
3966 skl_format_attr);
3967 WARN_ON(!x86_pmu.format_attrs);
3968 x86_pmu.cpu_events = hsw_events_attrs;
3969 pr_cont("Skylake events, ");
3970 break;
3971
3972 default:
3973 switch (x86_pmu.version) {
3974 case 1:
3975 x86_pmu.event_constraints = intel_v1_event_constraints;
3976 pr_cont("generic architected perfmon v1, ");
3977 break;
3978 default:
3979 /*
3980 * default constraints for v2 and up
3981 */
3982 x86_pmu.event_constraints = intel_gen_event_constraints;
3983 pr_cont("generic architected perfmon, ");
3984 break;
3985 }
3986 }
3987
3988 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
3989 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
3990 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
3991 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
3992 }
3993 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1;
3994
3995 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
3996 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
3997 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
3998 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
3999 }
4000
4001 x86_pmu.intel_ctrl |=
4002 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
4003
4004 if (x86_pmu.event_constraints) {
4005 /*
4006 * event on fixed counter2 (REF_CYCLES) only works on this
4007 * counter, so do not extend mask to generic counters
4008 */
4009 for_each_event_constraint(c, x86_pmu.event_constraints) {
4010 if (c->cmask == FIXED_EVENT_FLAGS
4011 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
4012 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
4013 }
4014 c->idxmsk64 &=
4015 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
4016 c->weight = hweight64(c->idxmsk64);
4017 }
4018 }
4019
4020 /*
4021 * Access LBR MSR may cause #GP under certain circumstances.
4022 * E.g. KVM doesn't support LBR MSR
4023 * Check all LBT MSR here.
4024 * Disable LBR access if any LBR MSRs can not be accessed.
4025 */
4026 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
4027 x86_pmu.lbr_nr = 0;
4028 for (i = 0; i < x86_pmu.lbr_nr; i++) {
4029 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
4030 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
4031 x86_pmu.lbr_nr = 0;
4032 }
4033
4034 if (x86_pmu.lbr_nr)
4035 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
4036 /*
4037 * Access extra MSR may cause #GP under certain circumstances.
4038 * E.g. KVM doesn't support offcore event
4039 * Check all extra_regs here.
4040 */
4041 if (x86_pmu.extra_regs) {
4042 for (er = x86_pmu.extra_regs; er->msr; er++) {
4043 er->extra_msr_access = check_msr(er->msr, 0x11UL);
4044 /* Disable LBR select mapping */
4045 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
4046 x86_pmu.lbr_sel_map = NULL;
4047 }
4048 }
4049
4050 /* Support full width counters using alternative MSR range */
4051 if (x86_pmu.intel_cap.full_width_write) {
4052 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
4053 x86_pmu.perfctr = MSR_IA32_PMC0;
4054 pr_cont("full-width counters, ");
4055 }
4056
4057 return 0;
4058 }
4059
4060 /*
4061 * HT bug: phase 2 init
4062 * Called once we have valid topology information to check
4063 * whether or not HT is enabled
4064 * If HT is off, then we disable the workaround
4065 */
4066 static __init int fixup_ht_bug(void)
4067 {
4068 int c;
4069 /*
4070 * problem not present on this CPU model, nothing to do
4071 */
4072 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
4073 return 0;
4074
4075 if (topology_max_smt_threads() > 1) {
4076 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
4077 return 0;
4078 }
4079
4080 if (lockup_detector_suspend() != 0) {
4081 pr_debug("failed to disable PMU erratum BJ122, BV98, HSD29 workaround\n");
4082 return 0;
4083 }
4084
4085 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
4086
4087 x86_pmu.start_scheduling = NULL;
4088 x86_pmu.commit_scheduling = NULL;
4089 x86_pmu.stop_scheduling = NULL;
4090
4091 lockup_detector_resume();
4092
4093 get_online_cpus();
4094
4095 for_each_online_cpu(c) {
4096 free_excl_cntrs(c);
4097 }
4098
4099 put_online_cpus();
4100 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
4101 return 0;
4102 }
4103 subsys_initcall(fixup_ht_bug)