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Merge branch 'semaphore' of git://git.kernel.org/pub/scm/linux/kernel/git/willy/misc
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc64 / kernel / time.c
1 /* time.c: UltraSparc timer and TOD clock support.
2 *
3 * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 *
6 * Based largely on code which is:
7 *
8 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
9 */
10
11 #include <linux/errno.h>
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/smp_lock.h>
15 #include <linux/kernel.h>
16 #include <linux/param.h>
17 #include <linux/string.h>
18 #include <linux/mm.h>
19 #include <linux/interrupt.h>
20 #include <linux/time.h>
21 #include <linux/timex.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/delay.h>
26 #include <linux/profile.h>
27 #include <linux/bcd.h>
28 #include <linux/jiffies.h>
29 #include <linux/cpufreq.h>
30 #include <linux/percpu.h>
31 #include <linux/miscdevice.h>
32 #include <linux/rtc.h>
33 #include <linux/kernel_stat.h>
34 #include <linux/clockchips.h>
35 #include <linux/clocksource.h>
36
37 #include <asm/oplib.h>
38 #include <asm/mostek.h>
39 #include <asm/timer.h>
40 #include <asm/irq.h>
41 #include <asm/io.h>
42 #include <asm/prom.h>
43 #include <asm/of_device.h>
44 #include <asm/starfire.h>
45 #include <asm/smp.h>
46 #include <asm/sections.h>
47 #include <asm/cpudata.h>
48 #include <asm/uaccess.h>
49 #include <asm/irq_regs.h>
50
51 #include "entry.h"
52
53 DEFINE_SPINLOCK(mostek_lock);
54 DEFINE_SPINLOCK(rtc_lock);
55 void __iomem *mstk48t02_regs = NULL;
56 #ifdef CONFIG_PCI
57 unsigned long ds1287_regs = 0UL;
58 static void __iomem *bq4802_regs;
59 #endif
60
61 static void __iomem *mstk48t08_regs;
62 static void __iomem *mstk48t59_regs;
63
64 static int set_rtc_mmss(unsigned long);
65
66 #define TICK_PRIV_BIT (1UL << 63)
67 #define TICKCMP_IRQ_BIT (1UL << 63)
68
69 #ifdef CONFIG_SMP
70 unsigned long profile_pc(struct pt_regs *regs)
71 {
72 unsigned long pc = instruction_pointer(regs);
73
74 if (in_lock_functions(pc))
75 return regs->u_regs[UREG_RETPC];
76 return pc;
77 }
78 EXPORT_SYMBOL(profile_pc);
79 #endif
80
81 static void tick_disable_protection(void)
82 {
83 /* Set things up so user can access tick register for profiling
84 * purposes. Also workaround BB_ERRATA_1 by doing a dummy
85 * read back of %tick after writing it.
86 */
87 __asm__ __volatile__(
88 " ba,pt %%xcc, 1f\n"
89 " nop\n"
90 " .align 64\n"
91 "1: rd %%tick, %%g2\n"
92 " add %%g2, 6, %%g2\n"
93 " andn %%g2, %0, %%g2\n"
94 " wrpr %%g2, 0, %%tick\n"
95 " rdpr %%tick, %%g0"
96 : /* no outputs */
97 : "r" (TICK_PRIV_BIT)
98 : "g2");
99 }
100
101 static void tick_disable_irq(void)
102 {
103 __asm__ __volatile__(
104 " ba,pt %%xcc, 1f\n"
105 " nop\n"
106 " .align 64\n"
107 "1: wr %0, 0x0, %%tick_cmpr\n"
108 " rd %%tick_cmpr, %%g0"
109 : /* no outputs */
110 : "r" (TICKCMP_IRQ_BIT));
111 }
112
113 static void tick_init_tick(void)
114 {
115 tick_disable_protection();
116 tick_disable_irq();
117 }
118
119 static unsigned long tick_get_tick(void)
120 {
121 unsigned long ret;
122
123 __asm__ __volatile__("rd %%tick, %0\n\t"
124 "mov %0, %0"
125 : "=r" (ret));
126
127 return ret & ~TICK_PRIV_BIT;
128 }
129
130 static int tick_add_compare(unsigned long adj)
131 {
132 unsigned long orig_tick, new_tick, new_compare;
133
134 __asm__ __volatile__("rd %%tick, %0"
135 : "=r" (orig_tick));
136
137 orig_tick &= ~TICKCMP_IRQ_BIT;
138
139 /* Workaround for Spitfire Errata (#54 I think??), I discovered
140 * this via Sun BugID 4008234, mentioned in Solaris-2.5.1 patch
141 * number 103640.
142 *
143 * On Blackbird writes to %tick_cmpr can fail, the
144 * workaround seems to be to execute the wr instruction
145 * at the start of an I-cache line, and perform a dummy
146 * read back from %tick_cmpr right after writing to it. -DaveM
147 */
148 __asm__ __volatile__("ba,pt %%xcc, 1f\n\t"
149 " add %1, %2, %0\n\t"
150 ".align 64\n"
151 "1:\n\t"
152 "wr %0, 0, %%tick_cmpr\n\t"
153 "rd %%tick_cmpr, %%g0\n\t"
154 : "=r" (new_compare)
155 : "r" (orig_tick), "r" (adj));
156
157 __asm__ __volatile__("rd %%tick, %0"
158 : "=r" (new_tick));
159 new_tick &= ~TICKCMP_IRQ_BIT;
160
161 return ((long)(new_tick - (orig_tick+adj))) > 0L;
162 }
163
164 static unsigned long tick_add_tick(unsigned long adj)
165 {
166 unsigned long new_tick;
167
168 /* Also need to handle Blackbird bug here too. */
169 __asm__ __volatile__("rd %%tick, %0\n\t"
170 "add %0, %1, %0\n\t"
171 "wrpr %0, 0, %%tick\n\t"
172 : "=&r" (new_tick)
173 : "r" (adj));
174
175 return new_tick;
176 }
177
178 static struct sparc64_tick_ops tick_operations __read_mostly = {
179 .name = "tick",
180 .init_tick = tick_init_tick,
181 .disable_irq = tick_disable_irq,
182 .get_tick = tick_get_tick,
183 .add_tick = tick_add_tick,
184 .add_compare = tick_add_compare,
185 .softint_mask = 1UL << 0,
186 };
187
188 struct sparc64_tick_ops *tick_ops __read_mostly = &tick_operations;
189
190 static void stick_disable_irq(void)
191 {
192 __asm__ __volatile__(
193 "wr %0, 0x0, %%asr25"
194 : /* no outputs */
195 : "r" (TICKCMP_IRQ_BIT));
196 }
197
198 static void stick_init_tick(void)
199 {
200 /* Writes to the %tick and %stick register are not
201 * allowed on sun4v. The Hypervisor controls that
202 * bit, per-strand.
203 */
204 if (tlb_type != hypervisor) {
205 tick_disable_protection();
206 tick_disable_irq();
207
208 /* Let the user get at STICK too. */
209 __asm__ __volatile__(
210 " rd %%asr24, %%g2\n"
211 " andn %%g2, %0, %%g2\n"
212 " wr %%g2, 0, %%asr24"
213 : /* no outputs */
214 : "r" (TICK_PRIV_BIT)
215 : "g1", "g2");
216 }
217
218 stick_disable_irq();
219 }
220
221 static unsigned long stick_get_tick(void)
222 {
223 unsigned long ret;
224
225 __asm__ __volatile__("rd %%asr24, %0"
226 : "=r" (ret));
227
228 return ret & ~TICK_PRIV_BIT;
229 }
230
231 static unsigned long stick_add_tick(unsigned long adj)
232 {
233 unsigned long new_tick;
234
235 __asm__ __volatile__("rd %%asr24, %0\n\t"
236 "add %0, %1, %0\n\t"
237 "wr %0, 0, %%asr24\n\t"
238 : "=&r" (new_tick)
239 : "r" (adj));
240
241 return new_tick;
242 }
243
244 static int stick_add_compare(unsigned long adj)
245 {
246 unsigned long orig_tick, new_tick;
247
248 __asm__ __volatile__("rd %%asr24, %0"
249 : "=r" (orig_tick));
250 orig_tick &= ~TICKCMP_IRQ_BIT;
251
252 __asm__ __volatile__("wr %0, 0, %%asr25"
253 : /* no outputs */
254 : "r" (orig_tick + adj));
255
256 __asm__ __volatile__("rd %%asr24, %0"
257 : "=r" (new_tick));
258 new_tick &= ~TICKCMP_IRQ_BIT;
259
260 return ((long)(new_tick - (orig_tick+adj))) > 0L;
261 }
262
263 static struct sparc64_tick_ops stick_operations __read_mostly = {
264 .name = "stick",
265 .init_tick = stick_init_tick,
266 .disable_irq = stick_disable_irq,
267 .get_tick = stick_get_tick,
268 .add_tick = stick_add_tick,
269 .add_compare = stick_add_compare,
270 .softint_mask = 1UL << 16,
271 };
272
273 /* On Hummingbird the STICK/STICK_CMPR register is implemented
274 * in I/O space. There are two 64-bit registers each, the
275 * first holds the low 32-bits of the value and the second holds
276 * the high 32-bits.
277 *
278 * Since STICK is constantly updating, we have to access it carefully.
279 *
280 * The sequence we use to read is:
281 * 1) read high
282 * 2) read low
283 * 3) read high again, if it rolled re-read both low and high again.
284 *
285 * Writing STICK safely is also tricky:
286 * 1) write low to zero
287 * 2) write high
288 * 3) write low
289 */
290 #define HBIRD_STICKCMP_ADDR 0x1fe0000f060UL
291 #define HBIRD_STICK_ADDR 0x1fe0000f070UL
292
293 static unsigned long __hbird_read_stick(void)
294 {
295 unsigned long ret, tmp1, tmp2, tmp3;
296 unsigned long addr = HBIRD_STICK_ADDR+8;
297
298 __asm__ __volatile__("ldxa [%1] %5, %2\n"
299 "1:\n\t"
300 "sub %1, 0x8, %1\n\t"
301 "ldxa [%1] %5, %3\n\t"
302 "add %1, 0x8, %1\n\t"
303 "ldxa [%1] %5, %4\n\t"
304 "cmp %4, %2\n\t"
305 "bne,a,pn %%xcc, 1b\n\t"
306 " mov %4, %2\n\t"
307 "sllx %4, 32, %4\n\t"
308 "or %3, %4, %0\n\t"
309 : "=&r" (ret), "=&r" (addr),
310 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3)
311 : "i" (ASI_PHYS_BYPASS_EC_E), "1" (addr));
312
313 return ret;
314 }
315
316 static void __hbird_write_stick(unsigned long val)
317 {
318 unsigned long low = (val & 0xffffffffUL);
319 unsigned long high = (val >> 32UL);
320 unsigned long addr = HBIRD_STICK_ADDR;
321
322 __asm__ __volatile__("stxa %%g0, [%0] %4\n\t"
323 "add %0, 0x8, %0\n\t"
324 "stxa %3, [%0] %4\n\t"
325 "sub %0, 0x8, %0\n\t"
326 "stxa %2, [%0] %4"
327 : "=&r" (addr)
328 : "0" (addr), "r" (low), "r" (high),
329 "i" (ASI_PHYS_BYPASS_EC_E));
330 }
331
332 static void __hbird_write_compare(unsigned long val)
333 {
334 unsigned long low = (val & 0xffffffffUL);
335 unsigned long high = (val >> 32UL);
336 unsigned long addr = HBIRD_STICKCMP_ADDR + 0x8UL;
337
338 __asm__ __volatile__("stxa %3, [%0] %4\n\t"
339 "sub %0, 0x8, %0\n\t"
340 "stxa %2, [%0] %4"
341 : "=&r" (addr)
342 : "0" (addr), "r" (low), "r" (high),
343 "i" (ASI_PHYS_BYPASS_EC_E));
344 }
345
346 static void hbtick_disable_irq(void)
347 {
348 __hbird_write_compare(TICKCMP_IRQ_BIT);
349 }
350
351 static void hbtick_init_tick(void)
352 {
353 tick_disable_protection();
354
355 /* XXX This seems to be necessary to 'jumpstart' Hummingbird
356 * XXX into actually sending STICK interrupts. I think because
357 * XXX of how we store %tick_cmpr in head.S this somehow resets the
358 * XXX {TICK + STICK} interrupt mux. -DaveM
359 */
360 __hbird_write_stick(__hbird_read_stick());
361
362 hbtick_disable_irq();
363 }
364
365 static unsigned long hbtick_get_tick(void)
366 {
367 return __hbird_read_stick() & ~TICK_PRIV_BIT;
368 }
369
370 static unsigned long hbtick_add_tick(unsigned long adj)
371 {
372 unsigned long val;
373
374 val = __hbird_read_stick() + adj;
375 __hbird_write_stick(val);
376
377 return val;
378 }
379
380 static int hbtick_add_compare(unsigned long adj)
381 {
382 unsigned long val = __hbird_read_stick();
383 unsigned long val2;
384
385 val &= ~TICKCMP_IRQ_BIT;
386 val += adj;
387 __hbird_write_compare(val);
388
389 val2 = __hbird_read_stick() & ~TICKCMP_IRQ_BIT;
390
391 return ((long)(val2 - val)) > 0L;
392 }
393
394 static struct sparc64_tick_ops hbtick_operations __read_mostly = {
395 .name = "hbtick",
396 .init_tick = hbtick_init_tick,
397 .disable_irq = hbtick_disable_irq,
398 .get_tick = hbtick_get_tick,
399 .add_tick = hbtick_add_tick,
400 .add_compare = hbtick_add_compare,
401 .softint_mask = 1UL << 0,
402 };
403
404 static unsigned long timer_ticks_per_nsec_quotient __read_mostly;
405
406 int update_persistent_clock(struct timespec now)
407 {
408 return set_rtc_mmss(now.tv_sec);
409 }
410
411 /* Kick start a stopped clock (procedure from the Sun NVRAM/hostid FAQ). */
412 static void __init kick_start_clock(void)
413 {
414 void __iomem *regs = mstk48t02_regs;
415 u8 sec, tmp;
416 int i, count;
417
418 prom_printf("CLOCK: Clock was stopped. Kick start ");
419
420 spin_lock_irq(&mostek_lock);
421
422 /* Turn on the kick start bit to start the oscillator. */
423 tmp = mostek_read(regs + MOSTEK_CREG);
424 tmp |= MSTK_CREG_WRITE;
425 mostek_write(regs + MOSTEK_CREG, tmp);
426 tmp = mostek_read(regs + MOSTEK_SEC);
427 tmp &= ~MSTK_STOP;
428 mostek_write(regs + MOSTEK_SEC, tmp);
429 tmp = mostek_read(regs + MOSTEK_HOUR);
430 tmp |= MSTK_KICK_START;
431 mostek_write(regs + MOSTEK_HOUR, tmp);
432 tmp = mostek_read(regs + MOSTEK_CREG);
433 tmp &= ~MSTK_CREG_WRITE;
434 mostek_write(regs + MOSTEK_CREG, tmp);
435
436 spin_unlock_irq(&mostek_lock);
437
438 /* Delay to allow the clock oscillator to start. */
439 sec = MSTK_REG_SEC(regs);
440 for (i = 0; i < 3; i++) {
441 while (sec == MSTK_REG_SEC(regs))
442 for (count = 0; count < 100000; count++)
443 /* nothing */ ;
444 prom_printf(".");
445 sec = MSTK_REG_SEC(regs);
446 }
447 prom_printf("\n");
448
449 spin_lock_irq(&mostek_lock);
450
451 /* Turn off kick start and set a "valid" time and date. */
452 tmp = mostek_read(regs + MOSTEK_CREG);
453 tmp |= MSTK_CREG_WRITE;
454 mostek_write(regs + MOSTEK_CREG, tmp);
455 tmp = mostek_read(regs + MOSTEK_HOUR);
456 tmp &= ~MSTK_KICK_START;
457 mostek_write(regs + MOSTEK_HOUR, tmp);
458 MSTK_SET_REG_SEC(regs,0);
459 MSTK_SET_REG_MIN(regs,0);
460 MSTK_SET_REG_HOUR(regs,0);
461 MSTK_SET_REG_DOW(regs,5);
462 MSTK_SET_REG_DOM(regs,1);
463 MSTK_SET_REG_MONTH(regs,8);
464 MSTK_SET_REG_YEAR(regs,1996 - MSTK_YEAR_ZERO);
465 tmp = mostek_read(regs + MOSTEK_CREG);
466 tmp &= ~MSTK_CREG_WRITE;
467 mostek_write(regs + MOSTEK_CREG, tmp);
468
469 spin_unlock_irq(&mostek_lock);
470
471 /* Ensure the kick start bit is off. If it isn't, turn it off. */
472 while (mostek_read(regs + MOSTEK_HOUR) & MSTK_KICK_START) {
473 prom_printf("CLOCK: Kick start still on!\n");
474
475 spin_lock_irq(&mostek_lock);
476
477 tmp = mostek_read(regs + MOSTEK_CREG);
478 tmp |= MSTK_CREG_WRITE;
479 mostek_write(regs + MOSTEK_CREG, tmp);
480
481 tmp = mostek_read(regs + MOSTEK_HOUR);
482 tmp &= ~MSTK_KICK_START;
483 mostek_write(regs + MOSTEK_HOUR, tmp);
484
485 tmp = mostek_read(regs + MOSTEK_CREG);
486 tmp &= ~MSTK_CREG_WRITE;
487 mostek_write(regs + MOSTEK_CREG, tmp);
488
489 spin_unlock_irq(&mostek_lock);
490 }
491
492 prom_printf("CLOCK: Kick start procedure successful.\n");
493 }
494
495 /* Return nonzero if the clock chip battery is low. */
496 static int __init has_low_battery(void)
497 {
498 void __iomem *regs = mstk48t02_regs;
499 u8 data1, data2;
500
501 spin_lock_irq(&mostek_lock);
502
503 data1 = mostek_read(regs + MOSTEK_EEPROM); /* Read some data. */
504 mostek_write(regs + MOSTEK_EEPROM, ~data1); /* Write back the complement. */
505 data2 = mostek_read(regs + MOSTEK_EEPROM); /* Read back the complement. */
506 mostek_write(regs + MOSTEK_EEPROM, data1); /* Restore original value. */
507
508 spin_unlock_irq(&mostek_lock);
509
510 return (data1 == data2); /* Was the write blocked? */
511 }
512
513 static void __init mostek_set_system_time(void __iomem *mregs)
514 {
515 unsigned int year, mon, day, hour, min, sec;
516 u8 tmp;
517
518 spin_lock_irq(&mostek_lock);
519
520 /* Traditional Mostek chip. */
521 tmp = mostek_read(mregs + MOSTEK_CREG);
522 tmp |= MSTK_CREG_READ;
523 mostek_write(mregs + MOSTEK_CREG, tmp);
524
525 sec = MSTK_REG_SEC(mregs);
526 min = MSTK_REG_MIN(mregs);
527 hour = MSTK_REG_HOUR(mregs);
528 day = MSTK_REG_DOM(mregs);
529 mon = MSTK_REG_MONTH(mregs);
530 year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) );
531
532 xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
533 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
534 set_normalized_timespec(&wall_to_monotonic,
535 -xtime.tv_sec, -xtime.tv_nsec);
536
537 tmp = mostek_read(mregs + MOSTEK_CREG);
538 tmp &= ~MSTK_CREG_READ;
539 mostek_write(mregs + MOSTEK_CREG, tmp);
540
541 spin_unlock_irq(&mostek_lock);
542 }
543
544 /* Probe for the real time clock chip. */
545 static void __init set_system_time(void)
546 {
547 unsigned int year, mon, day, hour, min, sec;
548 void __iomem *mregs = mstk48t02_regs;
549 #ifdef CONFIG_PCI
550 unsigned long dregs = ds1287_regs;
551 void __iomem *bregs = bq4802_regs;
552 #else
553 unsigned long dregs = 0UL;
554 void __iomem *bregs = 0UL;
555 #endif
556
557 if (!mregs && !dregs && !bregs) {
558 prom_printf("Something wrong, clock regs not mapped yet.\n");
559 prom_halt();
560 }
561
562 if (mregs) {
563 mostek_set_system_time(mregs);
564 return;
565 }
566
567 if (bregs) {
568 unsigned char val = readb(bregs + 0x0e);
569 unsigned int century;
570
571 /* BQ4802 RTC chip. */
572
573 writeb(val | 0x08, bregs + 0x0e);
574
575 sec = readb(bregs + 0x00);
576 min = readb(bregs + 0x02);
577 hour = readb(bregs + 0x04);
578 day = readb(bregs + 0x06);
579 mon = readb(bregs + 0x09);
580 year = readb(bregs + 0x0a);
581 century = readb(bregs + 0x0f);
582
583 writeb(val, bregs + 0x0e);
584
585 BCD_TO_BIN(sec);
586 BCD_TO_BIN(min);
587 BCD_TO_BIN(hour);
588 BCD_TO_BIN(day);
589 BCD_TO_BIN(mon);
590 BCD_TO_BIN(year);
591 BCD_TO_BIN(century);
592
593 year += (century * 100);
594 } else {
595 /* Dallas 12887 RTC chip. */
596
597 do {
598 sec = CMOS_READ(RTC_SECONDS);
599 min = CMOS_READ(RTC_MINUTES);
600 hour = CMOS_READ(RTC_HOURS);
601 day = CMOS_READ(RTC_DAY_OF_MONTH);
602 mon = CMOS_READ(RTC_MONTH);
603 year = CMOS_READ(RTC_YEAR);
604 } while (sec != CMOS_READ(RTC_SECONDS));
605
606 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
607 BCD_TO_BIN(sec);
608 BCD_TO_BIN(min);
609 BCD_TO_BIN(hour);
610 BCD_TO_BIN(day);
611 BCD_TO_BIN(mon);
612 BCD_TO_BIN(year);
613 }
614 if ((year += 1900) < 1970)
615 year += 100;
616 }
617
618 xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
619 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
620 set_normalized_timespec(&wall_to_monotonic,
621 -xtime.tv_sec, -xtime.tv_nsec);
622 }
623
624 /* davem suggests we keep this within the 4M locked kernel image */
625 static u32 starfire_get_time(void)
626 {
627 static char obp_gettod[32];
628 static u32 unix_tod;
629
630 sprintf(obp_gettod, "h# %08x unix-gettod",
631 (unsigned int) (long) &unix_tod);
632 prom_feval(obp_gettod);
633
634 return unix_tod;
635 }
636
637 static int starfire_set_time(u32 val)
638 {
639 /* Do nothing, time is set using the service processor
640 * console on this platform.
641 */
642 return 0;
643 }
644
645 static u32 hypervisor_get_time(void)
646 {
647 unsigned long ret, time;
648 int retries = 10000;
649
650 retry:
651 ret = sun4v_tod_get(&time);
652 if (ret == HV_EOK)
653 return time;
654 if (ret == HV_EWOULDBLOCK) {
655 if (--retries > 0) {
656 udelay(100);
657 goto retry;
658 }
659 printk(KERN_WARNING "SUN4V: tod_get() timed out.\n");
660 return 0;
661 }
662 printk(KERN_WARNING "SUN4V: tod_get() not supported.\n");
663 return 0;
664 }
665
666 static int hypervisor_set_time(u32 secs)
667 {
668 unsigned long ret;
669 int retries = 10000;
670
671 retry:
672 ret = sun4v_tod_set(secs);
673 if (ret == HV_EOK)
674 return 0;
675 if (ret == HV_EWOULDBLOCK) {
676 if (--retries > 0) {
677 udelay(100);
678 goto retry;
679 }
680 printk(KERN_WARNING "SUN4V: tod_set() timed out.\n");
681 return -EAGAIN;
682 }
683 printk(KERN_WARNING "SUN4V: tod_set() not supported.\n");
684 return -EOPNOTSUPP;
685 }
686
687 static int __init clock_model_matches(const char *model)
688 {
689 if (strcmp(model, "mk48t02") &&
690 strcmp(model, "mk48t08") &&
691 strcmp(model, "mk48t59") &&
692 strcmp(model, "m5819") &&
693 strcmp(model, "m5819p") &&
694 strcmp(model, "m5823") &&
695 strcmp(model, "ds1287") &&
696 strcmp(model, "bq4802"))
697 return 0;
698
699 return 1;
700 }
701
702 static int __devinit clock_probe(struct of_device *op, const struct of_device_id *match)
703 {
704 struct device_node *dp = op->node;
705 const char *model = of_get_property(dp, "model", NULL);
706 const char *compat = of_get_property(dp, "compatible", NULL);
707 unsigned long size, flags;
708 void __iomem *regs;
709
710 if (!model)
711 model = compat;
712
713 if (!model || !clock_model_matches(model))
714 return -ENODEV;
715
716 /* On an Enterprise system there can be multiple mostek clocks.
717 * We should only match the one that is on the central FHC bus.
718 */
719 if (!strcmp(dp->parent->name, "fhc") &&
720 strcmp(dp->parent->parent->name, "central") != 0)
721 return -ENODEV;
722
723 size = (op->resource[0].end - op->resource[0].start) + 1;
724 regs = of_ioremap(&op->resource[0], 0, size, "clock");
725 if (!regs)
726 return -ENOMEM;
727
728 #ifdef CONFIG_PCI
729 if (!strcmp(model, "ds1287") ||
730 !strcmp(model, "m5819") ||
731 !strcmp(model, "m5819p") ||
732 !strcmp(model, "m5823")) {
733 ds1287_regs = (unsigned long) regs;
734 } else if (!strcmp(model, "bq4802")) {
735 bq4802_regs = regs;
736 } else
737 #endif
738 if (model[5] == '0' && model[6] == '2') {
739 mstk48t02_regs = regs;
740 } else if(model[5] == '0' && model[6] == '8') {
741 mstk48t08_regs = regs;
742 mstk48t02_regs = mstk48t08_regs + MOSTEK_48T08_48T02;
743 } else {
744 mstk48t59_regs = regs;
745 mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
746 }
747
748 printk(KERN_INFO "%s: Clock regs at %p\n", dp->full_name, regs);
749
750 local_irq_save(flags);
751
752 if (mstk48t02_regs != NULL) {
753 /* Report a low battery voltage condition. */
754 if (has_low_battery())
755 prom_printf("NVRAM: Low battery voltage!\n");
756
757 /* Kick start the clock if it is completely stopped. */
758 if (mostek_read(mstk48t02_regs + MOSTEK_SEC) & MSTK_STOP)
759 kick_start_clock();
760 }
761
762 set_system_time();
763
764 local_irq_restore(flags);
765
766 return 0;
767 }
768
769 static struct of_device_id clock_match[] = {
770 {
771 .name = "eeprom",
772 },
773 {
774 .name = "rtc",
775 },
776 {},
777 };
778
779 static struct of_platform_driver clock_driver = {
780 .match_table = clock_match,
781 .probe = clock_probe,
782 .driver = {
783 .name = "clock",
784 },
785 };
786
787 static int __init clock_init(void)
788 {
789 if (this_is_starfire) {
790 xtime.tv_sec = starfire_get_time();
791 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
792 set_normalized_timespec(&wall_to_monotonic,
793 -xtime.tv_sec, -xtime.tv_nsec);
794 return 0;
795 }
796 if (tlb_type == hypervisor) {
797 xtime.tv_sec = hypervisor_get_time();
798 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
799 set_normalized_timespec(&wall_to_monotonic,
800 -xtime.tv_sec, -xtime.tv_nsec);
801 return 0;
802 }
803
804 return of_register_driver(&clock_driver, &of_platform_bus_type);
805 }
806
807 /* Must be after subsys_initcall() so that busses are probed. Must
808 * be before device_initcall() because things like the RTC driver
809 * need to see the clock registers.
810 */
811 fs_initcall(clock_init);
812
813 /* This is gets the master TICK_INT timer going. */
814 static unsigned long sparc64_init_timers(void)
815 {
816 struct device_node *dp;
817 unsigned long clock;
818
819 dp = of_find_node_by_path("/");
820 if (tlb_type == spitfire) {
821 unsigned long ver, manuf, impl;
822
823 __asm__ __volatile__ ("rdpr %%ver, %0"
824 : "=&r" (ver));
825 manuf = ((ver >> 48) & 0xffff);
826 impl = ((ver >> 32) & 0xffff);
827 if (manuf == 0x17 && impl == 0x13) {
828 /* Hummingbird, aka Ultra-IIe */
829 tick_ops = &hbtick_operations;
830 clock = of_getintprop_default(dp, "stick-frequency", 0);
831 } else {
832 tick_ops = &tick_operations;
833 clock = local_cpu_data().clock_tick;
834 }
835 } else {
836 tick_ops = &stick_operations;
837 clock = of_getintprop_default(dp, "stick-frequency", 0);
838 }
839
840 return clock;
841 }
842
843 struct freq_table {
844 unsigned long clock_tick_ref;
845 unsigned int ref_freq;
846 };
847 static DEFINE_PER_CPU(struct freq_table, sparc64_freq_table) = { 0, 0 };
848
849 unsigned long sparc64_get_clock_tick(unsigned int cpu)
850 {
851 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu);
852
853 if (ft->clock_tick_ref)
854 return ft->clock_tick_ref;
855 return cpu_data(cpu).clock_tick;
856 }
857
858 #ifdef CONFIG_CPU_FREQ
859
860 static int sparc64_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
861 void *data)
862 {
863 struct cpufreq_freqs *freq = data;
864 unsigned int cpu = freq->cpu;
865 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu);
866
867 if (!ft->ref_freq) {
868 ft->ref_freq = freq->old;
869 ft->clock_tick_ref = cpu_data(cpu).clock_tick;
870 }
871 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
872 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
873 (val == CPUFREQ_RESUMECHANGE)) {
874 cpu_data(cpu).clock_tick =
875 cpufreq_scale(ft->clock_tick_ref,
876 ft->ref_freq,
877 freq->new);
878 }
879
880 return 0;
881 }
882
883 static struct notifier_block sparc64_cpufreq_notifier_block = {
884 .notifier_call = sparc64_cpufreq_notifier
885 };
886
887 static int __init register_sparc64_cpufreq_notifier(void)
888 {
889
890 cpufreq_register_notifier(&sparc64_cpufreq_notifier_block,
891 CPUFREQ_TRANSITION_NOTIFIER);
892 return 0;
893 }
894
895 core_initcall(register_sparc64_cpufreq_notifier);
896
897 #endif /* CONFIG_CPU_FREQ */
898
899 static int sparc64_next_event(unsigned long delta,
900 struct clock_event_device *evt)
901 {
902 return tick_ops->add_compare(delta) ? -ETIME : 0;
903 }
904
905 static void sparc64_timer_setup(enum clock_event_mode mode,
906 struct clock_event_device *evt)
907 {
908 switch (mode) {
909 case CLOCK_EVT_MODE_ONESHOT:
910 case CLOCK_EVT_MODE_RESUME:
911 break;
912
913 case CLOCK_EVT_MODE_SHUTDOWN:
914 tick_ops->disable_irq();
915 break;
916
917 case CLOCK_EVT_MODE_PERIODIC:
918 case CLOCK_EVT_MODE_UNUSED:
919 WARN_ON(1);
920 break;
921 };
922 }
923
924 static struct clock_event_device sparc64_clockevent = {
925 .features = CLOCK_EVT_FEAT_ONESHOT,
926 .set_mode = sparc64_timer_setup,
927 .set_next_event = sparc64_next_event,
928 .rating = 100,
929 .shift = 30,
930 .irq = -1,
931 };
932 static DEFINE_PER_CPU(struct clock_event_device, sparc64_events);
933
934 void timer_interrupt(int irq, struct pt_regs *regs)
935 {
936 struct pt_regs *old_regs = set_irq_regs(regs);
937 unsigned long tick_mask = tick_ops->softint_mask;
938 int cpu = smp_processor_id();
939 struct clock_event_device *evt = &per_cpu(sparc64_events, cpu);
940
941 clear_softint(tick_mask);
942
943 irq_enter();
944
945 kstat_this_cpu.irqs[0]++;
946
947 if (unlikely(!evt->event_handler)) {
948 printk(KERN_WARNING
949 "Spurious SPARC64 timer interrupt on cpu %d\n", cpu);
950 } else
951 evt->event_handler(evt);
952
953 irq_exit();
954
955 set_irq_regs(old_regs);
956 }
957
958 void __devinit setup_sparc64_timer(void)
959 {
960 struct clock_event_device *sevt;
961 unsigned long pstate;
962
963 /* Guarantee that the following sequences execute
964 * uninterrupted.
965 */
966 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
967 "wrpr %0, %1, %%pstate"
968 : "=r" (pstate)
969 : "i" (PSTATE_IE));
970
971 tick_ops->init_tick();
972
973 /* Restore PSTATE_IE. */
974 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
975 : /* no outputs */
976 : "r" (pstate));
977
978 sevt = &__get_cpu_var(sparc64_events);
979
980 memcpy(sevt, &sparc64_clockevent, sizeof(*sevt));
981 sevt->cpumask = cpumask_of_cpu(smp_processor_id());
982
983 clockevents_register_device(sevt);
984 }
985
986 #define SPARC64_NSEC_PER_CYC_SHIFT 10UL
987
988 static struct clocksource clocksource_tick = {
989 .rating = 100,
990 .mask = CLOCKSOURCE_MASK(64),
991 .shift = 16,
992 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
993 };
994
995 static void __init setup_clockevent_multiplier(unsigned long hz)
996 {
997 unsigned long mult, shift = 32;
998
999 while (1) {
1000 mult = div_sc(hz, NSEC_PER_SEC, shift);
1001 if (mult && (mult >> 32UL) == 0UL)
1002 break;
1003
1004 shift--;
1005 }
1006
1007 sparc64_clockevent.shift = shift;
1008 sparc64_clockevent.mult = mult;
1009 }
1010
1011 static unsigned long tb_ticks_per_usec __read_mostly;
1012
1013 void __delay(unsigned long loops)
1014 {
1015 unsigned long bclock, now;
1016
1017 bclock = tick_ops->get_tick();
1018 do {
1019 now = tick_ops->get_tick();
1020 } while ((now-bclock) < loops);
1021 }
1022 EXPORT_SYMBOL(__delay);
1023
1024 void udelay(unsigned long usecs)
1025 {
1026 __delay(tb_ticks_per_usec * usecs);
1027 }
1028 EXPORT_SYMBOL(udelay);
1029
1030 void __init time_init(void)
1031 {
1032 unsigned long clock = sparc64_init_timers();
1033
1034 tb_ticks_per_usec = clock / USEC_PER_SEC;
1035
1036 timer_ticks_per_nsec_quotient =
1037 clocksource_hz2mult(clock, SPARC64_NSEC_PER_CYC_SHIFT);
1038
1039 clocksource_tick.name = tick_ops->name;
1040 clocksource_tick.mult =
1041 clocksource_hz2mult(clock,
1042 clocksource_tick.shift);
1043 clocksource_tick.read = tick_ops->get_tick;
1044
1045 printk("clocksource: mult[%x] shift[%d]\n",
1046 clocksource_tick.mult, clocksource_tick.shift);
1047
1048 clocksource_register(&clocksource_tick);
1049
1050 sparc64_clockevent.name = tick_ops->name;
1051
1052 setup_clockevent_multiplier(clock);
1053
1054 sparc64_clockevent.max_delta_ns =
1055 clockevent_delta2ns(0x7fffffffffffffffUL, &sparc64_clockevent);
1056 sparc64_clockevent.min_delta_ns =
1057 clockevent_delta2ns(0xF, &sparc64_clockevent);
1058
1059 printk("clockevent: mult[%lx] shift[%d]\n",
1060 sparc64_clockevent.mult, sparc64_clockevent.shift);
1061
1062 setup_sparc64_timer();
1063 }
1064
1065 unsigned long long sched_clock(void)
1066 {
1067 unsigned long ticks = tick_ops->get_tick();
1068
1069 return (ticks * timer_ticks_per_nsec_quotient)
1070 >> SPARC64_NSEC_PER_CYC_SHIFT;
1071 }
1072
1073 static int set_rtc_mmss(unsigned long nowtime)
1074 {
1075 int real_seconds, real_minutes, chip_minutes;
1076 void __iomem *mregs = mstk48t02_regs;
1077 #ifdef CONFIG_PCI
1078 unsigned long dregs = ds1287_regs;
1079 void __iomem *bregs = bq4802_regs;
1080 #else
1081 unsigned long dregs = 0UL;
1082 void __iomem *bregs = 0UL;
1083 #endif
1084 unsigned long flags;
1085 u8 tmp;
1086
1087 /*
1088 * Not having a register set can lead to trouble.
1089 * Also starfire doesn't have a tod clock.
1090 */
1091 if (!mregs && !dregs && !bregs)
1092 return -1;
1093
1094 if (mregs) {
1095 spin_lock_irqsave(&mostek_lock, flags);
1096
1097 /* Read the current RTC minutes. */
1098 tmp = mostek_read(mregs + MOSTEK_CREG);
1099 tmp |= MSTK_CREG_READ;
1100 mostek_write(mregs + MOSTEK_CREG, tmp);
1101
1102 chip_minutes = MSTK_REG_MIN(mregs);
1103
1104 tmp = mostek_read(mregs + MOSTEK_CREG);
1105 tmp &= ~MSTK_CREG_READ;
1106 mostek_write(mregs + MOSTEK_CREG, tmp);
1107
1108 /*
1109 * since we're only adjusting minutes and seconds,
1110 * don't interfere with hour overflow. This avoids
1111 * messing with unknown time zones but requires your
1112 * RTC not to be off by more than 15 minutes
1113 */
1114 real_seconds = nowtime % 60;
1115 real_minutes = nowtime / 60;
1116 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1117 real_minutes += 30; /* correct for half hour time zone */
1118 real_minutes %= 60;
1119
1120 if (abs(real_minutes - chip_minutes) < 30) {
1121 tmp = mostek_read(mregs + MOSTEK_CREG);
1122 tmp |= MSTK_CREG_WRITE;
1123 mostek_write(mregs + MOSTEK_CREG, tmp);
1124
1125 MSTK_SET_REG_SEC(mregs,real_seconds);
1126 MSTK_SET_REG_MIN(mregs,real_minutes);
1127
1128 tmp = mostek_read(mregs + MOSTEK_CREG);
1129 tmp &= ~MSTK_CREG_WRITE;
1130 mostek_write(mregs + MOSTEK_CREG, tmp);
1131
1132 spin_unlock_irqrestore(&mostek_lock, flags);
1133
1134 return 0;
1135 } else {
1136 spin_unlock_irqrestore(&mostek_lock, flags);
1137
1138 return -1;
1139 }
1140 } else if (bregs) {
1141 int retval = 0;
1142 unsigned char val = readb(bregs + 0x0e);
1143
1144 /* BQ4802 RTC chip. */
1145
1146 writeb(val | 0x08, bregs + 0x0e);
1147
1148 chip_minutes = readb(bregs + 0x02);
1149 BCD_TO_BIN(chip_minutes);
1150 real_seconds = nowtime % 60;
1151 real_minutes = nowtime / 60;
1152 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1153 real_minutes += 30;
1154 real_minutes %= 60;
1155
1156 if (abs(real_minutes - chip_minutes) < 30) {
1157 BIN_TO_BCD(real_seconds);
1158 BIN_TO_BCD(real_minutes);
1159 writeb(real_seconds, bregs + 0x00);
1160 writeb(real_minutes, bregs + 0x02);
1161 } else {
1162 printk(KERN_WARNING
1163 "set_rtc_mmss: can't update from %d to %d\n",
1164 chip_minutes, real_minutes);
1165 retval = -1;
1166 }
1167
1168 writeb(val, bregs + 0x0e);
1169
1170 return retval;
1171 } else {
1172 int retval = 0;
1173 unsigned char save_control, save_freq_select;
1174
1175 /* Stolen from arch/i386/kernel/time.c, see there for
1176 * credits and descriptive comments.
1177 */
1178 spin_lock_irqsave(&rtc_lock, flags);
1179 save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
1180 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
1181
1182 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
1183 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
1184
1185 chip_minutes = CMOS_READ(RTC_MINUTES);
1186 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
1187 BCD_TO_BIN(chip_minutes);
1188 real_seconds = nowtime % 60;
1189 real_minutes = nowtime / 60;
1190 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1191 real_minutes += 30;
1192 real_minutes %= 60;
1193
1194 if (abs(real_minutes - chip_minutes) < 30) {
1195 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
1196 BIN_TO_BCD(real_seconds);
1197 BIN_TO_BCD(real_minutes);
1198 }
1199 CMOS_WRITE(real_seconds,RTC_SECONDS);
1200 CMOS_WRITE(real_minutes,RTC_MINUTES);
1201 } else {
1202 printk(KERN_WARNING
1203 "set_rtc_mmss: can't update from %d to %d\n",
1204 chip_minutes, real_minutes);
1205 retval = -1;
1206 }
1207
1208 CMOS_WRITE(save_control, RTC_CONTROL);
1209 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1210 spin_unlock_irqrestore(&rtc_lock, flags);
1211
1212 return retval;
1213 }
1214 }
1215
1216 #define RTC_IS_OPEN 0x01 /* means /dev/rtc is in use */
1217 static unsigned char mini_rtc_status; /* bitmapped status byte. */
1218
1219 #define FEBRUARY 2
1220 #define STARTOFTIME 1970
1221 #define SECDAY 86400L
1222 #define SECYR (SECDAY * 365)
1223 #define leapyear(year) ((year) % 4 == 0 && \
1224 ((year) % 100 != 0 || (year) % 400 == 0))
1225 #define days_in_year(a) (leapyear(a) ? 366 : 365)
1226 #define days_in_month(a) (month_days[(a) - 1])
1227
1228 static int month_days[12] = {
1229 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
1230 };
1231
1232 /*
1233 * This only works for the Gregorian calendar - i.e. after 1752 (in the UK)
1234 */
1235 static void GregorianDay(struct rtc_time * tm)
1236 {
1237 int leapsToDate;
1238 int lastYear;
1239 int day;
1240 int MonthOffset[] = { 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 };
1241
1242 lastYear = tm->tm_year - 1;
1243
1244 /*
1245 * Number of leap corrections to apply up to end of last year
1246 */
1247 leapsToDate = lastYear / 4 - lastYear / 100 + lastYear / 400;
1248
1249 /*
1250 * This year is a leap year if it is divisible by 4 except when it is
1251 * divisible by 100 unless it is divisible by 400
1252 *
1253 * e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 was
1254 */
1255 day = tm->tm_mon > 2 && leapyear(tm->tm_year);
1256
1257 day += lastYear*365 + leapsToDate + MonthOffset[tm->tm_mon-1] +
1258 tm->tm_mday;
1259
1260 tm->tm_wday = day % 7;
1261 }
1262
1263 static void to_tm(int tim, struct rtc_time *tm)
1264 {
1265 register int i;
1266 register long hms, day;
1267
1268 day = tim / SECDAY;
1269 hms = tim % SECDAY;
1270
1271 /* Hours, minutes, seconds are easy */
1272 tm->tm_hour = hms / 3600;
1273 tm->tm_min = (hms % 3600) / 60;
1274 tm->tm_sec = (hms % 3600) % 60;
1275
1276 /* Number of years in days */
1277 for (i = STARTOFTIME; day >= days_in_year(i); i++)
1278 day -= days_in_year(i);
1279 tm->tm_year = i;
1280
1281 /* Number of months in days left */
1282 if (leapyear(tm->tm_year))
1283 days_in_month(FEBRUARY) = 29;
1284 for (i = 1; day >= days_in_month(i); i++)
1285 day -= days_in_month(i);
1286 days_in_month(FEBRUARY) = 28;
1287 tm->tm_mon = i;
1288
1289 /* Days are what is left over (+1) from all that. */
1290 tm->tm_mday = day + 1;
1291
1292 /*
1293 * Determine the day of week
1294 */
1295 GregorianDay(tm);
1296 }
1297
1298 /* Both Starfire and SUN4V give us seconds since Jan 1st, 1970,
1299 * aka Unix time. So we have to convert to/from rtc_time.
1300 */
1301 static void starfire_get_rtc_time(struct rtc_time *time)
1302 {
1303 u32 seconds = starfire_get_time();
1304
1305 to_tm(seconds, time);
1306 time->tm_year -= 1900;
1307 time->tm_mon -= 1;
1308 }
1309
1310 static int starfire_set_rtc_time(struct rtc_time *time)
1311 {
1312 u32 seconds = mktime(time->tm_year + 1900, time->tm_mon + 1,
1313 time->tm_mday, time->tm_hour,
1314 time->tm_min, time->tm_sec);
1315
1316 return starfire_set_time(seconds);
1317 }
1318
1319 static void hypervisor_get_rtc_time(struct rtc_time *time)
1320 {
1321 u32 seconds = hypervisor_get_time();
1322
1323 to_tm(seconds, time);
1324 time->tm_year -= 1900;
1325 time->tm_mon -= 1;
1326 }
1327
1328 static int hypervisor_set_rtc_time(struct rtc_time *time)
1329 {
1330 u32 seconds = mktime(time->tm_year + 1900, time->tm_mon + 1,
1331 time->tm_mday, time->tm_hour,
1332 time->tm_min, time->tm_sec);
1333
1334 return hypervisor_set_time(seconds);
1335 }
1336
1337 #ifdef CONFIG_PCI
1338 static void bq4802_get_rtc_time(struct rtc_time *time)
1339 {
1340 unsigned char val = readb(bq4802_regs + 0x0e);
1341 unsigned int century;
1342
1343 writeb(val | 0x08, bq4802_regs + 0x0e);
1344
1345 time->tm_sec = readb(bq4802_regs + 0x00);
1346 time->tm_min = readb(bq4802_regs + 0x02);
1347 time->tm_hour = readb(bq4802_regs + 0x04);
1348 time->tm_mday = readb(bq4802_regs + 0x06);
1349 time->tm_mon = readb(bq4802_regs + 0x09);
1350 time->tm_year = readb(bq4802_regs + 0x0a);
1351 time->tm_wday = readb(bq4802_regs + 0x08);
1352 century = readb(bq4802_regs + 0x0f);
1353
1354 writeb(val, bq4802_regs + 0x0e);
1355
1356 BCD_TO_BIN(time->tm_sec);
1357 BCD_TO_BIN(time->tm_min);
1358 BCD_TO_BIN(time->tm_hour);
1359 BCD_TO_BIN(time->tm_mday);
1360 BCD_TO_BIN(time->tm_mon);
1361 BCD_TO_BIN(time->tm_year);
1362 BCD_TO_BIN(time->tm_wday);
1363 BCD_TO_BIN(century);
1364
1365 time->tm_year += (century * 100);
1366 time->tm_year -= 1900;
1367
1368 time->tm_mon--;
1369 }
1370
1371 static int bq4802_set_rtc_time(struct rtc_time *time)
1372 {
1373 unsigned char val = readb(bq4802_regs + 0x0e);
1374 unsigned char sec, min, hrs, day, mon, yrs, century;
1375 unsigned int year;
1376
1377 year = time->tm_year + 1900;
1378 century = year / 100;
1379 yrs = year % 100;
1380
1381 mon = time->tm_mon + 1; /* tm_mon starts at zero */
1382 day = time->tm_mday;
1383 hrs = time->tm_hour;
1384 min = time->tm_min;
1385 sec = time->tm_sec;
1386
1387 BIN_TO_BCD(sec);
1388 BIN_TO_BCD(min);
1389 BIN_TO_BCD(hrs);
1390 BIN_TO_BCD(day);
1391 BIN_TO_BCD(mon);
1392 BIN_TO_BCD(yrs);
1393 BIN_TO_BCD(century);
1394
1395 writeb(val | 0x08, bq4802_regs + 0x0e);
1396
1397 writeb(sec, bq4802_regs + 0x00);
1398 writeb(min, bq4802_regs + 0x02);
1399 writeb(hrs, bq4802_regs + 0x04);
1400 writeb(day, bq4802_regs + 0x06);
1401 writeb(mon, bq4802_regs + 0x09);
1402 writeb(yrs, bq4802_regs + 0x0a);
1403 writeb(century, bq4802_regs + 0x0f);
1404
1405 writeb(val, bq4802_regs + 0x0e);
1406
1407 return 0;
1408 }
1409
1410 static void cmos_get_rtc_time(struct rtc_time *rtc_tm)
1411 {
1412 unsigned char ctrl;
1413
1414 rtc_tm->tm_sec = CMOS_READ(RTC_SECONDS);
1415 rtc_tm->tm_min = CMOS_READ(RTC_MINUTES);
1416 rtc_tm->tm_hour = CMOS_READ(RTC_HOURS);
1417 rtc_tm->tm_mday = CMOS_READ(RTC_DAY_OF_MONTH);
1418 rtc_tm->tm_mon = CMOS_READ(RTC_MONTH);
1419 rtc_tm->tm_year = CMOS_READ(RTC_YEAR);
1420 rtc_tm->tm_wday = CMOS_READ(RTC_DAY_OF_WEEK);
1421
1422 ctrl = CMOS_READ(RTC_CONTROL);
1423 if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
1424 BCD_TO_BIN(rtc_tm->tm_sec);
1425 BCD_TO_BIN(rtc_tm->tm_min);
1426 BCD_TO_BIN(rtc_tm->tm_hour);
1427 BCD_TO_BIN(rtc_tm->tm_mday);
1428 BCD_TO_BIN(rtc_tm->tm_mon);
1429 BCD_TO_BIN(rtc_tm->tm_year);
1430 BCD_TO_BIN(rtc_tm->tm_wday);
1431 }
1432
1433 if (rtc_tm->tm_year <= 69)
1434 rtc_tm->tm_year += 100;
1435
1436 rtc_tm->tm_mon--;
1437 }
1438
1439 static int cmos_set_rtc_time(struct rtc_time *rtc_tm)
1440 {
1441 unsigned char mon, day, hrs, min, sec;
1442 unsigned char save_control, save_freq_select;
1443 unsigned int yrs;
1444
1445 yrs = rtc_tm->tm_year;
1446 mon = rtc_tm->tm_mon + 1;
1447 day = rtc_tm->tm_mday;
1448 hrs = rtc_tm->tm_hour;
1449 min = rtc_tm->tm_min;
1450 sec = rtc_tm->tm_sec;
1451
1452 if (yrs >= 100)
1453 yrs -= 100;
1454
1455 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
1456 BIN_TO_BCD(sec);
1457 BIN_TO_BCD(min);
1458 BIN_TO_BCD(hrs);
1459 BIN_TO_BCD(day);
1460 BIN_TO_BCD(mon);
1461 BIN_TO_BCD(yrs);
1462 }
1463
1464 save_control = CMOS_READ(RTC_CONTROL);
1465 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
1466 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1467 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
1468
1469 CMOS_WRITE(yrs, RTC_YEAR);
1470 CMOS_WRITE(mon, RTC_MONTH);
1471 CMOS_WRITE(day, RTC_DAY_OF_MONTH);
1472 CMOS_WRITE(hrs, RTC_HOURS);
1473 CMOS_WRITE(min, RTC_MINUTES);
1474 CMOS_WRITE(sec, RTC_SECONDS);
1475
1476 CMOS_WRITE(save_control, RTC_CONTROL);
1477 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1478
1479 return 0;
1480 }
1481 #endif /* CONFIG_PCI */
1482
1483 static void mostek_get_rtc_time(struct rtc_time *rtc_tm)
1484 {
1485 void __iomem *regs = mstk48t02_regs;
1486 u8 tmp;
1487
1488 spin_lock_irq(&mostek_lock);
1489
1490 tmp = mostek_read(regs + MOSTEK_CREG);
1491 tmp |= MSTK_CREG_READ;
1492 mostek_write(regs + MOSTEK_CREG, tmp);
1493
1494 rtc_tm->tm_sec = MSTK_REG_SEC(regs);
1495 rtc_tm->tm_min = MSTK_REG_MIN(regs);
1496 rtc_tm->tm_hour = MSTK_REG_HOUR(regs);
1497 rtc_tm->tm_mday = MSTK_REG_DOM(regs);
1498 rtc_tm->tm_mon = MSTK_REG_MONTH(regs);
1499 rtc_tm->tm_year = MSTK_CVT_YEAR( MSTK_REG_YEAR(regs) );
1500 rtc_tm->tm_wday = MSTK_REG_DOW(regs);
1501
1502 tmp = mostek_read(regs + MOSTEK_CREG);
1503 tmp &= ~MSTK_CREG_READ;
1504 mostek_write(regs + MOSTEK_CREG, tmp);
1505
1506 spin_unlock_irq(&mostek_lock);
1507
1508 rtc_tm->tm_mon--;
1509 rtc_tm->tm_wday--;
1510 rtc_tm->tm_year -= 1900;
1511 }
1512
1513 static int mostek_set_rtc_time(struct rtc_time *rtc_tm)
1514 {
1515 unsigned char mon, day, hrs, min, sec, wday;
1516 void __iomem *regs = mstk48t02_regs;
1517 unsigned int yrs;
1518 u8 tmp;
1519
1520 yrs = rtc_tm->tm_year + 1900;
1521 mon = rtc_tm->tm_mon + 1;
1522 day = rtc_tm->tm_mday;
1523 wday = rtc_tm->tm_wday + 1;
1524 hrs = rtc_tm->tm_hour;
1525 min = rtc_tm->tm_min;
1526 sec = rtc_tm->tm_sec;
1527
1528 spin_lock_irq(&mostek_lock);
1529
1530 tmp = mostek_read(regs + MOSTEK_CREG);
1531 tmp |= MSTK_CREG_WRITE;
1532 mostek_write(regs + MOSTEK_CREG, tmp);
1533
1534 MSTK_SET_REG_SEC(regs, sec);
1535 MSTK_SET_REG_MIN(regs, min);
1536 MSTK_SET_REG_HOUR(regs, hrs);
1537 MSTK_SET_REG_DOW(regs, wday);
1538 MSTK_SET_REG_DOM(regs, day);
1539 MSTK_SET_REG_MONTH(regs, mon);
1540 MSTK_SET_REG_YEAR(regs, yrs - MSTK_YEAR_ZERO);
1541
1542 tmp = mostek_read(regs + MOSTEK_CREG);
1543 tmp &= ~MSTK_CREG_WRITE;
1544 mostek_write(regs + MOSTEK_CREG, tmp);
1545
1546 spin_unlock_irq(&mostek_lock);
1547
1548 return 0;
1549 }
1550
1551 struct mini_rtc_ops {
1552 void (*get_rtc_time)(struct rtc_time *);
1553 int (*set_rtc_time)(struct rtc_time *);
1554 };
1555
1556 static struct mini_rtc_ops starfire_rtc_ops = {
1557 .get_rtc_time = starfire_get_rtc_time,
1558 .set_rtc_time = starfire_set_rtc_time,
1559 };
1560
1561 static struct mini_rtc_ops hypervisor_rtc_ops = {
1562 .get_rtc_time = hypervisor_get_rtc_time,
1563 .set_rtc_time = hypervisor_set_rtc_time,
1564 };
1565
1566 #ifdef CONFIG_PCI
1567 static struct mini_rtc_ops bq4802_rtc_ops = {
1568 .get_rtc_time = bq4802_get_rtc_time,
1569 .set_rtc_time = bq4802_set_rtc_time,
1570 };
1571
1572 static struct mini_rtc_ops cmos_rtc_ops = {
1573 .get_rtc_time = cmos_get_rtc_time,
1574 .set_rtc_time = cmos_set_rtc_time,
1575 };
1576 #endif /* CONFIG_PCI */
1577
1578 static struct mini_rtc_ops mostek_rtc_ops = {
1579 .get_rtc_time = mostek_get_rtc_time,
1580 .set_rtc_time = mostek_set_rtc_time,
1581 };
1582
1583 static struct mini_rtc_ops *mini_rtc_ops;
1584
1585 static inline void mini_get_rtc_time(struct rtc_time *time)
1586 {
1587 unsigned long flags;
1588
1589 spin_lock_irqsave(&rtc_lock, flags);
1590 mini_rtc_ops->get_rtc_time(time);
1591 spin_unlock_irqrestore(&rtc_lock, flags);
1592 }
1593
1594 static inline int mini_set_rtc_time(struct rtc_time *time)
1595 {
1596 unsigned long flags;
1597 int err;
1598
1599 spin_lock_irqsave(&rtc_lock, flags);
1600 err = mini_rtc_ops->set_rtc_time(time);
1601 spin_unlock_irqrestore(&rtc_lock, flags);
1602
1603 return err;
1604 }
1605
1606 static int mini_rtc_ioctl(struct inode *inode, struct file *file,
1607 unsigned int cmd, unsigned long arg)
1608 {
1609 struct rtc_time wtime;
1610 void __user *argp = (void __user *)arg;
1611
1612 switch (cmd) {
1613
1614 case RTC_PLL_GET:
1615 return -EINVAL;
1616
1617 case RTC_PLL_SET:
1618 return -EINVAL;
1619
1620 case RTC_UIE_OFF: /* disable ints from RTC updates. */
1621 return 0;
1622
1623 case RTC_UIE_ON: /* enable ints for RTC updates. */
1624 return -EINVAL;
1625
1626 case RTC_RD_TIME: /* Read the time/date from RTC */
1627 /* this doesn't get week-day, who cares */
1628 memset(&wtime, 0, sizeof(wtime));
1629 mini_get_rtc_time(&wtime);
1630
1631 return copy_to_user(argp, &wtime, sizeof(wtime)) ? -EFAULT : 0;
1632
1633 case RTC_SET_TIME: /* Set the RTC */
1634 {
1635 int year, days;
1636
1637 if (!capable(CAP_SYS_TIME))
1638 return -EACCES;
1639
1640 if (copy_from_user(&wtime, argp, sizeof(wtime)))
1641 return -EFAULT;
1642
1643 year = wtime.tm_year + 1900;
1644 days = month_days[wtime.tm_mon] +
1645 ((wtime.tm_mon == 1) && leapyear(year));
1646
1647 if ((wtime.tm_mon < 0 || wtime.tm_mon > 11) ||
1648 (wtime.tm_mday < 1))
1649 return -EINVAL;
1650
1651 if (wtime.tm_mday < 0 || wtime.tm_mday > days)
1652 return -EINVAL;
1653
1654 if (wtime.tm_hour < 0 || wtime.tm_hour >= 24 ||
1655 wtime.tm_min < 0 || wtime.tm_min >= 60 ||
1656 wtime.tm_sec < 0 || wtime.tm_sec >= 60)
1657 return -EINVAL;
1658
1659 return mini_set_rtc_time(&wtime);
1660 }
1661 }
1662
1663 return -EINVAL;
1664 }
1665
1666 static int mini_rtc_open(struct inode *inode, struct file *file)
1667 {
1668 lock_kernel();
1669 if (mini_rtc_status & RTC_IS_OPEN) {
1670 unlock_kernel();
1671 return -EBUSY;
1672 }
1673
1674 mini_rtc_status |= RTC_IS_OPEN;
1675 unlock_kernel();
1676
1677 return 0;
1678 }
1679
1680 static int mini_rtc_release(struct inode *inode, struct file *file)
1681 {
1682 mini_rtc_status &= ~RTC_IS_OPEN;
1683 return 0;
1684 }
1685
1686
1687 static const struct file_operations mini_rtc_fops = {
1688 .owner = THIS_MODULE,
1689 .ioctl = mini_rtc_ioctl,
1690 .open = mini_rtc_open,
1691 .release = mini_rtc_release,
1692 };
1693
1694 static struct miscdevice rtc_mini_dev =
1695 {
1696 .minor = RTC_MINOR,
1697 .name = "rtc",
1698 .fops = &mini_rtc_fops,
1699 };
1700
1701 static int __init rtc_mini_init(void)
1702 {
1703 int retval;
1704
1705 if (tlb_type == hypervisor)
1706 mini_rtc_ops = &hypervisor_rtc_ops;
1707 else if (this_is_starfire)
1708 mini_rtc_ops = &starfire_rtc_ops;
1709 #ifdef CONFIG_PCI
1710 else if (bq4802_regs)
1711 mini_rtc_ops = &bq4802_rtc_ops;
1712 else if (ds1287_regs)
1713 mini_rtc_ops = &cmos_rtc_ops;
1714 #endif /* CONFIG_PCI */
1715 else if (mstk48t02_regs)
1716 mini_rtc_ops = &mostek_rtc_ops;
1717 else
1718 return -ENODEV;
1719
1720 printk(KERN_INFO "Mini RTC Driver\n");
1721
1722 retval = misc_register(&rtc_mini_dev);
1723 if (retval < 0)
1724 return retval;
1725
1726 return 0;
1727 }
1728
1729 static void __exit rtc_mini_exit(void)
1730 {
1731 misc_deregister(&rtc_mini_dev);
1732 }
1733
1734 int __devinit read_current_timer(unsigned long *timer_val)
1735 {
1736 *timer_val = tick_ops->get_tick();
1737 return 0;
1738 }
1739
1740 module_init(rtc_mini_init);
1741 module_exit(rtc_mini_exit);
kernel source for telekom puls (alcatel/mediatek)