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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc64 / kernel / time.c
1 /* time.c: UltraSparc timer and TOD clock support.
2 *
3 * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 *
6 * Based largely on code which is:
7 *
8 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
9 */
10
11 #include <linux/errno.h>
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/smp_lock.h>
15 #include <linux/kernel.h>
16 #include <linux/param.h>
17 #include <linux/string.h>
18 #include <linux/mm.h>
19 #include <linux/interrupt.h>
20 #include <linux/time.h>
21 #include <linux/timex.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/delay.h>
26 #include <linux/profile.h>
27 #include <linux/bcd.h>
28 #include <linux/jiffies.h>
29 #include <linux/cpufreq.h>
30 #include <linux/percpu.h>
31 #include <linux/miscdevice.h>
32 #include <linux/rtc.h>
33 #include <linux/kernel_stat.h>
34 #include <linux/clockchips.h>
35 #include <linux/clocksource.h>
36
37 #include <asm/oplib.h>
38 #include <asm/mostek.h>
39 #include <asm/timer.h>
40 #include <asm/irq.h>
41 #include <asm/io.h>
42 #include <asm/prom.h>
43 #include <asm/of_device.h>
44 #include <asm/starfire.h>
45 #include <asm/smp.h>
46 #include <asm/sections.h>
47 #include <asm/cpudata.h>
48 #include <asm/uaccess.h>
49 #include <asm/irq_regs.h>
50
51 #include "entry.h"
52
53 DEFINE_SPINLOCK(mostek_lock);
54 DEFINE_SPINLOCK(rtc_lock);
55 void __iomem *mstk48t02_regs = NULL;
56 #ifdef CONFIG_PCI
57 unsigned long ds1287_regs = 0UL;
58 static void __iomem *bq4802_regs;
59 #endif
60
61 static void __iomem *mstk48t08_regs;
62 static void __iomem *mstk48t59_regs;
63
64 static int set_rtc_mmss(unsigned long);
65
66 #define TICK_PRIV_BIT (1UL << 63)
67 #define TICKCMP_IRQ_BIT (1UL << 63)
68
69 #ifdef CONFIG_SMP
70 unsigned long profile_pc(struct pt_regs *regs)
71 {
72 unsigned long pc = instruction_pointer(regs);
73
74 if (in_lock_functions(pc))
75 return regs->u_regs[UREG_RETPC];
76 return pc;
77 }
78 EXPORT_SYMBOL(profile_pc);
79 #endif
80
81 static void tick_disable_protection(void)
82 {
83 /* Set things up so user can access tick register for profiling
84 * purposes. Also workaround BB_ERRATA_1 by doing a dummy
85 * read back of %tick after writing it.
86 */
87 __asm__ __volatile__(
88 " ba,pt %%xcc, 1f\n"
89 " nop\n"
90 " .align 64\n"
91 "1: rd %%tick, %%g2\n"
92 " add %%g2, 6, %%g2\n"
93 " andn %%g2, %0, %%g2\n"
94 " wrpr %%g2, 0, %%tick\n"
95 " rdpr %%tick, %%g0"
96 : /* no outputs */
97 : "r" (TICK_PRIV_BIT)
98 : "g2");
99 }
100
101 static void tick_disable_irq(void)
102 {
103 __asm__ __volatile__(
104 " ba,pt %%xcc, 1f\n"
105 " nop\n"
106 " .align 64\n"
107 "1: wr %0, 0x0, %%tick_cmpr\n"
108 " rd %%tick_cmpr, %%g0"
109 : /* no outputs */
110 : "r" (TICKCMP_IRQ_BIT));
111 }
112
113 static void tick_init_tick(void)
114 {
115 tick_disable_protection();
116 tick_disable_irq();
117 }
118
119 static unsigned long tick_get_tick(void)
120 {
121 unsigned long ret;
122
123 __asm__ __volatile__("rd %%tick, %0\n\t"
124 "mov %0, %0"
125 : "=r" (ret));
126
127 return ret & ~TICK_PRIV_BIT;
128 }
129
130 static int tick_add_compare(unsigned long adj)
131 {
132 unsigned long orig_tick, new_tick, new_compare;
133
134 __asm__ __volatile__("rd %%tick, %0"
135 : "=r" (orig_tick));
136
137 orig_tick &= ~TICKCMP_IRQ_BIT;
138
139 /* Workaround for Spitfire Errata (#54 I think??), I discovered
140 * this via Sun BugID 4008234, mentioned in Solaris-2.5.1 patch
141 * number 103640.
142 *
143 * On Blackbird writes to %tick_cmpr can fail, the
144 * workaround seems to be to execute the wr instruction
145 * at the start of an I-cache line, and perform a dummy
146 * read back from %tick_cmpr right after writing to it. -DaveM
147 */
148 __asm__ __volatile__("ba,pt %%xcc, 1f\n\t"
149 " add %1, %2, %0\n\t"
150 ".align 64\n"
151 "1:\n\t"
152 "wr %0, 0, %%tick_cmpr\n\t"
153 "rd %%tick_cmpr, %%g0\n\t"
154 : "=r" (new_compare)
155 : "r" (orig_tick), "r" (adj));
156
157 __asm__ __volatile__("rd %%tick, %0"
158 : "=r" (new_tick));
159 new_tick &= ~TICKCMP_IRQ_BIT;
160
161 return ((long)(new_tick - (orig_tick+adj))) > 0L;
162 }
163
164 static unsigned long tick_add_tick(unsigned long adj)
165 {
166 unsigned long new_tick;
167
168 /* Also need to handle Blackbird bug here too. */
169 __asm__ __volatile__("rd %%tick, %0\n\t"
170 "add %0, %1, %0\n\t"
171 "wrpr %0, 0, %%tick\n\t"
172 : "=&r" (new_tick)
173 : "r" (adj));
174
175 return new_tick;
176 }
177
178 static struct sparc64_tick_ops tick_operations __read_mostly = {
179 .name = "tick",
180 .init_tick = tick_init_tick,
181 .disable_irq = tick_disable_irq,
182 .get_tick = tick_get_tick,
183 .add_tick = tick_add_tick,
184 .add_compare = tick_add_compare,
185 .softint_mask = 1UL << 0,
186 };
187
188 struct sparc64_tick_ops *tick_ops __read_mostly = &tick_operations;
189
190 static void stick_disable_irq(void)
191 {
192 __asm__ __volatile__(
193 "wr %0, 0x0, %%asr25"
194 : /* no outputs */
195 : "r" (TICKCMP_IRQ_BIT));
196 }
197
198 static void stick_init_tick(void)
199 {
200 /* Writes to the %tick and %stick register are not
201 * allowed on sun4v. The Hypervisor controls that
202 * bit, per-strand.
203 */
204 if (tlb_type != hypervisor) {
205 tick_disable_protection();
206 tick_disable_irq();
207
208 /* Let the user get at STICK too. */
209 __asm__ __volatile__(
210 " rd %%asr24, %%g2\n"
211 " andn %%g2, %0, %%g2\n"
212 " wr %%g2, 0, %%asr24"
213 : /* no outputs */
214 : "r" (TICK_PRIV_BIT)
215 : "g1", "g2");
216 }
217
218 stick_disable_irq();
219 }
220
221 static unsigned long stick_get_tick(void)
222 {
223 unsigned long ret;
224
225 __asm__ __volatile__("rd %%asr24, %0"
226 : "=r" (ret));
227
228 return ret & ~TICK_PRIV_BIT;
229 }
230
231 static unsigned long stick_add_tick(unsigned long adj)
232 {
233 unsigned long new_tick;
234
235 __asm__ __volatile__("rd %%asr24, %0\n\t"
236 "add %0, %1, %0\n\t"
237 "wr %0, 0, %%asr24\n\t"
238 : "=&r" (new_tick)
239 : "r" (adj));
240
241 return new_tick;
242 }
243
244 static int stick_add_compare(unsigned long adj)
245 {
246 unsigned long orig_tick, new_tick;
247
248 __asm__ __volatile__("rd %%asr24, %0"
249 : "=r" (orig_tick));
250 orig_tick &= ~TICKCMP_IRQ_BIT;
251
252 __asm__ __volatile__("wr %0, 0, %%asr25"
253 : /* no outputs */
254 : "r" (orig_tick + adj));
255
256 __asm__ __volatile__("rd %%asr24, %0"
257 : "=r" (new_tick));
258 new_tick &= ~TICKCMP_IRQ_BIT;
259
260 return ((long)(new_tick - (orig_tick+adj))) > 0L;
261 }
262
263 static struct sparc64_tick_ops stick_operations __read_mostly = {
264 .name = "stick",
265 .init_tick = stick_init_tick,
266 .disable_irq = stick_disable_irq,
267 .get_tick = stick_get_tick,
268 .add_tick = stick_add_tick,
269 .add_compare = stick_add_compare,
270 .softint_mask = 1UL << 16,
271 };
272
273 /* On Hummingbird the STICK/STICK_CMPR register is implemented
274 * in I/O space. There are two 64-bit registers each, the
275 * first holds the low 32-bits of the value and the second holds
276 * the high 32-bits.
277 *
278 * Since STICK is constantly updating, we have to access it carefully.
279 *
280 * The sequence we use to read is:
281 * 1) read high
282 * 2) read low
283 * 3) read high again, if it rolled re-read both low and high again.
284 *
285 * Writing STICK safely is also tricky:
286 * 1) write low to zero
287 * 2) write high
288 * 3) write low
289 */
290 #define HBIRD_STICKCMP_ADDR 0x1fe0000f060UL
291 #define HBIRD_STICK_ADDR 0x1fe0000f070UL
292
293 static unsigned long __hbird_read_stick(void)
294 {
295 unsigned long ret, tmp1, tmp2, tmp3;
296 unsigned long addr = HBIRD_STICK_ADDR+8;
297
298 __asm__ __volatile__("ldxa [%1] %5, %2\n"
299 "1:\n\t"
300 "sub %1, 0x8, %1\n\t"
301 "ldxa [%1] %5, %3\n\t"
302 "add %1, 0x8, %1\n\t"
303 "ldxa [%1] %5, %4\n\t"
304 "cmp %4, %2\n\t"
305 "bne,a,pn %%xcc, 1b\n\t"
306 " mov %4, %2\n\t"
307 "sllx %4, 32, %4\n\t"
308 "or %3, %4, %0\n\t"
309 : "=&r" (ret), "=&r" (addr),
310 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3)
311 : "i" (ASI_PHYS_BYPASS_EC_E), "1" (addr));
312
313 return ret;
314 }
315
316 static void __hbird_write_stick(unsigned long val)
317 {
318 unsigned long low = (val & 0xffffffffUL);
319 unsigned long high = (val >> 32UL);
320 unsigned long addr = HBIRD_STICK_ADDR;
321
322 __asm__ __volatile__("stxa %%g0, [%0] %4\n\t"
323 "add %0, 0x8, %0\n\t"
324 "stxa %3, [%0] %4\n\t"
325 "sub %0, 0x8, %0\n\t"
326 "stxa %2, [%0] %4"
327 : "=&r" (addr)
328 : "0" (addr), "r" (low), "r" (high),
329 "i" (ASI_PHYS_BYPASS_EC_E));
330 }
331
332 static void __hbird_write_compare(unsigned long val)
333 {
334 unsigned long low = (val & 0xffffffffUL);
335 unsigned long high = (val >> 32UL);
336 unsigned long addr = HBIRD_STICKCMP_ADDR + 0x8UL;
337
338 __asm__ __volatile__("stxa %3, [%0] %4\n\t"
339 "sub %0, 0x8, %0\n\t"
340 "stxa %2, [%0] %4"
341 : "=&r" (addr)
342 : "0" (addr), "r" (low), "r" (high),
343 "i" (ASI_PHYS_BYPASS_EC_E));
344 }
345
346 static void hbtick_disable_irq(void)
347 {
348 __hbird_write_compare(TICKCMP_IRQ_BIT);
349 }
350
351 static void hbtick_init_tick(void)
352 {
353 tick_disable_protection();
354
355 /* XXX This seems to be necessary to 'jumpstart' Hummingbird
356 * XXX into actually sending STICK interrupts. I think because
357 * XXX of how we store %tick_cmpr in head.S this somehow resets the
358 * XXX {TICK + STICK} interrupt mux. -DaveM
359 */
360 __hbird_write_stick(__hbird_read_stick());
361
362 hbtick_disable_irq();
363 }
364
365 static unsigned long hbtick_get_tick(void)
366 {
367 return __hbird_read_stick() & ~TICK_PRIV_BIT;
368 }
369
370 static unsigned long hbtick_add_tick(unsigned long adj)
371 {
372 unsigned long val;
373
374 val = __hbird_read_stick() + adj;
375 __hbird_write_stick(val);
376
377 return val;
378 }
379
380 static int hbtick_add_compare(unsigned long adj)
381 {
382 unsigned long val = __hbird_read_stick();
383 unsigned long val2;
384
385 val &= ~TICKCMP_IRQ_BIT;
386 val += adj;
387 __hbird_write_compare(val);
388
389 val2 = __hbird_read_stick() & ~TICKCMP_IRQ_BIT;
390
391 return ((long)(val2 - val)) > 0L;
392 }
393
394 static struct sparc64_tick_ops hbtick_operations __read_mostly = {
395 .name = "hbtick",
396 .init_tick = hbtick_init_tick,
397 .disable_irq = hbtick_disable_irq,
398 .get_tick = hbtick_get_tick,
399 .add_tick = hbtick_add_tick,
400 .add_compare = hbtick_add_compare,
401 .softint_mask = 1UL << 0,
402 };
403
404 static unsigned long timer_ticks_per_nsec_quotient __read_mostly;
405
406 int update_persistent_clock(struct timespec now)
407 {
408 return set_rtc_mmss(now.tv_sec);
409 }
410
411 /* Kick start a stopped clock (procedure from the Sun NVRAM/hostid FAQ). */
412 static void __init kick_start_clock(void)
413 {
414 void __iomem *regs = mstk48t02_regs;
415 u8 sec, tmp;
416 int i, count;
417
418 prom_printf("CLOCK: Clock was stopped. Kick start ");
419
420 spin_lock_irq(&mostek_lock);
421
422 /* Turn on the kick start bit to start the oscillator. */
423 tmp = mostek_read(regs + MOSTEK_CREG);
424 tmp |= MSTK_CREG_WRITE;
425 mostek_write(regs + MOSTEK_CREG, tmp);
426 tmp = mostek_read(regs + MOSTEK_SEC);
427 tmp &= ~MSTK_STOP;
428 mostek_write(regs + MOSTEK_SEC, tmp);
429 tmp = mostek_read(regs + MOSTEK_HOUR);
430 tmp |= MSTK_KICK_START;
431 mostek_write(regs + MOSTEK_HOUR, tmp);
432 tmp = mostek_read(regs + MOSTEK_CREG);
433 tmp &= ~MSTK_CREG_WRITE;
434 mostek_write(regs + MOSTEK_CREG, tmp);
435
436 spin_unlock_irq(&mostek_lock);
437
438 /* Delay to allow the clock oscillator to start. */
439 sec = MSTK_REG_SEC(regs);
440 for (i = 0; i < 3; i++) {
441 while (sec == MSTK_REG_SEC(regs))
442 for (count = 0; count < 100000; count++)
443 /* nothing */ ;
444 prom_printf(".");
445 sec = MSTK_REG_SEC(regs);
446 }
447 prom_printf("\n");
448
449 spin_lock_irq(&mostek_lock);
450
451 /* Turn off kick start and set a "valid" time and date. */
452 tmp = mostek_read(regs + MOSTEK_CREG);
453 tmp |= MSTK_CREG_WRITE;
454 mostek_write(regs + MOSTEK_CREG, tmp);
455 tmp = mostek_read(regs + MOSTEK_HOUR);
456 tmp &= ~MSTK_KICK_START;
457 mostek_write(regs + MOSTEK_HOUR, tmp);
458 MSTK_SET_REG_SEC(regs,0);
459 MSTK_SET_REG_MIN(regs,0);
460 MSTK_SET_REG_HOUR(regs,0);
461 MSTK_SET_REG_DOW(regs,5);
462 MSTK_SET_REG_DOM(regs,1);
463 MSTK_SET_REG_MONTH(regs,8);
464 MSTK_SET_REG_YEAR(regs,1996 - MSTK_YEAR_ZERO);
465 tmp = mostek_read(regs + MOSTEK_CREG);
466 tmp &= ~MSTK_CREG_WRITE;
467 mostek_write(regs + MOSTEK_CREG, tmp);
468
469 spin_unlock_irq(&mostek_lock);
470
471 /* Ensure the kick start bit is off. If it isn't, turn it off. */
472 while (mostek_read(regs + MOSTEK_HOUR) & MSTK_KICK_START) {
473 prom_printf("CLOCK: Kick start still on!\n");
474
475 spin_lock_irq(&mostek_lock);
476
477 tmp = mostek_read(regs + MOSTEK_CREG);
478 tmp |= MSTK_CREG_WRITE;
479 mostek_write(regs + MOSTEK_CREG, tmp);
480
481 tmp = mostek_read(regs + MOSTEK_HOUR);
482 tmp &= ~MSTK_KICK_START;
483 mostek_write(regs + MOSTEK_HOUR, tmp);
484
485 tmp = mostek_read(regs + MOSTEK_CREG);
486 tmp &= ~MSTK_CREG_WRITE;
487 mostek_write(regs + MOSTEK_CREG, tmp);
488
489 spin_unlock_irq(&mostek_lock);
490 }
491
492 prom_printf("CLOCK: Kick start procedure successful.\n");
493 }
494
495 /* Return nonzero if the clock chip battery is low. */
496 static int __init has_low_battery(void)
497 {
498 void __iomem *regs = mstk48t02_regs;
499 u8 data1, data2;
500
501 spin_lock_irq(&mostek_lock);
502
503 data1 = mostek_read(regs + MOSTEK_EEPROM); /* Read some data. */
504 mostek_write(regs + MOSTEK_EEPROM, ~data1); /* Write back the complement. */
505 data2 = mostek_read(regs + MOSTEK_EEPROM); /* Read back the complement. */
506 mostek_write(regs + MOSTEK_EEPROM, data1); /* Restore original value. */
507
508 spin_unlock_irq(&mostek_lock);
509
510 return (data1 == data2); /* Was the write blocked? */
511 }
512
513 static void __init mostek_set_system_time(void __iomem *mregs)
514 {
515 unsigned int year, mon, day, hour, min, sec;
516 u8 tmp;
517
518 spin_lock_irq(&mostek_lock);
519
520 /* Traditional Mostek chip. */
521 tmp = mostek_read(mregs + MOSTEK_CREG);
522 tmp |= MSTK_CREG_READ;
523 mostek_write(mregs + MOSTEK_CREG, tmp);
524
525 sec = MSTK_REG_SEC(mregs);
526 min = MSTK_REG_MIN(mregs);
527 hour = MSTK_REG_HOUR(mregs);
528 day = MSTK_REG_DOM(mregs);
529 mon = MSTK_REG_MONTH(mregs);
530 year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) );
531
532 xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
533 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
534 set_normalized_timespec(&wall_to_monotonic,
535 -xtime.tv_sec, -xtime.tv_nsec);
536
537 tmp = mostek_read(mregs + MOSTEK_CREG);
538 tmp &= ~MSTK_CREG_READ;
539 mostek_write(mregs + MOSTEK_CREG, tmp);
540
541 spin_unlock_irq(&mostek_lock);
542 }
543
544 /* Probe for the real time clock chip. */
545 static void __init set_system_time(void)
546 {
547 unsigned int year, mon, day, hour, min, sec;
548 void __iomem *mregs = mstk48t02_regs;
549 #ifdef CONFIG_PCI
550 unsigned long dregs = ds1287_regs;
551 void __iomem *bregs = bq4802_regs;
552 #else
553 unsigned long dregs = 0UL;
554 void __iomem *bregs = 0UL;
555 #endif
556
557 if (!mregs && !dregs && !bregs) {
558 prom_printf("Something wrong, clock regs not mapped yet.\n");
559 prom_halt();
560 }
561
562 if (mregs) {
563 mostek_set_system_time(mregs);
564 return;
565 }
566
567 if (bregs) {
568 unsigned char val = readb(bregs + 0x0e);
569 unsigned int century;
570
571 /* BQ4802 RTC chip. */
572
573 writeb(val | 0x08, bregs + 0x0e);
574
575 sec = readb(bregs + 0x00);
576 min = readb(bregs + 0x02);
577 hour = readb(bregs + 0x04);
578 day = readb(bregs + 0x06);
579 mon = readb(bregs + 0x09);
580 year = readb(bregs + 0x0a);
581 century = readb(bregs + 0x0f);
582
583 writeb(val, bregs + 0x0e);
584
585 BCD_TO_BIN(sec);
586 BCD_TO_BIN(min);
587 BCD_TO_BIN(hour);
588 BCD_TO_BIN(day);
589 BCD_TO_BIN(mon);
590 BCD_TO_BIN(year);
591 BCD_TO_BIN(century);
592
593 year += (century * 100);
594 } else {
595 /* Dallas 12887 RTC chip. */
596
597 do {
598 sec = CMOS_READ(RTC_SECONDS);
599 min = CMOS_READ(RTC_MINUTES);
600 hour = CMOS_READ(RTC_HOURS);
601 day = CMOS_READ(RTC_DAY_OF_MONTH);
602 mon = CMOS_READ(RTC_MONTH);
603 year = CMOS_READ(RTC_YEAR);
604 } while (sec != CMOS_READ(RTC_SECONDS));
605
606 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
607 BCD_TO_BIN(sec);
608 BCD_TO_BIN(min);
609 BCD_TO_BIN(hour);
610 BCD_TO_BIN(day);
611 BCD_TO_BIN(mon);
612 BCD_TO_BIN(year);
613 }
614 if ((year += 1900) < 1970)
615 year += 100;
616 }
617
618 xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
619 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
620 set_normalized_timespec(&wall_to_monotonic,
621 -xtime.tv_sec, -xtime.tv_nsec);
622 }
623
624 /* davem suggests we keep this within the 4M locked kernel image */
625 static u32 starfire_get_time(void)
626 {
627 static char obp_gettod[32];
628 static u32 unix_tod;
629
630 sprintf(obp_gettod, "h# %08x unix-gettod",
631 (unsigned int) (long) &unix_tod);
632 prom_feval(obp_gettod);
633
634 return unix_tod;
635 }
636
637 static int starfire_set_time(u32 val)
638 {
639 /* Do nothing, time is set using the service processor
640 * console on this platform.
641 */
642 return 0;
643 }
644
645 static u32 hypervisor_get_time(void)
646 {
647 unsigned long ret, time;
648 int retries = 10000;
649
650 retry:
651 ret = sun4v_tod_get(&time);
652 if (ret == HV_EOK)
653 return time;
654 if (ret == HV_EWOULDBLOCK) {
655 if (--retries > 0) {
656 udelay(100);
657 goto retry;
658 }
659 printk(KERN_WARNING "SUN4V: tod_get() timed out.\n");
660 return 0;
661 }
662 printk(KERN_WARNING "SUN4V: tod_get() not supported.\n");
663 return 0;
664 }
665
666 static int hypervisor_set_time(u32 secs)
667 {
668 unsigned long ret;
669 int retries = 10000;
670
671 retry:
672 ret = sun4v_tod_set(secs);
673 if (ret == HV_EOK)
674 return 0;
675 if (ret == HV_EWOULDBLOCK) {
676 if (--retries > 0) {
677 udelay(100);
678 goto retry;
679 }
680 printk(KERN_WARNING "SUN4V: tod_set() timed out.\n");
681 return -EAGAIN;
682 }
683 printk(KERN_WARNING "SUN4V: tod_set() not supported.\n");
684 return -EOPNOTSUPP;
685 }
686
687 static int __init clock_model_matches(const char *model)
688 {
689 if (strcmp(model, "mk48t02") &&
690 strcmp(model, "mk48t08") &&
691 strcmp(model, "mk48t59") &&
692 strcmp(model, "m5819") &&
693 strcmp(model, "m5819p") &&
694 strcmp(model, "m5823") &&
695 strcmp(model, "ds1287") &&
696 strcmp(model, "bq4802"))
697 return 0;
698
699 return 1;
700 }
701
702 static int __devinit clock_probe(struct of_device *op, const struct of_device_id *match)
703 {
704 struct device_node *dp = op->node;
705 const char *model = of_get_property(dp, "model", NULL);
706 const char *compat = of_get_property(dp, "compatible", NULL);
707 unsigned long size, flags;
708 void __iomem *regs;
709
710 if (!model)
711 model = compat;
712
713 if (!model || !clock_model_matches(model))
714 return -ENODEV;
715
716 /* On an Enterprise system there can be multiple mostek clocks.
717 * We should only match the one that is on the central FHC bus.
718 */
719 if (!strcmp(dp->parent->name, "fhc") &&
720 strcmp(dp->parent->parent->name, "central") != 0)
721 return -ENODEV;
722
723 size = (op->resource[0].end - op->resource[0].start) + 1;
724 regs = of_ioremap(&op->resource[0], 0, size, "clock");
725 if (!regs)
726 return -ENOMEM;
727
728 #ifdef CONFIG_PCI
729 if (!strcmp(model, "ds1287") ||
730 !strcmp(model, "m5819") ||
731 !strcmp(model, "m5819p") ||
732 !strcmp(model, "m5823")) {
733 ds1287_regs = (unsigned long) regs;
734 } else if (!strcmp(model, "bq4802")) {
735 bq4802_regs = regs;
736 } else
737 #endif
738 if (model[5] == '0' && model[6] == '2') {
739 mstk48t02_regs = regs;
740 } else if(model[5] == '0' && model[6] == '8') {
741 mstk48t08_regs = regs;
742 mstk48t02_regs = mstk48t08_regs + MOSTEK_48T08_48T02;
743 } else {
744 mstk48t59_regs = regs;
745 mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
746 }
747
748 printk(KERN_INFO "%s: Clock regs at %p\n", dp->full_name, regs);
749
750 local_irq_save(flags);
751
752 if (mstk48t02_regs != NULL) {
753 /* Report a low battery voltage condition. */
754 if (has_low_battery())
755 prom_printf("NVRAM: Low battery voltage!\n");
756
757 /* Kick start the clock if it is completely stopped. */
758 if (mostek_read(mstk48t02_regs + MOSTEK_SEC) & MSTK_STOP)
759 kick_start_clock();
760 }
761
762 set_system_time();
763
764 local_irq_restore(flags);
765
766 return 0;
767 }
768
769 static struct of_device_id clock_match[] = {
770 {
771 .name = "eeprom",
772 },
773 {
774 .name = "rtc",
775 },
776 {},
777 };
778
779 static struct of_platform_driver clock_driver = {
780 .match_table = clock_match,
781 .probe = clock_probe,
782 .driver = {
783 .name = "clock",
784 },
785 };
786
787 static int __init clock_init(void)
788 {
789 if (this_is_starfire) {
790 xtime.tv_sec = starfire_get_time();
791 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
792 set_normalized_timespec(&wall_to_monotonic,
793 -xtime.tv_sec, -xtime.tv_nsec);
794 return 0;
795 }
796 if (tlb_type == hypervisor) {
797 xtime.tv_sec = hypervisor_get_time();
798 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
799 set_normalized_timespec(&wall_to_monotonic,
800 -xtime.tv_sec, -xtime.tv_nsec);
801 return 0;
802 }
803
804 return of_register_driver(&clock_driver, &of_platform_bus_type);
805 }
806
807 /* Must be after subsys_initcall() so that busses are probed. Must
808 * be before device_initcall() because things like the RTC driver
809 * need to see the clock registers.
810 */
811 fs_initcall(clock_init);
812
813 /* This is gets the master TICK_INT timer going. */
814 static unsigned long sparc64_init_timers(void)
815 {
816 struct device_node *dp;
817 unsigned long clock;
818
819 dp = of_find_node_by_path("/");
820 if (tlb_type == spitfire) {
821 unsigned long ver, manuf, impl;
822
823 __asm__ __volatile__ ("rdpr %%ver, %0"
824 : "=&r" (ver));
825 manuf = ((ver >> 48) & 0xffff);
826 impl = ((ver >> 32) & 0xffff);
827 if (manuf == 0x17 && impl == 0x13) {
828 /* Hummingbird, aka Ultra-IIe */
829 tick_ops = &hbtick_operations;
830 clock = of_getintprop_default(dp, "stick-frequency", 0);
831 } else {
832 tick_ops = &tick_operations;
833 clock = local_cpu_data().clock_tick;
834 }
835 } else {
836 tick_ops = &stick_operations;
837 clock = of_getintprop_default(dp, "stick-frequency", 0);
838 }
839
840 return clock;
841 }
842
843 struct freq_table {
844 unsigned long clock_tick_ref;
845 unsigned int ref_freq;
846 };
847 static DEFINE_PER_CPU(struct freq_table, sparc64_freq_table) = { 0, 0 };
848
849 unsigned long sparc64_get_clock_tick(unsigned int cpu)
850 {
851 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu);
852
853 if (ft->clock_tick_ref)
854 return ft->clock_tick_ref;
855 return cpu_data(cpu).clock_tick;
856 }
857
858 #ifdef CONFIG_CPU_FREQ
859
860 static int sparc64_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
861 void *data)
862 {
863 struct cpufreq_freqs *freq = data;
864 unsigned int cpu = freq->cpu;
865 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu);
866
867 if (!ft->ref_freq) {
868 ft->ref_freq = freq->old;
869 ft->clock_tick_ref = cpu_data(cpu).clock_tick;
870 }
871 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
872 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
873 (val == CPUFREQ_RESUMECHANGE)) {
874 cpu_data(cpu).clock_tick =
875 cpufreq_scale(ft->clock_tick_ref,
876 ft->ref_freq,
877 freq->new);
878 }
879
880 return 0;
881 }
882
883 static struct notifier_block sparc64_cpufreq_notifier_block = {
884 .notifier_call = sparc64_cpufreq_notifier
885 };
886
887 #endif /* CONFIG_CPU_FREQ */
888
889 static int sparc64_next_event(unsigned long delta,
890 struct clock_event_device *evt)
891 {
892 return tick_ops->add_compare(delta) ? -ETIME : 0;
893 }
894
895 static void sparc64_timer_setup(enum clock_event_mode mode,
896 struct clock_event_device *evt)
897 {
898 switch (mode) {
899 case CLOCK_EVT_MODE_ONESHOT:
900 case CLOCK_EVT_MODE_RESUME:
901 break;
902
903 case CLOCK_EVT_MODE_SHUTDOWN:
904 tick_ops->disable_irq();
905 break;
906
907 case CLOCK_EVT_MODE_PERIODIC:
908 case CLOCK_EVT_MODE_UNUSED:
909 WARN_ON(1);
910 break;
911 };
912 }
913
914 static struct clock_event_device sparc64_clockevent = {
915 .features = CLOCK_EVT_FEAT_ONESHOT,
916 .set_mode = sparc64_timer_setup,
917 .set_next_event = sparc64_next_event,
918 .rating = 100,
919 .shift = 30,
920 .irq = -1,
921 };
922 static DEFINE_PER_CPU(struct clock_event_device, sparc64_events);
923
924 void timer_interrupt(int irq, struct pt_regs *regs)
925 {
926 struct pt_regs *old_regs = set_irq_regs(regs);
927 unsigned long tick_mask = tick_ops->softint_mask;
928 int cpu = smp_processor_id();
929 struct clock_event_device *evt = &per_cpu(sparc64_events, cpu);
930
931 clear_softint(tick_mask);
932
933 irq_enter();
934
935 kstat_this_cpu.irqs[0]++;
936
937 if (unlikely(!evt->event_handler)) {
938 printk(KERN_WARNING
939 "Spurious SPARC64 timer interrupt on cpu %d\n", cpu);
940 } else
941 evt->event_handler(evt);
942
943 irq_exit();
944
945 set_irq_regs(old_regs);
946 }
947
948 void __devinit setup_sparc64_timer(void)
949 {
950 struct clock_event_device *sevt;
951 unsigned long pstate;
952
953 /* Guarantee that the following sequences execute
954 * uninterrupted.
955 */
956 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
957 "wrpr %0, %1, %%pstate"
958 : "=r" (pstate)
959 : "i" (PSTATE_IE));
960
961 tick_ops->init_tick();
962
963 /* Restore PSTATE_IE. */
964 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
965 : /* no outputs */
966 : "r" (pstate));
967
968 sevt = &__get_cpu_var(sparc64_events);
969
970 memcpy(sevt, &sparc64_clockevent, sizeof(*sevt));
971 sevt->cpumask = cpumask_of_cpu(smp_processor_id());
972
973 clockevents_register_device(sevt);
974 }
975
976 #define SPARC64_NSEC_PER_CYC_SHIFT 10UL
977
978 static struct clocksource clocksource_tick = {
979 .rating = 100,
980 .mask = CLOCKSOURCE_MASK(64),
981 .shift = 16,
982 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
983 };
984
985 static void __init setup_clockevent_multiplier(unsigned long hz)
986 {
987 unsigned long mult, shift = 32;
988
989 while (1) {
990 mult = div_sc(hz, NSEC_PER_SEC, shift);
991 if (mult && (mult >> 32UL) == 0UL)
992 break;
993
994 shift--;
995 }
996
997 sparc64_clockevent.shift = shift;
998 sparc64_clockevent.mult = mult;
999 }
1000
1001 static unsigned long tb_ticks_per_usec __read_mostly;
1002
1003 void __delay(unsigned long loops)
1004 {
1005 unsigned long bclock, now;
1006
1007 bclock = tick_ops->get_tick();
1008 do {
1009 now = tick_ops->get_tick();
1010 } while ((now-bclock) < loops);
1011 }
1012 EXPORT_SYMBOL(__delay);
1013
1014 void udelay(unsigned long usecs)
1015 {
1016 __delay(tb_ticks_per_usec * usecs);
1017 }
1018 EXPORT_SYMBOL(udelay);
1019
1020 void __init time_init(void)
1021 {
1022 unsigned long clock = sparc64_init_timers();
1023
1024 tb_ticks_per_usec = clock / USEC_PER_SEC;
1025
1026 timer_ticks_per_nsec_quotient =
1027 clocksource_hz2mult(clock, SPARC64_NSEC_PER_CYC_SHIFT);
1028
1029 clocksource_tick.name = tick_ops->name;
1030 clocksource_tick.mult =
1031 clocksource_hz2mult(clock,
1032 clocksource_tick.shift);
1033 clocksource_tick.read = tick_ops->get_tick;
1034
1035 printk("clocksource: mult[%x] shift[%d]\n",
1036 clocksource_tick.mult, clocksource_tick.shift);
1037
1038 clocksource_register(&clocksource_tick);
1039
1040 sparc64_clockevent.name = tick_ops->name;
1041
1042 setup_clockevent_multiplier(clock);
1043
1044 sparc64_clockevent.max_delta_ns =
1045 clockevent_delta2ns(0x7fffffffffffffffUL, &sparc64_clockevent);
1046 sparc64_clockevent.min_delta_ns =
1047 clockevent_delta2ns(0xF, &sparc64_clockevent);
1048
1049 printk("clockevent: mult[%lx] shift[%d]\n",
1050 sparc64_clockevent.mult, sparc64_clockevent.shift);
1051
1052 setup_sparc64_timer();
1053
1054 #ifdef CONFIG_CPU_FREQ
1055 cpufreq_register_notifier(&sparc64_cpufreq_notifier_block,
1056 CPUFREQ_TRANSITION_NOTIFIER);
1057 #endif
1058 }
1059
1060 unsigned long long sched_clock(void)
1061 {
1062 unsigned long ticks = tick_ops->get_tick();
1063
1064 return (ticks * timer_ticks_per_nsec_quotient)
1065 >> SPARC64_NSEC_PER_CYC_SHIFT;
1066 }
1067
1068 static int set_rtc_mmss(unsigned long nowtime)
1069 {
1070 int real_seconds, real_minutes, chip_minutes;
1071 void __iomem *mregs = mstk48t02_regs;
1072 #ifdef CONFIG_PCI
1073 unsigned long dregs = ds1287_regs;
1074 void __iomem *bregs = bq4802_regs;
1075 #else
1076 unsigned long dregs = 0UL;
1077 void __iomem *bregs = 0UL;
1078 #endif
1079 unsigned long flags;
1080 u8 tmp;
1081
1082 /*
1083 * Not having a register set can lead to trouble.
1084 * Also starfire doesn't have a tod clock.
1085 */
1086 if (!mregs && !dregs && !bregs)
1087 return -1;
1088
1089 if (mregs) {
1090 spin_lock_irqsave(&mostek_lock, flags);
1091
1092 /* Read the current RTC minutes. */
1093 tmp = mostek_read(mregs + MOSTEK_CREG);
1094 tmp |= MSTK_CREG_READ;
1095 mostek_write(mregs + MOSTEK_CREG, tmp);
1096
1097 chip_minutes = MSTK_REG_MIN(mregs);
1098
1099 tmp = mostek_read(mregs + MOSTEK_CREG);
1100 tmp &= ~MSTK_CREG_READ;
1101 mostek_write(mregs + MOSTEK_CREG, tmp);
1102
1103 /*
1104 * since we're only adjusting minutes and seconds,
1105 * don't interfere with hour overflow. This avoids
1106 * messing with unknown time zones but requires your
1107 * RTC not to be off by more than 15 minutes
1108 */
1109 real_seconds = nowtime % 60;
1110 real_minutes = nowtime / 60;
1111 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1112 real_minutes += 30; /* correct for half hour time zone */
1113 real_minutes %= 60;
1114
1115 if (abs(real_minutes - chip_minutes) < 30) {
1116 tmp = mostek_read(mregs + MOSTEK_CREG);
1117 tmp |= MSTK_CREG_WRITE;
1118 mostek_write(mregs + MOSTEK_CREG, tmp);
1119
1120 MSTK_SET_REG_SEC(mregs,real_seconds);
1121 MSTK_SET_REG_MIN(mregs,real_minutes);
1122
1123 tmp = mostek_read(mregs + MOSTEK_CREG);
1124 tmp &= ~MSTK_CREG_WRITE;
1125 mostek_write(mregs + MOSTEK_CREG, tmp);
1126
1127 spin_unlock_irqrestore(&mostek_lock, flags);
1128
1129 return 0;
1130 } else {
1131 spin_unlock_irqrestore(&mostek_lock, flags);
1132
1133 return -1;
1134 }
1135 } else if (bregs) {
1136 int retval = 0;
1137 unsigned char val = readb(bregs + 0x0e);
1138
1139 /* BQ4802 RTC chip. */
1140
1141 writeb(val | 0x08, bregs + 0x0e);
1142
1143 chip_minutes = readb(bregs + 0x02);
1144 BCD_TO_BIN(chip_minutes);
1145 real_seconds = nowtime % 60;
1146 real_minutes = nowtime / 60;
1147 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1148 real_minutes += 30;
1149 real_minutes %= 60;
1150
1151 if (abs(real_minutes - chip_minutes) < 30) {
1152 BIN_TO_BCD(real_seconds);
1153 BIN_TO_BCD(real_minutes);
1154 writeb(real_seconds, bregs + 0x00);
1155 writeb(real_minutes, bregs + 0x02);
1156 } else {
1157 printk(KERN_WARNING
1158 "set_rtc_mmss: can't update from %d to %d\n",
1159 chip_minutes, real_minutes);
1160 retval = -1;
1161 }
1162
1163 writeb(val, bregs + 0x0e);
1164
1165 return retval;
1166 } else {
1167 int retval = 0;
1168 unsigned char save_control, save_freq_select;
1169
1170 /* Stolen from arch/i386/kernel/time.c, see there for
1171 * credits and descriptive comments.
1172 */
1173 spin_lock_irqsave(&rtc_lock, flags);
1174 save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
1175 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
1176
1177 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
1178 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
1179
1180 chip_minutes = CMOS_READ(RTC_MINUTES);
1181 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
1182 BCD_TO_BIN(chip_minutes);
1183 real_seconds = nowtime % 60;
1184 real_minutes = nowtime / 60;
1185 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1186 real_minutes += 30;
1187 real_minutes %= 60;
1188
1189 if (abs(real_minutes - chip_minutes) < 30) {
1190 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
1191 BIN_TO_BCD(real_seconds);
1192 BIN_TO_BCD(real_minutes);
1193 }
1194 CMOS_WRITE(real_seconds,RTC_SECONDS);
1195 CMOS_WRITE(real_minutes,RTC_MINUTES);
1196 } else {
1197 printk(KERN_WARNING
1198 "set_rtc_mmss: can't update from %d to %d\n",
1199 chip_minutes, real_minutes);
1200 retval = -1;
1201 }
1202
1203 CMOS_WRITE(save_control, RTC_CONTROL);
1204 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1205 spin_unlock_irqrestore(&rtc_lock, flags);
1206
1207 return retval;
1208 }
1209 }
1210
1211 #define RTC_IS_OPEN 0x01 /* means /dev/rtc is in use */
1212 static unsigned char mini_rtc_status; /* bitmapped status byte. */
1213
1214 #define FEBRUARY 2
1215 #define STARTOFTIME 1970
1216 #define SECDAY 86400L
1217 #define SECYR (SECDAY * 365)
1218 #define leapyear(year) ((year) % 4 == 0 && \
1219 ((year) % 100 != 0 || (year) % 400 == 0))
1220 #define days_in_year(a) (leapyear(a) ? 366 : 365)
1221 #define days_in_month(a) (month_days[(a) - 1])
1222
1223 static int month_days[12] = {
1224 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
1225 };
1226
1227 /*
1228 * This only works for the Gregorian calendar - i.e. after 1752 (in the UK)
1229 */
1230 static void GregorianDay(struct rtc_time * tm)
1231 {
1232 int leapsToDate;
1233 int lastYear;
1234 int day;
1235 int MonthOffset[] = { 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 };
1236
1237 lastYear = tm->tm_year - 1;
1238
1239 /*
1240 * Number of leap corrections to apply up to end of last year
1241 */
1242 leapsToDate = lastYear / 4 - lastYear / 100 + lastYear / 400;
1243
1244 /*
1245 * This year is a leap year if it is divisible by 4 except when it is
1246 * divisible by 100 unless it is divisible by 400
1247 *
1248 * e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 was
1249 */
1250 day = tm->tm_mon > 2 && leapyear(tm->tm_year);
1251
1252 day += lastYear*365 + leapsToDate + MonthOffset[tm->tm_mon-1] +
1253 tm->tm_mday;
1254
1255 tm->tm_wday = day % 7;
1256 }
1257
1258 static void to_tm(int tim, struct rtc_time *tm)
1259 {
1260 register int i;
1261 register long hms, day;
1262
1263 day = tim / SECDAY;
1264 hms = tim % SECDAY;
1265
1266 /* Hours, minutes, seconds are easy */
1267 tm->tm_hour = hms / 3600;
1268 tm->tm_min = (hms % 3600) / 60;
1269 tm->tm_sec = (hms % 3600) % 60;
1270
1271 /* Number of years in days */
1272 for (i = STARTOFTIME; day >= days_in_year(i); i++)
1273 day -= days_in_year(i);
1274 tm->tm_year = i;
1275
1276 /* Number of months in days left */
1277 if (leapyear(tm->tm_year))
1278 days_in_month(FEBRUARY) = 29;
1279 for (i = 1; day >= days_in_month(i); i++)
1280 day -= days_in_month(i);
1281 days_in_month(FEBRUARY) = 28;
1282 tm->tm_mon = i;
1283
1284 /* Days are what is left over (+1) from all that. */
1285 tm->tm_mday = day + 1;
1286
1287 /*
1288 * Determine the day of week
1289 */
1290 GregorianDay(tm);
1291 }
1292
1293 /* Both Starfire and SUN4V give us seconds since Jan 1st, 1970,
1294 * aka Unix time. So we have to convert to/from rtc_time.
1295 */
1296 static void starfire_get_rtc_time(struct rtc_time *time)
1297 {
1298 u32 seconds = starfire_get_time();
1299
1300 to_tm(seconds, time);
1301 time->tm_year -= 1900;
1302 time->tm_mon -= 1;
1303 }
1304
1305 static int starfire_set_rtc_time(struct rtc_time *time)
1306 {
1307 u32 seconds = mktime(time->tm_year + 1900, time->tm_mon + 1,
1308 time->tm_mday, time->tm_hour,
1309 time->tm_min, time->tm_sec);
1310
1311 return starfire_set_time(seconds);
1312 }
1313
1314 static void hypervisor_get_rtc_time(struct rtc_time *time)
1315 {
1316 u32 seconds = hypervisor_get_time();
1317
1318 to_tm(seconds, time);
1319 time->tm_year -= 1900;
1320 time->tm_mon -= 1;
1321 }
1322
1323 static int hypervisor_set_rtc_time(struct rtc_time *time)
1324 {
1325 u32 seconds = mktime(time->tm_year + 1900, time->tm_mon + 1,
1326 time->tm_mday, time->tm_hour,
1327 time->tm_min, time->tm_sec);
1328
1329 return hypervisor_set_time(seconds);
1330 }
1331
1332 #ifdef CONFIG_PCI
1333 static void bq4802_get_rtc_time(struct rtc_time *time)
1334 {
1335 unsigned char val = readb(bq4802_regs + 0x0e);
1336 unsigned int century;
1337
1338 writeb(val | 0x08, bq4802_regs + 0x0e);
1339
1340 time->tm_sec = readb(bq4802_regs + 0x00);
1341 time->tm_min = readb(bq4802_regs + 0x02);
1342 time->tm_hour = readb(bq4802_regs + 0x04);
1343 time->tm_mday = readb(bq4802_regs + 0x06);
1344 time->tm_mon = readb(bq4802_regs + 0x09);
1345 time->tm_year = readb(bq4802_regs + 0x0a);
1346 time->tm_wday = readb(bq4802_regs + 0x08);
1347 century = readb(bq4802_regs + 0x0f);
1348
1349 writeb(val, bq4802_regs + 0x0e);
1350
1351 BCD_TO_BIN(time->tm_sec);
1352 BCD_TO_BIN(time->tm_min);
1353 BCD_TO_BIN(time->tm_hour);
1354 BCD_TO_BIN(time->tm_mday);
1355 BCD_TO_BIN(time->tm_mon);
1356 BCD_TO_BIN(time->tm_year);
1357 BCD_TO_BIN(time->tm_wday);
1358 BCD_TO_BIN(century);
1359
1360 time->tm_year += (century * 100);
1361 time->tm_year -= 1900;
1362
1363 time->tm_mon--;
1364 }
1365
1366 static int bq4802_set_rtc_time(struct rtc_time *time)
1367 {
1368 unsigned char val = readb(bq4802_regs + 0x0e);
1369 unsigned char sec, min, hrs, day, mon, yrs, century;
1370 unsigned int year;
1371
1372 year = time->tm_year + 1900;
1373 century = year / 100;
1374 yrs = year % 100;
1375
1376 mon = time->tm_mon + 1; /* tm_mon starts at zero */
1377 day = time->tm_mday;
1378 hrs = time->tm_hour;
1379 min = time->tm_min;
1380 sec = time->tm_sec;
1381
1382 BIN_TO_BCD(sec);
1383 BIN_TO_BCD(min);
1384 BIN_TO_BCD(hrs);
1385 BIN_TO_BCD(day);
1386 BIN_TO_BCD(mon);
1387 BIN_TO_BCD(yrs);
1388 BIN_TO_BCD(century);
1389
1390 writeb(val | 0x08, bq4802_regs + 0x0e);
1391
1392 writeb(sec, bq4802_regs + 0x00);
1393 writeb(min, bq4802_regs + 0x02);
1394 writeb(hrs, bq4802_regs + 0x04);
1395 writeb(day, bq4802_regs + 0x06);
1396 writeb(mon, bq4802_regs + 0x09);
1397 writeb(yrs, bq4802_regs + 0x0a);
1398 writeb(century, bq4802_regs + 0x0f);
1399
1400 writeb(val, bq4802_regs + 0x0e);
1401
1402 return 0;
1403 }
1404
1405 static void cmos_get_rtc_time(struct rtc_time *rtc_tm)
1406 {
1407 unsigned char ctrl;
1408
1409 rtc_tm->tm_sec = CMOS_READ(RTC_SECONDS);
1410 rtc_tm->tm_min = CMOS_READ(RTC_MINUTES);
1411 rtc_tm->tm_hour = CMOS_READ(RTC_HOURS);
1412 rtc_tm->tm_mday = CMOS_READ(RTC_DAY_OF_MONTH);
1413 rtc_tm->tm_mon = CMOS_READ(RTC_MONTH);
1414 rtc_tm->tm_year = CMOS_READ(RTC_YEAR);
1415 rtc_tm->tm_wday = CMOS_READ(RTC_DAY_OF_WEEK);
1416
1417 ctrl = CMOS_READ(RTC_CONTROL);
1418 if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
1419 BCD_TO_BIN(rtc_tm->tm_sec);
1420 BCD_TO_BIN(rtc_tm->tm_min);
1421 BCD_TO_BIN(rtc_tm->tm_hour);
1422 BCD_TO_BIN(rtc_tm->tm_mday);
1423 BCD_TO_BIN(rtc_tm->tm_mon);
1424 BCD_TO_BIN(rtc_tm->tm_year);
1425 BCD_TO_BIN(rtc_tm->tm_wday);
1426 }
1427
1428 if (rtc_tm->tm_year <= 69)
1429 rtc_tm->tm_year += 100;
1430
1431 rtc_tm->tm_mon--;
1432 }
1433
1434 static int cmos_set_rtc_time(struct rtc_time *rtc_tm)
1435 {
1436 unsigned char mon, day, hrs, min, sec;
1437 unsigned char save_control, save_freq_select;
1438 unsigned int yrs;
1439
1440 yrs = rtc_tm->tm_year;
1441 mon = rtc_tm->tm_mon + 1;
1442 day = rtc_tm->tm_mday;
1443 hrs = rtc_tm->tm_hour;
1444 min = rtc_tm->tm_min;
1445 sec = rtc_tm->tm_sec;
1446
1447 if (yrs >= 100)
1448 yrs -= 100;
1449
1450 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
1451 BIN_TO_BCD(sec);
1452 BIN_TO_BCD(min);
1453 BIN_TO_BCD(hrs);
1454 BIN_TO_BCD(day);
1455 BIN_TO_BCD(mon);
1456 BIN_TO_BCD(yrs);
1457 }
1458
1459 save_control = CMOS_READ(RTC_CONTROL);
1460 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
1461 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1462 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
1463
1464 CMOS_WRITE(yrs, RTC_YEAR);
1465 CMOS_WRITE(mon, RTC_MONTH);
1466 CMOS_WRITE(day, RTC_DAY_OF_MONTH);
1467 CMOS_WRITE(hrs, RTC_HOURS);
1468 CMOS_WRITE(min, RTC_MINUTES);
1469 CMOS_WRITE(sec, RTC_SECONDS);
1470
1471 CMOS_WRITE(save_control, RTC_CONTROL);
1472 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1473
1474 return 0;
1475 }
1476 #endif /* CONFIG_PCI */
1477
1478 static void mostek_get_rtc_time(struct rtc_time *rtc_tm)
1479 {
1480 void __iomem *regs = mstk48t02_regs;
1481 u8 tmp;
1482
1483 spin_lock_irq(&mostek_lock);
1484
1485 tmp = mostek_read(regs + MOSTEK_CREG);
1486 tmp |= MSTK_CREG_READ;
1487 mostek_write(regs + MOSTEK_CREG, tmp);
1488
1489 rtc_tm->tm_sec = MSTK_REG_SEC(regs);
1490 rtc_tm->tm_min = MSTK_REG_MIN(regs);
1491 rtc_tm->tm_hour = MSTK_REG_HOUR(regs);
1492 rtc_tm->tm_mday = MSTK_REG_DOM(regs);
1493 rtc_tm->tm_mon = MSTK_REG_MONTH(regs);
1494 rtc_tm->tm_year = MSTK_CVT_YEAR( MSTK_REG_YEAR(regs) );
1495 rtc_tm->tm_wday = MSTK_REG_DOW(regs);
1496
1497 tmp = mostek_read(regs + MOSTEK_CREG);
1498 tmp &= ~MSTK_CREG_READ;
1499 mostek_write(regs + MOSTEK_CREG, tmp);
1500
1501 spin_unlock_irq(&mostek_lock);
1502
1503 rtc_tm->tm_mon--;
1504 rtc_tm->tm_wday--;
1505 rtc_tm->tm_year -= 1900;
1506 }
1507
1508 static int mostek_set_rtc_time(struct rtc_time *rtc_tm)
1509 {
1510 unsigned char mon, day, hrs, min, sec, wday;
1511 void __iomem *regs = mstk48t02_regs;
1512 unsigned int yrs;
1513 u8 tmp;
1514
1515 yrs = rtc_tm->tm_year + 1900;
1516 mon = rtc_tm->tm_mon + 1;
1517 day = rtc_tm->tm_mday;
1518 wday = rtc_tm->tm_wday + 1;
1519 hrs = rtc_tm->tm_hour;
1520 min = rtc_tm->tm_min;
1521 sec = rtc_tm->tm_sec;
1522
1523 spin_lock_irq(&mostek_lock);
1524
1525 tmp = mostek_read(regs + MOSTEK_CREG);
1526 tmp |= MSTK_CREG_WRITE;
1527 mostek_write(regs + MOSTEK_CREG, tmp);
1528
1529 MSTK_SET_REG_SEC(regs, sec);
1530 MSTK_SET_REG_MIN(regs, min);
1531 MSTK_SET_REG_HOUR(regs, hrs);
1532 MSTK_SET_REG_DOW(regs, wday);
1533 MSTK_SET_REG_DOM(regs, day);
1534 MSTK_SET_REG_MONTH(regs, mon);
1535 MSTK_SET_REG_YEAR(regs, yrs - MSTK_YEAR_ZERO);
1536
1537 tmp = mostek_read(regs + MOSTEK_CREG);
1538 tmp &= ~MSTK_CREG_WRITE;
1539 mostek_write(regs + MOSTEK_CREG, tmp);
1540
1541 spin_unlock_irq(&mostek_lock);
1542
1543 return 0;
1544 }
1545
1546 struct mini_rtc_ops {
1547 void (*get_rtc_time)(struct rtc_time *);
1548 int (*set_rtc_time)(struct rtc_time *);
1549 };
1550
1551 static struct mini_rtc_ops starfire_rtc_ops = {
1552 .get_rtc_time = starfire_get_rtc_time,
1553 .set_rtc_time = starfire_set_rtc_time,
1554 };
1555
1556 static struct mini_rtc_ops hypervisor_rtc_ops = {
1557 .get_rtc_time = hypervisor_get_rtc_time,
1558 .set_rtc_time = hypervisor_set_rtc_time,
1559 };
1560
1561 #ifdef CONFIG_PCI
1562 static struct mini_rtc_ops bq4802_rtc_ops = {
1563 .get_rtc_time = bq4802_get_rtc_time,
1564 .set_rtc_time = bq4802_set_rtc_time,
1565 };
1566
1567 static struct mini_rtc_ops cmos_rtc_ops = {
1568 .get_rtc_time = cmos_get_rtc_time,
1569 .set_rtc_time = cmos_set_rtc_time,
1570 };
1571 #endif /* CONFIG_PCI */
1572
1573 static struct mini_rtc_ops mostek_rtc_ops = {
1574 .get_rtc_time = mostek_get_rtc_time,
1575 .set_rtc_time = mostek_set_rtc_time,
1576 };
1577
1578 static struct mini_rtc_ops *mini_rtc_ops;
1579
1580 static inline void mini_get_rtc_time(struct rtc_time *time)
1581 {
1582 unsigned long flags;
1583
1584 spin_lock_irqsave(&rtc_lock, flags);
1585 mini_rtc_ops->get_rtc_time(time);
1586 spin_unlock_irqrestore(&rtc_lock, flags);
1587 }
1588
1589 static inline int mini_set_rtc_time(struct rtc_time *time)
1590 {
1591 unsigned long flags;
1592 int err;
1593
1594 spin_lock_irqsave(&rtc_lock, flags);
1595 err = mini_rtc_ops->set_rtc_time(time);
1596 spin_unlock_irqrestore(&rtc_lock, flags);
1597
1598 return err;
1599 }
1600
1601 static int mini_rtc_ioctl(struct inode *inode, struct file *file,
1602 unsigned int cmd, unsigned long arg)
1603 {
1604 struct rtc_time wtime;
1605 void __user *argp = (void __user *)arg;
1606
1607 switch (cmd) {
1608
1609 case RTC_PLL_GET:
1610 return -EINVAL;
1611
1612 case RTC_PLL_SET:
1613 return -EINVAL;
1614
1615 case RTC_UIE_OFF: /* disable ints from RTC updates. */
1616 return 0;
1617
1618 case RTC_UIE_ON: /* enable ints for RTC updates. */
1619 return -EINVAL;
1620
1621 case RTC_RD_TIME: /* Read the time/date from RTC */
1622 /* this doesn't get week-day, who cares */
1623 memset(&wtime, 0, sizeof(wtime));
1624 mini_get_rtc_time(&wtime);
1625
1626 return copy_to_user(argp, &wtime, sizeof(wtime)) ? -EFAULT : 0;
1627
1628 case RTC_SET_TIME: /* Set the RTC */
1629 {
1630 int year, days;
1631
1632 if (!capable(CAP_SYS_TIME))
1633 return -EACCES;
1634
1635 if (copy_from_user(&wtime, argp, sizeof(wtime)))
1636 return -EFAULT;
1637
1638 year = wtime.tm_year + 1900;
1639 days = month_days[wtime.tm_mon] +
1640 ((wtime.tm_mon == 1) && leapyear(year));
1641
1642 if ((wtime.tm_mon < 0 || wtime.tm_mon > 11) ||
1643 (wtime.tm_mday < 1))
1644 return -EINVAL;
1645
1646 if (wtime.tm_mday < 0 || wtime.tm_mday > days)
1647 return -EINVAL;
1648
1649 if (wtime.tm_hour < 0 || wtime.tm_hour >= 24 ||
1650 wtime.tm_min < 0 || wtime.tm_min >= 60 ||
1651 wtime.tm_sec < 0 || wtime.tm_sec >= 60)
1652 return -EINVAL;
1653
1654 return mini_set_rtc_time(&wtime);
1655 }
1656 }
1657
1658 return -EINVAL;
1659 }
1660
1661 static int mini_rtc_open(struct inode *inode, struct file *file)
1662 {
1663 lock_kernel();
1664 if (mini_rtc_status & RTC_IS_OPEN) {
1665 unlock_kernel();
1666 return -EBUSY;
1667 }
1668
1669 mini_rtc_status |= RTC_IS_OPEN;
1670 unlock_kernel();
1671
1672 return 0;
1673 }
1674
1675 static int mini_rtc_release(struct inode *inode, struct file *file)
1676 {
1677 mini_rtc_status &= ~RTC_IS_OPEN;
1678 return 0;
1679 }
1680
1681
1682 static const struct file_operations mini_rtc_fops = {
1683 .owner = THIS_MODULE,
1684 .ioctl = mini_rtc_ioctl,
1685 .open = mini_rtc_open,
1686 .release = mini_rtc_release,
1687 };
1688
1689 static struct miscdevice rtc_mini_dev =
1690 {
1691 .minor = RTC_MINOR,
1692 .name = "rtc",
1693 .fops = &mini_rtc_fops,
1694 };
1695
1696 static int __init rtc_mini_init(void)
1697 {
1698 int retval;
1699
1700 if (tlb_type == hypervisor)
1701 mini_rtc_ops = &hypervisor_rtc_ops;
1702 else if (this_is_starfire)
1703 mini_rtc_ops = &starfire_rtc_ops;
1704 #ifdef CONFIG_PCI
1705 else if (bq4802_regs)
1706 mini_rtc_ops = &bq4802_rtc_ops;
1707 else if (ds1287_regs)
1708 mini_rtc_ops = &cmos_rtc_ops;
1709 #endif /* CONFIG_PCI */
1710 else if (mstk48t02_regs)
1711 mini_rtc_ops = &mostek_rtc_ops;
1712 else
1713 return -ENODEV;
1714
1715 printk(KERN_INFO "Mini RTC Driver\n");
1716
1717 retval = misc_register(&rtc_mini_dev);
1718 if (retval < 0)
1719 return retval;
1720
1721 return 0;
1722 }
1723
1724 static void __exit rtc_mini_exit(void)
1725 {
1726 misc_deregister(&rtc_mini_dev);
1727 }
1728
1729 int __devinit read_current_timer(unsigned long *timer_val)
1730 {
1731 *timer_val = tick_ops->get_tick();
1732 return 0;
1733 }
1734
1735 module_init(rtc_mini_init);
1736 module_exit(rtc_mini_exit);
kernel source for telekom puls (alcatel/mediatek)