projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge with /usr/src/ntfs-2.6.git
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc64 / kernel / sbus.c
1 /* $Id: sbus.c,v 1.19 2002/01/23 11:27:32 davem Exp $
2 * sbus.c: UltraSparc SBUS controller support.
3 *
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 #include <linux/mm.h>
10 #include <linux/spinlock.h>
11 #include <linux/slab.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14
15 #include <asm/page.h>
16 #include <asm/sbus.h>
17 #include <asm/io.h>
18 #include <asm/upa.h>
19 #include <asm/cache.h>
20 #include <asm/dma.h>
21 #include <asm/irq.h>
22 #include <asm/starfire.h>
23
24 #include "iommu_common.h"
25
26 /* These should be allocated on an SMP_CACHE_BYTES
27 * aligned boundary for optimal performance.
28 *
29 * On SYSIO, using an 8K page size we have 1GB of SBUS
30 * DMA space mapped. We divide this space into equally
31 * sized clusters. We allocate a DMA mapping from the
32 * cluster that matches the order of the allocation, or
33 * if the order is greater than the number of clusters,
34 * we try to allocate from the last cluster.
35 */
36
37 #define NCLUSTERS 8UL
38 #define ONE_GIG (1UL * 1024UL * 1024UL * 1024UL)
39 #define CLUSTER_SIZE (ONE_GIG / NCLUSTERS)
40 #define CLUSTER_MASK (CLUSTER_SIZE - 1)
41 #define CLUSTER_NPAGES (CLUSTER_SIZE >> IO_PAGE_SHIFT)
42 #define MAP_BASE ((u32)0xc0000000)
43
44 struct sbus_iommu {
45 /*0x00*/spinlock_t lock;
46
47 /*0x08*/iopte_t *page_table;
48 /*0x10*/unsigned long strbuf_regs;
49 /*0x18*/unsigned long iommu_regs;
50 /*0x20*/unsigned long sbus_control_reg;
51
52 /*0x28*/volatile unsigned long strbuf_flushflag;
53
54 /* If NCLUSTERS is ever decresed to 4 or lower,
55 * you must increase the size of the type of
56 * these counters. You have been duly warned. -DaveM
57 */
58 /*0x30*/struct {
59 u16 next;
60 u16 flush;
61 } alloc_info[NCLUSTERS];
62
63 /* The lowest used consistent mapping entry. Since
64 * we allocate consistent maps out of cluster 0 this
65 * is relative to the beginning of closter 0.
66 */
67 /*0x50*/u32 lowest_consistent_map;
68 };
69
70 /* Offsets from iommu_regs */
71 #define SYSIO_IOMMUREG_BASE 0x2400UL
72 #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
73 #define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */
74 #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
75 #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
76 #define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */
77 #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
78 #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */
79 #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */
80
81 #define IOMMU_DRAM_VALID (1UL << 30UL)
82
83 static void __iommu_flushall(struct sbus_iommu *iommu)
84 {
85 unsigned long tag = iommu->iommu_regs + IOMMU_TAGDIAG;
86 int entry;
87
88 for (entry = 0; entry < 16; entry++) {
89 upa_writeq(0, tag);
90 tag += 8UL;
91 }
92 upa_readq(iommu->sbus_control_reg);
93
94 for (entry = 0; entry < NCLUSTERS; entry++) {
95 iommu->alloc_info[entry].flush =
96 iommu->alloc_info[entry].next;
97 }
98 }
99
100 static void iommu_flush(struct sbus_iommu *iommu, u32 base, unsigned long npages)
101 {
102 while (npages--)
103 upa_writeq(base + (npages << IO_PAGE_SHIFT),
104 iommu->iommu_regs + IOMMU_FLUSH);
105 upa_readq(iommu->sbus_control_reg);
106 }
107
108 /* Offsets from strbuf_regs */
109 #define SYSIO_STRBUFREG_BASE 0x2800UL
110 #define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */
111 #define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */
112 #define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */
113 #define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */
114 #define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */
115 #define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */
116 #define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */
117
118 #define STRBUF_TAG_VALID 0x02UL
119
120 static void sbus_strbuf_flush(struct sbus_iommu *iommu, u32 base, unsigned long npages)
121 {
122 unsigned long n;
123 int limit;
124
125 iommu->strbuf_flushflag = 0UL;
126 n = npages;
127 while (n--)
128 upa_writeq(base + (n << IO_PAGE_SHIFT),
129 iommu->strbuf_regs + STRBUF_PFLUSH);
130
131 /* Whoopee cushion! */
132 upa_writeq(__pa(&iommu->strbuf_flushflag),
133 iommu->strbuf_regs + STRBUF_FSYNC);
134 upa_readq(iommu->sbus_control_reg);
135
136 limit = 100000;
137 while (iommu->strbuf_flushflag == 0UL) {
138 limit--;
139 if (!limit)
140 break;
141 udelay(1);
142 membar("#LoadLoad");
143 }
144 if (!limit)
145 printk(KERN_WARNING "sbus_strbuf_flush: flushflag timeout "
146 "vaddr[%08x] npages[%ld]\n",
147 base, npages);
148 }
149
150 static iopte_t *alloc_streaming_cluster(struct sbus_iommu *iommu, unsigned long npages)
151 {
152 iopte_t *iopte, *limit, *first, *cluster;
153 unsigned long cnum, ent, nent, flush_point, found;
154
155 cnum = 0;
156 nent = 1;
157 while ((1UL << cnum) < npages)
158 cnum++;
159 if(cnum >= NCLUSTERS) {
160 nent = 1UL << (cnum - NCLUSTERS);
161 cnum = NCLUSTERS - 1;
162 }
163 iopte = iommu->page_table + (cnum * CLUSTER_NPAGES);
164
165 if (cnum == 0)
166 limit = (iommu->page_table +
167 iommu->lowest_consistent_map);
168 else
169 limit = (iopte + CLUSTER_NPAGES);
170
171 iopte += ((ent = iommu->alloc_info[cnum].next) << cnum);
172 flush_point = iommu->alloc_info[cnum].flush;
173
174 first = iopte;
175 cluster = NULL;
176 found = 0;
177 for (;;) {
178 if (iopte_val(*iopte) == 0UL) {
179 found++;
180 if (!cluster)
181 cluster = iopte;
182 } else {
183 /* Used cluster in the way */
184 cluster = NULL;
185 found = 0;
186 }
187
188 if (found == nent)
189 break;
190
191 iopte += (1 << cnum);
192 ent++;
193 if (iopte >= limit) {
194 iopte = (iommu->page_table + (cnum * CLUSTER_NPAGES));
195 ent = 0;
196
197 /* Multiple cluster allocations must not wrap */
198 cluster = NULL;
199 found = 0;
200 }
201 if (ent == flush_point)
202 __iommu_flushall(iommu);
203 if (iopte == first)
204 goto bad;
205 }
206
207 /* ent/iopte points to the last cluster entry we're going to use,
208 * so save our place for the next allocation.
209 */
210 if ((iopte + (1 << cnum)) >= limit)
211 ent = 0;
212 else
213 ent = ent + 1;
214 iommu->alloc_info[cnum].next = ent;
215 if (ent == flush_point)
216 __iommu_flushall(iommu);
217
218 /* I've got your streaming cluster right here buddy boy... */
219 return cluster;
220
221 bad:
222 printk(KERN_EMERG "sbus: alloc_streaming_cluster of npages(%ld) failed!\n",
223 npages);
224 return NULL;
225 }
226
227 static void free_streaming_cluster(struct sbus_iommu *iommu, u32 base, unsigned long npages)
228 {
229 unsigned long cnum, ent, nent;
230 iopte_t *iopte;
231
232 cnum = 0;
233 nent = 1;
234 while ((1UL << cnum) < npages)
235 cnum++;
236 if(cnum >= NCLUSTERS) {
237 nent = 1UL << (cnum - NCLUSTERS);
238 cnum = NCLUSTERS - 1;
239 }
240 ent = (base & CLUSTER_MASK) >> (IO_PAGE_SHIFT + cnum);
241 iopte = iommu->page_table + ((base - MAP_BASE) >> IO_PAGE_SHIFT);
242 do {
243 iopte_val(*iopte) = 0UL;
244 iopte += 1 << cnum;
245 } while(--nent);
246
247 /* If the global flush might not have caught this entry,
248 * adjust the flush point such that we will flush before
249 * ever trying to reuse it.
250 */
251 #define between(X,Y,Z) (((Z) - (Y)) >= ((X) - (Y)))
252 if (between(ent, iommu->alloc_info[cnum].next, iommu->alloc_info[cnum].flush))
253 iommu->alloc_info[cnum].flush = ent;
254 #undef between
255 }
256
257 /* We allocate consistent mappings from the end of cluster zero. */
258 static iopte_t *alloc_consistent_cluster(struct sbus_iommu *iommu, unsigned long npages)
259 {
260 iopte_t *iopte;
261
262 iopte = iommu->page_table + (1 * CLUSTER_NPAGES);
263 while (iopte > iommu->page_table) {
264 iopte--;
265 if (!(iopte_val(*iopte) & IOPTE_VALID)) {
266 unsigned long tmp = npages;
267
268 while (--tmp) {
269 iopte--;
270 if (iopte_val(*iopte) & IOPTE_VALID)
271 break;
272 }
273 if (tmp == 0) {
274 u32 entry = (iopte - iommu->page_table);
275
276 if (entry < iommu->lowest_consistent_map)
277 iommu->lowest_consistent_map = entry;
278 return iopte;
279 }
280 }
281 }
282 return NULL;
283 }
284
285 static void free_consistent_cluster(struct sbus_iommu *iommu, u32 base, unsigned long npages)
286 {
287 iopte_t *iopte = iommu->page_table + ((base - MAP_BASE) >> IO_PAGE_SHIFT);
288
289 if ((iopte - iommu->page_table) == iommu->lowest_consistent_map) {
290 iopte_t *walk = iopte + npages;
291 iopte_t *limit;
292
293 limit = iommu->page_table + CLUSTER_NPAGES;
294 while (walk < limit) {
295 if (iopte_val(*walk) != 0UL)
296 break;
297 walk++;
298 }
299 iommu->lowest_consistent_map =
300 (walk - iommu->page_table);
301 }
302
303 while (npages--)
304 *iopte++ = __iopte(0UL);
305 }
306
307 void *sbus_alloc_consistent(struct sbus_dev *sdev, size_t size, dma_addr_t *dvma_addr)
308 {
309 unsigned long order, first_page, flags;
310 struct sbus_iommu *iommu;
311 iopte_t *iopte;
312 void *ret;
313 int npages;
314
315 if (size <= 0 || sdev == NULL || dvma_addr == NULL)
316 return NULL;
317
318 size = IO_PAGE_ALIGN(size);
319 order = get_order(size);
320 if (order >= 10)
321 return NULL;
322 first_page = __get_free_pages(GFP_KERNEL, order);
323 if (first_page == 0UL)
324 return NULL;
325 memset((char *)first_page, 0, PAGE_SIZE << order);
326
327 iommu = sdev->bus->iommu;
328
329 spin_lock_irqsave(&iommu->lock, flags);
330 iopte = alloc_consistent_cluster(iommu, size >> IO_PAGE_SHIFT);
331 if (iopte == NULL) {
332 spin_unlock_irqrestore(&iommu->lock, flags);
333 free_pages(first_page, order);
334 return NULL;
335 }
336
337 /* Ok, we're committed at this point. */
338 *dvma_addr = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
339 ret = (void *) first_page;
340 npages = size >> IO_PAGE_SHIFT;
341 while (npages--) {
342 *iopte++ = __iopte(IOPTE_VALID | IOPTE_CACHE | IOPTE_WRITE |
343 (__pa(first_page) & IOPTE_PAGE));
344 first_page += IO_PAGE_SIZE;
345 }
346 iommu_flush(iommu, *dvma_addr, size >> IO_PAGE_SHIFT);
347 spin_unlock_irqrestore(&iommu->lock, flags);
348
349 return ret;
350 }
351
352 void sbus_free_consistent(struct sbus_dev *sdev, size_t size, void *cpu, dma_addr_t dvma)
353 {
354 unsigned long order, npages;
355 struct sbus_iommu *iommu;
356
357 if (size <= 0 || sdev == NULL || cpu == NULL)
358 return;
359
360 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
361 iommu = sdev->bus->iommu;
362
363 spin_lock_irq(&iommu->lock);
364 free_consistent_cluster(iommu, dvma, npages);
365 iommu_flush(iommu, dvma, npages);
366 spin_unlock_irq(&iommu->lock);
367
368 order = get_order(size);
369 if (order < 10)
370 free_pages((unsigned long)cpu, order);
371 }
372
373 dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr, size_t size, int dir)
374 {
375 struct sbus_iommu *iommu = sdev->bus->iommu;
376 unsigned long npages, pbase, flags;
377 iopte_t *iopte;
378 u32 dma_base, offset;
379 unsigned long iopte_bits;
380
381 if (dir == SBUS_DMA_NONE)
382 BUG();
383
384 pbase = (unsigned long) ptr;
385 offset = (u32) (pbase & ~IO_PAGE_MASK);
386 size = (IO_PAGE_ALIGN(pbase + size) - (pbase & IO_PAGE_MASK));
387 pbase = (unsigned long) __pa(pbase & IO_PAGE_MASK);
388
389 spin_lock_irqsave(&iommu->lock, flags);
390 npages = size >> IO_PAGE_SHIFT;
391 iopte = alloc_streaming_cluster(iommu, npages);
392 if (iopte == NULL)
393 goto bad;
394 dma_base = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
395 npages = size >> IO_PAGE_SHIFT;
396 iopte_bits = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE;
397 if (dir != SBUS_DMA_TODEVICE)
398 iopte_bits |= IOPTE_WRITE;
399 while (npages--) {
400 *iopte++ = __iopte(iopte_bits | (pbase & IOPTE_PAGE));
401 pbase += IO_PAGE_SIZE;
402 }
403 npages = size >> IO_PAGE_SHIFT;
404 spin_unlock_irqrestore(&iommu->lock, flags);
405
406 return (dma_base | offset);
407
408 bad:
409 spin_unlock_irqrestore(&iommu->lock, flags);
410 BUG();
411 return 0;
412 }
413
414 void sbus_unmap_single(struct sbus_dev *sdev, dma_addr_t dma_addr, size_t size, int direction)
415 {
416 struct sbus_iommu *iommu = sdev->bus->iommu;
417 u32 dma_base = dma_addr & IO_PAGE_MASK;
418 unsigned long flags;
419
420 size = (IO_PAGE_ALIGN(dma_addr + size) - dma_base);
421
422 spin_lock_irqsave(&iommu->lock, flags);
423 free_streaming_cluster(iommu, dma_base, size >> IO_PAGE_SHIFT);
424 sbus_strbuf_flush(iommu, dma_base, size >> IO_PAGE_SHIFT);
425 spin_unlock_irqrestore(&iommu->lock, flags);
426 }
427
428 #define SG_ENT_PHYS_ADDRESS(SG) \
429 (__pa(page_address((SG)->page)) + (SG)->offset)
430
431 static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg, int nused, int nelems, unsigned long iopte_bits)
432 {
433 struct scatterlist *dma_sg = sg;
434 struct scatterlist *sg_end = sg + nelems;
435 int i;
436
437 for (i = 0; i < nused; i++) {
438 unsigned long pteval = ~0UL;
439 u32 dma_npages;
440
441 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
442 dma_sg->dma_length +
443 ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
444 do {
445 unsigned long offset;
446 signed int len;
447
448 /* If we are here, we know we have at least one
449 * more page to map. So walk forward until we
450 * hit a page crossing, and begin creating new
451 * mappings from that spot.
452 */
453 for (;;) {
454 unsigned long tmp;
455
456 tmp = (unsigned long) SG_ENT_PHYS_ADDRESS(sg);
457 len = sg->length;
458 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
459 pteval = tmp & IO_PAGE_MASK;
460 offset = tmp & (IO_PAGE_SIZE - 1UL);
461 break;
462 }
463 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
464 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
465 offset = 0UL;
466 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
467 break;
468 }
469 sg++;
470 }
471
472 pteval = ((pteval & IOPTE_PAGE) | iopte_bits);
473 while (len > 0) {
474 *iopte++ = __iopte(pteval);
475 pteval += IO_PAGE_SIZE;
476 len -= (IO_PAGE_SIZE - offset);
477 offset = 0;
478 dma_npages--;
479 }
480
481 pteval = (pteval & IOPTE_PAGE) + len;
482 sg++;
483
484 /* Skip over any tail mappings we've fully mapped,
485 * adjusting pteval along the way. Stop when we
486 * detect a page crossing event.
487 */
488 while (sg < sg_end &&
489 (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
490 (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
491 ((pteval ^
492 (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
493 pteval += sg->length;
494 sg++;
495 }
496 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
497 pteval = ~0UL;
498 } while (dma_npages != 0);
499 dma_sg++;
500 }
501 }
502
503 int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int dir)
504 {
505 struct sbus_iommu *iommu = sdev->bus->iommu;
506 unsigned long flags, npages;
507 iopte_t *iopte;
508 u32 dma_base;
509 struct scatterlist *sgtmp;
510 int used;
511 unsigned long iopte_bits;
512
513 if (dir == SBUS_DMA_NONE)
514 BUG();
515
516 /* Fast path single entry scatterlists. */
517 if (nents == 1) {
518 sg->dma_address =
519 sbus_map_single(sdev,
520 (page_address(sg->page) + sg->offset),
521 sg->length, dir);
522 sg->dma_length = sg->length;
523 return 1;
524 }
525
526 npages = prepare_sg(sg, nents);
527
528 spin_lock_irqsave(&iommu->lock, flags);
529 iopte = alloc_streaming_cluster(iommu, npages);
530 if (iopte == NULL)
531 goto bad;
532 dma_base = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
533
534 /* Normalize DVMA addresses. */
535 sgtmp = sg;
536 used = nents;
537
538 while (used && sgtmp->dma_length) {
539 sgtmp->dma_address += dma_base;
540 sgtmp++;
541 used--;
542 }
543 used = nents - used;
544
545 iopte_bits = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE;
546 if (dir != SBUS_DMA_TODEVICE)
547 iopte_bits |= IOPTE_WRITE;
548
549 fill_sg(iopte, sg, used, nents, iopte_bits);
550 #ifdef VERIFY_SG
551 verify_sglist(sg, nents, iopte, npages);
552 #endif
553 spin_unlock_irqrestore(&iommu->lock, flags);
554
555 return used;
556
557 bad:
558 spin_unlock_irqrestore(&iommu->lock, flags);
559 BUG();
560 return 0;
561 }
562
563 void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
564 {
565 unsigned long size, flags;
566 struct sbus_iommu *iommu;
567 u32 dvma_base;
568 int i;
569
570 /* Fast path single entry scatterlists. */
571 if (nents == 1) {
572 sbus_unmap_single(sdev, sg->dma_address, sg->dma_length, direction);
573 return;
574 }
575
576 dvma_base = sg[0].dma_address & IO_PAGE_MASK;
577 for (i = 0; i < nents; i++) {
578 if (sg[i].dma_length == 0)
579 break;
580 }
581 i--;
582 size = IO_PAGE_ALIGN(sg[i].dma_address + sg[i].dma_length) - dvma_base;
583
584 iommu = sdev->bus->iommu;
585 spin_lock_irqsave(&iommu->lock, flags);
586 free_streaming_cluster(iommu, dvma_base, size >> IO_PAGE_SHIFT);
587 sbus_strbuf_flush(iommu, dvma_base, size >> IO_PAGE_SHIFT);
588 spin_unlock_irqrestore(&iommu->lock, flags);
589 }
590
591 void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev, dma_addr_t base, size_t size, int direction)
592 {
593 struct sbus_iommu *iommu = sdev->bus->iommu;
594 unsigned long flags;
595
596 size = (IO_PAGE_ALIGN(base + size) - (base & IO_PAGE_MASK));
597
598 spin_lock_irqsave(&iommu->lock, flags);
599 sbus_strbuf_flush(iommu, base & IO_PAGE_MASK, size >> IO_PAGE_SHIFT);
600 spin_unlock_irqrestore(&iommu->lock, flags);
601 }
602
603 void sbus_dma_sync_single_for_device(struct sbus_dev *sdev, dma_addr_t base, size_t size, int direction)
604 {
605 }
606
607 void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
608 {
609 struct sbus_iommu *iommu = sdev->bus->iommu;
610 unsigned long flags, size;
611 u32 base;
612 int i;
613
614 base = sg[0].dma_address & IO_PAGE_MASK;
615 for (i = 0; i < nents; i++) {
616 if (sg[i].dma_length == 0)
617 break;
618 }
619 i--;
620 size = IO_PAGE_ALIGN(sg[i].dma_address + sg[i].dma_length) - base;
621
622 spin_lock_irqsave(&iommu->lock, flags);
623 sbus_strbuf_flush(iommu, base, size >> IO_PAGE_SHIFT);
624 spin_unlock_irqrestore(&iommu->lock, flags);
625 }
626
627 void sbus_dma_sync_sg_for_device(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
628 {
629 }
630
631 /* Enable 64-bit DVMA mode for the given device. */
632 void sbus_set_sbus64(struct sbus_dev *sdev, int bursts)
633 {
634 struct sbus_iommu *iommu = sdev->bus->iommu;
635 int slot = sdev->slot;
636 unsigned long cfg_reg;
637 u64 val;
638
639 cfg_reg = iommu->sbus_control_reg;
640 switch (slot) {
641 case 0:
642 cfg_reg += 0x20UL;
643 break;
644 case 1:
645 cfg_reg += 0x28UL;
646 break;
647 case 2:
648 cfg_reg += 0x30UL;
649 break;
650 case 3:
651 cfg_reg += 0x38UL;
652 break;
653 case 13:
654 cfg_reg += 0x40UL;
655 break;
656 case 14:
657 cfg_reg += 0x48UL;
658 break;
659 case 15:
660 cfg_reg += 0x50UL;
661 break;
662
663 default:
664 return;
665 };
666
667 val = upa_readq(cfg_reg);
668 if (val & (1UL << 14UL)) {
669 /* Extended transfer mode already enabled. */
670 return;
671 }
672
673 val |= (1UL << 14UL);
674
675 if (bursts & DMA_BURST8)
676 val |= (1UL << 1UL);
677 if (bursts & DMA_BURST16)
678 val |= (1UL << 2UL);
679 if (bursts & DMA_BURST32)
680 val |= (1UL << 3UL);
681 if (bursts & DMA_BURST64)
682 val |= (1UL << 4UL);
683 upa_writeq(val, cfg_reg);
684 }
685
686 /* SBUS SYSIO INO number to Sparc PIL level. */
687 static unsigned char sysio_ino_to_pil[] = {
688 0, 4, 4, 7, 5, 7, 8, 9, /* SBUS slot 0 */
689 0, 4, 4, 7, 5, 7, 8, 9, /* SBUS slot 1 */
690 0, 4, 4, 7, 5, 7, 8, 9, /* SBUS slot 2 */
691 0, 4, 4, 7, 5, 7, 8, 9, /* SBUS slot 3 */
692 4, /* Onboard SCSI */
693 5, /* Onboard Ethernet */
694 /*XXX*/ 8, /* Onboard BPP */
695 0, /* Bogon */
696 13, /* Audio */
697 /*XXX*/15, /* PowerFail */
698 0, /* Bogon */
699 0, /* Bogon */
700 12, /* Zilog Serial Channels (incl. Keyboard/Mouse lines) */
701 11, /* Floppy */
702 0, /* Spare Hardware (bogon for now) */
703 0, /* Keyboard (bogon for now) */
704 0, /* Mouse (bogon for now) */
705 0, /* Serial (bogon for now) */
706 0, 0, /* Bogon, Bogon */
707 10, /* Timer 0 */
708 11, /* Timer 1 */
709 0, 0, /* Bogon, Bogon */
710 15, /* Uncorrectable SBUS Error */
711 15, /* Correctable SBUS Error */
712 15, /* SBUS Error */
713 /*XXX*/ 0, /* Power Management (bogon for now) */
714 };
715
716 /* INO number to IMAP register offset for SYSIO external IRQ's.
717 * This should conform to both Sunfire/Wildfire server and Fusion
718 * desktop designs.
719 */
720 #define SYSIO_IMAP_SLOT0 0x2c04UL
721 #define SYSIO_IMAP_SLOT1 0x2c0cUL
722 #define SYSIO_IMAP_SLOT2 0x2c14UL
723 #define SYSIO_IMAP_SLOT3 0x2c1cUL
724 #define SYSIO_IMAP_SCSI 0x3004UL
725 #define SYSIO_IMAP_ETH 0x300cUL
726 #define SYSIO_IMAP_BPP 0x3014UL
727 #define SYSIO_IMAP_AUDIO 0x301cUL
728 #define SYSIO_IMAP_PFAIL 0x3024UL
729 #define SYSIO_IMAP_KMS 0x302cUL
730 #define SYSIO_IMAP_FLPY 0x3034UL
731 #define SYSIO_IMAP_SHW 0x303cUL
732 #define SYSIO_IMAP_KBD 0x3044UL
733 #define SYSIO_IMAP_MS 0x304cUL
734 #define SYSIO_IMAP_SER 0x3054UL
735 #define SYSIO_IMAP_TIM0 0x3064UL
736 #define SYSIO_IMAP_TIM1 0x306cUL
737 #define SYSIO_IMAP_UE 0x3074UL
738 #define SYSIO_IMAP_CE 0x307cUL
739 #define SYSIO_IMAP_SBERR 0x3084UL
740 #define SYSIO_IMAP_PMGMT 0x308cUL
741 #define SYSIO_IMAP_GFX 0x3094UL
742 #define SYSIO_IMAP_EUPA 0x309cUL
743
744 #define bogon ((unsigned long) -1)
745 static unsigned long sysio_irq_offsets[] = {
746 /* SBUS Slot 0 --> 3, level 1 --> 7 */
747 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
748 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
749 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
750 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
751 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
752 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
753 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
754 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
755
756 /* Onboard devices (not relevant/used on SunFire). */
757 SYSIO_IMAP_SCSI,
758 SYSIO_IMAP_ETH,
759 SYSIO_IMAP_BPP,
760 bogon,
761 SYSIO_IMAP_AUDIO,
762 SYSIO_IMAP_PFAIL,
763 bogon,
764 bogon,
765 SYSIO_IMAP_KMS,
766 SYSIO_IMAP_FLPY,
767 SYSIO_IMAP_SHW,
768 SYSIO_IMAP_KBD,
769 SYSIO_IMAP_MS,
770 SYSIO_IMAP_SER,
771 bogon,
772 bogon,
773 SYSIO_IMAP_TIM0,
774 SYSIO_IMAP_TIM1,
775 bogon,
776 bogon,
777 SYSIO_IMAP_UE,
778 SYSIO_IMAP_CE,
779 SYSIO_IMAP_SBERR,
780 SYSIO_IMAP_PMGMT,
781 };
782
783 #undef bogon
784
785 #define NUM_SYSIO_OFFSETS (sizeof(sysio_irq_offsets) / sizeof(sysio_irq_offsets[0]))
786
787 /* Convert Interrupt Mapping register pointer to associated
788 * Interrupt Clear register pointer, SYSIO specific version.
789 */
790 #define SYSIO_ICLR_UNUSED0 0x3400UL
791 #define SYSIO_ICLR_SLOT0 0x340cUL
792 #define SYSIO_ICLR_SLOT1 0x344cUL
793 #define SYSIO_ICLR_SLOT2 0x348cUL
794 #define SYSIO_ICLR_SLOT3 0x34ccUL
795 static unsigned long sysio_imap_to_iclr(unsigned long imap)
796 {
797 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
798 return imap + diff;
799 }
800
801 unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
802 {
803 struct sbus_bus *sbus = (struct sbus_bus *)buscookie;
804 struct sbus_iommu *iommu = sbus->iommu;
805 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
806 unsigned long imap, iclr;
807 int pil, sbus_level = 0;
808
809 pil = sysio_ino_to_pil[ino];
810 if (!pil) {
811 printk("sbus_irq_build: Bad SYSIO INO[%x]\n", ino);
812 panic("Bad SYSIO IRQ translations...");
813 }
814
815 if (PIL_RESERVED(pil))
816 BUG();
817
818 imap = sysio_irq_offsets[ino];
819 if (imap == ((unsigned long)-1)) {
820 prom_printf("get_irq_translations: Bad SYSIO INO[%x] cpu[%d]\n",
821 ino, pil);
822 prom_halt();
823 }
824 imap += reg_base;
825
826 /* SYSIO inconsistency. For external SLOTS, we have to select
827 * the right ICLR register based upon the lower SBUS irq level
828 * bits.
829 */
830 if (ino >= 0x20) {
831 iclr = sysio_imap_to_iclr(imap);
832 } else {
833 int sbus_slot = (ino & 0x18)>>3;
834
835 sbus_level = ino & 0x7;
836
837 switch(sbus_slot) {
838 case 0:
839 iclr = reg_base + SYSIO_ICLR_SLOT0;
840 break;
841 case 1:
842 iclr = reg_base + SYSIO_ICLR_SLOT1;
843 break;
844 case 2:
845 iclr = reg_base + SYSIO_ICLR_SLOT2;
846 break;
847 default:
848 case 3:
849 iclr = reg_base + SYSIO_ICLR_SLOT3;
850 break;
851 };
852
853 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
854 }
855 return build_irq(pil, sbus_level, iclr, imap);
856 }
857
858 /* Error interrupt handling. */
859 #define SYSIO_UE_AFSR 0x0030UL
860 #define SYSIO_UE_AFAR 0x0038UL
861 #define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
862 #define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
863 #define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
864 #define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
865 #define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
866 #define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
867 #define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
868 #define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */
869 #define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
870 #define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
871 #define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
872 static irqreturn_t sysio_ue_handler(int irq, void *dev_id, struct pt_regs *regs)
873 {
874 struct sbus_bus *sbus = dev_id;
875 struct sbus_iommu *iommu = sbus->iommu;
876 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
877 unsigned long afsr_reg, afar_reg;
878 unsigned long afsr, afar, error_bits;
879 int reported;
880
881 afsr_reg = reg_base + SYSIO_UE_AFSR;
882 afar_reg = reg_base + SYSIO_UE_AFAR;
883
884 /* Latch error status. */
885 afsr = upa_readq(afsr_reg);
886 afar = upa_readq(afar_reg);
887
888 /* Clear primary/secondary error status bits. */
889 error_bits = afsr &
890 (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR |
891 SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
892 upa_writeq(error_bits, afsr_reg);
893
894 /* Log the error. */
895 printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
896 sbus->portid,
897 (((error_bits & SYSIO_UEAFSR_PPIO) ?
898 "PIO" :
899 ((error_bits & SYSIO_UEAFSR_PDRD) ?
900 "DVMA Read" :
901 ((error_bits & SYSIO_UEAFSR_PDWR) ?
902 "DVMA Write" : "???")))));
903 printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
904 sbus->portid,
905 (afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
906 (afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
907 (afsr & SYSIO_UEAFSR_MID) >> 37UL);
908 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
909 printk("SYSIO[%x]: Secondary UE errors [", sbus->portid);
910 reported = 0;
911 if (afsr & SYSIO_UEAFSR_SPIO) {
912 reported++;
913 printk("(PIO)");
914 }
915 if (afsr & SYSIO_UEAFSR_SDRD) {
916 reported++;
917 printk("(DVMA Read)");
918 }
919 if (afsr & SYSIO_UEAFSR_SDWR) {
920 reported++;
921 printk("(DVMA Write)");
922 }
923 if (!reported)
924 printk("(none)");
925 printk("]\n");
926
927 return IRQ_HANDLED;
928 }
929
930 #define SYSIO_CE_AFSR 0x0040UL
931 #define SYSIO_CE_AFAR 0x0048UL
932 #define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
933 #define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
934 #define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
935 #define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */
936 #define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
937 #define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
938 #define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
939 #define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
940 #define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */
941 #define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
942 #define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
943 #define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
944 static irqreturn_t sysio_ce_handler(int irq, void *dev_id, struct pt_regs *regs)
945 {
946 struct sbus_bus *sbus = dev_id;
947 struct sbus_iommu *iommu = sbus->iommu;
948 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
949 unsigned long afsr_reg, afar_reg;
950 unsigned long afsr, afar, error_bits;
951 int reported;
952
953 afsr_reg = reg_base + SYSIO_CE_AFSR;
954 afar_reg = reg_base + SYSIO_CE_AFAR;
955
956 /* Latch error status. */
957 afsr = upa_readq(afsr_reg);
958 afar = upa_readq(afar_reg);
959
960 /* Clear primary/secondary error status bits. */
961 error_bits = afsr &
962 (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR |
963 SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
964 upa_writeq(error_bits, afsr_reg);
965
966 printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
967 sbus->portid,
968 (((error_bits & SYSIO_CEAFSR_PPIO) ?
969 "PIO" :
970 ((error_bits & SYSIO_CEAFSR_PDRD) ?
971 "DVMA Read" :
972 ((error_bits & SYSIO_CEAFSR_PDWR) ?
973 "DVMA Write" : "???")))));
974
975 /* XXX Use syndrome and afar to print out module string just like
976 * XXX UDB CE trap handler does... -DaveM
977 */
978 printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
979 sbus->portid,
980 (afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
981 (afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
982 (afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
983 (afsr & SYSIO_CEAFSR_MID) >> 37UL);
984 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
985
986 printk("SYSIO[%x]: Secondary CE errors [", sbus->portid);
987 reported = 0;
988 if (afsr & SYSIO_CEAFSR_SPIO) {
989 reported++;
990 printk("(PIO)");
991 }
992 if (afsr & SYSIO_CEAFSR_SDRD) {
993 reported++;
994 printk("(DVMA Read)");
995 }
996 if (afsr & SYSIO_CEAFSR_SDWR) {
997 reported++;
998 printk("(DVMA Write)");
999 }
1000 if (!reported)
1001 printk("(none)");
1002 printk("]\n");
1003
1004 return IRQ_HANDLED;
1005 }
1006
1007 #define SYSIO_SBUS_AFSR 0x2010UL
1008 #define SYSIO_SBUS_AFAR 0x2018UL
1009 #define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */
1010 #define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */
1011 #define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */
1012 #define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */
1013 #define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */
1014 #define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */
1015 #define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */
1016 #define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */
1017 #define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */
1018 #define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */
1019 #define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */
1020 #define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */
1021 static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id, struct pt_regs *regs)
1022 {
1023 struct sbus_bus *sbus = dev_id;
1024 struct sbus_iommu *iommu = sbus->iommu;
1025 unsigned long afsr_reg, afar_reg, reg_base;
1026 unsigned long afsr, afar, error_bits;
1027 int reported;
1028
1029 reg_base = iommu->sbus_control_reg - 0x2000UL;
1030 afsr_reg = reg_base + SYSIO_SBUS_AFSR;
1031 afar_reg = reg_base + SYSIO_SBUS_AFAR;
1032
1033 afsr = upa_readq(afsr_reg);
1034 afar = upa_readq(afar_reg);
1035
1036 /* Clear primary/secondary error status bits. */
1037 error_bits = afsr &
1038 (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR |
1039 SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
1040 upa_writeq(error_bits, afsr_reg);
1041
1042 /* Log the error. */
1043 printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
1044 sbus->portid,
1045 (((error_bits & SYSIO_SBAFSR_PLE) ?
1046 "Late PIO Error" :
1047 ((error_bits & SYSIO_SBAFSR_PTO) ?
1048 "Time Out" :
1049 ((error_bits & SYSIO_SBAFSR_PBERR) ?
1050 "Error Ack" : "???")))),
1051 (afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
1052 printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
1053 sbus->portid,
1054 (afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
1055 (afsr & SYSIO_SBAFSR_MID) >> 37UL);
1056 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
1057 printk("SYSIO[%x]: Secondary SBUS errors [", sbus->portid);
1058 reported = 0;
1059 if (afsr & SYSIO_SBAFSR_SLE) {
1060 reported++;
1061 printk("(Late PIO Error)");
1062 }
1063 if (afsr & SYSIO_SBAFSR_STO) {
1064 reported++;
1065 printk("(Time Out)");
1066 }
1067 if (afsr & SYSIO_SBAFSR_SBERR) {
1068 reported++;
1069 printk("(Error Ack)");
1070 }
1071 if (!reported)
1072 printk("(none)");
1073 printk("]\n");
1074
1075 /* XXX check iommu/strbuf for further error status XXX */
1076
1077 return IRQ_HANDLED;
1078 }
1079
1080 #define ECC_CONTROL 0x0020UL
1081 #define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */
1082 #define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */
1083 #define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */
1084
1085 #define SYSIO_UE_INO 0x34
1086 #define SYSIO_CE_INO 0x35
1087 #define SYSIO_SBUSERR_INO 0x36
1088
1089 static void __init sysio_register_error_handlers(struct sbus_bus *sbus)
1090 {
1091 struct sbus_iommu *iommu = sbus->iommu;
1092 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
1093 unsigned int irq;
1094 u64 control;
1095
1096 irq = sbus_build_irq(sbus, SYSIO_UE_INO);
1097 if (request_irq(irq, sysio_ue_handler,
1098 SA_SHIRQ, "SYSIO UE", sbus) < 0) {
1099 prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
1100 sbus->portid);
1101 prom_halt();
1102 }
1103
1104 irq = sbus_build_irq(sbus, SYSIO_CE_INO);
1105 if (request_irq(irq, sysio_ce_handler,
1106 SA_SHIRQ, "SYSIO CE", sbus) < 0) {
1107 prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
1108 sbus->portid);
1109 prom_halt();
1110 }
1111
1112 irq = sbus_build_irq(sbus, SYSIO_SBUSERR_INO);
1113 if (request_irq(irq, sysio_sbus_error_handler,
1114 SA_SHIRQ, "SYSIO SBUS Error", sbus) < 0) {
1115 prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
1116 sbus->portid);
1117 prom_halt();
1118 }
1119
1120 /* Now turn the error interrupts on and also enable ECC checking. */
1121 upa_writeq((SYSIO_ECNTRL_ECCEN |
1122 SYSIO_ECNTRL_UEEN |
1123 SYSIO_ECNTRL_CEEN),
1124 reg_base + ECC_CONTROL);
1125
1126 control = upa_readq(iommu->sbus_control_reg);
1127 control |= 0x100UL; /* SBUS Error Interrupt Enable */
1128 upa_writeq(control, iommu->sbus_control_reg);
1129 }
1130
1131 /* Boot time initialization. */
1132 void __init sbus_iommu_init(int prom_node, struct sbus_bus *sbus)
1133 {
1134 struct linux_prom64_registers rprop;
1135 struct sbus_iommu *iommu;
1136 unsigned long regs, tsb_base;
1137 u64 control;
1138 int err, i;
1139
1140 sbus->portid = prom_getintdefault(sbus->prom_node,
1141 "upa-portid", -1);
1142
1143 err = prom_getproperty(prom_node, "reg",
1144 (char *)&rprop, sizeof(rprop));
1145 if (err < 0) {
1146 prom_printf("sbus_iommu_init: Cannot map SYSIO control registers.\n");
1147 prom_halt();
1148 }
1149 regs = rprop.phys_addr;
1150
1151 iommu = kmalloc(sizeof(*iommu) + SMP_CACHE_BYTES, GFP_ATOMIC);
1152 if (iommu == NULL) {
1153 prom_printf("sbus_iommu_init: Fatal error, kmalloc(iommu) failed\n");
1154 prom_halt();
1155 }
1156
1157 /* Align on E$ line boundary. */
1158 iommu = (struct sbus_iommu *)
1159 (((unsigned long)iommu + (SMP_CACHE_BYTES - 1UL)) &
1160 ~(SMP_CACHE_BYTES - 1UL));
1161
1162 memset(iommu, 0, sizeof(*iommu));
1163
1164 /* We start with no consistent mappings. */
1165 iommu->lowest_consistent_map = CLUSTER_NPAGES;
1166
1167 for (i = 0; i < NCLUSTERS; i++) {
1168 iommu->alloc_info[i].flush = 0;
1169 iommu->alloc_info[i].next = 0;
1170 }
1171
1172 /* Setup spinlock. */
1173 spin_lock_init(&iommu->lock);
1174
1175 /* Init register offsets. */
1176 iommu->iommu_regs = regs + SYSIO_IOMMUREG_BASE;
1177 iommu->strbuf_regs = regs + SYSIO_STRBUFREG_BASE;
1178
1179 /* The SYSIO SBUS control register is used for dummy reads
1180 * in order to ensure write completion.
1181 */
1182 iommu->sbus_control_reg = regs + 0x2000UL;
1183
1184 /* Link into SYSIO software state. */
1185 sbus->iommu = iommu;
1186
1187 printk("SYSIO: UPA portID %x, at %016lx\n",
1188 sbus->portid, regs);
1189
1190 /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
1191 control = upa_readq(iommu->iommu_regs + IOMMU_CONTROL);
1192 control = ((7UL << 16UL) |
1193 (0UL << 2UL) |
1194 (1UL << 1UL) |
1195 (1UL << 0UL));
1196
1197 /* Using the above configuration we need 1MB iommu page
1198 * table (128K ioptes * 8 bytes per iopte). This is
1199 * page order 7 on UltraSparc.
1200 */
1201 tsb_base = __get_free_pages(GFP_ATOMIC, get_order(IO_TSB_SIZE));
1202 if (tsb_base == 0UL) {
1203 prom_printf("sbus_iommu_init: Fatal error, cannot alloc TSB table.\n");
1204 prom_halt();
1205 }
1206
1207 iommu->page_table = (iopte_t *) tsb_base;
1208 memset(iommu->page_table, 0, IO_TSB_SIZE);
1209
1210 upa_writeq(control, iommu->iommu_regs + IOMMU_CONTROL);
1211
1212 /* Clean out any cruft in the IOMMU using
1213 * diagnostic accesses.
1214 */
1215 for (i = 0; i < 16; i++) {
1216 unsigned long dram = iommu->iommu_regs + IOMMU_DRAMDIAG;
1217 unsigned long tag = iommu->iommu_regs + IOMMU_TAGDIAG;
1218
1219 dram += (unsigned long)i * 8UL;
1220 tag += (unsigned long)i * 8UL;
1221 upa_writeq(0, dram);
1222 upa_writeq(0, tag);
1223 }
1224 upa_readq(iommu->sbus_control_reg);
1225
1226 /* Give the TSB to SYSIO. */
1227 upa_writeq(__pa(tsb_base), iommu->iommu_regs + IOMMU_TSBBASE);
1228
1229 /* Setup streaming buffer, DE=1 SB_EN=1 */
1230 control = (1UL << 1UL) | (1UL << 0UL);
1231 upa_writeq(control, iommu->strbuf_regs + STRBUF_CONTROL);
1232
1233 /* Clear out the tags using diagnostics. */
1234 for (i = 0; i < 16; i++) {
1235 unsigned long ptag, ltag;
1236
1237 ptag = iommu->strbuf_regs + STRBUF_PTAGDIAG;
1238 ltag = iommu->strbuf_regs + STRBUF_LTAGDIAG;
1239 ptag += (unsigned long)i * 8UL;
1240 ltag += (unsigned long)i * 8UL;
1241
1242 upa_writeq(0UL, ptag);
1243 upa_writeq(0UL, ltag);
1244 }
1245
1246 /* Enable DVMA arbitration for all devices/slots. */
1247 control = upa_readq(iommu->sbus_control_reg);
1248 control |= 0x3fUL;
1249 upa_writeq(control, iommu->sbus_control_reg);
1250
1251 /* Now some Xfire specific grot... */
1252 if (this_is_starfire)
1253 sbus->starfire_cookie = starfire_hookup(sbus->portid);
1254 else
1255 sbus->starfire_cookie = NULL;
1256
1257 sysio_register_error_handlers(sbus);
1258 }
kernel source for telekom puls (alcatel/mediatek)