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sparc: Annotate of_device_id arrays with const or __initdata.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc64 / kernel / pci_psycho.c
1 /* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14 #include <linux/of_device.h>
15
16 #include <asm/iommu.h>
17 #include <asm/irq.h>
18 #include <asm/starfire.h>
19 #include <asm/prom.h>
20
21 #include "pci_impl.h"
22 #include "iommu_common.h"
23
24 #define DRIVER_NAME "psycho"
25 #define PFX DRIVER_NAME ": "
26
27 /* All PSYCHO registers are 64-bits. The following accessor
28 * routines are how they are accessed. The REG parameter
29 * is a physical address.
30 */
31 #define psycho_read(__reg) \
32 ({ u64 __ret; \
33 __asm__ __volatile__("ldxa [%1] %2, %0" \
34 : "=r" (__ret) \
35 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
36 : "memory"); \
37 __ret; \
38 })
39 #define psycho_write(__reg, __val) \
40 __asm__ __volatile__("stxa %0, [%1] %2" \
41 : /* no outputs */ \
42 : "r" (__val), "r" (__reg), \
43 "i" (ASI_PHYS_BYPASS_EC_E) \
44 : "memory")
45
46 /* Misc. PSYCHO PCI controller register offsets and definitions. */
47 #define PSYCHO_CONTROL 0x0010UL
48 #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
49 #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
50 #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
51 #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
52 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
53 #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
54 #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
55 #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
56 #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
57 #define PSYCHO_PCIA_CTRL 0x2000UL
58 #define PSYCHO_PCIB_CTRL 0x4000UL
59 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
60 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
61 #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
62 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
63 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
64 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
65 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
66 #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
67 #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
68 #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
69 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
70 #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
71
72 /* U2P Programmer's Manual, page 13-55, configuration space
73 * address format:
74 *
75 * 32 24 23 16 15 11 10 8 7 2 1 0
76 * ---------------------------------------------------------
77 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
78 * ---------------------------------------------------------
79 */
80 #define PSYCHO_CONFIG_BASE(PBM) \
81 ((PBM)->config_space | (1UL << 24))
82 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
83 (((unsigned long)(BUS) << 16) | \
84 ((unsigned long)(DEVFN) << 8) | \
85 ((unsigned long)(REG)))
86
87 static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
88 unsigned char bus,
89 unsigned int devfn,
90 int where)
91 {
92 if (!pbm)
93 return NULL;
94 return (void *)
95 (PSYCHO_CONFIG_BASE(pbm) |
96 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
97 }
98
99 /* PSYCHO error handling support. */
100 enum psycho_error_type {
101 UE_ERR, CE_ERR, PCI_ERR
102 };
103
104 /* Helper function of IOMMU error checking, which checks out
105 * the state of the streaming buffers. The IOMMU lock is
106 * held when this is called.
107 *
108 * For the PCI error case we know which PBM (and thus which
109 * streaming buffer) caused the error, but for the uncorrectable
110 * error case we do not. So we always check both streaming caches.
111 */
112 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
113 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
114 #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
115 #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
116 #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
117 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
118 #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
119 #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
120 #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
121 #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
122 #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
123 #define PSYCHO_STC_DATA_A 0xb000UL
124 #define PSYCHO_STC_DATA_B 0xc000UL
125 #define PSYCHO_STC_ERR_A 0xb400UL
126 #define PSYCHO_STC_ERR_B 0xc400UL
127 #define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
128 #define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
129 #define PSYCHO_STC_TAG_A 0xb800UL
130 #define PSYCHO_STC_TAG_B 0xc800UL
131 #define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
132 #define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
133 #define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
134 #define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
135 #define PSYCHO_STC_LINE_A 0xb900UL
136 #define PSYCHO_STC_LINE_B 0xc900UL
137 #define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
138 #define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
139 #define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
140 #define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
141 #define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
142 #define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
143
144 static DEFINE_SPINLOCK(stc_buf_lock);
145 static unsigned long stc_error_buf[128];
146 static unsigned long stc_tag_buf[16];
147 static unsigned long stc_line_buf[16];
148
149 static void __psycho_check_one_stc(struct pci_pbm_info *pbm,
150 int is_pbm_a)
151 {
152 struct strbuf *strbuf = &pbm->stc;
153 unsigned long regbase = pbm->controller_regs;
154 unsigned long err_base, tag_base, line_base;
155 u64 control;
156 int i;
157
158 if (is_pbm_a) {
159 err_base = regbase + PSYCHO_STC_ERR_A;
160 tag_base = regbase + PSYCHO_STC_TAG_A;
161 line_base = regbase + PSYCHO_STC_LINE_A;
162 } else {
163 err_base = regbase + PSYCHO_STC_ERR_B;
164 tag_base = regbase + PSYCHO_STC_TAG_B;
165 line_base = regbase + PSYCHO_STC_LINE_B;
166 }
167
168 spin_lock(&stc_buf_lock);
169
170 /* This is __REALLY__ dangerous. When we put the
171 * streaming buffer into diagnostic mode to probe
172 * it's tags and error status, we _must_ clear all
173 * of the line tag valid bits before re-enabling
174 * the streaming buffer. If any dirty data lives
175 * in the STC when we do this, we will end up
176 * invalidating it before it has a chance to reach
177 * main memory.
178 */
179 control = psycho_read(strbuf->strbuf_control);
180 psycho_write(strbuf->strbuf_control,
181 (control | PSYCHO_STRBUF_CTRL_DENAB));
182 for (i = 0; i < 128; i++) {
183 unsigned long val;
184
185 val = psycho_read(err_base + (i * 8UL));
186 psycho_write(err_base + (i * 8UL), 0UL);
187 stc_error_buf[i] = val;
188 }
189 for (i = 0; i < 16; i++) {
190 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
191 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
192 psycho_write(tag_base + (i * 8UL), 0UL);
193 psycho_write(line_base + (i * 8UL), 0UL);
194 }
195
196 /* OK, state is logged, exit diagnostic mode. */
197 psycho_write(strbuf->strbuf_control, control);
198
199 for (i = 0; i < 16; i++) {
200 int j, saw_error, first, last;
201
202 saw_error = 0;
203 first = i * 8;
204 last = first + 8;
205 for (j = first; j < last; j++) {
206 unsigned long errval = stc_error_buf[j];
207 if (errval != 0) {
208 saw_error++;
209 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
210 pbm->name,
211 j,
212 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
213 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
214 }
215 }
216 if (saw_error != 0) {
217 unsigned long tagval = stc_tag_buf[i];
218 unsigned long lineval = stc_line_buf[i];
219 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
220 pbm->name,
221 i,
222 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
223 (tagval & PSYCHO_STCTAG_VPN),
224 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
225 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
226 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
227 "V(%d)FOFN(%d)]\n",
228 pbm->name,
229 i,
230 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
231 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
232 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
233 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
234 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
235 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
236 }
237 }
238
239 spin_unlock(&stc_buf_lock);
240 }
241
242 static void __psycho_check_stc_error(struct pci_pbm_info *pbm,
243 unsigned long afsr,
244 unsigned long afar,
245 enum psycho_error_type type)
246 {
247 __psycho_check_one_stc(pbm,
248 (pbm == &pbm->parent->pbm_A));
249 }
250
251 /* When an Uncorrectable Error or a PCI Error happens, we
252 * interrogate the IOMMU state to see if it is the cause.
253 */
254 #define PSYCHO_IOMMU_CONTROL 0x0200UL
255 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
256 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
257 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
258 #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
259 #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
260 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
261 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
262 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
263 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
264 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
265 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
266 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
267 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
268 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
269 #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
270 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
271 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
272 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
273 #define PSYCHO_IOMMU_TSBBASE 0x0208UL
274 #define PSYCHO_IOMMU_FLUSH 0x0210UL
275 #define PSYCHO_IOMMU_TAG 0xa580UL
276 #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
277 #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
278 #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
279 #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
280 #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
281 #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
282 #define PSYCHO_IOMMU_DATA 0xa600UL
283 #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
284 #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
285 #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
286 static void psycho_check_iommu_error(struct pci_pbm_info *pbm,
287 unsigned long afsr,
288 unsigned long afar,
289 enum psycho_error_type type)
290 {
291 struct iommu *iommu = pbm->iommu;
292 unsigned long iommu_tag[16];
293 unsigned long iommu_data[16];
294 unsigned long flags;
295 u64 control;
296 int i;
297
298 spin_lock_irqsave(&iommu->lock, flags);
299 control = psycho_read(iommu->iommu_control);
300 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
301 char *type_string;
302
303 /* Clear the error encountered bit. */
304 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
305 psycho_write(iommu->iommu_control, control);
306
307 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
308 case 0:
309 type_string = "Protection Error";
310 break;
311 case 1:
312 type_string = "Invalid Error";
313 break;
314 case 2:
315 type_string = "TimeOut Error";
316 break;
317 case 3:
318 default:
319 type_string = "ECC Error";
320 break;
321 };
322 printk("%s: IOMMU Error, type[%s]\n",
323 pbm->name, type_string);
324
325 /* Put the IOMMU into diagnostic mode and probe
326 * it's TLB for entries with error status.
327 *
328 * It is very possible for another DVMA to occur
329 * while we do this probe, and corrupt the system
330 * further. But we are so screwed at this point
331 * that we are likely to crash hard anyways, so
332 * get as much diagnostic information to the
333 * console as we can.
334 */
335 psycho_write(iommu->iommu_control,
336 control | PSYCHO_IOMMU_CTRL_DENAB);
337 for (i = 0; i < 16; i++) {
338 unsigned long base = pbm->controller_regs;
339
340 iommu_tag[i] =
341 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
342 iommu_data[i] =
343 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
344
345 /* Now clear out the entry. */
346 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
347 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
348 }
349
350 /* Leave diagnostic mode. */
351 psycho_write(iommu->iommu_control, control);
352
353 for (i = 0; i < 16; i++) {
354 unsigned long tag, data;
355
356 tag = iommu_tag[i];
357 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
358 continue;
359
360 data = iommu_data[i];
361 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
362 case 0:
363 type_string = "Protection Error";
364 break;
365 case 1:
366 type_string = "Invalid Error";
367 break;
368 case 2:
369 type_string = "TimeOut Error";
370 break;
371 case 3:
372 default:
373 type_string = "ECC Error";
374 break;
375 };
376 printk("%s: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
377 pbm->name, i, type_string,
378 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
379 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
380 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
381 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
382 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
383 pbm->name, i,
384 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
385 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
386 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
387 }
388 }
389 __psycho_check_stc_error(pbm, afsr, afar, type);
390 spin_unlock_irqrestore(&iommu->lock, flags);
391 }
392
393 /* Uncorrectable Errors. Cause of the error and the address are
394 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
395 * relating to UPA interface transactions.
396 */
397 #define PSYCHO_UE_AFSR 0x0030UL
398 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
399 #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
400 #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
401 #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
402 #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
403 #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
404 #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
405 #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
406 #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
407 #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
408 #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
409 #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
410 #define PSYCHO_UE_AFAR 0x0038UL
411
412 static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
413 {
414 struct pci_pbm_info *pbm = dev_id;
415 struct pci_controller_info *p = pbm->parent;
416 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR;
417 unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR;
418 unsigned long afsr, afar, error_bits;
419 int reported;
420
421 /* Latch uncorrectable error status. */
422 afar = psycho_read(afar_reg);
423 afsr = psycho_read(afsr_reg);
424
425 /* Clear the primary/secondary error status bits. */
426 error_bits = afsr &
427 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
428 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
429 if (!error_bits)
430 return IRQ_NONE;
431 psycho_write(afsr_reg, error_bits);
432
433 /* Log the error. */
434 printk("%s: Uncorrectable Error, primary error type[%s]\n",
435 pbm->name,
436 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
437 "PIO" :
438 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
439 "DMA Read" :
440 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
441 "DMA Write" : "???")))));
442 printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
443 pbm->name,
444 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
445 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
446 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
447 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
448 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
449 printk("%s: UE Secondary errors [", pbm->name);
450 reported = 0;
451 if (afsr & PSYCHO_UEAFSR_SPIO) {
452 reported++;
453 printk("(PIO)");
454 }
455 if (afsr & PSYCHO_UEAFSR_SDRD) {
456 reported++;
457 printk("(DMA Read)");
458 }
459 if (afsr & PSYCHO_UEAFSR_SDWR) {
460 reported++;
461 printk("(DMA Write)");
462 }
463 if (!reported)
464 printk("(none)");
465 printk("]\n");
466
467 /* Interrogate both IOMMUs for error status. */
468 psycho_check_iommu_error(&p->pbm_A, afsr, afar, UE_ERR);
469 psycho_check_iommu_error(&p->pbm_B, afsr, afar, UE_ERR);
470
471 return IRQ_HANDLED;
472 }
473
474 /* Correctable Errors. */
475 #define PSYCHO_CE_AFSR 0x0040UL
476 #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
477 #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
478 #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
479 #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
480 #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
481 #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
482 #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
483 #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
484 #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
485 #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
486 #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
487 #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
488 #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
489 #define PSYCHO_CE_AFAR 0x0040UL
490
491 static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
492 {
493 struct pci_pbm_info *pbm = dev_id;
494 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR;
495 unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR;
496 unsigned long afsr, afar, error_bits;
497 int reported;
498
499 /* Latch error status. */
500 afar = psycho_read(afar_reg);
501 afsr = psycho_read(afsr_reg);
502
503 /* Clear primary/secondary error status bits. */
504 error_bits = afsr &
505 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
506 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
507 if (!error_bits)
508 return IRQ_NONE;
509 psycho_write(afsr_reg, error_bits);
510
511 /* Log the error. */
512 printk("%s: Correctable Error, primary error type[%s]\n",
513 pbm->name,
514 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
515 "PIO" :
516 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
517 "DMA Read" :
518 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
519 "DMA Write" : "???")))));
520
521 /* XXX Use syndrome and afar to print out module string just like
522 * XXX UDB CE trap handler does... -DaveM
523 */
524 printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
525 "UPA_MID[%02lx] was_block(%d)\n",
526 pbm->name,
527 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
528 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
529 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
530 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
531 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
532 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
533 printk("%s: CE Secondary errors [", pbm->name);
534 reported = 0;
535 if (afsr & PSYCHO_CEAFSR_SPIO) {
536 reported++;
537 printk("(PIO)");
538 }
539 if (afsr & PSYCHO_CEAFSR_SDRD) {
540 reported++;
541 printk("(DMA Read)");
542 }
543 if (afsr & PSYCHO_CEAFSR_SDWR) {
544 reported++;
545 printk("(DMA Write)");
546 }
547 if (!reported)
548 printk("(none)");
549 printk("]\n");
550
551 return IRQ_HANDLED;
552 }
553
554 /* PCI Errors. They are signalled by the PCI bus module since they
555 * are associated with a specific bus segment.
556 */
557 #define PSYCHO_PCI_AFSR_A 0x2010UL
558 #define PSYCHO_PCI_AFSR_B 0x4010UL
559 #define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
560 #define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
561 #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
562 #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
563 #define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
564 #define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
565 #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
566 #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
567 #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
568 #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
569 #define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
570 #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
571 #define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
572 #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
573 #define PSYCHO_PCI_AFAR_A 0x2018UL
574 #define PSYCHO_PCI_AFAR_B 0x4018UL
575
576 static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a)
577 {
578 unsigned long csr_reg, csr, csr_error_bits;
579 irqreturn_t ret = IRQ_NONE;
580 u16 stat;
581
582 if (is_pbm_a) {
583 csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL;
584 } else {
585 csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL;
586 }
587 csr = psycho_read(csr_reg);
588 csr_error_bits =
589 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
590 if (csr_error_bits) {
591 /* Clear the errors. */
592 psycho_write(csr_reg, csr);
593
594 /* Log 'em. */
595 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
596 printk("%s: PCI streaming byte hole error asserted.\n",
597 pbm->name);
598 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
599 printk("%s: PCI SERR signal asserted.\n", pbm->name);
600 ret = IRQ_HANDLED;
601 }
602 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
603 if (stat & (PCI_STATUS_PARITY |
604 PCI_STATUS_SIG_TARGET_ABORT |
605 PCI_STATUS_REC_TARGET_ABORT |
606 PCI_STATUS_REC_MASTER_ABORT |
607 PCI_STATUS_SIG_SYSTEM_ERROR)) {
608 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
609 pbm->name, stat);
610 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
611 ret = IRQ_HANDLED;
612 }
613 return ret;
614 }
615
616 static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
617 {
618 struct pci_pbm_info *pbm = dev_id;
619 struct pci_controller_info *p = pbm->parent;
620 unsigned long afsr_reg, afar_reg;
621 unsigned long afsr, afar, error_bits;
622 int is_pbm_a, reported;
623
624 is_pbm_a = (pbm == &pbm->parent->pbm_A);
625 if (is_pbm_a) {
626 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A;
627 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A;
628 } else {
629 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B;
630 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B;
631 }
632
633 /* Latch error status. */
634 afar = psycho_read(afar_reg);
635 afsr = psycho_read(afsr_reg);
636
637 /* Clear primary/secondary error status bits. */
638 error_bits = afsr &
639 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
640 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
641 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
642 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
643 if (!error_bits)
644 return psycho_pcierr_intr_other(pbm, is_pbm_a);
645 psycho_write(afsr_reg, error_bits);
646
647 /* Log the error. */
648 printk("%s: PCI Error, primary error type[%s]\n",
649 pbm->name,
650 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
651 "Master Abort" :
652 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
653 "Target Abort" :
654 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
655 "Excessive Retries" :
656 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
657 "Parity Error" : "???"))))));
658 printk("%s: bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
659 pbm->name,
660 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
661 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
662 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
663 printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
664 printk("%s: PCI Secondary errors [", pbm->name);
665 reported = 0;
666 if (afsr & PSYCHO_PCIAFSR_SMA) {
667 reported++;
668 printk("(Master Abort)");
669 }
670 if (afsr & PSYCHO_PCIAFSR_STA) {
671 reported++;
672 printk("(Target Abort)");
673 }
674 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
675 reported++;
676 printk("(Excessive Retries)");
677 }
678 if (afsr & PSYCHO_PCIAFSR_SPERR) {
679 reported++;
680 printk("(Parity Error)");
681 }
682 if (!reported)
683 printk("(none)");
684 printk("]\n");
685
686 /* For the error types shown, scan PBM's PCI bus for devices
687 * which have logged that error type.
688 */
689
690 /* If we see a Target Abort, this could be the result of an
691 * IOMMU translation error of some sort. It is extremely
692 * useful to log this information as usually it indicates
693 * a bug in the IOMMU support code or a PCI device driver.
694 */
695 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
696 psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
697 pci_scan_for_target_abort(pbm, pbm->pci_bus);
698 }
699 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
700 pci_scan_for_master_abort(pbm, pbm->pci_bus);
701
702 /* For excessive retries, PSYCHO/PBM will abort the device
703 * and there is no way to specifically check for excessive
704 * retries in the config space status registers. So what
705 * we hope is that we'll catch it via the master/target
706 * abort events.
707 */
708
709 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
710 pci_scan_for_parity_error(pbm, pbm->pci_bus);
711
712 return IRQ_HANDLED;
713 }
714
715 /* XXX What about PowerFail/PowerManagement??? -DaveM */
716 #define PSYCHO_ECC_CTRL 0x0020
717 #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
718 #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
719 #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
720 static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
721 {
722 struct of_device *op = of_find_device_by_node(pbm->prom_node);
723 unsigned long base = pbm->controller_regs;
724 u64 tmp;
725 int err;
726
727 if (!op)
728 return;
729
730 /* Psycho interrupt property order is:
731 * 0: PCIERR INO for this PBM
732 * 1: UE ERR
733 * 2: CE ERR
734 * 3: POWER FAIL
735 * 4: SPARE HARDWARE
736 * 5: POWER MANAGEMENT
737 */
738
739 if (op->num_irqs < 6)
740 return;
741
742 /* We really mean to ignore the return result here. Two
743 * PCI controller share the same interrupt numbers and
744 * drive the same front-end hardware. Whichever of the
745 * two get in here first will register the IRQ handler
746 * the second will just error out since we do not pass in
747 * IRQF_SHARED.
748 */
749 err = request_irq(op->irqs[1], psycho_ue_intr, 0,
750 "PSYCHO_UE", pbm);
751 err = request_irq(op->irqs[2], psycho_ce_intr, 0,
752 "PSYCHO_CE", pbm);
753
754 /* This one, however, ought not to fail. We can just warn
755 * about it since the system can still operate properly even
756 * if this fails.
757 */
758 err = request_irq(op->irqs[0], psycho_pcierr_intr, 0,
759 "PSYCHO_PCIERR", pbm);
760 if (err)
761 printk(KERN_WARNING "%s: Could not register PCIERR, "
762 "err=%d\n", pbm->name, err);
763
764 /* Enable UE and CE interrupts for controller. */
765 psycho_write(base + PSYCHO_ECC_CTRL,
766 (PSYCHO_ECCCTRL_EE |
767 PSYCHO_ECCCTRL_UE |
768 PSYCHO_ECCCTRL_CE));
769
770 /* Enable PCI Error interrupts and clear error
771 * bits for each PBM.
772 */
773 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
774 tmp |= (PSYCHO_PCICTRL_SERR |
775 PSYCHO_PCICTRL_SBH_ERR |
776 PSYCHO_PCICTRL_EEN);
777 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
778 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
779
780 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
781 tmp |= (PSYCHO_PCICTRL_SERR |
782 PSYCHO_PCICTRL_SBH_ERR |
783 PSYCHO_PCICTRL_EEN);
784 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
785 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
786 }
787
788 /* PSYCHO boot time probing and initialization. */
789 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
790 {
791 u8 *addr;
792
793 /* Set cache-line size to 64 bytes, this is actually
794 * a nop but I do it for completeness.
795 */
796 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
797 0, PCI_CACHE_LINE_SIZE);
798 pci_config_write8(addr, 64 / sizeof(u32));
799
800 /* Set PBM latency timer to 64 PCI clocks. */
801 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
802 0, PCI_LATENCY_TIMER);
803 pci_config_write8(addr, 64);
804 }
805
806 static void __init psycho_scan_bus(struct pci_pbm_info *pbm)
807 {
808 pbm_config_busmastering(pbm);
809 pbm->is_66mhz_capable = 0;
810 pbm->pci_bus = pci_scan_one_pbm(pbm);
811
812 /* After the PCI bus scan is complete, we can register
813 * the error interrupt handlers.
814 */
815 psycho_register_error_handlers(pbm);
816 }
817
818 static int psycho_iommu_init(struct pci_pbm_info *pbm)
819 {
820 struct iommu *iommu = pbm->iommu;
821 unsigned long i;
822 u64 control;
823 int err;
824
825 /* Register addresses. */
826 iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL;
827 iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE;
828 iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH;
829 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL);
830
831 /* PSYCHO's IOMMU lacks ctx flushing. */
832 iommu->iommu_ctxflush = 0;
833
834 /* We use the main control register of PSYCHO as the write
835 * completion register.
836 */
837 iommu->write_complete_reg = pbm->controller_regs + PSYCHO_CONTROL;
838
839 /*
840 * Invalidate TLB Entries.
841 */
842 control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL);
843 control |= PSYCHO_IOMMU_CTRL_DENAB;
844 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control);
845 for (i = 0; i < 16; i++) {
846 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
847 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
848 }
849
850 /* Leave diag mode enabled for full-flushing done
851 * in pci_iommu.c
852 */
853 err = iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff,
854 pbm->numa_node);
855 if (err) {
856 printk(KERN_ERR PFX "iommu_table_init() fails\n");
857 return err;
858 }
859
860 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TSBBASE,
861 __pa(iommu->page_table));
862
863 control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL);
864 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
865 control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
866 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control);
867
868 /* If necessary, hook us up for starfire IRQ translations. */
869 if (this_is_starfire)
870 starfire_hookup(pbm->portid);
871
872 return 0;
873 }
874
875 #define PSYCHO_IRQ_RETRY 0x1a00UL
876 #define PSYCHO_PCIA_DIAG 0x2020UL
877 #define PSYCHO_PCIB_DIAG 0x4020UL
878 #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
879 #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
880 #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
881 #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
882 #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
883 #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
884 #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
885 #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
886
887 static void psycho_controller_hwinit(struct pci_pbm_info *pbm)
888 {
889 u64 tmp;
890
891 psycho_write(pbm->controller_regs + PSYCHO_IRQ_RETRY, 5);
892
893 /* Enable arbiter for all PCI slots. */
894 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_CTRL);
895 tmp |= PSYCHO_PCICTRL_AEN;
896 psycho_write(pbm->controller_regs + PSYCHO_PCIA_CTRL, tmp);
897
898 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_CTRL);
899 tmp |= PSYCHO_PCICTRL_AEN;
900 psycho_write(pbm->controller_regs + PSYCHO_PCIB_CTRL, tmp);
901
902 /* Disable DMA write / PIO read synchronization on
903 * both PCI bus segments.
904 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
905 */
906 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_DIAG);
907 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
908 psycho_write(pbm->controller_regs + PSYCHO_PCIA_DIAG, tmp);
909
910 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_DIAG);
911 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
912 psycho_write(pbm->controller_regs + PSYCHO_PCIB_DIAG, tmp);
913 }
914
915 static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
916 int is_pbm_a)
917 {
918 unsigned long base = pbm->controller_regs;
919 u64 control;
920
921 if (is_pbm_a) {
922 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
923 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
924 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
925 } else {
926 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
927 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
928 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
929 }
930 /* PSYCHO's streaming buffer lacks ctx flushing. */
931 pbm->stc.strbuf_ctxflush = 0;
932 pbm->stc.strbuf_ctxmatch_base = 0;
933
934 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
935 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
936 + 63UL)
937 & ~63UL);
938 pbm->stc.strbuf_flushflag_pa = (unsigned long)
939 __pa(pbm->stc.strbuf_flushflag);
940
941 /* Enable the streaming buffer. We have to be careful
942 * just in case OBP left it with LRU locking enabled.
943 *
944 * It is possible to control if PBM will be rerun on
945 * line misses. Currently I just retain whatever setting
946 * OBP left us with. All checks so far show it having
947 * a value of zero.
948 */
949 #undef PSYCHO_STRBUF_RERUN_ENABLE
950 #undef PSYCHO_STRBUF_RERUN_DISABLE
951 control = psycho_read(pbm->stc.strbuf_control);
952 control |= PSYCHO_STRBUF_CTRL_ENAB;
953 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
954 #ifdef PSYCHO_STRBUF_RERUN_ENABLE
955 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
956 #else
957 #ifdef PSYCHO_STRBUF_RERUN_DISABLE
958 control |= PSYCHO_STRBUF_CTRL_RRDIS;
959 #endif
960 #endif
961 psycho_write(pbm->stc.strbuf_control, control);
962
963 pbm->stc.strbuf_enabled = 1;
964 }
965
966 #define PSYCHO_IOSPACE_A 0x002000000UL
967 #define PSYCHO_IOSPACE_B 0x002010000UL
968 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
969 #define PSYCHO_MEMSPACE_A 0x100000000UL
970 #define PSYCHO_MEMSPACE_B 0x180000000UL
971 #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
972
973 static void __init psycho_pbm_init(struct pci_controller_info *p,
974 struct device_node *dp, int is_pbm_a)
975 {
976 struct property *prop;
977 struct pci_pbm_info *pbm;
978
979 if (is_pbm_a)
980 pbm = &p->pbm_A;
981 else
982 pbm = &p->pbm_B;
983
984 pbm->next = pci_pbm_root;
985 pci_pbm_root = pbm;
986
987 pbm->numa_node = -1;
988
989 pbm->pci_ops = &sun4u_pci_ops;
990 pbm->config_space_reg_bits = 8;
991
992 pbm->index = pci_num_pbms++;
993
994 pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
995 pbm->chip_version = 0;
996 prop = of_find_property(dp, "version#", NULL);
997 if (prop)
998 pbm->chip_version = *(int *) prop->value;
999 pbm->chip_revision = 0;
1000 prop = of_find_property(dp, "module-revision#", NULL);
1001 if (prop)
1002 pbm->chip_revision = *(int *) prop->value;
1003
1004 pbm->parent = p;
1005 pbm->prom_node = dp;
1006 pbm->name = dp->full_name;
1007
1008 printk(KERN_INFO "%s: PSYCHO PCI Bus Module ver[%x:%x]\n",
1009 pbm->name,
1010 pbm->chip_version, pbm->chip_revision);
1011
1012 pci_determine_mem_io_space(pbm);
1013
1014 pci_get_pbm_props(pbm);
1015
1016 psycho_pbm_strbuf_init(pbm, is_pbm_a);
1017
1018 psycho_scan_bus(pbm);
1019 }
1020
1021 #define PSYCHO_CONFIGSPACE 0x001000000UL
1022
1023 static int __devinit psycho_probe(struct of_device *op,
1024 const struct of_device_id *match)
1025 {
1026 const struct linux_prom64_registers *pr_regs;
1027 struct device_node *dp = op->node;
1028 struct pci_controller_info *p;
1029 struct pci_pbm_info *pbm;
1030 struct iommu *iommu;
1031 int is_pbm_a, err;
1032 const u32 *p32;
1033 u32 upa_portid;
1034
1035 upa_portid = 0xff;
1036 p32 = of_get_property(dp, "upa-portid", NULL);
1037 if (p32)
1038 upa_portid = *p32;
1039
1040 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1041 struct pci_controller_info *p = pbm->parent;
1042
1043 if (p->pbm_A.portid == upa_portid) {
1044 is_pbm_a = (p->pbm_A.prom_node == NULL);
1045 psycho_pbm_init(p, dp, is_pbm_a);
1046 return 0;
1047 }
1048 }
1049
1050 err = -ENOMEM;
1051 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1052 if (!p) {
1053 printk(KERN_ERR PFX "Cannot allocate controller info.\n");
1054 goto out_free;
1055 }
1056
1057 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1058 if (!iommu) {
1059 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
1060 goto out_free;
1061 }
1062
1063 p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1064
1065 p->pbm_A.portid = upa_portid;
1066 p->pbm_B.portid = upa_portid;
1067
1068 pr_regs = of_get_property(dp, "reg", NULL);
1069 err = -ENODEV;
1070 if (!pr_regs) {
1071 printk(KERN_ERR PFX "No reg property.\n");
1072 goto out_free;
1073 }
1074
1075 p->pbm_A.controller_regs = pr_regs[2].phys_addr;
1076 p->pbm_B.controller_regs = pr_regs[2].phys_addr;
1077
1078 p->pbm_A.config_space = p->pbm_B.config_space =
1079 (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1080
1081 psycho_controller_hwinit(&p->pbm_A);
1082
1083 err = psycho_iommu_init(&p->pbm_A);
1084 if (err)
1085 goto out_free;
1086
1087 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
1088
1089 psycho_pbm_init(p, dp, is_pbm_a);
1090
1091 return 0;
1092
1093 out_free:
1094 if (p) {
1095 if (p->pbm_A.iommu)
1096 kfree(p->pbm_A.iommu);
1097 kfree(p);
1098 }
1099 return err;
1100 }
1101
1102 static struct of_device_id __initdata psycho_match[] = {
1103 {
1104 .name = "pci",
1105 .compatible = "pci108e,8000",
1106 },
1107 {},
1108 };
1109
1110 static struct of_platform_driver psycho_driver = {
1111 .name = DRIVER_NAME,
1112 .match_table = psycho_match,
1113 .probe = psycho_probe,
1114 };
1115
1116 static int __init psycho_init(void)
1117 {
1118 return of_register_driver(&psycho_driver, &of_bus_type);
1119 }
1120
1121 subsys_initcall(psycho_init);
kernel source for telekom puls (alcatel/mediatek)