arch/sparc64/kernel/chmc.c

   1 /* chmc.c: Driver for UltraSPARC-III memory controller.
   2  *
   3  * Copyright (C) 2001, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/kernel.h>
   8 #include <linux/types.h>
   9 #include <linux/slab.h>
  10 #include <linux/list.h>
  11 #include <linux/string.h>
  12 #include <linux/sched.h>
  13 #include <linux/smp.h>
  14 #include <linux/errno.h>
  15 #include <linux/init.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <asm/spitfire.h>
  19 #include <asm/chmctrl.h>
  20 #include <asm/cpudata.h>
  21 #include <asm/oplib.h>
  22 #include <asm/prom.h>
  23 #include <asm/head.h>
  24 #include <asm/io.h>
  25
  26 #define DRV_MODULE_NAME         "chmc"
  27 #define PFX DRV_MODULE_NAME     ": "
  28 #define DRV_MODULE_VERSION      "0.2"
  29
  30 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  31 MODULE_DESCRIPTION("UltraSPARC-III memory controller driver");
  32 MODULE_LICENSE("GPL");
  33 MODULE_VERSION(DRV_MODULE_VERSION);
  34
  35 #define CHMCTRL_NDGRPS  2
  36 #define CHMCTRL_NDIMMS  4
  37
  38 #define DIMMS_PER_MC    (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS)
  39
  40 /* OBP memory-layout property format. */
  41 struct obp_map {
  42         unsigned char   dimm_map[144];
  43         unsigned char   pin_map[576];
  44 };
  45
  46 #define DIMM_LABEL_SZ   8
  47
  48 struct obp_mem_layout {
  49         /* One max 8-byte string label per DIMM.  Usually
  50          * this matches the label on the motherboard where
  51          * that DIMM resides.
  52          */
  53         char            dimm_labels[DIMMS_PER_MC][DIMM_LABEL_SZ];
  54
  55         /* If symmetric use map[0], else it is
  56          * asymmetric and map[1] should be used.
  57          */
  58         char            symmetric;
  59
  60         struct obp_map  map[2];
  61 };
  62
  63 #define CHMCTRL_NBANKS  4
  64
  65 struct bank_info {
  66         struct mctrl_info       *mp;
  67         int                     bank_id;
  68
  69         u64                     raw_reg;
  70         int                     valid;
  71         int                     uk;
  72         int                     um;
  73         int                     lk;
  74         int                     lm;
  75         int                     interleave;
  76         unsigned long           base;
  77         unsigned long           size;
  78 };
  79
  80 struct mctrl_info {
  81         struct list_head        list;
  82         int                     portid;
  83
  84         struct obp_mem_layout   layout_prop;
  85         int                     layout_size;
  86
  87         void __iomem            *regs;
  88
  89         u64                     timing_control1;
  90         u64                     timing_control2;
  91         u64                     timing_control3;
  92         u64                     timing_control4;
  93         u64                     memaddr_control;
  94
  95         struct bank_info        logical_banks[CHMCTRL_NBANKS];
  96 };
  97
  98 static LIST_HEAD(mctrl_list);
  99
 100 /* Does BANK decode PHYS_ADDR? */
 101 static int bank_match(struct bank_info *bp, unsigned long phys_addr)
 102 {
 103         unsigned long upper_bits = (phys_addr & PA_UPPER_BITS) >> PA_UPPER_BITS_SHIFT;
 104         unsigned long lower_bits = (phys_addr & PA_LOWER_BITS) >> PA_LOWER_BITS_SHIFT;
 105
 106         /* Bank must be enabled to match. */
 107         if (bp->valid == 0)
 108                 return 0;
 109
 110         /* Would BANK match upper bits? */
 111         upper_bits ^= bp->um;           /* What bits are different? */
 112         upper_bits  = ~upper_bits;      /* Invert. */
 113         upper_bits |= bp->uk;           /* What bits don't matter for matching? */
 114         upper_bits  = ~upper_bits;      /* Invert. */
 115
 116         if (upper_bits)
 117                 return 0;
 118
 119         /* Would BANK match lower bits? */
 120         lower_bits ^= bp->lm;           /* What bits are different? */
 121         lower_bits  = ~lower_bits;      /* Invert. */
 122         lower_bits |= bp->lk;           /* What bits don't matter for matching? */
 123         lower_bits  = ~lower_bits;      /* Invert. */
 124
 125         if (lower_bits)
 126                 return 0;
 127
 128         /* I always knew you'd be the one. */
 129         return 1;
 130 }
 131
 132 /* Given PHYS_ADDR, search memory controller banks for a match. */
 133 static struct bank_info *find_bank(unsigned long phys_addr)
 134 {
 135         struct list_head *mctrl_head = &mctrl_list;
 136         struct list_head *mctrl_entry = mctrl_head->next;
 137
 138         for (;;) {
 139                 struct mctrl_info *mp =
 140                         list_entry(mctrl_entry, struct mctrl_info, list);
 141                 int bank_no;
 142
 143                 if (mctrl_entry == mctrl_head)
 144                         break;
 145                 mctrl_entry = mctrl_entry->next;
 146
 147                 for (bank_no = 0; bank_no < CHMCTRL_NBANKS; bank_no++) {
 148                         struct bank_info *bp;
 149
 150                         bp = &mp->logical_banks[bank_no];
 151                         if (bank_match(bp, phys_addr))
 152                                 return bp;
 153                 }
 154         }
 155
 156         return NULL;
 157 }
 158
 159 /* This is the main purpose of this driver. */
 160 #define SYNDROME_MIN    -1
 161 #define SYNDROME_MAX    144
 162 int chmc_getunumber(int syndrome_code,
 163                     unsigned long phys_addr,
 164                     char *buf, int buflen)
 165 {
 166         struct bank_info *bp;
 167         struct obp_mem_layout *prop;
 168         int bank_in_controller, first_dimm;
 169
 170         bp = find_bank(phys_addr);
 171         if (bp == NULL ||
 172             syndrome_code < SYNDROME_MIN ||
 173             syndrome_code > SYNDROME_MAX) {
 174                 buf[0] = '?';
 175                 buf[1] = '?';
 176                 buf[2] = '?';
 177                 buf[3] = '\0';
 178                 return 0;
 179         }
 180
 181         prop = &bp->mp->layout_prop;
 182         bank_in_controller = bp->bank_id & (CHMCTRL_NBANKS - 1);
 183         first_dimm  = (bank_in_controller & (CHMCTRL_NDGRPS - 1));
 184         first_dimm *= CHMCTRL_NDIMMS;
 185
 186         if (syndrome_code != SYNDROME_MIN) {
 187                 struct obp_map *map;
 188                 int qword, where_in_line, where, map_index, map_offset;
 189                 unsigned int map_val;
 190
 191                 /* Yaay, single bit error so we can figure out
 192                  * the exact dimm.
 193                  */
 194                 if (prop->symmetric)
 195                         map = &prop->map[0];
 196                 else
 197                         map = &prop->map[1];
 198
 199                 /* Covert syndrome code into the way the bits are
 200                  * positioned on the bus.
 201                  */
 202                 if (syndrome_code < 144 - 16)
 203                         syndrome_code += 16;
 204                 else if (syndrome_code < 144)
 205                         syndrome_code -= (144 - 7);
 206                 else if (syndrome_code < (144 + 3))
 207                         syndrome_code -= (144 + 3 - 4);
 208                 else
 209                         syndrome_code -= 144 + 3;
 210
 211                 /* All this magic has to do with how a cache line
 212                  * comes over the wire on Safari.  A 64-bit line
 213                  * comes over in 4 quadword cycles, each of which
 214                  * transmit ECC/MTAG info as well as the actual
 215                  * data.  144 bits per quadword, 576 total.
 216                  */
 217 #define LINE_SIZE       64
 218 #define LINE_ADDR_MSK   (LINE_SIZE - 1)
 219 #define QW_PER_LINE     4
 220 #define QW_BYTES        (LINE_SIZE / QW_PER_LINE)
 221 #define QW_BITS         144
 222 #define LAST_BIT        (576 - 1)
 223
 224                 qword = (phys_addr & LINE_ADDR_MSK) / QW_BYTES;
 225                 where_in_line = ((3 - qword) * QW_BITS) + syndrome_code;
 226                 where = (LAST_BIT - where_in_line);
 227                 map_index = where >> 2;
 228                 map_offset = where & 0x3;
 229                 map_val = map->dimm_map[map_index];
 230                 map_val = ((map_val >> ((3 - map_offset) << 1)) & (2 - 1));
 231
 232                 sprintf(buf, "%s, pin %3d",
 233                         prop->dimm_labels[first_dimm + map_val],
 234                         map->pin_map[where_in_line]);
 235         } else {
 236                 int dimm;
 237
 238                 /* Multi-bit error, we just dump out all the
 239                  * dimm labels associated with this bank.
 240                  */
 241                 for (dimm = 0; dimm < CHMCTRL_NDIMMS; dimm++) {
 242                         sprintf(buf, "%s ",
 243                                 prop->dimm_labels[first_dimm + dimm]);
 244                         buf += strlen(buf);
 245                 }
 246         }
 247         return 0;
 248 }
 249
 250 /* Accessing the registers is slightly complicated.  If you want
 251  * to get at the memory controller which is on the same processor
 252  * the code is executing, you must use special ASI load/store else
 253  * you go through the global mapping.
 254  */
 255 static u64 read_mcreg(struct mctrl_info *mp, unsigned long offset)
 256 {
 257         unsigned long ret, this_cpu;
 258
 259         preempt_disable();
 260
 261         this_cpu = real_hard_smp_processor_id();
 262
 263         if (mp->portid == this_cpu) {
 264                 __asm__ __volatile__("ldxa      [%1] %2, %0"
 265                                      : "=r" (ret)
 266                                      : "r" (offset), "i" (ASI_MCU_CTRL_REG));
 267         } else {
 268                 __asm__ __volatile__("ldxa      [%1] %2, %0"
 269                                      : "=r" (ret)
 270                                      : "r" (mp->regs + offset),
 271                                        "i" (ASI_PHYS_BYPASS_EC_E));
 272         }
 273
 274         preempt_enable();
 275
 276         return ret;
 277 }
 278
 279 #if 0 /* currently unused */
 280 static void write_mcreg(struct mctrl_info *mp, unsigned long offset, u64 val)
 281 {
 282         if (mp->portid == smp_processor_id()) {
 283                 __asm__ __volatile__("stxa      %0, [%1] %2"
 284                                      : : "r" (val),
 285                                          "r" (offset), "i" (ASI_MCU_CTRL_REG));
 286         } else {
 287                 __asm__ __volatile__("ldxa      %0, [%1] %2"
 288                                      : : "r" (val),
 289                                          "r" (mp->regs + offset),
 290                                          "i" (ASI_PHYS_BYPASS_EC_E));
 291         }
 292 }
 293 #endif
 294
 295 static void interpret_one_decode_reg(struct mctrl_info *mp, int which_bank, u64 val)
 296 {
 297         struct bank_info *p = &mp->logical_banks[which_bank];
 298
 299         p->mp = mp;
 300         p->bank_id = (CHMCTRL_NBANKS * mp->portid) + which_bank;
 301         p->raw_reg = val;
 302         p->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT;
 303         p->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT;
 304         p->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT;
 305         p->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT;
 306         p->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT;
 307
 308         p->base  =  (p->um);
 309         p->base &= ~(p->uk);
 310         p->base <<= PA_UPPER_BITS_SHIFT;
 311
 312         switch(p->lk) {
 313         case 0xf:
 314         default:
 315                 p->interleave = 1;
 316                 break;
 317
 318         case 0xe:
 319                 p->interleave = 2;
 320                 break;
 321
 322         case 0xc:
 323                 p->interleave = 4;
 324                 break;
 325
 326         case 0x8:
 327                 p->interleave = 8;
 328                 break;
 329
 330         case 0x0:
 331                 p->interleave = 16;
 332                 break;
 333         };
 334
 335         /* UK[10] is reserved, and UK[11] is not set for the SDRAM
 336          * bank size definition.
 337          */
 338         p->size = (((unsigned long)p->uk &
 339                     ((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT;
 340         p->size /= p->interleave;
 341 }
 342
 343 static void fetch_decode_regs(struct mctrl_info *mp)
 344 {
 345         if (mp->layout_size == 0)
 346                 return;
 347
 348         interpret_one_decode_reg(mp, 0,
 349                                  read_mcreg(mp, CHMCTRL_DECODE1));
 350         interpret_one_decode_reg(mp, 1,
 351                                  read_mcreg(mp, CHMCTRL_DECODE2));
 352         interpret_one_decode_reg(mp, 2,
 353                                  read_mcreg(mp, CHMCTRL_DECODE3));
 354         interpret_one_decode_reg(mp, 3,
 355                                  read_mcreg(mp, CHMCTRL_DECODE4));
 356 }
 357
 358 static int __devinit chmc_probe(struct of_device *op,
 359                                 const struct of_device_id *match)
 360 {
 361         struct device_node *dp = op->node;
 362         struct mctrl_info *mp;
 363         unsigned long ver;
 364         const void *pval;
 365         int len, portid;
 366
 367         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 368         if ((ver >> 32UL) == __JALAPENO_ID ||
 369             (ver >> 32UL) == __SERRANO_ID)
 370                 return -ENODEV;
 371
 372         mp = kzalloc(sizeof(*mp), GFP_KERNEL);
 373         if (!mp)
 374                 return -ENOMEM;
 375
 376         portid = of_getintprop_default(dp, "portid", -1);
 377         if (portid == -1)
 378                 goto fail;
 379
 380         mp->portid = portid;
 381         pval = of_get_property(dp, "memory-layout", &len);
 382         mp->layout_size = len;
 383         if (!pval)
 384                 mp->layout_size = 0;
 385         else {
 386                 if (mp->layout_size > sizeof(mp->layout_prop)) {
 387                         printk(KERN_ERR PFX "Unexpected memory-layout property "
 388                                "size %d.\n", mp->layout_size);
 389                         goto fail;
 390                 }
 391                 memcpy(&mp->layout_prop, pval, len);
 392         }
 393
 394         mp->regs = of_ioremap(&op->resource[0], 0, 0x48, "chmc");
 395         if (!mp->regs) {
 396                 printk(KERN_ERR PFX "Could not map registers.\n");
 397                 goto fail;
 398         }
 399
 400         if (mp->layout_size != 0UL) {
 401                 mp->timing_control1 = read_mcreg(mp, CHMCTRL_TCTRL1);
 402                 mp->timing_control2 = read_mcreg(mp, CHMCTRL_TCTRL2);
 403                 mp->timing_control3 = read_mcreg(mp, CHMCTRL_TCTRL3);
 404                 mp->timing_control4 = read_mcreg(mp, CHMCTRL_TCTRL4);
 405                 mp->memaddr_control = read_mcreg(mp, CHMCTRL_MACTRL);
 406         }
 407
 408         fetch_decode_regs(mp);
 409
 410         list_add(&mp->list, &mctrl_list);
 411
 412         /* Report the device. */
 413         printk(KERN_INFO PFX "UltraSPARC-III memory controller at %s [%s]\n",
 414                dp->full_name,
 415                (mp->layout_size ? "ACTIVE" : "INACTIVE"));
 416
 417         dev_set_drvdata(&op->dev, mp);
 418
 419         return 0;
 420
 421 fail:
 422         if (mp) {
 423                 if (mp->regs != NULL)
 424                         of_iounmap(&op->resource[0], mp->regs, 0x48);
 425                 kfree(mp);
 426         }
 427         return -1;
 428 }
 429
 430 static int __devexit chmc_remove(struct of_device *op)
 431 {
 432         struct mctrl_info *mp = dev_get_drvdata(&op->dev);
 433
 434         if (mp) {
 435                 list_del(&mp->list);
 436                 of_iounmap(&op->resource[0], mp->regs, 0x48);
 437                 kfree(mp);
 438         }
 439         return 0;
 440 }
 441
 442 static struct of_device_id chmc_match[] = {
 443         {
 444                 .name = "memory-controller",
 445         },
 446         {},
 447 };
 448 MODULE_DEVICE_TABLE(of, chmc_match);
 449
 450 static struct of_platform_driver chmc_driver = {
 451         .name           = "chmc",
 452         .match_table    = chmc_match,
 453         .probe          = chmc_probe,
 454         .remove         = __devexit_p(chmc_remove),
 455 };
 456
 457 static inline bool chmc_platform(void)
 458 {
 459         if (tlb_type == cheetah || tlb_type == cheetah_plus)
 460                 return true;
 461         return false;
 462 }
 463
 464 static int __init chmc_init(void)
 465 {
 466         if (!chmc_platform())
 467                 return -ENODEV;
 468
 469         return of_register_driver(&chmc_driver, &of_bus_type);
 470 }
 471
 472 static void __exit chmc_cleanup(void)
 473 {
 474         if (chmc_platform())
 475                 of_unregister_driver(&chmc_driver);
 476 }
 477
 478 module_init(chmc_init);
 479 module_exit(chmc_cleanup);