1 /* chmc.c: Driver for UltraSPARC-III memory controller.
3 * Copyright (C) 2001, 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 #include <linux/slab.h>
10 #include <linux/list.h>
11 #include <linux/string.h>
12 #include <linux/sched.h>
13 #include <linux/smp.h>
14 #include <linux/errno.h>
15 #include <linux/init.h>
17 #include <linux/of_device.h>
18 #include <asm/spitfire.h>
19 #include <asm/chmctrl.h>
20 #include <asm/cpudata.h>
21 #include <asm/oplib.h>
25 #include <asm/memctrl.h>
27 #define DRV_MODULE_NAME "chmc"
28 #define PFX DRV_MODULE_NAME ": "
29 #define DRV_MODULE_VERSION "0.2"
31 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
32 MODULE_DESCRIPTION("UltraSPARC-III memory controller driver");
33 MODULE_LICENSE("GPL");
34 MODULE_VERSION(DRV_MODULE_VERSION
);
36 #define CHMCTRL_NDGRPS 2
37 #define CHMCTRL_NDIMMS 4
39 #define CHMC_DIMMS_PER_MC (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS)
41 /* OBP memory-layout property format. */
43 unsigned char dimm_map
[144];
44 unsigned char pin_map
[576];
47 #define DIMM_LABEL_SZ 8
49 struct chmc_obp_mem_layout
{
50 /* One max 8-byte string label per DIMM. Usually
51 * this matches the label on the motherboard where
54 char dimm_labels
[CHMC_DIMMS_PER_MC
][DIMM_LABEL_SZ
];
56 /* If symmetric use map[0], else it is
57 * asymmetric and map[1] should be used.
61 struct chmc_obp_map map
[2];
64 #define CHMCTRL_NBANKS 4
66 struct chmc_bank_info
{
82 struct list_head list
;
85 struct chmc_obp_mem_layout layout_prop
;
96 struct chmc_bank_info logical_banks
[CHMCTRL_NBANKS
];
99 static LIST_HEAD(mctrl_list
);
101 /* Does BANK decode PHYS_ADDR? */
102 static int chmc_bank_match(struct chmc_bank_info
*bp
, unsigned long phys_addr
)
104 unsigned long upper_bits
= (phys_addr
& PA_UPPER_BITS
) >> PA_UPPER_BITS_SHIFT
;
105 unsigned long lower_bits
= (phys_addr
& PA_LOWER_BITS
) >> PA_LOWER_BITS_SHIFT
;
107 /* Bank must be enabled to match. */
111 /* Would BANK match upper bits? */
112 upper_bits
^= bp
->um
; /* What bits are different? */
113 upper_bits
= ~upper_bits
; /* Invert. */
114 upper_bits
|= bp
->uk
; /* What bits don't matter for matching? */
115 upper_bits
= ~upper_bits
; /* Invert. */
120 /* Would BANK match lower bits? */
121 lower_bits
^= bp
->lm
; /* What bits are different? */
122 lower_bits
= ~lower_bits
; /* Invert. */
123 lower_bits
|= bp
->lk
; /* What bits don't matter for matching? */
124 lower_bits
= ~lower_bits
; /* Invert. */
129 /* I always knew you'd be the one. */
133 /* Given PHYS_ADDR, search memory controller banks for a match. */
134 static struct chmc_bank_info
*chmc_find_bank(unsigned long phys_addr
)
136 struct list_head
*mctrl_head
= &mctrl_list
;
137 struct list_head
*mctrl_entry
= mctrl_head
->next
;
140 struct chmc
*p
= list_entry(mctrl_entry
, struct chmc
, list
);
143 if (mctrl_entry
== mctrl_head
)
145 mctrl_entry
= mctrl_entry
->next
;
147 for (bank_no
= 0; bank_no
< CHMCTRL_NBANKS
; bank_no
++) {
148 struct chmc_bank_info
*bp
;
150 bp
= &p
->logical_banks
[bank_no
];
151 if (chmc_bank_match(bp
, phys_addr
))
159 /* This is the main purpose of this driver. */
160 #define SYNDROME_MIN -1
161 #define SYNDROME_MAX 144
162 static int chmc_print_dimm(int syndrome_code
,
163 unsigned long phys_addr
,
164 char *buf
, int buflen
)
166 struct chmc_bank_info
*bp
;
167 struct chmc_obp_mem_layout
*prop
;
168 int bank_in_controller
, first_dimm
;
170 bp
= chmc_find_bank(phys_addr
);
172 syndrome_code
< SYNDROME_MIN
||
173 syndrome_code
> SYNDROME_MAX
) {
181 prop
= &bp
->p
->layout_prop
;
182 bank_in_controller
= bp
->bank_id
& (CHMCTRL_NBANKS
- 1);
183 first_dimm
= (bank_in_controller
& (CHMCTRL_NDGRPS
- 1));
184 first_dimm
*= CHMCTRL_NDIMMS
;
186 if (syndrome_code
!= SYNDROME_MIN
) {
187 struct chmc_obp_map
*map
;
188 int qword
, where_in_line
, where
, map_index
, map_offset
;
189 unsigned int map_val
;
191 /* Yaay, single bit error so we can figure out
199 /* Covert syndrome code into the way the bits are
200 * positioned on the bus.
202 if (syndrome_code
< 144 - 16)
204 else if (syndrome_code
< 144)
205 syndrome_code
-= (144 - 7);
206 else if (syndrome_code
< (144 + 3))
207 syndrome_code
-= (144 + 3 - 4);
209 syndrome_code
-= 144 + 3;
211 /* All this magic has to do with how a cache line
212 * comes over the wire on Safari. A 64-bit line
213 * comes over in 4 quadword cycles, each of which
214 * transmit ECC/MTAG info as well as the actual
215 * data. 144 bits per quadword, 576 total.
218 #define LINE_ADDR_MSK (LINE_SIZE - 1)
219 #define QW_PER_LINE 4
220 #define QW_BYTES (LINE_SIZE / QW_PER_LINE)
222 #define LAST_BIT (576 - 1)
224 qword
= (phys_addr
& LINE_ADDR_MSK
) / QW_BYTES
;
225 where_in_line
= ((3 - qword
) * QW_BITS
) + syndrome_code
;
226 where
= (LAST_BIT
- where_in_line
);
227 map_index
= where
>> 2;
228 map_offset
= where
& 0x3;
229 map_val
= map
->dimm_map
[map_index
];
230 map_val
= ((map_val
>> ((3 - map_offset
) << 1)) & (2 - 1));
232 sprintf(buf
, "%s, pin %3d",
233 prop
->dimm_labels
[first_dimm
+ map_val
],
234 map
->pin_map
[where_in_line
]);
238 /* Multi-bit error, we just dump out all the
239 * dimm labels associated with this bank.
241 for (dimm
= 0; dimm
< CHMCTRL_NDIMMS
; dimm
++) {
243 prop
->dimm_labels
[first_dimm
+ dimm
]);
250 /* Accessing the registers is slightly complicated. If you want
251 * to get at the memory controller which is on the same processor
252 * the code is executing, you must use special ASI load/store else
253 * you go through the global mapping.
255 static u64
chmc_read_mcreg(struct chmc
*p
, unsigned long offset
)
257 unsigned long ret
, this_cpu
;
261 this_cpu
= real_hard_smp_processor_id();
263 if (p
->portid
== this_cpu
) {
264 __asm__
__volatile__("ldxa [%1] %2, %0"
266 : "r" (offset
), "i" (ASI_MCU_CTRL_REG
));
268 __asm__
__volatile__("ldxa [%1] %2, %0"
270 : "r" (p
->regs
+ offset
),
271 "i" (ASI_PHYS_BYPASS_EC_E
));
279 #if 0 /* currently unused */
280 static void chmc_write_mcreg(struct chmc
*p
, unsigned long offset
, u64 val
)
282 if (p
->portid
== smp_processor_id()) {
283 __asm__
__volatile__("stxa %0, [%1] %2"
285 "r" (offset
), "i" (ASI_MCU_CTRL_REG
));
287 __asm__
__volatile__("ldxa %0, [%1] %2"
289 "r" (p
->regs
+ offset
),
290 "i" (ASI_PHYS_BYPASS_EC_E
));
295 static void chmc_interpret_one_decode_reg(struct chmc
*p
, int which_bank
, u64 val
)
297 struct chmc_bank_info
*bp
= &p
->logical_banks
[which_bank
];
300 bp
->bank_id
= (CHMCTRL_NBANKS
* p
->portid
) + which_bank
;
302 bp
->valid
= (val
& MEM_DECODE_VALID
) >> MEM_DECODE_VALID_SHIFT
;
303 bp
->uk
= (val
& MEM_DECODE_UK
) >> MEM_DECODE_UK_SHIFT
;
304 bp
->um
= (val
& MEM_DECODE_UM
) >> MEM_DECODE_UM_SHIFT
;
305 bp
->lk
= (val
& MEM_DECODE_LK
) >> MEM_DECODE_LK_SHIFT
;
306 bp
->lm
= (val
& MEM_DECODE_LM
) >> MEM_DECODE_LM_SHIFT
;
309 bp
->base
&= ~(bp
->uk
);
310 bp
->base
<<= PA_UPPER_BITS_SHIFT
;
335 /* UK[10] is reserved, and UK[11] is not set for the SDRAM
336 * bank size definition.
338 bp
->size
= (((unsigned long)bp
->uk
&
339 ((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT
;
340 bp
->size
/= bp
->interleave
;
343 static void chmc_fetch_decode_regs(struct chmc
*p
)
345 if (p
->layout_size
== 0)
348 chmc_interpret_one_decode_reg(p
, 0,
349 chmc_read_mcreg(p
, CHMCTRL_DECODE1
));
350 chmc_interpret_one_decode_reg(p
, 1,
351 chmc_read_mcreg(p
, CHMCTRL_DECODE2
));
352 chmc_interpret_one_decode_reg(p
, 2,
353 chmc_read_mcreg(p
, CHMCTRL_DECODE3
));
354 chmc_interpret_one_decode_reg(p
, 3,
355 chmc_read_mcreg(p
, CHMCTRL_DECODE4
));
358 static int __devinit
chmc_probe(struct of_device
*op
,
359 const struct of_device_id
*match
)
361 struct device_node
*dp
= op
->node
;
369 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
370 if ((ver
>> 32UL) == __JALAPENO_ID
||
371 (ver
>> 32UL) == __SERRANO_ID
)
374 portid
= of_getintprop_default(dp
, "portid", -1);
378 pval
= of_get_property(dp
, "memory-layout", &len
);
379 if (pval
&& len
> sizeof(p
->layout_prop
)) {
380 printk(KERN_ERR PFX
"Unexpected memory-layout property "
386 p
= kzalloc(sizeof(*p
), GFP_KERNEL
);
388 printk(KERN_ERR PFX
"Could not allocate struct chmc.\n");
393 p
->layout_size
= len
;
397 memcpy(&p
->layout_prop
, pval
, len
);
399 p
->regs
= of_ioremap(&op
->resource
[0], 0, 0x48, "chmc");
401 printk(KERN_ERR PFX
"Could not map registers.\n");
405 if (p
->layout_size
!= 0UL) {
406 p
->timing_control1
= chmc_read_mcreg(p
, CHMCTRL_TCTRL1
);
407 p
->timing_control2
= chmc_read_mcreg(p
, CHMCTRL_TCTRL2
);
408 p
->timing_control3
= chmc_read_mcreg(p
, CHMCTRL_TCTRL3
);
409 p
->timing_control4
= chmc_read_mcreg(p
, CHMCTRL_TCTRL4
);
410 p
->memaddr_control
= chmc_read_mcreg(p
, CHMCTRL_MACTRL
);
413 chmc_fetch_decode_regs(p
);
415 list_add(&p
->list
, &mctrl_list
);
417 /* Report the device. */
418 printk(KERN_INFO PFX
"UltraSPARC-III memory controller at %s [%s]\n",
420 (p
->layout_size
? "ACTIVE" : "INACTIVE"));
422 dev_set_drvdata(&op
->dev
, p
);
434 static int __devexit
chmc_remove(struct of_device
*op
)
436 struct chmc
*p
= dev_get_drvdata(&op
->dev
);
440 of_iounmap(&op
->resource
[0], p
->regs
, 0x48);
446 static struct of_device_id chmc_match
[] = {
448 .name
= "memory-controller",
452 MODULE_DEVICE_TABLE(of
, chmc_match
);
454 static struct of_platform_driver chmc_driver
= {
456 .match_table
= chmc_match
,
458 .remove
= __devexit_p(chmc_remove
),
461 static inline bool chmc_platform(void)
463 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
468 static int __init
chmc_init(void)
472 if (!chmc_platform())
475 ret
= register_dimm_printer(chmc_print_dimm
);
477 ret
= of_register_driver(&chmc_driver
, &of_bus_type
);
479 unregister_dimm_printer(chmc_print_dimm
);
484 static void __exit
chmc_cleanup(void)
486 if (chmc_platform()) {
487 unregister_dimm_printer(chmc_print_dimm
);
488 of_unregister_driver(&chmc_driver
);
492 module_init(chmc_init
);
493 module_exit(chmc_cleanup
);