1 /* chmc.c: Driver for UltraSPARC-III memory controller.
3 * Copyright (C) 2001, 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 #include <linux/slab.h>
10 #include <linux/list.h>
11 #include <linux/string.h>
12 #include <linux/sched.h>
13 #include <linux/smp.h>
14 #include <linux/errno.h>
15 #include <linux/init.h>
17 #include <linux/of_device.h>
18 #include <asm/spitfire.h>
19 #include <asm/chmctrl.h>
20 #include <asm/cpudata.h>
21 #include <asm/oplib.h>
26 #define DRV_MODULE_NAME "chmc"
27 #define PFX DRV_MODULE_NAME ": "
28 #define DRV_MODULE_VERSION "0.2"
30 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
31 MODULE_DESCRIPTION("UltraSPARC-III memory controller driver");
32 MODULE_LICENSE("GPL");
33 MODULE_VERSION(DRV_MODULE_VERSION
);
35 #define CHMCTRL_NDGRPS 2
36 #define CHMCTRL_NDIMMS 4
38 #define CHMC_DIMMS_PER_MC (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS)
40 /* OBP memory-layout property format. */
42 unsigned char dimm_map
[144];
43 unsigned char pin_map
[576];
46 #define DIMM_LABEL_SZ 8
48 struct chmc_obp_mem_layout
{
49 /* One max 8-byte string label per DIMM. Usually
50 * this matches the label on the motherboard where
53 char dimm_labels
[CHMC_DIMMS_PER_MC
][DIMM_LABEL_SZ
];
55 /* If symmetric use map[0], else it is
56 * asymmetric and map[1] should be used.
60 struct chmc_obp_map map
[2];
63 #define CHMCTRL_NBANKS 4
65 struct chmc_bank_info
{
81 struct list_head list
;
84 struct chmc_obp_mem_layout layout_prop
;
95 struct chmc_bank_info logical_banks
[CHMCTRL_NBANKS
];
98 static LIST_HEAD(mctrl_list
);
100 /* Does BANK decode PHYS_ADDR? */
101 static int chmc_bank_match(struct chmc_bank_info
*bp
, unsigned long phys_addr
)
103 unsigned long upper_bits
= (phys_addr
& PA_UPPER_BITS
) >> PA_UPPER_BITS_SHIFT
;
104 unsigned long lower_bits
= (phys_addr
& PA_LOWER_BITS
) >> PA_LOWER_BITS_SHIFT
;
106 /* Bank must be enabled to match. */
110 /* Would BANK match upper bits? */
111 upper_bits
^= bp
->um
; /* What bits are different? */
112 upper_bits
= ~upper_bits
; /* Invert. */
113 upper_bits
|= bp
->uk
; /* What bits don't matter for matching? */
114 upper_bits
= ~upper_bits
; /* Invert. */
119 /* Would BANK match lower bits? */
120 lower_bits
^= bp
->lm
; /* What bits are different? */
121 lower_bits
= ~lower_bits
; /* Invert. */
122 lower_bits
|= bp
->lk
; /* What bits don't matter for matching? */
123 lower_bits
= ~lower_bits
; /* Invert. */
128 /* I always knew you'd be the one. */
132 /* Given PHYS_ADDR, search memory controller banks for a match. */
133 static struct chmc_bank_info
*chmc_find_bank(unsigned long phys_addr
)
135 struct list_head
*mctrl_head
= &mctrl_list
;
136 struct list_head
*mctrl_entry
= mctrl_head
->next
;
139 struct chmc
*p
= list_entry(mctrl_entry
, struct chmc
, list
);
142 if (mctrl_entry
== mctrl_head
)
144 mctrl_entry
= mctrl_entry
->next
;
146 for (bank_no
= 0; bank_no
< CHMCTRL_NBANKS
; bank_no
++) {
147 struct chmc_bank_info
*bp
;
149 bp
= &p
->logical_banks
[bank_no
];
150 if (chmc_bank_match(bp
, phys_addr
))
158 /* This is the main purpose of this driver. */
159 #define SYNDROME_MIN -1
160 #define SYNDROME_MAX 144
161 int chmc_getunumber(int syndrome_code
,
162 unsigned long phys_addr
,
163 char *buf
, int buflen
)
165 struct chmc_bank_info
*bp
;
166 struct chmc_obp_mem_layout
*prop
;
167 int bank_in_controller
, first_dimm
;
169 bp
= chmc_find_bank(phys_addr
);
171 syndrome_code
< SYNDROME_MIN
||
172 syndrome_code
> SYNDROME_MAX
) {
180 prop
= &bp
->p
->layout_prop
;
181 bank_in_controller
= bp
->bank_id
& (CHMCTRL_NBANKS
- 1);
182 first_dimm
= (bank_in_controller
& (CHMCTRL_NDGRPS
- 1));
183 first_dimm
*= CHMCTRL_NDIMMS
;
185 if (syndrome_code
!= SYNDROME_MIN
) {
186 struct chmc_obp_map
*map
;
187 int qword
, where_in_line
, where
, map_index
, map_offset
;
188 unsigned int map_val
;
190 /* Yaay, single bit error so we can figure out
198 /* Covert syndrome code into the way the bits are
199 * positioned on the bus.
201 if (syndrome_code
< 144 - 16)
203 else if (syndrome_code
< 144)
204 syndrome_code
-= (144 - 7);
205 else if (syndrome_code
< (144 + 3))
206 syndrome_code
-= (144 + 3 - 4);
208 syndrome_code
-= 144 + 3;
210 /* All this magic has to do with how a cache line
211 * comes over the wire on Safari. A 64-bit line
212 * comes over in 4 quadword cycles, each of which
213 * transmit ECC/MTAG info as well as the actual
214 * data. 144 bits per quadword, 576 total.
217 #define LINE_ADDR_MSK (LINE_SIZE - 1)
218 #define QW_PER_LINE 4
219 #define QW_BYTES (LINE_SIZE / QW_PER_LINE)
221 #define LAST_BIT (576 - 1)
223 qword
= (phys_addr
& LINE_ADDR_MSK
) / QW_BYTES
;
224 where_in_line
= ((3 - qword
) * QW_BITS
) + syndrome_code
;
225 where
= (LAST_BIT
- where_in_line
);
226 map_index
= where
>> 2;
227 map_offset
= where
& 0x3;
228 map_val
= map
->dimm_map
[map_index
];
229 map_val
= ((map_val
>> ((3 - map_offset
) << 1)) & (2 - 1));
231 sprintf(buf
, "%s, pin %3d",
232 prop
->dimm_labels
[first_dimm
+ map_val
],
233 map
->pin_map
[where_in_line
]);
237 /* Multi-bit error, we just dump out all the
238 * dimm labels associated with this bank.
240 for (dimm
= 0; dimm
< CHMCTRL_NDIMMS
; dimm
++) {
242 prop
->dimm_labels
[first_dimm
+ dimm
]);
249 /* Accessing the registers is slightly complicated. If you want
250 * to get at the memory controller which is on the same processor
251 * the code is executing, you must use special ASI load/store else
252 * you go through the global mapping.
254 static u64
chmc_read_mcreg(struct chmc
*p
, unsigned long offset
)
256 unsigned long ret
, this_cpu
;
260 this_cpu
= real_hard_smp_processor_id();
262 if (p
->portid
== this_cpu
) {
263 __asm__
__volatile__("ldxa [%1] %2, %0"
265 : "r" (offset
), "i" (ASI_MCU_CTRL_REG
));
267 __asm__
__volatile__("ldxa [%1] %2, %0"
269 : "r" (p
->regs
+ offset
),
270 "i" (ASI_PHYS_BYPASS_EC_E
));
278 #if 0 /* currently unused */
279 static void chmc_write_mcreg(struct chmc
*p
, unsigned long offset
, u64 val
)
281 if (p
->portid
== smp_processor_id()) {
282 __asm__
__volatile__("stxa %0, [%1] %2"
284 "r" (offset
), "i" (ASI_MCU_CTRL_REG
));
286 __asm__
__volatile__("ldxa %0, [%1] %2"
288 "r" (p
->regs
+ offset
),
289 "i" (ASI_PHYS_BYPASS_EC_E
));
294 static void chmc_interpret_one_decode_reg(struct chmc
*p
, int which_bank
, u64 val
)
296 struct chmc_bank_info
*bp
= &p
->logical_banks
[which_bank
];
299 bp
->bank_id
= (CHMCTRL_NBANKS
* p
->portid
) + which_bank
;
301 bp
->valid
= (val
& MEM_DECODE_VALID
) >> MEM_DECODE_VALID_SHIFT
;
302 bp
->uk
= (val
& MEM_DECODE_UK
) >> MEM_DECODE_UK_SHIFT
;
303 bp
->um
= (val
& MEM_DECODE_UM
) >> MEM_DECODE_UM_SHIFT
;
304 bp
->lk
= (val
& MEM_DECODE_LK
) >> MEM_DECODE_LK_SHIFT
;
305 bp
->lm
= (val
& MEM_DECODE_LM
) >> MEM_DECODE_LM_SHIFT
;
308 bp
->base
&= ~(bp
->uk
);
309 bp
->base
<<= PA_UPPER_BITS_SHIFT
;
334 /* UK[10] is reserved, and UK[11] is not set for the SDRAM
335 * bank size definition.
337 bp
->size
= (((unsigned long)bp
->uk
&
338 ((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT
;
339 bp
->size
/= bp
->interleave
;
342 static void chmc_fetch_decode_regs(struct chmc
*p
)
344 if (p
->layout_size
== 0)
347 chmc_interpret_one_decode_reg(p
, 0,
348 chmc_read_mcreg(p
, CHMCTRL_DECODE1
));
349 chmc_interpret_one_decode_reg(p
, 1,
350 chmc_read_mcreg(p
, CHMCTRL_DECODE2
));
351 chmc_interpret_one_decode_reg(p
, 2,
352 chmc_read_mcreg(p
, CHMCTRL_DECODE3
));
353 chmc_interpret_one_decode_reg(p
, 3,
354 chmc_read_mcreg(p
, CHMCTRL_DECODE4
));
357 static int __devinit
chmc_probe(struct of_device
*op
,
358 const struct of_device_id
*match
)
360 struct device_node
*dp
= op
->node
;
368 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
369 if ((ver
>> 32UL) == __JALAPENO_ID
||
370 (ver
>> 32UL) == __SERRANO_ID
)
373 portid
= of_getintprop_default(dp
, "portid", -1);
377 pval
= of_get_property(dp
, "memory-layout", &len
);
378 if (pval
&& len
> sizeof(p
->layout_prop
)) {
379 printk(KERN_ERR PFX
"Unexpected memory-layout property "
385 p
= kzalloc(sizeof(*p
), GFP_KERNEL
);
387 printk(KERN_ERR PFX
"Could not allocate struct chmc.\n");
392 p
->layout_size
= len
;
396 memcpy(&p
->layout_prop
, pval
, len
);
398 p
->regs
= of_ioremap(&op
->resource
[0], 0, 0x48, "chmc");
400 printk(KERN_ERR PFX
"Could not map registers.\n");
404 if (p
->layout_size
!= 0UL) {
405 p
->timing_control1
= chmc_read_mcreg(p
, CHMCTRL_TCTRL1
);
406 p
->timing_control2
= chmc_read_mcreg(p
, CHMCTRL_TCTRL2
);
407 p
->timing_control3
= chmc_read_mcreg(p
, CHMCTRL_TCTRL3
);
408 p
->timing_control4
= chmc_read_mcreg(p
, CHMCTRL_TCTRL4
);
409 p
->memaddr_control
= chmc_read_mcreg(p
, CHMCTRL_MACTRL
);
412 chmc_fetch_decode_regs(p
);
414 list_add(&p
->list
, &mctrl_list
);
416 /* Report the device. */
417 printk(KERN_INFO PFX
"UltraSPARC-III memory controller at %s [%s]\n",
419 (p
->layout_size
? "ACTIVE" : "INACTIVE"));
421 dev_set_drvdata(&op
->dev
, p
);
433 static int __devexit
chmc_remove(struct of_device
*op
)
435 struct chmc
*p
= dev_get_drvdata(&op
->dev
);
439 of_iounmap(&op
->resource
[0], p
->regs
, 0x48);
445 static struct of_device_id chmc_match
[] = {
447 .name
= "memory-controller",
451 MODULE_DEVICE_TABLE(of
, chmc_match
);
453 static struct of_platform_driver chmc_driver
= {
455 .match_table
= chmc_match
,
457 .remove
= __devexit_p(chmc_remove
),
460 static inline bool chmc_platform(void)
462 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
467 static int __init
chmc_init(void)
469 if (!chmc_platform())
472 return of_register_driver(&chmc_driver
, &of_bus_type
);
475 static void __exit
chmc_cleanup(void)
478 of_unregister_driver(&chmc_driver
);
481 module_init(chmc_init
);
482 module_exit(chmc_cleanup
);