arch/sparc/kernel/head_64.S

   1 /* head.S: Initial boot code for the Sparc64 port of Linux.
   2  *
   3  * Copyright (C) 1996, 1997, 2007 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
   5  * Copyright (C) 1997, 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
   7  */
   8
   9 #include <linux/version.h>
  10 #include <linux/errno.h>
  11 #include <linux/threads.h>
  12 #include <linux/init.h>
  13 #include <linux/linkage.h>
  14 #include <asm/thread_info.h>
  15 #include <asm/asi.h>
  16 #include <asm/pstate.h>
  17 #include <asm/ptrace.h>
  18 #include <asm/spitfire.h>
  19 #include <asm/page.h>
  20 #include <asm/pgtable.h>
  21 #include <asm/errno.h>
  22 #include <asm/signal.h>
  23 #include <asm/processor.h>
  24 #include <asm/lsu.h>
  25 #include <asm/dcr.h>
  26 #include <asm/dcu.h>
  27 #include <asm/head.h>
  28 #include <asm/ttable.h>
  29 #include <asm/mmu.h>
  30 #include <asm/cpudata.h>
  31 #include <asm/pil.h>
  32 #include <asm/estate.h>
  33 #include <asm/sfafsr.h>
  34 #include <asm/unistd.h>
  35
  36 /* This section from from _start to sparc64_boot_end should fit into
  37  * 0x0000000000404000 to 0x0000000000408000.
  38  */
  39         .text
  40         .globl  start, _start, stext, _stext
  41 _start:
  42 start:
  43 _stext:
  44 stext:
  45 ! 0x0000000000404000
  46         b       sparc64_boot
  47          flushw                                 /* Flush register file.      */
  48
  49 /* This stuff has to be in sync with SILO and other potential boot loaders
  50  * Fields should be kept upward compatible and whenever any change is made,
  51  * HdrS version should be incremented.
  52  */
  53         .global root_flags, ram_flags, root_dev
  54         .global sparc_ramdisk_image, sparc_ramdisk_size
  55         .global sparc_ramdisk_image64
  56
  57         .ascii  "HdrS"
  58         .word   LINUX_VERSION_CODE
  59
  60         /* History:
  61          *
  62          * 0x0300 : Supports being located at other than 0x4000
  63          * 0x0202 : Supports kernel params string
  64          * 0x0201 : Supports reboot_command
  65          */
  66         .half   0x0301          /* HdrS version */
  67
  68 root_flags:
  69         .half   1
  70 root_dev:
  71         .half   0
  72 ram_flags:
  73         .half   0
  74 sparc_ramdisk_image:
  75         .word   0
  76 sparc_ramdisk_size:
  77         .word   0
  78         .xword  reboot_command
  79         .xword  bootstr_info
  80 sparc_ramdisk_image64:
  81         .xword  0
  82         .word   _end
  83
  84         /* PROM cif handler code address is in %o4.  */
  85 sparc64_boot:
  86         mov     %o4, %l7
  87
  88         /* We need to remap the kernel.  Use position independent
  89          * code to remap us to KERNBASE.
  90          *
  91          * SILO can invoke us with 32-bit address masking enabled,
  92          * so make sure that's clear.
  93          */
  94         rdpr    %pstate, %g1
  95         andn    %g1, PSTATE_AM, %g1
  96         wrpr    %g1, 0x0, %pstate
  97         ba,a,pt %xcc, 1f
  98
  99         .globl  prom_finddev_name, prom_chosen_path, prom_root_node
 100         .globl  prom_getprop_name, prom_mmu_name, prom_peer_name
 101         .globl  prom_callmethod_name, prom_translate_name, prom_root_compatible
 102         .globl  prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
 103         .globl  prom_boot_mapped_pc, prom_boot_mapping_mode
 104         .globl  prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
 105         .globl  prom_compatible_name, prom_cpu_path, prom_cpu_compatible
 106         .globl  is_sun4v, sun4v_chip_type, prom_set_trap_table_name
 107 prom_peer_name:
 108         .asciz  "peer"
 109 prom_compatible_name:
 110         .asciz  "compatible"
 111 prom_finddev_name:
 112         .asciz  "finddevice"
 113 prom_chosen_path:
 114         .asciz  "/chosen"
 115 prom_cpu_path:
 116         .asciz  "/cpu"
 117 prom_getprop_name:
 118         .asciz  "getprop"
 119 prom_mmu_name:
 120         .asciz  "mmu"
 121 prom_callmethod_name:
 122         .asciz  "call-method"
 123 prom_translate_name:
 124         .asciz  "translate"
 125 prom_map_name:
 126         .asciz  "map"
 127 prom_unmap_name:
 128         .asciz  "unmap"
 129 prom_set_trap_table_name:
 130         .asciz  "SUNW,set-trap-table"
 131 prom_sun4v_name:
 132         .asciz  "sun4v"
 133 prom_niagara_prefix:
 134         .asciz  "SUNW,UltraSPARC-T"
 135 prom_sparc_prefix:
 136         .asciz  "SPARC-T"
 137         .align  4
 138 prom_root_compatible:
 139         .skip   64
 140 prom_cpu_compatible:
 141         .skip   64
 142 prom_root_node:
 143         .word   0
 144 prom_mmu_ihandle_cache:
 145         .word   0
 146 prom_boot_mapped_pc:
 147         .word   0
 148 prom_boot_mapping_mode:
 149         .word   0
 150         .align  8
 151 prom_boot_mapping_phys_high:
 152         .xword  0
 153 prom_boot_mapping_phys_low:
 154         .xword  0
 155 is_sun4v:
 156         .word   0
 157 sun4v_chip_type:
 158         .word   SUN4V_CHIP_INVALID
 159 1:
 160         rd      %pc, %l0
 161
 162         mov     (1b - prom_peer_name), %l1
 163         sub     %l0, %l1, %l1
 164         mov     0, %l2
 165
 166         /* prom_root_node = prom_peer(0) */
 167         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "peer"
 168         mov     1, %l3
 169         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 1
 170         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 171         stx     %l2, [%sp + 2047 + 128 + 0x18]  ! arg1, 0
 172         stx     %g0, [%sp + 2047 + 128 + 0x20]  ! ret1
 173         call    %l7
 174          add    %sp, (2047 + 128), %o0          ! argument array
 175
 176         ldx     [%sp + 2047 + 128 + 0x20], %l4  ! prom root node
 177         mov     (1b - prom_root_node), %l1
 178         sub     %l0, %l1, %l1
 179         stw     %l4, [%l1]
 180
 181         mov     (1b - prom_getprop_name), %l1
 182         mov     (1b - prom_compatible_name), %l2
 183         mov     (1b - prom_root_compatible), %l5
 184         sub     %l0, %l1, %l1
 185         sub     %l0, %l2, %l2
 186         sub     %l0, %l5, %l5
 187
 188         /* prom_getproperty(prom_root_node, "compatible",
 189          *                  &prom_root_compatible, 64)
 190          */
 191         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "getprop"
 192         mov     4, %l3
 193         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 4
 194         mov     1, %l3
 195         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 196         stx     %l4, [%sp + 2047 + 128 + 0x18]  ! arg1, prom_root_node
 197         stx     %l2, [%sp + 2047 + 128 + 0x20]  ! arg2, "compatible"
 198         stx     %l5, [%sp + 2047 + 128 + 0x28]  ! arg3, &prom_root_compatible
 199         mov     64, %l3
 200         stx     %l3, [%sp + 2047 + 128 + 0x30]  ! arg4, size
 201         stx     %g0, [%sp + 2047 + 128 + 0x38]  ! ret1
 202         call    %l7
 203          add    %sp, (2047 + 128), %o0          ! argument array
 204
 205         mov     (1b - prom_finddev_name), %l1
 206         mov     (1b - prom_chosen_path), %l2
 207         mov     (1b - prom_boot_mapped_pc), %l3
 208         sub     %l0, %l1, %l1
 209         sub     %l0, %l2, %l2
 210         sub     %l0, %l3, %l3
 211         stw     %l0, [%l3]
 212         sub     %sp, (192 + 128), %sp
 213
 214         /* chosen_node = prom_finddevice("/chosen") */
 215         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "finddevice"
 216         mov     1, %l3
 217         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 1
 218         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 219         stx     %l2, [%sp + 2047 + 128 + 0x18]  ! arg1, "/chosen"
 220         stx     %g0, [%sp + 2047 + 128 + 0x20]  ! ret1
 221         call    %l7
 222          add    %sp, (2047 + 128), %o0          ! argument array
 223
 224         ldx     [%sp + 2047 + 128 + 0x20], %l4  ! chosen device node
 225
 226         mov     (1b - prom_getprop_name), %l1
 227         mov     (1b - prom_mmu_name), %l2
 228         mov     (1b - prom_mmu_ihandle_cache), %l5
 229         sub     %l0, %l1, %l1
 230         sub     %l0, %l2, %l2
 231         sub     %l0, %l5, %l5
 232
 233         /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
 234         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "getprop"
 235         mov     4, %l3
 236         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 4
 237         mov     1, %l3
 238         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 239         stx     %l4, [%sp + 2047 + 128 + 0x18]  ! arg1, chosen_node
 240         stx     %l2, [%sp + 2047 + 128 + 0x20]  ! arg2, "mmu"
 241         stx     %l5, [%sp + 2047 + 128 + 0x28]  ! arg3, &prom_mmu_ihandle_cache
 242         mov     4, %l3
 243         stx     %l3, [%sp + 2047 + 128 + 0x30]  ! arg4, sizeof(arg3)
 244         stx     %g0, [%sp + 2047 + 128 + 0x38]  ! ret1
 245         call    %l7
 246          add    %sp, (2047 + 128), %o0          ! argument array
 247
 248         mov     (1b - prom_callmethod_name), %l1
 249         mov     (1b - prom_translate_name), %l2
 250         sub     %l0, %l1, %l1
 251         sub     %l0, %l2, %l2
 252         lduw    [%l5], %l5                      ! prom_mmu_ihandle_cache
 253
 254         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "call-method"
 255         mov     3, %l3
 256         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 3
 257         mov     5, %l3
 258         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 5
 259         stx     %l2, [%sp + 2047 + 128 + 0x18]  ! arg1: "translate"
 260         stx     %l5, [%sp + 2047 + 128 + 0x20]  ! arg2: prom_mmu_ihandle_cache
 261         /* PAGE align */
 262         srlx    %l0, 13, %l3
 263         sllx    %l3, 13, %l3
 264         stx     %l3, [%sp + 2047 + 128 + 0x28]  ! arg3: vaddr, our PC
 265         stx     %g0, [%sp + 2047 + 128 + 0x30]  ! res1
 266         stx     %g0, [%sp + 2047 + 128 + 0x38]  ! res2
 267         stx     %g0, [%sp + 2047 + 128 + 0x40]  ! res3
 268         stx     %g0, [%sp + 2047 + 128 + 0x48]  ! res4
 269         stx     %g0, [%sp + 2047 + 128 + 0x50]  ! res5
 270         call    %l7
 271          add    %sp, (2047 + 128), %o0          ! argument array
 272
 273         ldx     [%sp + 2047 + 128 + 0x40], %l1  ! translation mode
 274         mov     (1b - prom_boot_mapping_mode), %l4
 275         sub     %l0, %l4, %l4
 276         stw     %l1, [%l4]
 277         mov     (1b - prom_boot_mapping_phys_high), %l4
 278         sub     %l0, %l4, %l4
 279         ldx     [%sp + 2047 + 128 + 0x48], %l2  ! physaddr high
 280         stx     %l2, [%l4 + 0x0]
 281         ldx     [%sp + 2047 + 128 + 0x50], %l3  ! physaddr low
 282         /* 4MB align */
 283         srlx    %l3, 22, %l3
 284         sllx    %l3, 22, %l3
 285         stx     %l3, [%l4 + 0x8]
 286
 287         /* Leave service as-is, "call-method" */
 288         mov     7, %l3
 289         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 7
 290         mov     1, %l3
 291         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 292         mov     (1b - prom_map_name), %l3
 293         sub     %l0, %l3, %l3
 294         stx     %l3, [%sp + 2047 + 128 + 0x18]  ! arg1: "map"
 295         /* Leave arg2 as-is, prom_mmu_ihandle_cache */
 296         mov     -1, %l3
 297         stx     %l3, [%sp + 2047 + 128 + 0x28]  ! arg3: mode (-1 default)
 298         /* 4MB align the kernel image size. */
 299         set     (_end - KERNBASE), %l3
 300         set     ((4 * 1024 * 1024) - 1), %l4
 301         add     %l3, %l4, %l3
 302         andn    %l3, %l4, %l3
 303         stx     %l3, [%sp + 2047 + 128 + 0x30]  ! arg4: roundup(ksize, 4MB)
 304         sethi   %hi(KERNBASE), %l3
 305         stx     %l3, [%sp + 2047 + 128 + 0x38]  ! arg5: vaddr (KERNBASE)
 306         stx     %g0, [%sp + 2047 + 128 + 0x40]  ! arg6: empty
 307         mov     (1b - prom_boot_mapping_phys_low), %l3
 308         sub     %l0, %l3, %l3
 309         ldx     [%l3], %l3
 310         stx     %l3, [%sp + 2047 + 128 + 0x48]  ! arg7: phys addr
 311         call    %l7
 312          add    %sp, (2047 + 128), %o0          ! argument array
 313
 314         add     %sp, (192 + 128), %sp
 315
 316         sethi   %hi(prom_root_compatible), %g1
 317         or      %g1, %lo(prom_root_compatible), %g1
 318         sethi   %hi(prom_sun4v_name), %g7
 319         or      %g7, %lo(prom_sun4v_name), %g7
 320         mov     5, %g3
 321 90:     ldub    [%g7], %g2
 322         ldub    [%g1], %g4
 323         cmp     %g2, %g4
 324         bne,pn  %icc, 80f
 325          add    %g7, 1, %g7
 326         subcc   %g3, 1, %g3
 327         bne,pt  %xcc, 90b
 328          add    %g1, 1, %g1
 329
 330         sethi   %hi(is_sun4v), %g1
 331         or      %g1, %lo(is_sun4v), %g1
 332         mov     1, %g7
 333         stw     %g7, [%g1]
 334
 335         /* cpu_node = prom_finddevice("/cpu") */
 336         mov     (1b - prom_finddev_name), %l1
 337         mov     (1b - prom_cpu_path), %l2
 338         sub     %l0, %l1, %l1
 339         sub     %l0, %l2, %l2
 340         sub     %sp, (192 + 128), %sp
 341
 342         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "finddevice"
 343         mov     1, %l3
 344         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 1
 345         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 346         stx     %l2, [%sp + 2047 + 128 + 0x18]  ! arg1, "/cpu"
 347         stx     %g0, [%sp + 2047 + 128 + 0x20]  ! ret1
 348         call    %l7
 349          add    %sp, (2047 + 128), %o0          ! argument array
 350
 351         ldx     [%sp + 2047 + 128 + 0x20], %l4  ! cpu device node
 352
 353         mov     (1b - prom_getprop_name), %l1
 354         mov     (1b - prom_compatible_name), %l2
 355         mov     (1b - prom_cpu_compatible), %l5
 356         sub     %l0, %l1, %l1
 357         sub     %l0, %l2, %l2
 358         sub     %l0, %l5, %l5
 359
 360         /* prom_getproperty(cpu_node, "compatible",
 361          *                  &prom_cpu_compatible, 64)
 362          */
 363         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "getprop"
 364         mov     4, %l3
 365         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 4
 366         mov     1, %l3
 367         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 368         stx     %l4, [%sp + 2047 + 128 + 0x18]  ! arg1, cpu_node
 369         stx     %l2, [%sp + 2047 + 128 + 0x20]  ! arg2, "compatible"
 370         stx     %l5, [%sp + 2047 + 128 + 0x28]  ! arg3, &prom_cpu_compatible
 371         mov     64, %l3
 372         stx     %l3, [%sp + 2047 + 128 + 0x30]  ! arg4, size
 373         stx     %g0, [%sp + 2047 + 128 + 0x38]  ! ret1
 374         call    %l7
 375          add    %sp, (2047 + 128), %o0          ! argument array
 376
 377         add     %sp, (192 + 128), %sp
 378
 379         sethi   %hi(prom_cpu_compatible), %g1
 380         or      %g1, %lo(prom_cpu_compatible), %g1
 381         sethi   %hi(prom_niagara_prefix), %g7
 382         or      %g7, %lo(prom_niagara_prefix), %g7
 383         mov     17, %g3
 384 90:     ldub    [%g7], %g2
 385         ldub    [%g1], %g4
 386         cmp     %g2, %g4
 387         bne,pn  %icc, 89f
 388          add    %g7, 1, %g7
 389         subcc   %g3, 1, %g3
 390         bne,pt  %xcc, 90b
 391          add    %g1, 1, %g1
 392         ba,pt   %xcc, 91f
 393          nop
 394
 395 89:     sethi   %hi(prom_cpu_compatible), %g1
 396         or      %g1, %lo(prom_cpu_compatible), %g1
 397         sethi   %hi(prom_sparc_prefix), %g7
 398         or      %g7, %lo(prom_sparc_prefix), %g7
 399         mov     7, %g3
 400 90:     ldub    [%g7], %g2
 401         ldub    [%g1], %g4
 402         cmp     %g2, %g4
 403         bne,pn  %icc, 4f
 404          add    %g7, 1, %g7
 405         subcc   %g3, 1, %g3
 406         bne,pt  %xcc, 90b
 407          add    %g1, 1, %g1
 408
 409         sethi   %hi(prom_cpu_compatible), %g1
 410         or      %g1, %lo(prom_cpu_compatible), %g1
 411         ldub    [%g1 + 7], %g2
 412         cmp     %g2, '3'
 413         be,pt   %xcc, 5f
 414          mov    SUN4V_CHIP_NIAGARA3, %g4
 415         ba,pt   %xcc, 4f
 416          nop
 417
 418 91:     sethi   %hi(prom_cpu_compatible), %g1
 419         or      %g1, %lo(prom_cpu_compatible), %g1
 420         ldub    [%g1 + 17], %g2
 421         cmp     %g2, '1'
 422         be,pt   %xcc, 5f
 423          mov    SUN4V_CHIP_NIAGARA1, %g4
 424         cmp     %g2, '2'
 425         be,pt   %xcc, 5f
 426          mov    SUN4V_CHIP_NIAGARA2, %g4
 427
 428 4:
 429         mov     SUN4V_CHIP_UNKNOWN, %g4
 430 5:      sethi   %hi(sun4v_chip_type), %g2
 431         or      %g2, %lo(sun4v_chip_type), %g2
 432         stw     %g4, [%g2]
 433
 434 80:
 435         BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
 436         BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
 437         BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
 438         ba,pt   %xcc, spitfire_boot
 439          nop
 440
 441 cheetah_plus_boot:
 442         /* Preserve OBP chosen DCU and DCR register settings.  */
 443         ba,pt   %xcc, cheetah_generic_boot
 444          nop
 445
 446 cheetah_boot:
 447         mov     DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
 448         wr      %g1, %asr18
 449
 450         sethi   %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
 451         or      %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
 452         sllx    %g7, 32, %g7
 453         or      %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
 454         stxa    %g7, [%g0] ASI_DCU_CONTROL_REG
 455         membar  #Sync
 456
 457 cheetah_generic_boot:
 458         mov     TSB_EXTENSION_P, %g3
 459         stxa    %g0, [%g3] ASI_DMMU
 460         stxa    %g0, [%g3] ASI_IMMU
 461         membar  #Sync
 462
 463         mov     TSB_EXTENSION_S, %g3
 464         stxa    %g0, [%g3] ASI_DMMU
 465         membar  #Sync
 466
 467         mov     TSB_EXTENSION_N, %g3
 468         stxa    %g0, [%g3] ASI_DMMU
 469         stxa    %g0, [%g3] ASI_IMMU
 470         membar  #Sync
 471
 472         ba,a,pt %xcc, jump_to_sun4u_init
 473
 474 spitfire_boot:
 475         /* Typically PROM has already enabled both MMU's and both on-chip
 476          * caches, but we do it here anyway just to be paranoid.
 477          */
 478         mov     (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
 479         stxa    %g1, [%g0] ASI_LSU_CONTROL
 480         membar  #Sync
 481
 482 jump_to_sun4u_init:
 483         /*
 484          * Make sure we are in privileged mode, have address masking,
 485          * using the ordinary globals and have enabled floating
 486          * point.
 487          *
 488          * Again, typically PROM has left %pil at 13 or similar, and
 489          * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
 490          */
 491         wrpr    %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
 492         wr      %g0, 0, %fprs
 493
 494         set     sun4u_init, %g2
 495         jmpl    %g2 + %g0, %g0
 496          nop
 497
 498         __REF
 499 sun4u_init:
 500         BRANCH_IF_SUN4V(g1, sun4v_init)
 501
 502         /* Set ctx 0 */
 503         mov             PRIMARY_CONTEXT, %g7
 504         stxa            %g0, [%g7] ASI_DMMU
 505         membar          #Sync
 506
 507         mov             SECONDARY_CONTEXT, %g7
 508         stxa            %g0, [%g7] ASI_DMMU
 509         membar  #Sync
 510
 511         ba,pt           %xcc, sun4u_continue
 512          nop
 513
 514 sun4v_init:
 515         /* Set ctx 0 */
 516         mov             PRIMARY_CONTEXT, %g7
 517         stxa            %g0, [%g7] ASI_MMU
 518         membar          #Sync
 519
 520         mov             SECONDARY_CONTEXT, %g7
 521         stxa            %g0, [%g7] ASI_MMU
 522         membar          #Sync
 523         ba,pt           %xcc, niagara_tlb_fixup
 524          nop
 525
 526 sun4u_continue:
 527         BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
 528
 529         ba,pt   %xcc, spitfire_tlb_fixup
 530          nop
 531
 532 niagara_tlb_fixup:
 533         mov     3, %g2          /* Set TLB type to hypervisor. */
 534         sethi   %hi(tlb_type), %g1
 535         stw     %g2, [%g1 + %lo(tlb_type)]
 536
 537         /* Patch copy/clear ops.  */
 538         sethi   %hi(sun4v_chip_type), %g1
 539         lduw    [%g1 + %lo(sun4v_chip_type)], %g1
 540         cmp     %g1, SUN4V_CHIP_NIAGARA1
 541         be,pt   %xcc, niagara_patch
 542          cmp    %g1, SUN4V_CHIP_NIAGARA2
 543         be,pt   %xcc, niagara2_patch
 544          nop
 545         cmp     %g1, SUN4V_CHIP_NIAGARA3
 546         be,pt   %xcc, niagara2_patch
 547          nop
 548
 549         call    generic_patch_copyops
 550          nop
 551         call    generic_patch_bzero
 552          nop
 553         call    generic_patch_pageops
 554          nop
 555
 556         ba,a,pt %xcc, 80f
 557 niagara2_patch:
 558         call    niagara2_patch_copyops
 559          nop
 560         call    niagara_patch_bzero
 561          nop
 562         call    niagara2_patch_pageops
 563          nop
 564
 565         ba,a,pt %xcc, 80f
 566
 567 niagara_patch:
 568         call    niagara_patch_copyops
 569          nop
 570         call    niagara_patch_bzero
 571          nop
 572         call    niagara_patch_pageops
 573          nop
 574
 575 80:
 576         /* Patch TLB/cache ops.  */
 577         call    hypervisor_patch_cachetlbops
 578          nop
 579
 580         ba,pt   %xcc, tlb_fixup_done
 581          nop
 582
 583 cheetah_tlb_fixup:
 584         mov     2, %g2          /* Set TLB type to cheetah+. */
 585         BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
 586
 587         mov     1, %g2          /* Set TLB type to cheetah. */
 588
 589 1:      sethi   %hi(tlb_type), %g1
 590         stw     %g2, [%g1 + %lo(tlb_type)]
 591
 592         /* Patch copy/page operations to cheetah optimized versions. */
 593         call    cheetah_patch_copyops
 594          nop
 595         call    cheetah_patch_copy_page
 596          nop
 597         call    cheetah_patch_cachetlbops
 598          nop
 599
 600         ba,pt   %xcc, tlb_fixup_done
 601          nop
 602
 603 spitfire_tlb_fixup:
 604         /* Set TLB type to spitfire. */
 605         mov     0, %g2
 606         sethi   %hi(tlb_type), %g1
 607         stw     %g2, [%g1 + %lo(tlb_type)]
 608
 609 tlb_fixup_done:
 610         sethi   %hi(init_thread_union), %g6
 611         or      %g6, %lo(init_thread_union), %g6
 612         ldx     [%g6 + TI_TASK], %g4
 613         mov     %sp, %l6
 614
 615         wr      %g0, ASI_P, %asi
 616         mov     1, %g1
 617         sllx    %g1, THREAD_SHIFT, %g1
 618         sub     %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
 619         add     %g6, %g1, %sp
 620         mov     0, %fp
 621
 622         /* Set per-cpu pointer initially to zero, this makes
 623          * the boot-cpu use the in-kernel-image per-cpu areas
 624          * before setup_per_cpu_area() is invoked.
 625          */
 626         clr     %g5
 627
 628         wrpr    %g0, 0, %wstate
 629         wrpr    %g0, 0x0, %tl
 630
 631         /* Clear the bss */
 632         sethi   %hi(__bss_start), %o0
 633         or      %o0, %lo(__bss_start), %o0
 634         sethi   %hi(_end), %o1
 635         or      %o1, %lo(_end), %o1
 636         call    __bzero
 637          sub    %o1, %o0, %o1
 638
 639 #ifdef CONFIG_LOCKDEP
 640         /* We have this call this super early, as even prom_init can grab
 641          * spinlocks and thus call into the lockdep code.
 642          */
 643         call    lockdep_init
 644          nop
 645 #endif
 646
 647         mov     %l6, %o1                        ! OpenPROM stack
 648         call    prom_init
 649          mov    %l7, %o0                        ! OpenPROM cif handler
 650
 651         /* Initialize current_thread_info()->cpu as early as possible.
 652          * In order to do that accurately we have to patch up the get_cpuid()
 653          * assembler sequences.  And that, in turn, requires that we know
 654          * if we are on a Starfire box or not.  While we're here, patch up
 655          * the sun4v sequences as well.
 656          */
 657         call    check_if_starfire
 658          nop
 659         call    per_cpu_patch
 660          nop
 661         call    sun4v_patch
 662          nop
 663
 664 #ifdef CONFIG_SMP
 665         call    hard_smp_processor_id
 666          nop
 667         cmp     %o0, NR_CPUS
 668         blu,pt  %xcc, 1f
 669          nop
 670         call    boot_cpu_id_too_large
 671          nop
 672         /* Not reached... */
 673
 674 1:
 675 #else
 676         mov     0, %o0
 677 #endif
 678         sth     %o0, [%g6 + TI_CPU]
 679
 680         call    prom_init_report
 681          nop
 682
 683         /* Off we go.... */
 684         call    start_kernel
 685          nop
 686         /* Not reached... */
 687
 688         .previous
 689
 690         /* This is meant to allow the sharing of this code between
 691          * boot processor invocation (via setup_tba() below) and
 692          * secondary processor startup (via trampoline.S).  The
 693          * former does use this code, the latter does not yet due
 694          * to some complexities.  That should be fixed up at some
 695          * point.
 696          *
 697          * There used to be enormous complexity wrt. transferring
 698          * over from the firmware's trap table to the Linux kernel's.
 699          * For example, there was a chicken & egg problem wrt. building
 700          * the OBP page tables, yet needing to be on the Linux kernel
 701          * trap table (to translate PAGE_OFFSET addresses) in order to
 702          * do that.
 703          *
 704          * We now handle OBP tlb misses differently, via linear lookups
 705          * into the prom_trans[] array.  So that specific problem no
 706          * longer exists.  Yet, unfortunately there are still some issues
 707          * preventing trampoline.S from using this code... ho hum.
 708          */
 709         .globl  setup_trap_table
 710 setup_trap_table:
 711         save    %sp, -192, %sp
 712
 713         /* Force interrupts to be disabled. */
 714         rdpr    %pstate, %l0
 715         andn    %l0, PSTATE_IE, %o1
 716         wrpr    %o1, 0x0, %pstate
 717         rdpr    %pil, %l1
 718         wrpr    %g0, PIL_NORMAL_MAX, %pil
 719
 720         /* Make the firmware call to jump over to the Linux trap table.  */
 721         sethi   %hi(is_sun4v), %o0
 722         lduw    [%o0 + %lo(is_sun4v)], %o0
 723         brz,pt  %o0, 1f
 724          nop
 725
 726         TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
 727         add     %g2, TRAP_PER_CPU_FAULT_INFO, %g2
 728         stxa    %g2, [%g0] ASI_SCRATCHPAD
 729
 730         /* Compute physical address:
 731          *
 732          * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
 733          */
 734         sethi   %hi(KERNBASE), %g3
 735         sub     %g2, %g3, %g2
 736         sethi   %hi(kern_base), %g3
 737         ldx     [%g3 + %lo(kern_base)], %g3
 738         add     %g2, %g3, %o1
 739         sethi   %hi(sparc64_ttable_tl0), %o0
 740
 741         set     prom_set_trap_table_name, %g2
 742         stx     %g2, [%sp + 2047 + 128 + 0x00]
 743         mov     2, %g2
 744         stx     %g2, [%sp + 2047 + 128 + 0x08]
 745         mov     0, %g2
 746         stx     %g2, [%sp + 2047 + 128 + 0x10]
 747         stx     %o0, [%sp + 2047 + 128 + 0x18]
 748         stx     %o1, [%sp + 2047 + 128 + 0x20]
 749         sethi   %hi(p1275buf), %g2
 750         or      %g2, %lo(p1275buf), %g2
 751         ldx     [%g2 + 0x08], %o1
 752         call    %o1
 753          add    %sp, (2047 + 128), %o0
 754
 755         ba,pt   %xcc, 2f
 756          nop
 757
 758 1:      sethi   %hi(sparc64_ttable_tl0), %o0
 759         set     prom_set_trap_table_name, %g2
 760         stx     %g2, [%sp + 2047 + 128 + 0x00]
 761         mov     1, %g2
 762         stx     %g2, [%sp + 2047 + 128 + 0x08]
 763         mov     0, %g2
 764         stx     %g2, [%sp + 2047 + 128 + 0x10]
 765         stx     %o0, [%sp + 2047 + 128 + 0x18]
 766         sethi   %hi(p1275buf), %g2
 767         or      %g2, %lo(p1275buf), %g2
 768         ldx     [%g2 + 0x08], %o1
 769         call    %o1
 770          add    %sp, (2047 + 128), %o0
 771
 772         /* Start using proper page size encodings in ctx register.  */
 773 2:      sethi   %hi(sparc64_kern_pri_context), %g3
 774         ldx     [%g3 + %lo(sparc64_kern_pri_context)], %g2
 775
 776         mov             PRIMARY_CONTEXT, %g1
 777
 778 661:    stxa            %g2, [%g1] ASI_DMMU
 779         .section        .sun4v_1insn_patch, "ax"
 780         .word           661b
 781         stxa            %g2, [%g1] ASI_MMU
 782         .previous
 783
 784         membar  #Sync
 785
 786         BRANCH_IF_SUN4V(o2, 1f)
 787
 788         /* Kill PROM timer */
 789         sethi   %hi(0x80000000), %o2
 790         sllx    %o2, 32, %o2
 791         wr      %o2, 0, %tick_cmpr
 792
 793         BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
 794
 795         ba,pt   %xcc, 2f
 796          nop
 797
 798         /* Disable STICK_INT interrupts. */
 799 1:
 800         sethi   %hi(0x80000000), %o2
 801         sllx    %o2, 32, %o2
 802         wr      %o2, %asr25
 803
 804 2:
 805         wrpr    %g0, %g0, %wstate
 806
 807         call    init_irqwork_curcpu
 808          nop
 809
 810         /* Now we can restore interrupt state. */
 811         wrpr    %l0, 0, %pstate
 812         wrpr    %l1, 0x0, %pil
 813
 814         ret
 815          restore
 816
 817         .globl  setup_tba
 818 setup_tba:
 819         save    %sp, -192, %sp
 820
 821         /* The boot processor is the only cpu which invokes this
 822          * routine, the other cpus set things up via trampoline.S.
 823          * So save the OBP trap table address here.
 824          */
 825         rdpr    %tba, %g7
 826         sethi   %hi(prom_tba), %o1
 827         or      %o1, %lo(prom_tba), %o1
 828         stx     %g7, [%o1]
 829
 830         call    setup_trap_table
 831          nop
 832
 833         ret
 834          restore
 835 sparc64_boot_end:
 836
 837 #include "etrap_64.S"
 838 #include "rtrap_64.S"
 839 #include "winfixup.S"
 840 #include "fpu_traps.S"
 841 #include "ivec.S"
 842 #include "getsetcc.S"
 843 #include "utrap.S"
 844 #include "spiterrs.S"
 845 #include "cherrs.S"
 846 #include "misctrap.S"
 847 #include "syscalls.S"
 848 #include "helpers.S"
 849 #include "hvcalls.S"
 850 #include "sun4v_tlb_miss.S"
 851 #include "sun4v_ivec.S"
 852 #include "ktlb.S"
 853 #include "tsb.S"
 854
 855 /*
 856  * The following skip makes sure the trap table in ttable.S is aligned
 857  * on a 32K boundary as required by the v9 specs for TBA register.
 858  *
 859  * We align to a 32K boundary, then we have the 32K kernel TSB,
 860  * the 64K kernel 4MB TSB, and then the 32K aligned trap table.
 861  */
 862 1:
 863         .skip   0x4000 + _start - 1b
 864
 865 ! 0x0000000000408000
 866
 867         .globl  swapper_tsb
 868 swapper_tsb:
 869         .skip   (32 * 1024)
 870
 871         .globl  swapper_4m_tsb
 872 swapper_4m_tsb:
 873         .skip   (64 * 1024)
 874
 875 ! 0x0000000000420000
 876
 877         /* Some care needs to be exercised if you try to move the
 878          * location of the trap table relative to other things.  For
 879          * one thing there are br* instructions in some of the
 880          * trap table entires which branch back to code in ktlb.S
 881          * Those instructions can only handle a signed 16-bit
 882          * displacement.
 883          *
 884          * There is a binutils bug (bugzilla #4558) which causes
 885          * the relocation overflow checks for such instructions to
 886          * not be done correctly.  So bintuils will not notice the
 887          * error and will instead write junk into the relocation and
 888          * you'll have an unbootable kernel.
 889          */
 890 #include "ttable.S"
 891
 892 ! 0x0000000000428000
 893
 894 #include "systbls_64.S"
 895
 896         .data
 897         .align  8
 898         .globl  prom_tba, tlb_type
 899 prom_tba:       .xword  0
 900 tlb_type:       .word   0       /* Must NOT end up in BSS */
 901         .section        ".fixup",#alloc,#execinstr
 902
 903         .globl  __ret_efault, __retl_efault, __ret_one, __retl_one
 904 ENTRY(__ret_efault)
 905         ret
 906          restore %g0, -EFAULT, %o0
 907 ENDPROC(__ret_efault)
 908
 909 ENTRY(__retl_efault)
 910         retl
 911          mov    -EFAULT, %o0
 912 ENDPROC(__retl_efault)
 913
 914 ENTRY(__retl_one)
 915         retl
 916          mov    1, %o0
 917 ENDPROC(__retl_one)
 918
 919 ENTRY(__ret_one_asi)
 920         wr      %g0, ASI_AIUS, %asi
 921         ret
 922          restore %g0, 1, %o0
 923 ENDPROC(__ret_one_asi)
 924
 925 ENTRY(__retl_one_asi)
 926         wr      %g0, ASI_AIUS, %asi
 927         retl
 928          mov    1, %o0
 929 ENDPROC(__retl_one_asi)
 930
 931 ENTRY(__retl_o1)
 932         retl
 933          mov    %o1, %o0
 934 ENDPROC(__retl_o1)