2 * 'traps.c' handles hardware traps and faults after we have saved some
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002 - 2007 Paul Mundt
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/hardirq.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/module.h>
20 #include <linux/kallsyms.h>
22 #include <linux/bug.h>
23 #include <linux/debug_locks.h>
24 #include <linux/kdebug.h>
25 #include <linux/kexec.h>
26 #include <linux/limits.h>
27 #include <asm/system.h>
28 #include <asm/uaccess.h>
30 #include <asm/kprobes.h>
33 # define TRAP_RESERVED_INST 4
34 # define TRAP_ILLEGAL_SLOT_INST 6
35 # define TRAP_ADDRESS_ERROR 9
36 # ifdef CONFIG_CPU_SH2A
37 # define TRAP_FPU_ERROR 13
38 # define TRAP_DIVZERO_ERROR 17
39 # define TRAP_DIVOVF_ERROR 18
42 #define TRAP_RESERVED_INST 12
43 #define TRAP_ILLEGAL_SLOT_INST 13
46 static void dump_mem(const char *str
, unsigned long bottom
, unsigned long top
)
51 printk("%s(0x%08lx to 0x%08lx)\n", str
, bottom
, top
);
53 for (p
= bottom
& ~31; p
< top
; ) {
54 printk("%04lx: ", p
& 0xffff);
56 for (i
= 0; i
< 8; i
++, p
+= 4) {
59 if (p
< bottom
|| p
>= top
)
62 if (__get_user(val
, (unsigned int __user
*)p
)) {
73 static DEFINE_SPINLOCK(die_lock
);
75 void die(const char * str
, struct pt_regs
* regs
, long err
)
77 static int die_counter
;
82 spin_lock_irq(&die_lock
);
85 printk("%s: %04lx [#%d]\n", str
, err
& 0xffff, ++die_counter
);
90 printk("Process: %s (pid: %d, stack limit = %p)\n", current
->comm
,
91 task_pid_nr(current
), task_stack_page(current
) + 1);
93 if (!user_mode(regs
) || in_interrupt())
94 dump_mem("Stack: ", regs
->regs
[15], THREAD_SIZE
+
95 (unsigned long)task_stack_page(current
));
97 notify_die(DIE_OOPS
, str
, regs
, err
, 255, SIGSEGV
);
100 add_taint(TAINT_DIE
);
101 spin_unlock_irq(&die_lock
);
103 if (kexec_should_crash(current
))
107 panic("Fatal exception in interrupt");
110 panic("Fatal exception");
116 static inline void die_if_kernel(const char *str
, struct pt_regs
*regs
,
119 if (!user_mode(regs
))
124 * try and fix up kernelspace address errors
125 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
126 * - kernel/userspace interfaces cause a jump to an appropriate handler
127 * - other kernel errors are bad
129 static void die_if_no_fixup(const char * str
, struct pt_regs
* regs
, long err
)
131 if (!user_mode(regs
)) {
132 const struct exception_table_entry
*fixup
;
133 fixup
= search_exception_tables(regs
->pc
);
135 regs
->pc
= fixup
->fixup
;
142 static inline void sign_extend(unsigned int count
, unsigned char *dst
)
144 #ifdef __LITTLE_ENDIAN__
145 if ((count
== 1) && dst
[0] & 0x80) {
150 if ((count
== 2) && dst
[1] & 0x80) {
155 if ((count
== 1) && dst
[3] & 0x80) {
160 if ((count
== 2) && dst
[2] & 0x80) {
167 static struct mem_access user_mem_access
= {
173 * handle an instruction that does an unaligned memory access by emulating the
175 * - note that PC _may not_ point to the faulting instruction
176 * (if that instruction is in a branch delay slot)
177 * - return 0 if emulation okay, -EFAULT on existential error
179 static int handle_unaligned_ins(opcode_t instruction
, struct pt_regs
*regs
,
180 struct mem_access
*ma
)
182 int ret
, index
, count
;
183 unsigned long *rm
, *rn
;
184 unsigned char *src
, *dst
;
185 unsigned char __user
*srcu
, *dstu
;
187 index
= (instruction
>>8)&15; /* 0x0F00 */
188 rn
= ®s
->regs
[index
];
190 index
= (instruction
>>4)&15; /* 0x00F0 */
191 rm
= ®s
->regs
[index
];
193 count
= 1<<(instruction
&3);
196 switch (instruction
>>12) {
197 case 0: /* mov.[bwl] to/from memory via r0+rn */
198 if (instruction
& 8) {
200 srcu
= (unsigned char __user
*)*rm
;
201 srcu
+= regs
->regs
[0];
202 dst
= (unsigned char *)rn
;
203 *(unsigned long *)dst
= 0;
205 #if !defined(__LITTLE_ENDIAN__)
208 if (ma
->from(dst
, srcu
, count
))
211 sign_extend(count
, dst
);
214 src
= (unsigned char *)rm
;
215 #if !defined(__LITTLE_ENDIAN__)
218 dstu
= (unsigned char __user
*)*rn
;
219 dstu
+= regs
->regs
[0];
221 if (ma
->to(dstu
, src
, count
))
227 case 1: /* mov.l Rm,@(disp,Rn) */
228 src
= (unsigned char*) rm
;
229 dstu
= (unsigned char __user
*)*rn
;
230 dstu
+= (instruction
&0x000F)<<2;
232 if (ma
->to(dstu
, src
, 4))
237 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
240 src
= (unsigned char*) rm
;
241 dstu
= (unsigned char __user
*)*rn
;
242 #if !defined(__LITTLE_ENDIAN__)
245 if (ma
->to(dstu
, src
, count
))
250 case 5: /* mov.l @(disp,Rm),Rn */
251 srcu
= (unsigned char __user
*)*rm
;
252 srcu
+= (instruction
& 0x000F) << 2;
253 dst
= (unsigned char *)rn
;
254 *(unsigned long *)dst
= 0;
256 if (ma
->from(dst
, srcu
, 4))
261 case 6: /* mov.[bwl] from memory, possibly with post-increment */
262 srcu
= (unsigned char __user
*)*rm
;
265 dst
= (unsigned char*) rn
;
266 *(unsigned long*)dst
= 0;
268 #if !defined(__LITTLE_ENDIAN__)
271 if (ma
->from(dst
, srcu
, count
))
273 sign_extend(count
, dst
);
278 switch ((instruction
&0xFF00)>>8) {
279 case 0x81: /* mov.w R0,@(disp,Rn) */
280 src
= (unsigned char *) ®s
->regs
[0];
281 #if !defined(__LITTLE_ENDIAN__)
284 dstu
= (unsigned char __user
*)*rm
; /* called Rn in the spec */
285 dstu
+= (instruction
& 0x000F) << 1;
287 if (ma
->to(dstu
, src
, 2))
292 case 0x85: /* mov.w @(disp,Rm),R0 */
293 srcu
= (unsigned char __user
*)*rm
;
294 srcu
+= (instruction
& 0x000F) << 1;
295 dst
= (unsigned char *) ®s
->regs
[0];
296 *(unsigned long *)dst
= 0;
298 #if !defined(__LITTLE_ENDIAN__)
301 if (ma
->from(dst
, srcu
, 2))
312 /* Argh. Address not only misaligned but also non-existent.
313 * Raise an EFAULT and see if it's trapped
315 die_if_no_fixup("Fault in unaligned fixup", regs
, 0);
320 * emulate the instruction in the delay slot
321 * - fetches the instruction from PC+2
323 static inline int handle_delayslot(struct pt_regs
*regs
,
324 opcode_t old_instruction
,
325 struct mem_access
*ma
)
327 opcode_t instruction
;
328 void __user
*addr
= (void __user
*)(regs
->pc
+
329 instruction_size(old_instruction
));
331 if (copy_from_user(&instruction
, addr
, sizeof(instruction
))) {
332 /* the instruction-fetch faulted */
337 die("delay-slot-insn faulting in handle_unaligned_delayslot",
341 return handle_unaligned_ins(instruction
, regs
, ma
);
345 * handle an instruction that does an unaligned memory access
346 * - have to be careful of branch delay-slot instructions that fault
348 * - if the branch would be taken PC points to the branch
349 * - if the branch would not be taken, PC points to delay-slot
351 * - PC always points to delayed branch
352 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
355 /* Macros to determine offset from current PC for branch instructions */
356 /* Explicit type coercion is used to force sign extension where needed */
357 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
358 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
361 * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
365 static int handle_unaligned_notify_count
= 10;
367 int handle_unaligned_access(opcode_t instruction
, struct pt_regs
*regs
,
368 struct mem_access
*ma
)
373 index
= (instruction
>>8)&15; /* 0x0F00 */
374 rm
= regs
->regs
[index
];
376 /* shout about the first ten userspace fixups */
377 if (user_mode(regs
) && handle_unaligned_notify_count
>0) {
378 handle_unaligned_notify_count
--;
380 printk(KERN_NOTICE
"Fixing up unaligned userspace access "
381 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
382 current
->comm
, task_pid_nr(current
),
383 (void *)regs
->pc
, instruction
);
387 switch (instruction
&0xF000) {
389 if (instruction
==0x000B) {
391 ret
= handle_delayslot(regs
, instruction
, ma
);
395 else if ((instruction
&0x00FF)==0x0023) {
397 ret
= handle_delayslot(regs
, instruction
, ma
);
401 else if ((instruction
&0x00FF)==0x0003) {
403 ret
= handle_delayslot(regs
, instruction
, ma
);
405 regs
->pr
= regs
->pc
+ 4;
410 /* mov.[bwl] to/from memory via r0+rn */
415 case 0x1000: /* mov.l Rm,@(disp,Rn) */
418 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
422 if ((instruction
&0x00FF)==0x002B) {
424 ret
= handle_delayslot(regs
, instruction
, ma
);
428 else if ((instruction
&0x00FF)==0x000B) {
430 ret
= handle_delayslot(regs
, instruction
, ma
);
432 regs
->pr
= regs
->pc
+ 4;
437 /* mov.[bwl] to/from memory via r0+rn */
442 case 0x5000: /* mov.l @(disp,Rm),Rn */
445 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
448 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
449 switch (instruction
&0x0F00) {
450 case 0x0100: /* mov.w R0,@(disp,Rm) */
452 case 0x0500: /* mov.w @(disp,Rm),R0 */
454 case 0x0B00: /* bf lab - no delayslot*/
456 case 0x0F00: /* bf/s lab */
457 ret
= handle_delayslot(regs
, instruction
, ma
);
459 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
460 if ((regs
->sr
& 0x00000001) != 0)
461 regs
->pc
+= 4; /* next after slot */
464 regs
->pc
+= SH_PC_8BIT_OFFSET(instruction
);
467 case 0x0900: /* bt lab - no delayslot */
469 case 0x0D00: /* bt/s lab */
470 ret
= handle_delayslot(regs
, instruction
, ma
);
472 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
473 if ((regs
->sr
& 0x00000001) == 0)
474 regs
->pc
+= 4; /* next after slot */
477 regs
->pc
+= SH_PC_8BIT_OFFSET(instruction
);
483 case 0xA000: /* bra label */
484 ret
= handle_delayslot(regs
, instruction
, ma
);
486 regs
->pc
+= SH_PC_12BIT_OFFSET(instruction
);
489 case 0xB000: /* bsr label */
490 ret
= handle_delayslot(regs
, instruction
, ma
);
492 regs
->pr
= regs
->pc
+ 4;
493 regs
->pc
+= SH_PC_12BIT_OFFSET(instruction
);
499 /* handle non-delay-slot instruction */
501 ret
= handle_unaligned_ins(instruction
, regs
, ma
);
503 regs
->pc
+= instruction_size(instruction
);
508 * Handle various address error exceptions:
509 * - instruction address error:
511 * PC >= 0x80000000 in user mode
512 * - data address error (read and write)
513 * misaligned data access
514 * access to >= 0x80000000 is user mode
515 * Unfortuntaly we can't distinguish between instruction address error
516 * and data address errors caused by read accesses.
518 asmlinkage
void do_address_error(struct pt_regs
*regs
,
519 unsigned long writeaccess
,
520 unsigned long address
)
522 unsigned long error_code
= 0;
525 opcode_t instruction
;
528 /* Intentional ifdef */
529 #ifdef CONFIG_CPU_HAS_SR_RB
530 error_code
= lookup_exception_vector();
535 if (user_mode(regs
)) {
536 int si_code
= BUS_ADRERR
;
540 /* bad PC is not something we can fix */
542 si_code
= BUS_ADRALN
;
547 if (copy_from_user(&instruction
, (void __user
*)(regs
->pc
),
548 sizeof(instruction
))) {
549 /* Argh. Fault on the instruction itself.
550 This should never happen non-SMP
556 tmp
= handle_unaligned_access(instruction
, regs
,
563 printk(KERN_NOTICE
"Sending SIGBUS to \"%s\" due to unaligned "
564 "access (PC %lx PR %lx)\n", current
->comm
, regs
->pc
,
567 info
.si_signo
= SIGBUS
;
569 info
.si_code
= si_code
;
570 info
.si_addr
= (void __user
*)address
;
571 force_sig_info(SIGBUS
, &info
, current
);
574 die("unaligned program counter", regs
, error_code
);
577 if (copy_from_user(&instruction
, (void __user
*)(regs
->pc
),
578 sizeof(instruction
))) {
579 /* Argh. Fault on the instruction itself.
580 This should never happen non-SMP
583 die("insn faulting in do_address_error", regs
, 0);
586 handle_unaligned_access(instruction
, regs
, &user_mem_access
);
593 * SH-DSP support gerg@snapgear.com.
595 int is_dsp_inst(struct pt_regs
*regs
)
597 unsigned short inst
= 0;
600 * Safe guard if DSP mode is already enabled or we're lacking
601 * the DSP altogether.
603 if (!(current_cpu_data
.flags
& CPU_HAS_DSP
) || (regs
->sr
& SR_DSP
))
606 get_user(inst
, ((unsigned short *) regs
->pc
));
610 /* Check for any type of DSP or support instruction */
611 if ((inst
== 0xf000) || (inst
== 0x4000))
617 #define is_dsp_inst(regs) (0)
618 #endif /* CONFIG_SH_DSP */
620 #ifdef CONFIG_CPU_SH2A
621 asmlinkage
void do_divide_error(unsigned long r4
, unsigned long r5
,
622 unsigned long r6
, unsigned long r7
,
623 struct pt_regs __regs
)
628 case TRAP_DIVZERO_ERROR
:
629 info
.si_code
= FPE_INTDIV
;
631 case TRAP_DIVOVF_ERROR
:
632 info
.si_code
= FPE_INTOVF
;
636 force_sig_info(SIGFPE
, &info
, current
);
640 asmlinkage
void do_reserved_inst(unsigned long r4
, unsigned long r5
,
641 unsigned long r6
, unsigned long r7
,
642 struct pt_regs __regs
)
644 struct pt_regs
*regs
= RELOC_HIDE(&__regs
, 0);
645 unsigned long error_code
;
646 struct task_struct
*tsk
= current
;
648 #ifdef CONFIG_SH_FPU_EMU
649 unsigned short inst
= 0;
652 get_user(inst
, (unsigned short*)regs
->pc
);
654 err
= do_fpu_inst(inst
, regs
);
656 regs
->pc
+= instruction_size(inst
);
659 /* not a FPU inst. */
663 /* Check if it's a DSP instruction */
664 if (is_dsp_inst(regs
)) {
665 /* Enable DSP mode, and restart instruction. */
671 error_code
= lookup_exception_vector();
674 force_sig(SIGILL
, tsk
);
675 die_if_no_fixup("reserved instruction", regs
, error_code
);
678 #ifdef CONFIG_SH_FPU_EMU
679 static int emulate_branch(unsigned short inst
, struct pt_regs
*regs
)
682 * bfs: 8fxx: PC+=d*2+4;
683 * bts: 8dxx: PC+=d*2+4;
684 * bra: axxx: PC+=D*2+4;
685 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
686 * braf:0x23: PC+=Rn*2+4;
687 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
689 * jsr: 4x0b: PC=Rn after PR=PC+4;
692 if (((inst
& 0xf000) == 0xb000) || /* bsr */
693 ((inst
& 0xf0ff) == 0x0003) || /* bsrf */
694 ((inst
& 0xf0ff) == 0x400b)) /* jsr */
695 regs
->pr
= regs
->pc
+ 4;
697 if ((inst
& 0xfd00) == 0x8d00) { /* bfs, bts */
698 regs
->pc
+= SH_PC_8BIT_OFFSET(inst
);
702 if ((inst
& 0xe000) == 0xa000) { /* bra, bsr */
703 regs
->pc
+= SH_PC_12BIT_OFFSET(inst
);
707 if ((inst
& 0xf0df) == 0x0003) { /* braf, bsrf */
708 regs
->pc
+= regs
->regs
[(inst
& 0x0f00) >> 8] + 4;
712 if ((inst
& 0xf0df) == 0x400b) { /* jmp, jsr */
713 regs
->pc
= regs
->regs
[(inst
& 0x0f00) >> 8];
717 if ((inst
& 0xffff) == 0x000b) { /* rts */
726 asmlinkage
void do_illegal_slot_inst(unsigned long r4
, unsigned long r5
,
727 unsigned long r6
, unsigned long r7
,
728 struct pt_regs __regs
)
730 struct pt_regs
*regs
= RELOC_HIDE(&__regs
, 0);
732 struct task_struct
*tsk
= current
;
734 if (kprobe_handle_illslot(regs
->pc
) == 0)
737 #ifdef CONFIG_SH_FPU_EMU
738 get_user(inst
, (unsigned short *)regs
->pc
+ 1);
739 if (!do_fpu_inst(inst
, regs
)) {
740 get_user(inst
, (unsigned short *)regs
->pc
);
741 if (!emulate_branch(inst
, regs
))
743 /* fault in branch.*/
745 /* not a FPU inst. */
748 inst
= lookup_exception_vector();
751 force_sig(SIGILL
, tsk
);
752 die_if_no_fixup("illegal slot instruction", regs
, inst
);
755 asmlinkage
void do_exception_error(unsigned long r4
, unsigned long r5
,
756 unsigned long r6
, unsigned long r7
,
757 struct pt_regs __regs
)
759 struct pt_regs
*regs
= RELOC_HIDE(&__regs
, 0);
762 ex
= lookup_exception_vector();
763 die_if_kernel("exception", regs
, ex
);
766 #if defined(CONFIG_SH_STANDARD_BIOS)
767 void *gdb_vbr_vector
;
769 static inline void __init
gdb_vbr_init(void)
771 register unsigned long vbr
;
774 * Read the old value of the VBR register to initialise
775 * the vector through which debug and BIOS traps are
776 * delegated by the Linux trap handler.
778 asm volatile("stc vbr, %0" : "=r" (vbr
));
780 gdb_vbr_vector
= (void *)(vbr
+ 0x100);
781 printk("Setting GDB trap vector to 0x%08lx\n",
782 (unsigned long)gdb_vbr_vector
);
786 void __cpuinit
per_cpu_trap_init(void)
788 extern void *vbr_base
;
790 #ifdef CONFIG_SH_STANDARD_BIOS
791 if (raw_smp_processor_id() == 0)
795 /* NOTE: The VBR value should be at P1
796 (or P2, virtural "fixed" address space).
797 It's definitely should not in physical address. */
799 asm volatile("ldc %0, vbr"
805 void *set_exception_table_vec(unsigned int vec
, void *handler
)
807 extern void *exception_handling_table
[];
810 old_handler
= exception_handling_table
[vec
];
811 exception_handling_table
[vec
] = handler
;
815 void __init
trap_init(void)
817 set_exception_table_vec(TRAP_RESERVED_INST
, do_reserved_inst
);
818 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST
, do_illegal_slot_inst
);
820 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
821 defined(CONFIG_SH_FPU_EMU)
823 * For SH-4 lacking an FPU, treat floating point instructions as
824 * reserved. They'll be handled in the math-emu case, or faulted on
827 set_exception_table_evt(0x800, do_reserved_inst
);
828 set_exception_table_evt(0x820, do_illegal_slot_inst
);
829 #elif defined(CONFIG_SH_FPU)
830 #ifdef CONFIG_CPU_SUBTYPE_SHX3
831 set_exception_table_evt(0xd80, fpu_state_restore_trap_handler
);
832 set_exception_table_evt(0xda0, fpu_state_restore_trap_handler
);
834 set_exception_table_evt(0x800, fpu_state_restore_trap_handler
);
835 set_exception_table_evt(0x820, fpu_state_restore_trap_handler
);
839 #ifdef CONFIG_CPU_SH2
840 set_exception_table_vec(TRAP_ADDRESS_ERROR
, address_error_trap_handler
);
842 #ifdef CONFIG_CPU_SH2A
843 set_exception_table_vec(TRAP_DIVZERO_ERROR
, do_divide_error
);
844 set_exception_table_vec(TRAP_DIVOVF_ERROR
, do_divide_error
);
846 set_exception_table_vec(TRAP_FPU_ERROR
, fpu_error_trap_handler
);
850 /* Setup VBR for boot cpu */
854 void show_trace(struct task_struct
*tsk
, unsigned long *sp
,
855 struct pt_regs
*regs
)
859 if (regs
&& user_mode(regs
))
862 printk("\nCall trace:\n");
864 while (!kstack_end(sp
)) {
866 if (kernel_text_address(addr
))
875 debug_show_held_locks(tsk
);
878 void show_stack(struct task_struct
*tsk
, unsigned long *sp
)
885 sp
= (unsigned long *)current_stack_pointer
;
887 sp
= (unsigned long *)tsk
->thread
.sp
;
889 stack
= (unsigned long)sp
;
890 dump_mem("Stack: ", stack
, THREAD_SIZE
+
891 (unsigned long)task_stack_page(tsk
));
892 show_trace(tsk
, sp
, NULL
);
895 void dump_stack(void)
897 show_stack(NULL
, NULL
);
899 EXPORT_SYMBOL(dump_stack
);