arch/ppc64/kernel/idle_power4.S

   1 /*
   2  *  This file contains the power_save function for 6xx & 7xxx CPUs
   3  *  rewritten in assembler
   4  *
   5  *  Warning ! This code assumes that if your machine has a 750fx
   6  *  it will have PLL 1 set to low speed mode (used during NAP/DOZE).
   7  *  if this is not the case some additional changes will have to
   8  *  be done to check a runtime var (a bit like powersave-nap)
   9  *
  10  *  This program is free software; you can redistribute it and/or
  11  *  modify it under the terms of the GNU General Public License
  12  *  as published by the Free Software Foundation; either version
  13  *  2 of the License, or (at your option) any later version.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/threads.h>
  18 #include <asm/processor.h>
  19 #include <asm/page.h>
  20 #include <asm/cputable.h>
  21 #include <asm/thread_info.h>
  22 #include <asm/ppc_asm.h>
  23 #include <asm/offsets.h>
  24
  25 #undef DEBUG
  26
  27         .text
  28
  29 /*
  30  * Here is the power_save_6xx function. This could eventually be
  31  * split into several functions & changing the function pointer
  32  * depending on the various features.
  33  */
  34 _GLOBAL(power4_idle)
  35 BEGIN_FTR_SECTION
  36         blr
  37 END_FTR_SECTION_IFCLR(CPU_FTR_CAN_NAP)
  38         /* We must dynamically check for the NAP feature as it
  39          * can be cleared by CPU init after the fixups are done
  40          */
  41         LOADBASE(r3,cur_cpu_spec)
  42         ld      r4,cur_cpu_spec@l(r3)
  43         ld      r4,CPU_SPEC_FEATURES(r4)
  44         andi.   r0,r4,CPU_FTR_CAN_NAP
  45         beqlr
  46         /* Now check if user or arch enabled NAP mode */
  47         LOADBASE(r3,powersave_nap)
  48         lwz     r4,powersave_nap@l(r3)
  49         cmpwi   0,r4,0
  50         beqlr
  51
  52         /* Clear MSR:EE */
  53         mfmsr   r7
  54         li      r4,0
  55         ori     r4,r4,MSR_EE
  56         andc    r0,r7,r4
  57         mtmsrd  r0
  58
  59         /* Check current_thread_info()->flags */
  60         clrrdi  r4,r1,THREAD_SHIFT
  61         ld      r4,TI_FLAGS(r4)
  62         andi.   r0,r4,_TIF_NEED_RESCHED
  63         beq     1f
  64         mtmsrd  r7      /* out of line this ? */
  65         blr
  66 1:
  67         /* Go to NAP now */
  68 BEGIN_FTR_SECTION
  69         DSSALL
  70         sync
  71 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
  72         oris    r7,r7,MSR_POW@h
  73         sync
  74         isync
  75         mtmsrd  r7
  76         isync
  77         sync
  78         blr
  79