arch/ppc/platforms/4xx/cpci405.c

   1 /*
   2  * Board setup routines for the esd CPCI-405 cPCI Board.
   3  *
   4  * Copyright 2001-2006 esd electronic system design - hannover germany
   5  *
   6  * Authors: Matthias Fuchs
   7  *          matthias.fuchs@esd-electronics.com
   8  *          Stefan Roese
   9  *          stefan.roese@esd-electronics.com
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  *
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/pci.h>
  20 #include <asm/system.h>
  21 #include <asm/pci-bridge.h>
  22 #include <asm/machdep.h>
  23 #include <asm/todc.h>
  24 #include <linux/serial.h>
  25 #include <linux/serial_core.h>
  26 #include <asm/ocp.h>
  27 #include <asm/ibm_ocp_pci.h>
  28 #include <platforms/4xx/ibm405gp.h>
  29
  30 #ifdef CONFIG_GEN_RTC
  31 void *cpci405_nvram;
  32 #endif
  33
  34 extern bd_t __res;
  35
  36 /*
  37  * Some IRQs unique to CPCI-405.
  38  */
  39 int __init
  40 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  41 {
  42         static char pci_irq_table[][4] =
  43         /*
  44          *      PCI IDSEL/INTPIN->INTLINE
  45          *      A       B       C       D
  46          */
  47         {
  48                 {28,    29,     30,     27},    /* IDSEL 15 - cPCI slot 8 */
  49                 {29,    30,     27,     28},    /* IDSEL 16 - cPCI slot 7 */
  50                 {30,    27,     28,     29},    /* IDSEL 17 - cPCI slot 6 */
  51                 {27,    28,     29,     30},    /* IDSEL 18 - cPCI slot 5 */
  52                 {28,    29,     30,     27},    /* IDSEL 19 - cPCI slot 4 */
  53                 {29,    30,     27,     28},    /* IDSEL 20 - cPCI slot 3 */
  54                 {30,    27,     28,     29},    /* IDSEL 21 - cPCI slot 2 */
  55         };
  56         const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
  57         return PCI_IRQ_TABLE_LOOKUP;
  58 };
  59
  60 /* The serial clock for the chip is an internal clock determined by
  61  * different clock speeds/dividers.
  62  * Calculate the proper input baud rate and setup the serial driver.
  63  */
  64 static void __init
  65 cpci405_early_serial_map(void)
  66 {
  67         u32 uart_div;
  68         int uart_clock;
  69         struct uart_port port;
  70
  71          /* Calculate the serial clock input frequency
  72           *
  73           * The uart clock is the cpu frequency (provided in the board info
  74           * structure) divided by the external UART Divisor.
  75           */
  76         uart_div = ((mfdcr(DCRN_CHCR_BASE) & CHR0_UDIV) >> 1) + 1;
  77         uart_clock = __res.bi_procfreq / uart_div;
  78
  79         /* Setup serial port access */
  80         memset(&port, 0, sizeof(port));
  81 #if defined(CONFIG_UART0_TTYS0)
  82         port.membase = (void*)UART0_IO_BASE;
  83         port.irq = UART0_INT;
  84 #else
  85         port.membase = (void*)UART1_IO_BASE;
  86         port.irq = UART1_INT;
  87 #endif
  88         port.uartclk = uart_clock;
  89         port.regshift = 0;
  90         port.iotype = UPIO_MEM;
  91         port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
  92         port.line = 0;
  93
  94         if (early_serial_setup(&port) != 0) {
  95                 printk("Early serial init of port 0 failed\n");
  96         }
  97 #if defined(CONFIG_UART0_TTYS0)
  98         port.membase = (void*)UART1_IO_BASE;
  99         port.irq = UART1_INT;
 100 #else
 101         port.membase = (void*)UART0_IO_BASE;
 102         port.irq = UART0_INT;
 103 #endif
 104         port.line = 1;
 105
 106         if (early_serial_setup(&port) != 0) {
 107                 printk("Early serial init of port 1 failed\n");
 108         }
 109 }
 110
 111 void __init
 112 cpci405_setup_arch(void)
 113 {
 114         ppc4xx_setup_arch();
 115
 116         ibm_ocp_set_emac(0, 0);
 117
 118         cpci405_early_serial_map();
 119
 120 #ifdef CONFIG_GEN_RTC
 121         TODC_INIT(TODC_TYPE_MK48T35,
 122                   cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
 123 #endif
 124 }
 125
 126 void __init
 127 bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 128 {
 129 #ifdef CONFIG_PCI
 130         unsigned int bar_response, bar;
 131
 132         /* Disable region first */
 133         out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
 134         /* PLB starting addr, PCI: 0x80000000 */
 135         out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
 136         /* PCI start addr, 0x80000000 */
 137         out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
 138         /* 512MB range of PLB to PCI */
 139         out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
 140         /* Enable no pre-fetch, enable region */
 141         out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
 142                                                 (PPC405_PCI_UPPER_MEM -
 143                                                  PPC405_PCI_MEM_BASE)) | 0x01));
 144
 145         /* Disable region one */
 146         out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 147         out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
 148         out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
 149         out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
 150         out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 151         out_le32((void *) &(pcip->ptm1ms), 0x00000001);
 152
 153         /* Disable region two */
 154         out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 155         out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
 156         out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
 157         out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
 158         out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 159         out_le32((void *) &(pcip->ptm2ms), 0x00000000);
 160         out_le32((void *) &(pcip->ptm2la), 0x00000000);
 161
 162         /* Zero config bars */
 163         for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 164                 early_write_config_dword(hose, hose->first_busno,
 165                                          PCI_FUNC(hose->first_busno), bar,
 166                                          0x00000000);
 167                 early_read_config_dword(hose, hose->first_busno,
 168                                         PCI_FUNC(hose->first_busno), bar,
 169                                         &bar_response);
 170         }
 171 #endif
 172 }
 173
 174 void __init
 175 cpci405_map_io(void)
 176 {
 177         ppc4xx_map_io();
 178
 179 #ifdef CONFIG_GEN_RTC
 180         cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE);
 181 #endif
 182 }
 183
 184 void __init
 185 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 186               unsigned long r6, unsigned long r7)
 187 {
 188         ppc4xx_init(r3, r4, r5, r6, r7);
 189
 190         ppc_md.setup_arch = cpci405_setup_arch;
 191         ppc_md.setup_io_mappings = cpci405_map_io;
 192
 193 #ifdef CONFIG_GEN_RTC
 194         ppc_md.time_init = todc_time_init;
 195         ppc_md.set_rtc_time = todc_set_rtc_time;
 196         ppc_md.get_rtc_time = todc_get_rtc_time;
 197         ppc_md.nvram_read_val = todc_direct_read_val;
 198         ppc_md.nvram_write_val = todc_direct_write_val;
 199 #endif
 200 }