2 * Copyright 2006, Segher Boessenkool, IBM Corporation.
3 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; version 2 of the
12 #include <linux/irq.h>
13 #include <linux/bootmem.h>
14 #include <linux/msi.h>
17 #include <asm/hw_irq.h>
18 #include <asm/ppc-pci.h>
19 #include <asm/msi_bitmap.h>
23 /* A bit ugly, can we get this from the pci_dev somehow? */
24 static struct mpic
*msi_mpic
;
26 static void mpic_u3msi_mask_irq(struct irq_data
*data
)
32 static void mpic_u3msi_unmask_irq(struct irq_data
*data
)
34 mpic_unmask_irq(data
);
38 static struct irq_chip mpic_u3msi_chip
= {
39 .irq_shutdown
= mpic_u3msi_mask_irq
,
40 .irq_mask
= mpic_u3msi_mask_irq
,
41 .irq_unmask
= mpic_u3msi_unmask_irq
,
42 .irq_eoi
= mpic_end_irq
,
43 .irq_set_type
= mpic_set_irq_type
,
44 .irq_set_affinity
= mpic_set_affinity
,
48 static u64
read_ht_magic_addr(struct pci_dev
*pdev
, unsigned int pos
)
54 pci_read_config_byte(pdev
, pos
+ HT_MSI_FLAGS
, &flags
);
56 if (flags
& HT_MSI_FLAGS_FIXED
)
57 return HT_MSI_FIXED_ADDR
;
59 pci_read_config_dword(pdev
, pos
+ HT_MSI_ADDR_LO
, &tmp
);
60 addr
= tmp
& HT_MSI_ADDR_LO_MASK
;
61 pci_read_config_dword(pdev
, pos
+ HT_MSI_ADDR_HI
, &tmp
);
62 addr
= addr
| ((u64
)tmp
<< 32);
67 static u64
find_ht_magic_addr(struct pci_dev
*pdev
, unsigned int hwirq
)
72 for (bus
= pdev
->bus
; bus
&& bus
->self
; bus
= bus
->parent
) {
73 pos
= pci_find_ht_capability(bus
->self
, HT_CAPTYPE_MSI_MAPPING
);
75 return read_ht_magic_addr(bus
->self
, pos
);
81 static u64
find_u4_magic_addr(struct pci_dev
*pdev
, unsigned int hwirq
)
83 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
85 /* U4 PCIe MSIs need to write to the special register in
86 * the bridge that generates interrupts. There should be
87 * theorically a register at 0xf8005000 where you just write
88 * the MSI number and that triggers the right interrupt, but
89 * unfortunately, this is busted in HW, the bridge endian swaps
90 * the value and hits the wrong nibble in the register.
92 * So instead we use another register set which is used normally
93 * for converting HT interrupts to MPIC interrupts, which decodes
94 * the interrupt number as part of the low address bits
96 * This will not work if we ever use more than one legacy MSI in
97 * a block but we never do. For one MSI or multiple MSI-X where
98 * each interrupt address can be specified separately, it works
101 if (of_device_is_compatible(hose
->dn
, "u4-pcie") ||
102 of_device_is_compatible(hose
->dn
, "U4-pcie"))
103 return 0xf8004000 | (hwirq
<< 4);
108 static int u3msi_msi_check_device(struct pci_dev
*pdev
, int nvec
, int type
)
110 if (type
== PCI_CAP_ID_MSIX
)
111 pr_debug("u3msi: MSI-X untested, trying anyway.\n");
113 /* If we can't find a magic address then MSI ain't gonna work */
114 if (find_ht_magic_addr(pdev
, 0) == 0 &&
115 find_u4_magic_addr(pdev
, 0) == 0) {
116 pr_debug("u3msi: no magic address found for %s\n",
124 static void u3msi_teardown_msi_irqs(struct pci_dev
*pdev
)
126 struct msi_desc
*entry
;
127 irq_hw_number_t hwirq
;
129 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
130 if (entry
->irq
== NO_IRQ
)
133 hwirq
= virq_to_hw(entry
->irq
);
134 irq_set_msi_desc(entry
->irq
, NULL
);
135 irq_dispose_mapping(entry
->irq
);
136 msi_bitmap_free_hwirqs(&msi_mpic
->msi_bitmap
, hwirq
, 1);
142 static int u3msi_setup_msi_irqs(struct pci_dev
*pdev
, int nvec
, int type
)
145 struct msi_desc
*entry
;
150 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
151 hwirq
= msi_bitmap_alloc_hwirqs(&msi_mpic
->msi_bitmap
, 1);
153 pr_debug("u3msi: failed allocating hwirq\n");
157 addr
= find_ht_magic_addr(pdev
, hwirq
);
159 addr
= find_u4_magic_addr(pdev
, hwirq
);
160 msg
.address_lo
= addr
& 0xFFFFFFFF;
161 msg
.address_hi
= addr
>> 32;
163 virq
= irq_create_mapping(msi_mpic
->irqhost
, hwirq
);
164 if (virq
== NO_IRQ
) {
165 pr_debug("u3msi: failed mapping hwirq 0x%x\n", hwirq
);
166 msi_bitmap_free_hwirqs(&msi_mpic
->msi_bitmap
, hwirq
, 1);
170 irq_set_msi_desc(virq
, entry
);
171 irq_set_chip(virq
, &mpic_u3msi_chip
);
172 irq_set_irq_type(virq
, IRQ_TYPE_EDGE_RISING
);
174 pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
175 virq
, hwirq
, (unsigned long)addr
);
177 printk("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
178 virq
, hwirq
, (unsigned long)addr
);
180 write_msi_msg(virq
, &msg
);
188 int mpic_u3msi_init(struct mpic
*mpic
)
192 rc
= mpic_msi_init_allocator(mpic
);
194 pr_debug("u3msi: Error allocating bitmap!\n");
198 pr_debug("u3msi: Registering MPIC U3 MSI callbacks.\n");
203 WARN_ON(ppc_md
.setup_msi_irqs
);
204 ppc_md
.setup_msi_irqs
= u3msi_setup_msi_irqs
;
205 ppc_md
.teardown_msi_irqs
= u3msi_teardown_msi_irqs
;
206 ppc_md
.msi_check_device
= u3msi_msi_check_device
;